diff options
author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-03-02 07:58:57 -0500 |
---|---|---|
committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-03-03 05:32:37 -0500 |
commit | e081c8463ac947e75f20ee11c6516f089efddaf6 (patch) | |
tree | 15ff57fba2082c63e494daf40d17530038258990 /drivers/gpu/drm/i915/intel_dp_mst.c | |
parent | 3dc38eea665f383c84cc8d858b9a7645c0b29c54 (diff) |
drm/i915: Remove duplicate DDI enabling logic from MST path
The logic to enable a DDI in intel_mst_pre_enable_dp() is essentially
the same as in intel_ddi_pre_enable_dp(). So reuse the latter function
by calling the post_disable hook on the intel_dig_port instead of
duplicating that code.
v2: Don't oops because of a NULL encoder->crtc. (Ville)
v3: Warn for MST + PORT_E too. (Ville)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302125857.14665-8-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp_mst.c | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index a8334e18c4fc..094cbdcbcd6d 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c | |||
@@ -159,26 +159,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, | |||
159 | 159 | ||
160 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | 160 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
161 | 161 | ||
162 | if (intel_dp->active_mst_links == 0) { | 162 | if (intel_dp->active_mst_links == 0) |
163 | intel_ddi_clk_select(&intel_dig_port->base, | 163 | intel_dig_port->base.pre_enable(&intel_dig_port->base, |
164 | pipe_config->shared_dpll); | 164 | pipe_config, NULL); |
165 | |||
166 | intel_display_power_get(dev_priv, | ||
167 | intel_dig_port->ddi_io_power_domain); | ||
168 | |||
169 | intel_prepare_dp_ddi_buffers(&intel_dig_port->base); | ||
170 | intel_dp_set_link_params(intel_dp, | ||
171 | pipe_config->port_clock, | ||
172 | pipe_config->lane_count, | ||
173 | true); | ||
174 | |||
175 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); | ||
176 | |||
177 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | ||
178 | |||
179 | intel_dp_start_link_train(intel_dp); | ||
180 | intel_dp_stop_link_train(intel_dp); | ||
181 | } | ||
182 | 165 | ||
183 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | 166 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, |
184 | connector->port, | 167 | connector->port, |