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authorDave Airlie <airlied@redhat.com>2015-10-02 01:41:17 -0400
committerDave Airlie <airlied@redhat.com>2015-10-02 01:41:17 -0400
commitd4070ff71363a2b6598633f23558f809600ebad2 (patch)
tree61a031eae18b88c1b563c9761a478db8fcff264b /drivers/gpu/drm/i915/intel_dp_mst.c
parent2d4df13c0f9ef56452b1d9a9016cb3946e17bfe5 (diff)
parentfd1ee4cc9326c97b52154ee2ef8cdd23ac6aae1c (diff)
Merge tag 'drm-intel-next-2015-09-11' of git://anongit.freedesktop.org/drm-intel into drm-next
- initialize backlight from VBT as fallback (Jani) - hpd A support from Ville - various atomic polish all over (mostly from Maarten) - first parts of virtualize gpu guest support on bdw from Zhiyuan Lv - GuC fixes from Alex - polish for the chv clocks code (Ville) - various things all over, as usual * tag 'drm-intel-next-2015-09-11' of git://anongit.freedesktop.org/drm-intel: (145 commits) drm/i915: Update DRIVER_DATE to 20150911 drm/i915: Remove one very outdated comment drm/i915: Use crtc->state for duplication. drm/i915: Do not handle a null plane state. drm/i915: Remove legacy plane updates for cursor and sprite planes. drm/i915: Use atomic state when changing cursor visibility. drm/i915: Use the atomic state in intel_update_primary_planes. drm/i915: Use the plane state in intel_crtc_info. drm/i915: Use atomic plane state in the primary plane update. drm/i915: add attached connector to hdmi container drm/i915: don't hard code vlv backlight frequency if unset drm/i915: initialize backlight max from VBT drm/i915: use pch backlight override on hsw too drm/i915/bxt: Clean up bxt_init_clock_gating drm/i915: Fix cmdparser STORE/LOAD command descriptors drm/i915: Dump pfit state as hex drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5 drm/i915: access the PP_CONTROL reg only pre GEN5 drm/i915: Refactor common ringbuffer allocation code drm/i915: use the yesno helper for logging ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c21
1 files changed, 9 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3e4be5a3becd..ff8ba55853be 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -39,7 +39,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
39 struct intel_dp *intel_dp = &intel_dig_port->dp; 39 struct intel_dp *intel_dp = &intel_dig_port->dp;
40 struct drm_atomic_state *state; 40 struct drm_atomic_state *state;
41 int bpp, i; 41 int bpp, i;
42 int lane_count, slots, rate; 42 int lane_count, slots;
43 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 43 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
44 struct drm_connector *drm_connector; 44 struct drm_connector *drm_connector;
45 struct intel_connector *connector, *found = NULL; 45 struct intel_connector *connector, *found = NULL;
@@ -56,20 +56,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
56 */ 56 */
57 lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 57 lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
58 58
59 rate = intel_dp_max_link_rate(intel_dp);
60 59
61 if (intel_dp->num_sink_rates) { 60 pipe_config->lane_count = lane_count;
62 intel_dp->link_bw = 0;
63 intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
64 } else {
65 intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
66 intel_dp->rate_select = 0;
67 }
68
69 intel_dp->lane_count = lane_count;
70 61
71 pipe_config->pipe_bpp = 24; 62 pipe_config->pipe_bpp = 24;
72 pipe_config->port_clock = rate; 63 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
73 64
74 state = pipe_config->base.state; 65 state = pipe_config->base.state;
75 66
@@ -184,6 +175,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
184 if (intel_dp->active_mst_links == 0) { 175 if (intel_dp->active_mst_links == 0) {
185 enum port port = intel_ddi_get_encoder_port(encoder); 176 enum port port = intel_ddi_get_encoder_port(encoder);
186 177
178 intel_dp_set_link_params(intel_dp, intel_crtc->config);
179
187 /* FIXME: add support for SKL */ 180 /* FIXME: add support for SKL */
188 if (INTEL_INFO(dev)->gen < 9) 181 if (INTEL_INFO(dev)->gen < 9)
189 I915_WRITE(PORT_CLK_SEL(port), 182 I915_WRITE(PORT_CLK_SEL(port),
@@ -286,6 +279,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
286 break; 279 break;
287 } 280 }
288 pipe_config->base.adjusted_mode.flags |= flags; 281 pipe_config->base.adjusted_mode.flags |= flags;
282
283 pipe_config->lane_count =
284 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
285
289 intel_dp_get_m_n(crtc, pipe_config); 286 intel_dp_get_m_n(crtc, pipe_config);
290 287
291 intel_ddi_clock_get(&intel_dig_port->base, pipe_config); 288 intel_ddi_clock_get(&intel_dig_port->base, pipe_config);