diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-03-23 03:15:55 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-03-23 03:15:55 -0400 |
commit | 628d4c46eef4fabe3ddbe07698577162c1cd5d41 (patch) | |
tree | 5e89f3deafd44c8b81543540c573af0c16dbb427 /drivers/gpu/drm/i915/intel_dp_mst.c | |
parent | 1e797f556c616a42f1e039b1ff1d3c58f61b6104 (diff) | |
parent | 65d1086c44791112188f6aebbdc3a27cab3736d3 (diff) |
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux into drm-misc-next
Resync with drm-next, I have a patch which currently can't be applied
because drm-misc-next lacked the latest drm/i915 code.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp_mst.c | 37 |
1 files changed, 12 insertions, 25 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index f51574f7f160..c1f62eb07c07 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c | |||
@@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
47 | 47 | ||
48 | pipe_config->has_pch_encoder = false; | 48 | pipe_config->has_pch_encoder = false; |
49 | bpp = 24; | 49 | bpp = 24; |
50 | if (intel_dp->compliance.test_data.bpc) { | ||
51 | bpp = intel_dp->compliance.test_data.bpc * 3; | ||
52 | DRM_DEBUG_KMS("Setting pipe bpp to %d\n", | ||
53 | bpp); | ||
54 | } | ||
50 | /* | 55 | /* |
51 | * for MST we always configure max link bw - the spec doesn't | 56 | * for MST we always configure max link bw - the spec doesn't |
52 | * seem to suggest we should do otherwise. | 57 | * seem to suggest we should do otherwise. |
@@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
55 | 60 | ||
56 | pipe_config->lane_count = lane_count; | 61 | pipe_config->lane_count = lane_count; |
57 | 62 | ||
58 | pipe_config->pipe_bpp = 24; | 63 | pipe_config->pipe_bpp = bpp; |
59 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); | 64 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); |
60 | 65 | ||
61 | state = pipe_config->base.state; | 66 | state = pipe_config->base.state; |
@@ -87,7 +92,6 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, | |||
87 | struct intel_dp *intel_dp = &intel_dig_port->dp; | 92 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
88 | struct intel_connector *connector = | 93 | struct intel_connector *connector = |
89 | to_intel_connector(old_conn_state->connector); | 94 | to_intel_connector(old_conn_state->connector); |
90 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | ||
91 | int ret; | 95 | int ret; |
92 | 96 | ||
93 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | 97 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
@@ -98,10 +102,8 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, | |||
98 | if (ret) { | 102 | if (ret) { |
99 | DRM_ERROR("failed to update payload %d\n", ret); | 103 | DRM_ERROR("failed to update payload %d\n", ret); |
100 | } | 104 | } |
101 | if (old_crtc_state->has_audio) { | 105 | if (old_crtc_state->has_audio) |
102 | intel_audio_codec_disable(encoder); | 106 | intel_audio_codec_disable(encoder); |
103 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | ||
104 | } | ||
105 | } | 107 | } |
106 | 108 | ||
107 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder, | 109 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder, |
@@ -156,23 +158,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, | |||
156 | 158 | ||
157 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | 159 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
158 | 160 | ||
159 | if (intel_dp->active_mst_links == 0) { | 161 | if (intel_dp->active_mst_links == 0) |
160 | intel_ddi_clk_select(&intel_dig_port->base, | 162 | intel_dig_port->base.pre_enable(&intel_dig_port->base, |
161 | pipe_config->shared_dpll); | 163 | pipe_config, NULL); |
162 | |||
163 | intel_prepare_dp_ddi_buffers(&intel_dig_port->base); | ||
164 | intel_dp_set_link_params(intel_dp, | ||
165 | pipe_config->port_clock, | ||
166 | pipe_config->lane_count, | ||
167 | true); | ||
168 | |||
169 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); | ||
170 | |||
171 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | ||
172 | |||
173 | intel_dp_start_link_train(intel_dp); | ||
174 | intel_dp_stop_link_train(intel_dp); | ||
175 | } | ||
176 | 164 | ||
177 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | 165 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, |
178 | connector->port, | 166 | connector->port, |
@@ -214,10 +202,8 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder, | |||
214 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | 202 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); |
215 | 203 | ||
216 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | 204 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); |
217 | if (pipe_config->has_audio) { | 205 | if (pipe_config->has_audio) |
218 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | ||
219 | intel_audio_codec_enable(encoder, pipe_config, conn_state); | 206 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
220 | } | ||
221 | } | 207 | } |
222 | 208 | ||
223 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | 209 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, |
@@ -548,6 +534,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum | |||
548 | DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); | 534 | DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); |
549 | 535 | ||
550 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | 536 | intel_encoder->type = INTEL_OUTPUT_DP_MST; |
537 | intel_encoder->power_domain = intel_dig_port->base.power_domain; | ||
551 | intel_encoder->port = intel_dig_port->port; | 538 | intel_encoder->port = intel_dig_port->port; |
552 | intel_encoder->crtc_mask = 0x7; | 539 | intel_encoder->crtc_mask = 0x7; |
553 | intel_encoder->cloneable = 0; | 540 | intel_encoder->cloneable = 0; |