drm/i915/mst: use max link not sink lane count

The source might not support as many lanes as the sink, or the link
training might have failed at higher lane counts. Take these into
account.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/cf59530acafaf9258fb643d321ad251b44f34e29.1491485983.git.jani.nikula@intel.com

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 094cbdcbcd6d..40608101cd3a 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -56,7 +56,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
          * for MST we always configure max link bw - the spec doesn't
          * seem to suggest we should do otherwise.
          */
-        lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+        lane_count = intel_dp_max_lane_count(intel_dp);
 
         pipe_config->lane_count = lane_count;
 
@@ -343,7 +343,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
         int max_rate, mode_rate, max_lanes, max_link_clock;
 
         max_link_clock = intel_dp_max_link_rate(intel_dp);
-        max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+        max_lanes = intel_dp_max_lane_count(intel_dp);
 
         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
         mode_rate = intel_dp_link_required(mode->clock, bpp);