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authorVille Syrjälä <ville.syrjala@linux.intel.com>2017-10-27 15:31:28 -0400
committerVille Syrjälä <ville.syrjala@linux.intel.com>2017-10-30 14:00:39 -0400
commit35686a44e4b87f45ebd426a7e2b074a54486844f (patch)
tree31627460f9547283a87ba52125eace87770f8449 /drivers/gpu/drm/i915/intel_dp_mst.c
parent1939ba51fd058b869c06aa084c0b9ae75bc721c6 (diff)
drm/i915: Use intel_ddi_get_config() for MST
Eliminate the partially duplicated DDI readout code from MST, and instead just call intel_ddi_get_config(). As a nice bonus we get more cross checking as intel_ddi_get_config() will populate output_types based on the actual mode of the DDI port. Additonally intel_ddi_get_config() must be changed to get the crtc from the passed in crtc state rather than from the encoder->crtc link. encoder->crtc really shouldn't be used anyway. v2: Rebased on BXT MST latency_optim fix Make intel_ddi_clock_get() static Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171027193128.14483-7-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c50
1 files changed, 1 insertions, 49 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index d523302e5081..6f11bb35f66f 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -286,56 +286,8 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
286{ 286{
287 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 287 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
288 struct intel_digital_port *intel_dig_port = intel_mst->primary; 288 struct intel_digital_port *intel_dig_port = intel_mst->primary;
289 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
291 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
292 u32 temp, flags = 0;
293
294 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
295
296 pipe_config->has_audio =
297 intel_ddi_is_audio_enabled(dev_priv, crtc);
298
299 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
300 if (temp & TRANS_DDI_PHSYNC)
301 flags |= DRM_MODE_FLAG_PHSYNC;
302 else
303 flags |= DRM_MODE_FLAG_NHSYNC;
304 if (temp & TRANS_DDI_PVSYNC)
305 flags |= DRM_MODE_FLAG_PVSYNC;
306 else
307 flags |= DRM_MODE_FLAG_NVSYNC;
308
309 switch (temp & TRANS_DDI_BPC_MASK) {
310 case TRANS_DDI_BPC_6:
311 pipe_config->pipe_bpp = 18;
312 break;
313 case TRANS_DDI_BPC_8:
314 pipe_config->pipe_bpp = 24;
315 break;
316 case TRANS_DDI_BPC_10:
317 pipe_config->pipe_bpp = 30;
318 break;
319 case TRANS_DDI_BPC_12:
320 pipe_config->pipe_bpp = 36;
321 break;
322 default:
323 break;
324 }
325 pipe_config->base.adjusted_mode.flags |= flags;
326
327 pipe_config->lane_count =
328 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
329
330 intel_dp_get_m_n(crtc, pipe_config);
331
332 intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
333 289
334 if (IS_GEN9_LP(dev_priv)) 290 intel_ddi_get_config(&intel_dig_port->base, pipe_config);
335 pipe_config->lane_lat_optim_mask =
336 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
337
338 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
339} 291}
340 292
341static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) 293static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)