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authorEugeni Dodonov <eugeni.dodonov@intel.com>2012-04-18 14:29:25 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-04-18 16:08:59 -0400
commit6f1d69b04fcd7ba16791165e8287d95e88bef848 (patch)
treefcfe2e587ec679441cde560d5a281fa61f412427 /drivers/gpu/drm/i915/intel_display.c
parentdde18883def89af28bd0c01aff3c7962b82dda18 (diff)
drm/i915: move clock gating functionality into intel_pm module
This moves the clock gating-related functions into intel_pm module. Also, please note that we do change the function type from static to non-static in this patch for the move, to prevent breaking bisecting with non-working intermediate commit. Those are returned back to static form in the following patch which setups a generic PM initialization function, which was split into a different one to simplify review. v2: rebase on top of latest drm-intel-next-queued to incorporate all the changes that went there meanwhile. Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c355
1 files changed, 1 insertions, 354 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4fb1982475d2..dec67aafbdc6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1515,7 +1515,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1515 * Plane regs are double buffered, going from enabled->disabled needs a 1515 * Plane regs are double buffered, going from enabled->disabled needs a
1516 * trigger in order to latch. The display address reg provides this. 1516 * trigger in order to latch. The display address reg provides this.
1517 */ 1517 */
1518static void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1518void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1519 enum plane plane) 1519 enum plane plane)
1520{ 1520{
1521 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1521 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
@@ -6351,359 +6351,6 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
6351 .output_poll_changed = intel_fb_output_poll_changed, 6351 .output_poll_changed = intel_fb_output_poll_changed,
6352}; 6352};
6353 6353
6354static void ironlake_init_clock_gating(struct drm_device *dev)
6355{
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6358
6359 /* Required for FBC */
6360 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6361 DPFCRUNIT_CLOCK_GATE_DISABLE |
6362 DPFDUNIT_CLOCK_GATE_DISABLE;
6363 /* Required for CxSR */
6364 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6365
6366 I915_WRITE(PCH_3DCGDIS0,
6367 MARIUNIT_CLOCK_GATE_DISABLE |
6368 SVSMUNIT_CLOCK_GATE_DISABLE);
6369 I915_WRITE(PCH_3DCGDIS1,
6370 VFMUNIT_CLOCK_GATE_DISABLE);
6371
6372 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6373
6374 /*
6375 * According to the spec the following bits should be set in
6376 * order to enable memory self-refresh
6377 * The bit 22/21 of 0x42004
6378 * The bit 5 of 0x42020
6379 * The bit 15 of 0x45000
6380 */
6381 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6382 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6383 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6384 I915_WRITE(ILK_DSPCLK_GATE,
6385 (I915_READ(ILK_DSPCLK_GATE) |
6386 ILK_DPARB_CLK_GATE));
6387 I915_WRITE(DISP_ARB_CTL,
6388 (I915_READ(DISP_ARB_CTL) |
6389 DISP_FBC_WM_DIS));
6390 I915_WRITE(WM3_LP_ILK, 0);
6391 I915_WRITE(WM2_LP_ILK, 0);
6392 I915_WRITE(WM1_LP_ILK, 0);
6393
6394 /*
6395 * Based on the document from hardware guys the following bits
6396 * should be set unconditionally in order to enable FBC.
6397 * The bit 22 of 0x42000
6398 * The bit 22 of 0x42004
6399 * The bit 7,8,9 of 0x42020.
6400 */
6401 if (IS_IRONLAKE_M(dev)) {
6402 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6403 I915_READ(ILK_DISPLAY_CHICKEN1) |
6404 ILK_FBCQ_DIS);
6405 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6406 I915_READ(ILK_DISPLAY_CHICKEN2) |
6407 ILK_DPARB_GATE);
6408 I915_WRITE(ILK_DSPCLK_GATE,
6409 I915_READ(ILK_DSPCLK_GATE) |
6410 ILK_DPFC_DIS1 |
6411 ILK_DPFC_DIS2 |
6412 ILK_CLK_FBC);
6413 }
6414
6415 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6416 I915_READ(ILK_DISPLAY_CHICKEN2) |
6417 ILK_ELPIN_409_SELECT);
6418 I915_WRITE(_3D_CHICKEN2,
6419 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6420 _3D_CHICKEN2_WM_READ_PIPELINED);
6421}
6422
6423static void gen6_init_clock_gating(struct drm_device *dev)
6424{
6425 struct drm_i915_private *dev_priv = dev->dev_private;
6426 int pipe;
6427 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6428
6429 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6430
6431 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6432 I915_READ(ILK_DISPLAY_CHICKEN2) |
6433 ILK_ELPIN_409_SELECT);
6434
6435 I915_WRITE(WM3_LP_ILK, 0);
6436 I915_WRITE(WM2_LP_ILK, 0);
6437 I915_WRITE(WM1_LP_ILK, 0);
6438
6439 /* clear masked bit */
6440 I915_WRITE(CACHE_MODE_0,
6441 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
6442
6443 I915_WRITE(GEN6_UCGCTL1,
6444 I915_READ(GEN6_UCGCTL1) |
6445 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6446 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6447
6448 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6449 * gating disable must be set. Failure to set it results in
6450 * flickering pixels due to Z write ordering failures after
6451 * some amount of runtime in the Mesa "fire" demo, and Unigine
6452 * Sanctuary and Tropics, and apparently anything else with
6453 * alpha test or pixel discard.
6454 *
6455 * According to the spec, bit 11 (RCCUNIT) must also be set,
6456 * but we didn't debug actual testcases to find it out.
6457 */
6458 I915_WRITE(GEN6_UCGCTL2,
6459 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6460 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6461
6462 /* Bspec says we need to always set all mask bits. */
6463 I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
6464 _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
6465
6466 /*
6467 * According to the spec the following bits should be
6468 * set in order to enable memory self-refresh and fbc:
6469 * The bit21 and bit22 of 0x42000
6470 * The bit21 and bit22 of 0x42004
6471 * The bit5 and bit7 of 0x42020
6472 * The bit14 of 0x70180
6473 * The bit14 of 0x71180
6474 */
6475 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6476 I915_READ(ILK_DISPLAY_CHICKEN1) |
6477 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6478 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6479 I915_READ(ILK_DISPLAY_CHICKEN2) |
6480 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6481 I915_WRITE(ILK_DSPCLK_GATE,
6482 I915_READ(ILK_DSPCLK_GATE) |
6483 ILK_DPARB_CLK_GATE |
6484 ILK_DPFD_CLK_GATE);
6485
6486 for_each_pipe(pipe) {
6487 I915_WRITE(DSPCNTR(pipe),
6488 I915_READ(DSPCNTR(pipe)) |
6489 DISPPLANE_TRICKLE_FEED_DISABLE);
6490 intel_flush_display_plane(dev_priv, pipe);
6491 }
6492}
6493
6494static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6495{
6496 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6497
6498 reg &= ~GEN7_FF_SCHED_MASK;
6499 reg |= GEN7_FF_TS_SCHED_HW;
6500 reg |= GEN7_FF_VS_SCHED_HW;
6501 reg |= GEN7_FF_DS_SCHED_HW;
6502
6503 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6504}
6505
6506static void ivybridge_init_clock_gating(struct drm_device *dev)
6507{
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509 int pipe;
6510 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6511
6512 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6513
6514 I915_WRITE(WM3_LP_ILK, 0);
6515 I915_WRITE(WM2_LP_ILK, 0);
6516 I915_WRITE(WM1_LP_ILK, 0);
6517
6518 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6519 * This implements the WaDisableRCZUnitClockGating workaround.
6520 */
6521 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6522
6523 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
6524
6525 I915_WRITE(IVB_CHICKEN3,
6526 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6527 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6528
6529 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
6530 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6531 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6532
6533 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
6534 I915_WRITE(GEN7_L3CNTLREG1,
6535 GEN7_WA_FOR_GEN7_L3_CONTROL);
6536 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6537 GEN7_WA_L3_CHICKEN_MODE);
6538
6539 /* This is required by WaCatErrorRejectionIssue */
6540 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6541 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6542 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6543
6544 for_each_pipe(pipe) {
6545 I915_WRITE(DSPCNTR(pipe),
6546 I915_READ(DSPCNTR(pipe)) |
6547 DISPPLANE_TRICKLE_FEED_DISABLE);
6548 intel_flush_display_plane(dev_priv, pipe);
6549 }
6550
6551 gen7_setup_fixed_func_scheduler(dev_priv);
6552}
6553
6554static void valleyview_init_clock_gating(struct drm_device *dev)
6555{
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557 int pipe;
6558 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6559
6560 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6561
6562 I915_WRITE(WM3_LP_ILK, 0);
6563 I915_WRITE(WM2_LP_ILK, 0);
6564 I915_WRITE(WM1_LP_ILK, 0);
6565
6566 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6567 * This implements the WaDisableRCZUnitClockGating workaround.
6568 */
6569 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6570
6571 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
6572
6573 I915_WRITE(IVB_CHICKEN3,
6574 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6575 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6576
6577 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
6578 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6579 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6580
6581 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
6582 I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
6583 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
6584
6585 /* This is required by WaCatErrorRejectionIssue */
6586 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6587 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6588 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6589
6590 for_each_pipe(pipe) {
6591 I915_WRITE(DSPCNTR(pipe),
6592 I915_READ(DSPCNTR(pipe)) |
6593 DISPPLANE_TRICKLE_FEED_DISABLE);
6594 intel_flush_display_plane(dev_priv, pipe);
6595 }
6596
6597 I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
6598 (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
6599 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
6600}
6601
6602static void g4x_init_clock_gating(struct drm_device *dev)
6603{
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 uint32_t dspclk_gate;
6606
6607 I915_WRITE(RENCLK_GATE_D1, 0);
6608 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6609 GS_UNIT_CLOCK_GATE_DISABLE |
6610 CL_UNIT_CLOCK_GATE_DISABLE);
6611 I915_WRITE(RAMCLK_GATE_D, 0);
6612 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6613 OVRUNIT_CLOCK_GATE_DISABLE |
6614 OVCUNIT_CLOCK_GATE_DISABLE;
6615 if (IS_GM45(dev))
6616 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6617 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6618}
6619
6620static void crestline_init_clock_gating(struct drm_device *dev)
6621{
6622 struct drm_i915_private *dev_priv = dev->dev_private;
6623
6624 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6625 I915_WRITE(RENCLK_GATE_D2, 0);
6626 I915_WRITE(DSPCLK_GATE_D, 0);
6627 I915_WRITE(RAMCLK_GATE_D, 0);
6628 I915_WRITE16(DEUC, 0);
6629}
6630
6631static void broadwater_init_clock_gating(struct drm_device *dev)
6632{
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634
6635 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6636 I965_RCC_CLOCK_GATE_DISABLE |
6637 I965_RCPB_CLOCK_GATE_DISABLE |
6638 I965_ISC_CLOCK_GATE_DISABLE |
6639 I965_FBC_CLOCK_GATE_DISABLE);
6640 I915_WRITE(RENCLK_GATE_D2, 0);
6641}
6642
6643static void gen3_init_clock_gating(struct drm_device *dev)
6644{
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6646 u32 dstate = I915_READ(D_STATE);
6647
6648 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6649 DSTATE_DOT_CLOCK_GATING;
6650 I915_WRITE(D_STATE, dstate);
6651}
6652
6653static void i85x_init_clock_gating(struct drm_device *dev)
6654{
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656
6657 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6658}
6659
6660static void i830_init_clock_gating(struct drm_device *dev)
6661{
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663
6664 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6665}
6666
6667static void ibx_init_clock_gating(struct drm_device *dev)
6668{
6669 struct drm_i915_private *dev_priv = dev->dev_private;
6670
6671 /*
6672 * On Ibex Peak and Cougar Point, we need to disable clock
6673 * gating for the panel power sequencer or it will fail to
6674 * start up when no ports are active.
6675 */
6676 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6677}
6678
6679static void cpt_init_clock_gating(struct drm_device *dev)
6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 int pipe;
6683
6684 /*
6685 * On Ibex Peak and Cougar Point, we need to disable clock
6686 * gating for the panel power sequencer or it will fail to
6687 * start up when no ports are active.
6688 */
6689 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6690 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6691 DPLS_EDP_PPS_FIX_DIS);
6692 /* Without this, mode sets may fail silently on FDI */
6693 for_each_pipe(pipe)
6694 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
6695}
6696
6697void intel_init_clock_gating(struct drm_device *dev)
6698{
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700
6701 dev_priv->display.init_clock_gating(dev);
6702
6703 if (dev_priv->display.init_pch_clock_gating)
6704 dev_priv->display.init_pch_clock_gating(dev);
6705}
6706
6707/* Set up chip specific display functions */ 6354/* Set up chip specific display functions */
6708static void intel_init_display(struct drm_device *dev) 6355static void intel_init_display(struct drm_device *dev)
6709{ 6356{
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