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authorVille Syrjälä <ville.syrjala@linux.intel.com>2016-11-18 14:52:57 -0500
committerVille Syrjälä <ville.syrjala@linux.intel.com>2016-12-15 07:55:30 -0500
commit2f3f4763c1ba9348984ed67aa60a16c86a9dab1c (patch)
tree72a152ffc765eda91f400b9b85ccb2b7d0ef38e3 /drivers/gpu/drm/i915/intel_display.c
parente14c23c647abfc1fed96a55ba376cd9675a54098 (diff)
drm/i915: Populate fb->format early for inherited fbs
Make sure the framebuffer format info is available as early as possible for fbs we inherit from the BIOS. This will allow us to use the fb as if it was fully formed before we register it. Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-22-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 030adf255afe..a760814ec974 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8717,6 +8717,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8717 fourcc = i9xx_format_to_fourcc(pixel_format); 8717 fourcc = i9xx_format_to_fourcc(pixel_format);
8718 fb->pixel_format = fourcc; 8718 fb->pixel_format = fourcc;
8719 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 8719 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8720 fb->format = drm_format_info(fourcc);
8720 8721
8721 if (INTEL_GEN(dev_priv) >= 4) { 8722 if (INTEL_GEN(dev_priv) >= 4) {
8722 if (plane_config->tiling) 8723 if (plane_config->tiling)
@@ -9748,6 +9749,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
9748 val & PLANE_CTL_ALPHA_MASK); 9749 val & PLANE_CTL_ALPHA_MASK);
9749 fb->pixel_format = fourcc; 9750 fb->pixel_format = fourcc;
9750 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9751 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9752 fb->format = drm_format_info(fourcc);
9751 9753
9752 tiling = val & PLANE_CTL_TILED_MASK; 9754 tiling = val & PLANE_CTL_TILED_MASK;
9753 switch (tiling) { 9755 switch (tiling) {
@@ -9863,6 +9865,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9863 fourcc = i9xx_format_to_fourcc(pixel_format); 9865 fourcc = i9xx_format_to_fourcc(pixel_format);
9864 fb->pixel_format = fourcc; 9866 fb->pixel_format = fourcc;
9865 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; 9867 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9868 fb->format = drm_format_info(fourcc);
9866 9869
9867 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; 9870 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9868 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 9871 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {