drm/i915/perf: enable perf support on ICL

No significant changes from either context offsets, nor report
formats, nor register whitelist.

v2: Also drop slice/unslice clock ratio changes (Matt)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180326133949.12469-3-lionel.g.landwerlin@intel.com

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index abaca6edeb71..30444bb3aaa1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -209,6 +209,7 @@
 #include "i915_oa_cflgt2.h"
 #include "i915_oa_cflgt3.h"
 #include "i915_oa_cnl.h"
+#include "i915_oa_icl.h"
 
 /* HW requires this to be a power of two, between 128k and 16M, though driver
  * is currently generally designed assuming the largest 16M size is used such
@@ -1840,7 +1841,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
          * be read back from automatically triggered reports, as part of the
          * RPT_ID field.
          */
-        if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
+        if (IS_GEN(dev_priv, 9, 11)) {
                 I915_WRITE(GEN8_OA_DEBUG,
                            _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
                                               GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -2935,6 +2936,8 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
                         i915_perf_load_test_config_cflgt3(dev_priv);
         } else if (IS_CANNONLAKE(dev_priv)) {
                 i915_perf_load_test_config_cnl(dev_priv);
+        } else if (IS_ICELAKE(dev_priv)) {
+                i915_perf_load_test_config_icl(dev_priv);
         }
 
         if (dev_priv->perf.oa.test_config.id == 0)
@@ -3467,7 +3470,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
 
                                 dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
                         }
-                } else if (IS_GEN10(dev_priv)) {
+                } else if (IS_GEN(dev_priv, 10, 11)) {
                         dev_priv->perf.oa.ops.is_valid_b_counter_reg =
                                 gen7_is_valid_b_counter_addr;
                         dev_priv->perf.oa.ops.is_valid_mux_reg =