drm/i915: Increase max fence pitch limit to 256KB on IVB+

BSpec contains several scattered notes which state that the maximum
fence stride was increased to 256KB on IVB.

Testing on real hardware agrees.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 6 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index b56185f4babb..537545be69db 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
                 tile_width = 512;
 
         /* check maximum stride & object size */
-        if (INTEL_INFO(dev)->gen >= 4) {
-                /* i965 stores the end address of the gtt mapping in the fence
-                 * reg, so dont bother to check the size */
+        /* i965+ stores the end address of the gtt mapping in the fence
+         * reg, so dont bother to check the size */
+        if (INTEL_INFO(dev)->gen >= 7) {
+                if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
+                        return false;
+        } else if (INTEL_INFO(dev)->gen >= 4) {
                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
                         return false;
         } else {