drm/i915: disable flushing_list/gpu_write_list

This is just the minimal patch to disable all this code so that we can
do decent amounts of QA before we rip it all out.

The complicating thing is that we need to flush the gpu caches after
the batchbuffer is emitted. Which is past the point of no return where
execbuffer can't fail any more (otherwise we risk submitting the same
batch multiple times).

Hence we need to add a flag to track whether any caches associated
with that ring are dirty. And emit the flush in add_request if that's
the case.

Note that this has a quite a few behaviour changes:
- Caches get flushed/invalidated unconditionally.
- Invalidation now happens after potential inter-ring sync.

I've bantered around a bit with Chris on irc whether this fixes
anything, and it might or might not. The only thing clear is that with
these changes it's much easier to reason about correctness.

Also rip out a lone get_next_request_seqno in the execbuffer
retire_commands function. I've dug around and I couldn't figure out
why that is still there, with the outstanding lazy request stuff it
shouldn't be necessary.

v2: Chris Wilson complained that I also invalidate the read caches
when flushing after a batchbuffer. Now optimized.

v3: Added some comments to explain the new flushing behaviour.

Cc: Eric Anholt <eric@anholt.net>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 12 insertions, 40 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f32d02464bce..88e2e114189c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -810,33 +810,16 @@ err:
         return ret;
 }
 
-static int
+static void
 i915_gem_execbuffer_flush(struct drm_device *dev,
                           uint32_t invalidate_domains,
-                          uint32_t flush_domains,
-                          uint32_t flush_rings)
+                          uint32_t flush_domains)
 {
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        int i, ret;
-
         if (flush_domains & I915_GEM_DOMAIN_CPU)
                 intel_gtt_chipset_flush();
 
         if (flush_domains & I915_GEM_DOMAIN_GTT)
                 wmb();
-
-        if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
-                for (i = 0; i < I915_NUM_RINGS; i++)
-                        if (flush_rings & (1 << i)) {
-                                ret = i915_gem_flush_ring(&dev_priv->ring[i],
-                                                          invalidate_domains,
-                                                          flush_domains);
-                                if (ret)
-                                        return ret;
-                        }
-        }
-
-        return 0;
 }
 
 static int
@@ -885,12 +868,9 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
                 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 
         if (cd.invalidate_domains | cd.flush_domains) {
-                ret = i915_gem_execbuffer_flush(ring->dev,
-                                                cd.invalidate_domains,
-                                                cd.flush_domains,
-                                                cd.flush_rings);
-                if (ret)
-                        return ret;
+                i915_gem_execbuffer_flush(ring->dev,
+                                          cd.invalidate_domains,
+                                          cd.flush_domains);
         }
 
         if (cd.flips) {
@@ -905,6 +885,11 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
                         return ret;
         }
 
+        /* Unconditionally invalidate gpu caches. */
+        ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS, 0);
+        if (ret)
+                return ret;
+
         return 0;
 }
 
@@ -983,26 +968,13 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
                                     struct intel_ring_buffer *ring)
 {
         struct drm_i915_gem_request *request;
-        u32 invalidate;
 
-        /*
-         * Ensure that the commands in the batch buffer are
-         * finished before the interrupt fires.
-         *
-         * The sampler always gets flushed on i965 (sigh).
-         */
-        invalidate = I915_GEM_DOMAIN_COMMAND;
-        if (INTEL_INFO(dev)->gen >= 4)
-                invalidate |= I915_GEM_DOMAIN_SAMPLER;
-        if (ring->flush(ring, invalidate, 0)) {
-                i915_gem_next_request_seqno(ring);
-                return;
-        }
+        /* Unconditionally force add_request to emit a full flush. */
+        ring->gpu_caches_dirty = true;
 
         /* Add a breadcrumb for the completion of the batch buffer */
         request = kzalloc(sizeof(*request), GFP_KERNEL);
         if (request == NULL || i915_add_request(ring, file, request)) {
-                i915_gem_next_request_seqno(ring);
                 kfree(request);
         }
 }