Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

Daniel writes:
- seqno wrap fixes and debug infrastructure from Mika Kuoppala and Chris
  Wilson
- some leftover kill-agp on gen6+ patches from Ben
- hotplug improvements from Damien
- clear fb when allocated from stolen, avoids dirt on the fbcon (Chris)
- Stolen mem support from Chris Wilson, one of the many steps to get to
  real fastboot support.
- Some DDI code cleanups from Paulo.
- Some refactorings around lvds and dp code.
- some random little bits&pieces

* tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm-intel: (93 commits)
  drm/i915: Return the real error code from intel_set_mode()
  drm/i915: Make GSM void
  drm/i915: Move GSM mapping into dev_priv
  drm/i915: Move even more gtt code to i915_gem_gtt
  drm/i915: Make next_seqno debugs entry to use i915_gem_set_seqno
  drm/i915: Introduce i915_gem_set_seqno()
  drm/i915: Always clear semaphore mboxes on seqno wrap
  drm/i915: Initialize hardware semaphore state on ring init
  drm/i915: Introduce ring set_seqno
  drm/i915: Missed conversion to gtt_pte_t
  drm/i915: Bug on unsupported swizzled platforms
  drm/i915: BUG() if fences are used on unsupported platform
  drm/i915: fixup overlay stolen memory leak
  drm/i915: clean up PIPECONF bpc #defines
  drm/i915: add intel_dp_set_signal_levels
  drm/i915: remove leftover display.update_wm assignment
  drm/i915: check for the PCH when setting pch_transcoder
  drm/i915: Clear the stolen fb before enabling
  drm/i915: Access to snooped system memory through the GTT is incoherent
  drm/i915: Remove stale comment about intel_dp_detect()
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_display.c

1 files changed, 0 insertions, 53 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d6a994a07393..163bb52bd3b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -150,17 +150,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
                           reloc->write_domain);
                 return ret;
         }
-        if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
-                     reloc->write_domain != target_obj->pending_write_domain)) {
-                DRM_DEBUG("Write domain conflict: "
-                          "obj %p target %d offset %d "
-                          "new %08x old %08x\n",
-                          obj, reloc->target_handle,
-                          (int) reloc->offset,
-                          reloc->write_domain,
-                          target_obj->pending_write_domain);
-                return ret;
-        }
 
         target_obj->pending_read_domains |= reloc->read_domains;
         target_obj->pending_write_domain |= reloc->write_domain;
@@ -602,44 +591,11 @@ err:
 }
 
 static int
-i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
-{
-        u32 plane, flip_mask;
-        int ret;
-
-        /* Check for any pending flips. As we only maintain a flip queue depth
-         * of 1, we can simply insert a WAIT for the next display flip prior
-         * to executing the batch and avoid stalling the CPU.
-         */
-
-        for (plane = 0; flips >> plane; plane++) {
-                if (((flips >> plane) & 1) == 0)
-                        continue;
-
-                if (plane)
-                        flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-                else
-                        flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-
-                ret = intel_ring_begin(ring, 2);
-                if (ret)
-                        return ret;
-
-                intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
-                intel_ring_emit(ring, MI_NOOP);
-                intel_ring_advance(ring);
-        }
-
-        return 0;
-}
-
-static int
 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
                                 struct list_head *objects)
 {
         struct drm_i915_gem_object *obj;
         uint32_t flush_domains = 0;
-        uint32_t flips = 0;
         int ret;
 
         list_for_each_entry(obj, objects, exec_list) {
@@ -650,18 +606,9 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
                         i915_gem_clflush_object(obj);
 
-                if (obj->base.pending_write_domain)
-                        flips |= atomic_read(&obj->pending_flip);
-
                 flush_domains |= obj->base.write_domain;
         }
 
-        if (flips) {
-                ret = i915_gem_execbuffer_wait_for_flips(ring, flips);
-                if (ret)
-                        return ret;
-        }
-
         if (flush_domains & I915_GEM_DOMAIN_CPU)
                 i915_gem_chipset_flush(ring->dev);