diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-08-17 02:57:56 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-08-17 03:01:08 -0400 |
commit | a22ddff8bedfe33eeb1330bbb7ef1fbe007a42c4 (patch) | |
tree | 61a2eb7fa62f5af10c2b913ca429e6b068b0eb2d /drivers/gpu/drm/i915/i915_gem_execbuffer.c | |
parent | 20d5a540e55a29daeef12706f9ee73baf5641c16 (diff) | |
parent | d9875690d9b89a866022ff49e3fcea892345ad92 (diff) |
Merge tag 'v3.6-rc2' into drm-intel-next
Backmerge Linux 3.6-rc2 to resolve a few funny conflicts before we put
even more madness on top:
- drivers/gpu/drm/i915/i915_irq.c: Just a spurious WARN removed in
-fixes, that has been changed in a variable-rename in -next, too.
- drivers/gpu/drm/i915/intel_ringbuffer.c: -next remove scratch_addr
(since all their users have been extracted in another fucntion),
-fixes added another user for a hw workaroudn.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_execbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 25b2c54e1261..afb312ee050c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c | |||
@@ -117,6 +117,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |||
117 | target_i915_obj = to_intel_bo(target_obj); | 117 | target_i915_obj = to_intel_bo(target_obj); |
118 | target_offset = target_i915_obj->gtt_offset; | 118 | target_offset = target_i915_obj->gtt_offset; |
119 | 119 | ||
120 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and | ||
121 | * pipe_control writes because the gpu doesn't properly redirect them | ||
122 | * through the ppgtt for non_secure batchbuffers. */ | ||
123 | if (unlikely(IS_GEN6(dev) && | ||
124 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | ||
125 | !target_i915_obj->has_global_gtt_mapping)) { | ||
126 | i915_gem_gtt_bind_object(target_i915_obj, | ||
127 | target_i915_obj->cache_level); | ||
128 | } | ||
129 | |||
120 | /* The target buffer should have appeared before us in the | 130 | /* The target buffer should have appeared before us in the |
121 | * exec_object list, so it should have a GTT space bound by now. | 131 | * exec_object list, so it should have a GTT space bound by now. |
122 | */ | 132 | */ |
@@ -225,16 +235,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |||
225 | io_mapping_unmap_atomic(reloc_page); | 235 | io_mapping_unmap_atomic(reloc_page); |
226 | } | 236 | } |
227 | 237 | ||
228 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and | ||
229 | * pipe_control writes because the gpu doesn't properly redirect them | ||
230 | * through the ppgtt for non_secure batchbuffers. */ | ||
231 | if (unlikely(IS_GEN6(dev) && | ||
232 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | ||
233 | !target_i915_obj->has_global_gtt_mapping)) { | ||
234 | i915_gem_gtt_bind_object(target_i915_obj, | ||
235 | target_i915_obj->cache_level); | ||
236 | } | ||
237 | |||
238 | /* and update the user's relocation entry */ | 238 | /* and update the user's relocation entry */ |
239 | reloc->presumed_offset = target_offset; | 239 | reloc->presumed_offset = target_offset; |
240 | 240 | ||