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authorChris Wilson <chris@chris-wilson.co.uk>2014-09-06 05:28:27 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-19 15:17:11 -0500
commit5c6c600354adac5f95fd41b178b084ac0182e14c (patch)
tree7c21cb65eea1843a73577964b72f2064e70fc46e /drivers/gpu/drm/i915/i915_gem_execbuffer.c
parent7ba717cf365d79f2b284e508205ec3d4a05fc41b (diff)
drm/i915: Remove DRI1 ring accessors and API
With the deprecation of UMS, and by association DRI1, we have a tough choice when updating the ring access routines. We either rewrite the DRI1 routines blindly without testing (so likely to be broken) or take the liberty of declaring them no longer supported and remove them entirely. This takes the latter approach. v2: Also remove the DRI1 sarea updates Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Fix rebase conflicts.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_execbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c43
1 files changed, 42 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e1ed85a6dc6d..b16eee061990 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1020,6 +1020,47 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
1020 return 0; 1020 return 0;
1021} 1021}
1022 1022
1023static int
1024i915_emit_box(struct intel_engine_cs *ring,
1025 struct drm_clip_rect *box,
1026 int DR1, int DR4)
1027{
1028 int ret;
1029
1030 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
1031 box->y2 <= 0 || box->x2 <= 0) {
1032 DRM_ERROR("Bad box %d,%d..%d,%d\n",
1033 box->x1, box->y1, box->x2, box->y2);
1034 return -EINVAL;
1035 }
1036
1037 if (INTEL_INFO(ring->dev)->gen >= 4) {
1038 ret = intel_ring_begin(ring, 4);
1039 if (ret)
1040 return ret;
1041
1042 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
1043 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1044 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1045 intel_ring_emit(ring, DR4);
1046 } else {
1047 ret = intel_ring_begin(ring, 6);
1048 if (ret)
1049 return ret;
1050
1051 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
1052 intel_ring_emit(ring, DR1);
1053 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
1054 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
1055 intel_ring_emit(ring, DR4);
1056 intel_ring_emit(ring, 0);
1057 }
1058 intel_ring_advance(ring);
1059
1060 return 0;
1061}
1062
1063
1023int 1064int
1024i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, 1065i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1025 struct intel_engine_cs *ring, 1066 struct intel_engine_cs *ring,
@@ -1148,7 +1189,7 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
1148 exec_len = args->batch_len; 1189 exec_len = args->batch_len;
1149 if (cliprects) { 1190 if (cliprects) {
1150 for (i = 0; i < args->num_cliprects; i++) { 1191 for (i = 0; i < args->num_cliprects; i++) {
1151 ret = i915_emit_box(dev, &cliprects[i], 1192 ret = i915_emit_box(ring, &cliprects[i],
1152 args->DR1, args->DR4); 1193 args->DR1, args->DR4);
1153 if (ret) 1194 if (ret)
1154 goto error; 1195 goto error;