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authorChris Wilson <chris@chris-wilson.co.uk>2015-11-20 09:16:39 -0500
committerJani Nikula <jani.nikula@intel.com>2015-12-22 04:52:27 -0500
commit62d622c1f8d34bde3e3b9fd06f15c35d4028a8ff (patch)
tree528f5027a9bd0bd6eac6fda0c4181acfa16067e7 /drivers/gpu/drm/i915/i915_gem.c
parent615cb24326bbe19834a1aba47677a6c80bdcfc01 (diff)
drm/i915: Set the map-and-fenceable flag for preallocated objects
As we mark the preallocated objects as bound, we should also flag them correctly as being map-and-fenceable (if appropriate!) so that later users do not get confused and try and rebind the pinned vma in order to get a map-and-fenceable binding. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: "Goel, Akash" <akash.goel@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: drm-intel-fixes@lists.freedesktop.org Link: http://patchwork.freedesktop.org/patch/msgid/1448029000-10616-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit d0710abbcd88b1ff17760e97d74a673e67b49ea1) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c43
1 files changed, 24 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 32e6aade6223..3163518ba19a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4080,6 +4080,29 @@ i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4080 return false; 4080 return false;
4081} 4081}
4082 4082
4083void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4084{
4085 struct drm_i915_gem_object *obj = vma->obj;
4086 bool mappable, fenceable;
4087 u32 fence_size, fence_alignment;
4088
4089 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4090 obj->base.size,
4091 obj->tiling_mode);
4092 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4093 obj->base.size,
4094 obj->tiling_mode,
4095 true);
4096
4097 fenceable = (vma->node.size == fence_size &&
4098 (vma->node.start & (fence_alignment - 1)) == 0);
4099
4100 mappable = (vma->node.start + fence_size <=
4101 to_i915(obj->base.dev)->gtt.mappable_end);
4102
4103 obj->map_and_fenceable = mappable && fenceable;
4104}
4105
4083static int 4106static int
4084i915_gem_object_do_pin(struct drm_i915_gem_object *obj, 4107i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4085 struct i915_address_space *vm, 4108 struct i915_address_space *vm,
@@ -4147,25 +4170,7 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4147 4170
4148 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && 4171 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4149 (bound ^ vma->bound) & GLOBAL_BIND) { 4172 (bound ^ vma->bound) & GLOBAL_BIND) {
4150 bool mappable, fenceable; 4173 __i915_vma_set_map_and_fenceable(vma);
4151 u32 fence_size, fence_alignment;
4152
4153 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4154 obj->base.size,
4155 obj->tiling_mode);
4156 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4157 obj->base.size,
4158 obj->tiling_mode,
4159 true);
4160
4161 fenceable = (vma->node.size == fence_size &&
4162 (vma->node.start & (fence_alignment - 1)) == 0);
4163
4164 mappable = (vma->node.start + fence_size <=
4165 dev_priv->gtt.mappable_end);
4166
4167 obj->map_and_fenceable = mappable && fenceable;
4168
4169 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); 4174 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4170 } 4175 }
4171 4176