aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_debugfs.c
diff options
context:
space:
mode:
authorShuang He <shuang.he@intel.com>2013-10-15 13:55:27 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-16 07:31:42 -0400
commit8bf1e9f1d2aa1fafd2b262683a13cbb7f934c6d0 (patch)
tree566a542be2daad123dda2cdd39a536f6ace3ae37 /drivers/gpu/drm/i915/i915_debugfs.c
parent73ae478cdf6ab886b107f39269cbbf6d33ad2abe (diff)
drm/i915: Expose latest 200 CRC value for pipe through debugfs
There are several points in the display pipeline where CRCs can be computed on the bits flowing there. For instance, it's usually possible to compute the CRCs of the primary plane, the sprite plane or the CRCs of the bits after the panel fitter (collectively called pipe CRCs). v2: Quite a bit of rework here and there (Damien) Signed-off-by: Shuang He <shuang.he@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Fix intermediate compile file reported by Wu Fengguang's kernel builder.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 72d04588eccb..e1d45aaf6881 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1732,6 +1732,36 @@ static int i915_pc8_status(struct seq_file *m, void *unused)
1732 return 0; 1732 return 0;
1733} 1733}
1734 1734
1735static int i915_pipe_crc(struct seq_file *m, void *data)
1736{
1737 struct drm_info_node *node = (struct drm_info_node *) m->private;
1738 struct drm_device *dev = node->minor->dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 enum pipe pipe = (enum pipe)node->info_ent->data;
1741 const struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1742 int i;
1743 int start;
1744
1745 if (!IS_IVYBRIDGE(dev)) {
1746 seq_puts(m, "unsupported\n");
1747 return 0;
1748 }
1749
1750 start = atomic_read(&pipe_crc->slot) + 1;
1751 seq_puts(m, " timestamp CRC1 CRC2 CRC3 CRC4 CRC5\n");
1752 for (i = 0; i < INTEL_PIPE_CRC_ENTRIES_NR; i++) {
1753 const struct intel_pipe_crc_entry *entry =
1754 &pipe_crc->entries[(start + i) %
1755 INTEL_PIPE_CRC_ENTRIES_NR];
1756
1757 seq_printf(m, "%12u %8x %8x %8x %8x %8x\n", entry->timestamp,
1758 entry->crc[0], entry->crc[1], entry->crc[2],
1759 entry->crc[3], entry->crc[4]);
1760 }
1761
1762 return 0;
1763}
1764
1735static int 1765static int
1736i915_wedged_get(void *data, u64 *val) 1766i915_wedged_get(void *data, u64 *val)
1737{ 1767{
@@ -2247,6 +2277,9 @@ static struct drm_info_list i915_debugfs_list[] = {
2247 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 2277 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2248 {"i915_energy_uJ", i915_energy_uJ, 0}, 2278 {"i915_energy_uJ", i915_energy_uJ, 0},
2249 {"i915_pc8_status", i915_pc8_status, 0}, 2279 {"i915_pc8_status", i915_pc8_status, 0},
2280 {"i915_pipe_A_crc", i915_pipe_crc, 0, (void *)PIPE_A},
2281 {"i915_pipe_B_crc", i915_pipe_crc, 0, (void *)PIPE_B},
2282 {"i915_pipe_C_crc", i915_pipe_crc, 0, (void *)PIPE_C},
2250}; 2283};
2251#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 2284#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2252 2285