drm/i915: add DPIO support

ValleyView puts some display related registers like the PLL controls and
dividers behind the DPIO bus.  Add simple indirect register access
routines to get to those registers.

v2: move new wait_for macro to intel_drv.h (Ben)
    fix DPIO_PKT double write (Ben)
    add debugfs file

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 48 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 66c90d4477a3..e74674b3097d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1503,6 +1503,53 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
         return 0;
 }
 
+static int i915_dpio_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int ret;
+
+
+        if (!IS_VALLEYVIEW(dev)) {
+                seq_printf(m, "unsupported\n");
+                return 0;
+        }
+
+        ret = mutex_lock_interruptible(&dev->mode_config.mutex);
+        if (ret)
+                return ret;
+
+        seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
+
+        seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_DIV_A));
+        seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_DIV_B));
+
+        seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
+        seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
+
+        seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+        seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+
+        seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
+        seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
+                   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
+
+        seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
+                   intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+
+        mutex_unlock(&dev->mode_config.mutex);
+
+        return 0;
+}
+
 static int
 i915_debugfs_common_open(struct inode *inode,
                          struct file *filp)
@@ -1845,6 +1892,7 @@ static struct drm_info_list i915_debugfs_list[] = {
         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
         {"i915_swizzle_info", i915_swizzle_info, 0},
         {"i915_ppgtt_info", i915_ppgtt_info, 0},
+        {"i915_dpio", i915_dpio_info, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)