Merge airlied/drm-next into drm-misc-next

Backmerge the main pull request to sync up with all the newly landed
drivers. Otherwise we'll have chaos even before 4.12 started in
earnest.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 19 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 9a4b23c3ee97..b9c8e2407682 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -481,7 +481,6 @@ struct parser_exec_state {
         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 
 static unsigned long bypass_scan_mask = 0;
-static bool bypass_batch_buffer_scan = true;
 
 /* ring ALL, type = 0 */
 static struct sub_op_bits sub_op_mi[] = {
@@ -1135,6 +1134,8 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
         u32 dword2 = cmd_val(s, 2);
         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
 
+        info->plane = PRIMARY_PLANE;
+
         switch (plane) {
         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
                 info->pipe = PIPE_A;
@@ -1148,12 +1149,28 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
                 info->pipe = PIPE_C;
                 info->event = PRIMARY_C_FLIP_DONE;
                 break;
+
+        case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
+                info->pipe = PIPE_A;
+                info->event = SPRITE_A_FLIP_DONE;
+                info->plane = SPRITE_PLANE;
+                break;
+        case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
+                info->pipe = PIPE_B;
+                info->event = SPRITE_B_FLIP_DONE;
+                info->plane = SPRITE_PLANE;
+                break;
+        case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
+                info->pipe = PIPE_C;
+                info->event = SPRITE_C_FLIP_DONE;
+                info->plane = SPRITE_PLANE;
+                break;
+
         default:
                 gvt_err("unknown plane code %d\n", plane);
                 return -EINVAL;
         }
 
-        info->pipe = PRIMARY_PLANE;
         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
         info->tile_val = (dword1 & GENMASK(2, 0));
         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
@@ -1525,9 +1542,6 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s)
 {
         struct intel_gvt *gvt = s->vgpu->gvt;
 
-        if (bypass_batch_buffer_scan)
-                return 0;
-
         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
                 /* BDW decides privilege based on address space */
                 if (cmd_val(s, 0) & (1 << 8))