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authorAlan Cox <alan@linux.intel.com>2012-03-08 11:02:05 -0500
committerDave Airlie <airlied@redhat.com>2012-03-10 08:05:44 -0500
commitc6265ff593467d472814aa9f16f89f6c1dc90a5d (patch)
tree2b1b8251a2ddedcbd31a1668f5ecd5a685628a90 /drivers/gpu/drm/gma500/psb_drv.h
parentc715bc1bf422543731b8833e899266b8be982a52 (diff)
gma500: rework register stuff sanely
Rework registers handling to prepare for Medfield. Signed-off-by: Alan Cox <alan@linux.intel.com> [split out from a single big patch] Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_drv.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index dee07e0d7c39..3c0bf7be2738 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -337,8 +337,6 @@ struct psb_state {
337 uint32_t savePFIT_CONTROL; 337 uint32_t savePFIT_CONTROL;
338 uint32_t savePaletteA[256]; 338 uint32_t savePaletteA[256];
339 uint32_t savePaletteB[256]; 339 uint32_t savePaletteB[256];
340 uint32_t saveBLC_PWM_CTL2;
341 uint32_t saveBLC_PWM_CTL;
342 uint32_t saveCLOCKGATING; 340 uint32_t saveCLOCKGATING;
343 uint32_t saveDSPARB; 341 uint32_t saveDSPARB;
344 uint32_t saveDSPATILEOFF; 342 uint32_t saveDSPATILEOFF;
@@ -350,8 +348,6 @@ struct psb_state {
350 uint32_t savePP_ON_DELAYS; 348 uint32_t savePP_ON_DELAYS;
351 uint32_t savePP_OFF_DELAYS; 349 uint32_t savePP_OFF_DELAYS;
352 uint32_t savePP_DIVISOR; 350 uint32_t savePP_DIVISOR;
353 uint32_t saveBSM;
354 uint32_t saveVBT;
355 uint32_t saveBCLRPAT_A; 351 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B; 352 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF; 353 uint32_t saveDSPALINOFF;
@@ -393,6 +389,16 @@ struct psb_state {
393 uint32_t savePWM_CONTROL_LOGIC; 389 uint32_t savePWM_CONTROL_LOGIC;
394}; 390};
395 391
392struct psb_save_area {
393 uint32_t saveBSM;
394 uint32_t saveVBT;
395 union {
396 struct psb_state psb;
397 };
398 uint32_t saveBLC_PWM_CTL2;
399 uint32_t saveBLC_PWM_CTL;
400};
401
396struct psb_ops; 402struct psb_ops;
397 403
398#define PSB_NUM_PIPE 3 404#define PSB_NUM_PIPE 3
@@ -520,7 +526,9 @@ struct drm_psb_private {
520 /* 526 /*
521 * Register state 527 * Register state
522 */ 528 */
523 struct psb_state regs; 529
530 struct psb_save_area regs;
531
524 /* MSI reg save */ 532 /* MSI reg save */
525 uint32_t msi_addr; 533 uint32_t msi_addr;
526 uint32_t msi_data; 534 uint32_t msi_data;