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authorAlan Cox <alan@linux.intel.com>2011-11-03 14:22:15 -0400
committerDave Airlie <airlied@redhat.com>2011-11-16 06:26:55 -0500
commit89c78134cc54dff016c83367912eb055637fa50c (patch)
tree2f0d9167e187726c47efabe9a4d7811f950d191c /drivers/gpu/drm/gma500/psb_device.c
parent5c49fd3aa0ab025e5f94617249db10a33138f37b (diff)
gma500: Add Poulsbo support
This provides the specific code for Poulsbo, some of which is also used for the later chipsets. We support the GTT, the 2D engine (for console), and the display setup/management. We do not support 3D or the video overlays. In theory enough public info is available to do the video overlay work but that represents a large task. Framebuffer X will run nicely with this but do *NOT* use the VESA X server at the same time as KMS. With a Dell mini 10 things like Xfce4 are nice and usable even when compositing as the CPU has a good path to the memory. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_device.c')
-rw-r--r--drivers/gpu/drm/gma500/psb_device.c353
1 files changed, 353 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c
new file mode 100644
index 000000000000..46591323595a
--- /dev/null
+++ b/drivers/gpu/drm/gma500/psb_device.c
@@ -0,0 +1,353 @@
1/**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#include <linux/backlight.h>
21#include <drm/drmP.h>
22#include <drm/drm.h>
23#include "psb_drm.h"
24#include "psb_drv.h"
25#include "psb_reg.h"
26#include "psb_intel_reg.h"
27#include "intel_bios.h"
28
29
30static int psb_output_init(struct drm_device *dev)
31{
32 struct drm_psb_private *dev_priv = dev->dev_private;
33 psb_intel_lvds_init(dev, &dev_priv->mode_dev);
34 psb_intel_sdvo_init(dev, SDVOB);
35 return 0;
36}
37
38#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
39
40/*
41 * Poulsbo Backlight Interfaces
42 */
43
44#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
45#define BLC_PWM_FREQ_CALC_CONSTANT 32
46#define MHz 1000000
47
48#define PSB_BLC_PWM_PRECISION_FACTOR 10
49#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
50#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
51
52#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
53#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
54
55static int psb_brightness;
56static struct backlight_device *psb_backlight_device;
57
58static int psb_get_brightness(struct backlight_device *bd)
59{
60 /* return locally cached var instead of HW read (due to DPST etc.) */
61 /* FIXME: ideally return actual value in case firmware fiddled with
62 it */
63 return psb_brightness;
64}
65
66
67static int psb_backlight_setup(struct drm_device *dev)
68{
69 struct drm_psb_private *dev_priv = dev->dev_private;
70 unsigned long core_clock;
71 /* u32 bl_max_freq; */
72 /* unsigned long value; */
73 u16 bl_max_freq;
74 uint32_t value;
75 uint32_t blc_pwm_precision_factor;
76
77 /* get bl_max_freq and pol from dev_priv*/
78 if (!dev_priv->lvds_bl) {
79 dev_err(dev->dev, "Has no valid LVDS backlight info\n");
80 return -ENOENT;
81 }
82 bl_max_freq = dev_priv->lvds_bl->freq;
83 blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
84
85 core_clock = dev_priv->core_freq;
86
87 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
88 value *= blc_pwm_precision_factor;
89 value /= bl_max_freq;
90 value /= blc_pwm_precision_factor;
91
92 if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
93 value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
94 return -ERANGE;
95 else {
96 value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
97 REG_WRITE(BLC_PWM_CTL,
98 (value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
99 }
100 return 0;
101}
102
103static int psb_set_brightness(struct backlight_device *bd)
104{
105 struct drm_device *dev = bl_get_data(psb_backlight_device);
106 int level = bd->props.brightness;
107
108 /* Percentage 1-100% being valid */
109 if (level < 1)
110 level = 1;
111
112 psb_intel_lvds_set_brightness(dev, level);
113 psb_brightness = level;
114 return 0;
115}
116
117static const struct backlight_ops psb_ops = {
118 .get_brightness = psb_get_brightness,
119 .update_status = psb_set_brightness,
120};
121
122static int psb_backlight_init(struct drm_device *dev)
123{
124 struct drm_psb_private *dev_priv = dev->dev_private;
125 int ret;
126 struct backlight_properties props;
127
128 memset(&props, 0, sizeof(struct backlight_properties));
129 props.max_brightness = 100;
130 props.type = BACKLIGHT_PLATFORM;
131
132 psb_backlight_device = backlight_device_register("psb-bl",
133 NULL, (void *)dev, &psb_ops, &props);
134 if (IS_ERR(psb_backlight_device))
135 return PTR_ERR(psb_backlight_device);
136
137 ret = psb_backlight_setup(dev);
138 if (ret < 0) {
139 backlight_device_unregister(psb_backlight_device);
140 psb_backlight_device = NULL;
141 return ret;
142 }
143 psb_backlight_device->props.brightness = 100;
144 psb_backlight_device->props.max_brightness = 100;
145 backlight_update_status(psb_backlight_device);
146 dev_priv->backlight_device = psb_backlight_device;
147 return 0;
148}
149
150#endif
151
152/*
153 * Provide the Poulsbo specific chip logic and low level methods
154 * for power management
155 */
156
157static void psb_init_pm(struct drm_device *dev)
158{
159 struct drm_psb_private *dev_priv = dev->dev_private;
160
161 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
162 gating &= ~3; /* Disable 2D clock gating */
163 gating |= 1;
164 PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
165 PSB_RSGX32(PSB_CR_CLKGATECTL);
166}
167
168/**
169 * psb_save_display_registers - save registers lost on suspend
170 * @dev: our DRM device
171 *
172 * Save the state we need in order to be able to restore the interface
173 * upon resume from suspend
174 */
175static int psb_save_display_registers(struct drm_device *dev)
176{
177 struct drm_psb_private *dev_priv = dev->dev_private;
178 struct drm_crtc *crtc;
179 struct drm_connector *connector;
180
181 /* Display arbitration control + watermarks */
182 dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
183 dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
184 dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
185 dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
186 dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
187 dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
188 dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
189 dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
190
191 /* Save crtc and output state */
192 mutex_lock(&dev->mode_config.mutex);
193 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
194 if (drm_helper_crtc_in_use(crtc))
195 crtc->funcs->save(crtc);
196 }
197
198 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
199 connector->funcs->save(connector);
200
201 mutex_unlock(&dev->mode_config.mutex);
202 return 0;
203}
204
205/**
206 * psb_restore_display_registers - restore lost register state
207 * @dev: our DRM device
208 *
209 * Restore register state that was lost during suspend and resume.
210 */
211static int psb_restore_display_registers(struct drm_device *dev)
212{
213 struct drm_psb_private *dev_priv = dev->dev_private;
214 struct drm_crtc *crtc;
215 struct drm_connector *connector;
216 int pp_stat;
217
218 /* Display arbitration + watermarks */
219 PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
220 PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
221 PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
222 PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
223 PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
224 PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
225 PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
226 PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
227
228 /*make sure VGA plane is off. it initializes to on after reset!*/
229 PSB_WVDC32(0x80000000, VGACNTRL);
230
231 mutex_lock(&dev->mode_config.mutex);
232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
233 if (drm_helper_crtc_in_use(crtc))
234 crtc->funcs->restore(crtc);
235
236 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
237 connector->funcs->restore(connector);
238
239 mutex_unlock(&dev->mode_config.mutex);
240
241 if (dev_priv->iLVDS_enable) {
242 /*shutdown the panel*/
243 PSB_WVDC32(0, PP_CONTROL);
244 do {
245 pp_stat = PSB_RVDC32(PP_STATUS);
246 } while (pp_stat & 0x80000000);
247
248 /* Turn off the plane */
249 PSB_WVDC32(0x58000000, DSPACNTR);
250 PSB_WVDC32(0, DSPASURF);/*trigger the plane disable*/
251 /* Wait ~4 ticks */
252 msleep(4);
253 /* Turn off pipe */
254 PSB_WVDC32(0x0, PIPEACONF);
255 /* Wait ~8 ticks */
256 msleep(8);
257
258 /* Turn off PLLs */
259 PSB_WVDC32(0, MRST_DPLL_A);
260 } else {
261 PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
262 PSB_WVDC32(0x0, PIPEACONF);
263 PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
264 while (REG_READ(0x70008) & 0x40000000)
265 cpu_relax();
266 while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
267 != DPI_FIFO_EMPTY)
268 cpu_relax();
269 PSB_WVDC32(0, DEVICE_READY_REG);
270 }
271 return 0;
272}
273
274static int psb_power_down(struct drm_device *dev)
275{
276 return 0;
277}
278
279static int psb_power_up(struct drm_device *dev)
280{
281 return 0;
282}
283
284static void psb_get_core_freq(struct drm_device *dev)
285{
286 uint32_t clock;
287 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
288 struct drm_psb_private *dev_priv = dev->dev_private;
289
290 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
291 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
292
293 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
294 pci_read_config_dword(pci_root, 0xD4, &clock);
295 pci_dev_put(pci_root);
296
297 switch (clock & 0x07) {
298 case 0:
299 dev_priv->core_freq = 100;
300 break;
301 case 1:
302 dev_priv->core_freq = 133;
303 break;
304 case 2:
305 dev_priv->core_freq = 150;
306 break;
307 case 3:
308 dev_priv->core_freq = 178;
309 break;
310 case 4:
311 dev_priv->core_freq = 200;
312 break;
313 case 5:
314 case 6:
315 case 7:
316 dev_priv->core_freq = 266;
317 default:
318 dev_priv->core_freq = 0;
319 }
320}
321
322static int psb_chip_setup(struct drm_device *dev)
323{
324 psb_get_core_freq(dev);
325 gma_intel_opregion_init(dev);
326 psb_intel_init_bios(dev);
327 return 0;
328}
329
330const struct psb_ops psb_chip_ops = {
331 .name = "Poulsbo",
332 .accel_2d = 1,
333 .pipes = 2,
334 .crtcs = 2,
335 .sgx_offset = PSB_SGX_OFFSET,
336 .chip_setup = psb_chip_setup,
337
338 .crtc_helper = &psb_intel_helper_funcs,
339 .crtc_funcs = &psb_intel_crtc_funcs,
340
341 .output_init = psb_output_init,
342
343#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
344 .backlight_init = psb_backlight_init,
345#endif
346
347 .init_pm = psb_init_pm,
348 .save_regs = psb_save_display_registers,
349 .restore_regs = psb_restore_display_registers,
350 .power_down = psb_power_down,
351 .power_up = psb_power_up,
352};
353