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authorMarek Szyprowski <m.szyprowski@samsung.com>2015-08-30 11:53:57 -0400
committerInki Dae <daeinki@gmail.com>2015-08-30 12:03:02 -0400
commitfbbb1e1a7f170cb560224d9694f1afd851bcf47f (patch)
treed907031af3ddb23dac04bfc8660a4fe5be8160fc /drivers/gpu/drm/exynos/exynos_mixer.c
parent74f230d2a7e36c27fde38db20ebfb7ddb9c4a116 (diff)
drm/exynos: Properly report supported formats for each device
Exynos DRM reported that all planes for all supported sub-devices supports only three pixel formats: XRGB24, ARGB24 and NV12. This patch lets each Exynos DRM sub-drivers to provide the list of supported pixel formats and registers this list to DRM core. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_mixer.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c30
1 files changed, 28 insertions, 2 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index d7e781153cff..7f81cce966d4 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -43,6 +43,7 @@
43 43
44#define MIXER_WIN_NR 3 44#define MIXER_WIN_NR 3
45#define MIXER_DEFAULT_WIN 0 45#define MIXER_DEFAULT_WIN 0
46#define VP_DEFAULT_WIN 2
46 47
47/* The pixelformats that are natively supported by the mixer. */ 48/* The pixelformats that are natively supported by the mixer. */
48#define MXR_FORMAT_RGB565 4 49#define MXR_FORMAT_RGB565 4
@@ -74,6 +75,19 @@ enum mixer_flag_bits {
74 MXR_BIT_VSYNC, 75 MXR_BIT_VSYNC,
75}; 76};
76 77
78static const uint32_t mixer_formats[] = {
79 DRM_FORMAT_XRGB4444,
80 DRM_FORMAT_XRGB1555,
81 DRM_FORMAT_RGB565,
82 DRM_FORMAT_XRGB8888,
83 DRM_FORMAT_ARGB8888,
84};
85
86static const uint32_t vp_formats[] = {
87 DRM_FORMAT_NV12,
88 DRM_FORMAT_NV21,
89};
90
77struct mixer_context { 91struct mixer_context {
78 struct platform_device *pdev; 92 struct platform_device *pdev;
79 struct device *dev; 93 struct device *dev;
@@ -1171,7 +1185,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
1171 struct mixer_context *ctx = dev_get_drvdata(dev); 1185 struct mixer_context *ctx = dev_get_drvdata(dev);
1172 struct drm_device *drm_dev = data; 1186 struct drm_device *drm_dev = data;
1173 struct exynos_drm_plane *exynos_plane; 1187 struct exynos_drm_plane *exynos_plane;
1174 enum drm_plane_type type;
1175 unsigned int zpos; 1188 unsigned int zpos;
1176 int ret; 1189 int ret;
1177 1190
@@ -1180,10 +1193,23 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
1180 return ret; 1193 return ret;
1181 1194
1182 for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) { 1195 for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) {
1196 enum drm_plane_type type;
1197 const uint32_t *formats;
1198 unsigned int fcount;
1199
1183 type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY : 1200 type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
1184 DRM_PLANE_TYPE_OVERLAY; 1201 DRM_PLANE_TYPE_OVERLAY;
1202 if (zpos < VP_DEFAULT_WIN) {
1203 formats = mixer_formats;
1204 fcount = ARRAY_SIZE(mixer_formats);
1205 } else {
1206 formats = vp_formats;
1207 fcount = ARRAY_SIZE(vp_formats);
1208 }
1209
1185 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 1210 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
1186 1 << ctx->pipe, type, zpos); 1211 1 << ctx->pipe, type, formats, fcount,
1212 zpos);
1187 if (ret) 1213 if (ret)
1188 return ret; 1214 return ret;
1189 } 1215 }