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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2017-08-01 15:00:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 18:16:40 -0400
commitfb3466a450cc4684654367ae2f47fc3fc7846574 (patch)
tree770a983af4307fc4d2120e133a9ccb17ea95c9bf /drivers/gpu/drm/amd
parent503a7c6f2518be909fa61276ee002846524b588b (diff)
drm/amd/display: Flattening core_dc to dc
-Flattening core_dc to dc Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c73
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c162
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_debug.c20
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c3
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c19
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c1
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_resource.c22
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_stream.c14
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_surface.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h71
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c9
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h6
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c22
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c72
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h12
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c26
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c26
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h10
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c18
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c46
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h8
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c1
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c108
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c34
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_dc.h55
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_types.h8
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h12
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h1
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h50
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/resource.h15
-rw-r--r--drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c6
-rw-r--r--drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c1
-rw-r--r--drivers/gpu/drm/amd/display/include/logger_interface.h10
-rw-r--r--drivers/gpu/drm/amd/display/modules/freesync/freesync.c11
51 files changed, 507 insertions, 527 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 6fb1b9a91993..f0dfd3c3c12c 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -27,7 +27,6 @@
27#include "dcn_calcs.h" 27#include "dcn_calcs.h"
28#include "dcn_calc_auto.h" 28#include "dcn_calc_auto.h"
29#include "dc.h" 29#include "dc.h"
30#include "core_dc.h"
31#include "dal_asic_id.h" 30#include "dal_asic_id.h"
32 31
33#include "resource.h" 32#include "resource.h"
@@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params (
399} 398}
400 399
401static void dcn_bw_calc_rq_dlg_ttu( 400static void dcn_bw_calc_rq_dlg_ttu(
402 const struct core_dc *dc, 401 const struct dc *dc,
403 const struct dcn_bw_internal_vars *v, 402 const struct dcn_bw_internal_vars *v,
404 struct pipe_ctx *pipe, 403 struct pipe_ctx *pipe,
405 int in_idx) 404 int in_idx)
@@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params(
674 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; 673 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
675} 674}
676 675
677static bool dcn_bw_apply_registry_override(struct core_dc *dc) 676static bool dcn_bw_apply_registry_override(struct dc *dc)
678{ 677{
679 bool updated = false; 678 bool updated = false;
680 679
681 kernel_fpu_begin(); 680 kernel_fpu_begin();
682 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns 681 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
683 && dc->public.debug.sr_exit_time_ns) { 682 && dc->debug.sr_exit_time_ns) {
684 updated = true; 683 updated = true;
685 dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; 684 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
686 } 685 }
687 686
688 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) 687 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
689 != dc->public.debug.sr_enter_plus_exit_time_ns 688 != dc->debug.sr_enter_plus_exit_time_ns
690 && dc->public.debug.sr_enter_plus_exit_time_ns) { 689 && dc->debug.sr_enter_plus_exit_time_ns) {
691 updated = true; 690 updated = true;
692 dc->dcn_soc->sr_enter_plus_exit_time = 691 dc->dcn_soc->sr_enter_plus_exit_time =
693 dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; 692 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
694 } 693 }
695 694
696 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns 695 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
697 && dc->public.debug.urgent_latency_ns) { 696 && dc->debug.urgent_latency_ns) {
698 updated = true; 697 updated = true;
699 dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; 698 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
700 } 699 }
701 700
702 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) 701 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
703 != dc->public.debug.percent_of_ideal_drambw 702 != dc->debug.percent_of_ideal_drambw
704 && dc->public.debug.percent_of_ideal_drambw) { 703 && dc->debug.percent_of_ideal_drambw) {
705 updated = true; 704 updated = true;
706 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = 705 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
707 dc->public.debug.percent_of_ideal_drambw; 706 dc->debug.percent_of_ideal_drambw;
708 } 707 }
709 708
710 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) 709 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
711 != dc->public.debug.dram_clock_change_latency_ns 710 != dc->debug.dram_clock_change_latency_ns
712 && dc->public.debug.dram_clock_change_latency_ns) { 711 && dc->debug.dram_clock_change_latency_ns) {
713 updated = true; 712 updated = true;
714 dc->dcn_soc->dram_clock_change_latency = 713 dc->dcn_soc->dram_clock_change_latency =
715 dc->public.debug.dram_clock_change_latency_ns / 1000.0; 714 dc->debug.dram_clock_change_latency_ns / 1000.0;
716 } 715 }
717 kernel_fpu_end(); 716 kernel_fpu_end();
718 717
@@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc)
720} 719}
721 720
722bool dcn_validate_bandwidth( 721bool dcn_validate_bandwidth(
723 const struct core_dc *dc, 722 struct dc *dc,
724 struct validate_context *context) 723 struct validate_context *context)
725{ 724{
726 const struct resource_pool *pool = dc->res_pool; 725 const struct resource_pool *pool = dc->res_pool;
@@ -730,8 +729,8 @@ bool dcn_validate_bandwidth(
730 bool bw_limit_pass; 729 bool bw_limit_pass;
731 float bw_limit; 730 float bw_limit;
732 731
733 if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) 732 if (dcn_bw_apply_registry_override(dc))
734 dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); 733 dcn_bw_sync_calcs_and_dml(dc);
735 734
736 memset(v, 0, sizeof(*v)); 735 memset(v, 0, sizeof(*v));
737 kernel_fpu_begin(); 736 kernel_fpu_begin();
@@ -850,7 +849,7 @@ bool dcn_validate_bandwidth(
850 v->phyclk_per_state[1] = v->phyclkv_mid0p72; 849 v->phyclk_per_state[1] = v->phyclkv_mid0p72;
851 v->phyclk_per_state[0] = v->phyclkv_min0p65; 850 v->phyclk_per_state[0] = v->phyclkv_min0p65;
852 851
853 if (dc->public.debug.disable_pipe_split) { 852 if (dc->debug.disable_pipe_split) {
854 v->max_dispclk[0] = v->max_dppclk_vmin0p65; 853 v->max_dispclk[0] = v->max_dppclk_vmin0p65;
855 } 854 }
856 855
@@ -982,15 +981,15 @@ bool dcn_validate_bandwidth(
982 mode_support_and_system_configuration(v); 981 mode_support_and_system_configuration(v);
983 982
984 if (v->voltage_level == 0 && 983 if (v->voltage_level == 0 &&
985 (dc->public.debug.sr_exit_time_dpm0_ns 984 (dc->debug.sr_exit_time_dpm0_ns
986 || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) { 985 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
987 struct core_dc *dc_core = DC_TO_CORE(&dc->public); 986 struct dc *dc_core = dc;
988 987
989 if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns) 988 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
990 v->sr_enter_plus_exit_time = 989 v->sr_enter_plus_exit_time =
991 dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; 990 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
992 if (dc->public.debug.sr_exit_time_dpm0_ns) 991 if (dc->debug.sr_exit_time_dpm0_ns)
993 v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f; 992 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
994 dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; 993 dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
995 dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; 994 dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
996 mode_support_and_system_configuration(v); 995 mode_support_and_system_configuration(v);
@@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth(
1020 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); 1019 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1021 context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); 1020 context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1022 context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); 1021 context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
1023 if (dc->public.debug.max_disp_clk == true) 1022 if (dc->debug.max_disp_clk == true)
1024 context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); 1023 context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1025 context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; 1024 context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
1026 1025
@@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth(
1109 1108
1110 input_idx++; 1109 input_idx++;
1111 } 1110 }
1112 if (dc->public.debug.use_dml_wm) 1111 if (dc->debug.use_dml_wm)
1113 dcn_dml_wm_override(v, (struct display_mode_lib *) 1112 dcn_dml_wm_override(v, (struct display_mode_lib *)
1114 &dc->dml, context, pool); 1113 &dc->dml, context, pool);
1115 } 1114 }
1116 1115
1117 if (v->voltage_level == 0) { 1116 if (v->voltage_level == 0) {
1118 struct core_dc *dc_core = DC_TO_CORE(&dc->public); 1117 struct dc *dc_core = dc;
1119 1118
1120 dc_core->dml.soc.sr_enter_plus_exit_time_us = 1119 dc_core->dml.soc.sr_enter_plus_exit_time_us =
1121 dc_core->dcn_soc->sr_enter_plus_exit_time; 1120 dc_core->dcn_soc->sr_enter_plus_exit_time;
@@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth(
1138} 1137}
1139 1138
1140unsigned int dcn_find_normalized_clock_vdd_Level( 1139unsigned int dcn_find_normalized_clock_vdd_Level(
1141 const struct core_dc *dc, 1140 const struct dc *dc,
1142 enum dm_pp_clock_type clocks_type, 1141 enum dm_pp_clock_type clocks_type,
1143 int clocks_in_khz) 1142 int clocks_in_khz)
1144{ 1143{
@@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level(
1228} 1227}
1229 1228
1230unsigned int dcn_find_dcfclk_suits_all( 1229unsigned int dcn_find_dcfclk_suits_all(
1231 const struct core_dc *dc, 1230 const struct dc *dc,
1232 struct clocks_value *clocks) 1231 struct clocks_value *clocks)
1233{ 1232{
1234 unsigned vdd_level, vdd_level_temp; 1233 unsigned vdd_level, vdd_level_temp;
@@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all(
1270 return dcf_clk; 1269 return dcf_clk;
1271} 1270}
1272 1271
1273void dcn_bw_update_from_pplib(struct core_dc *dc) 1272void dcn_bw_update_from_pplib(struct dc *dc)
1274{ 1273{
1275 struct dc_context *ctx = dc->ctx; 1274 struct dc_context *ctx = dc->ctx;
1276 struct dm_pp_clock_levels_with_voltage clks = {0}; 1275 struct dm_pp_clock_levels_with_voltage clks = {0};
@@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
1310 kernel_fpu_end(); 1309 kernel_fpu_end();
1311} 1310}
1312 1311
1313void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) 1312void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1314{ 1313{
1315 struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0}; 1314 struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0};
1316 int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, 1315 int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz,
@@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
1388 dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges); 1387 dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges);
1389} 1388}
1390 1389
1391void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) 1390void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1392{ 1391{
1393 kernel_fpu_begin(); 1392 kernel_fpu_begin();
1394 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, 1393 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 40d65b758994..44c7b52e4a00 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -35,7 +35,6 @@
35#include "clock_source.h" 35#include "clock_source.h"
36#include "dc_bios_types.h" 36#include "dc_bios_types.h"
37 37
38#include "dce_calcs.h"
39#include "bios_parser_interface.h" 38#include "bios_parser_interface.h"
40#include "include/irq_service_interface.h" 39#include "include/irq_service_interface.h"
41#include "transform.h" 40#include "transform.h"
@@ -52,7 +51,7 @@
52/******************************************************************************* 51/*******************************************************************************
53 * Private functions 52 * Private functions
54 ******************************************************************************/ 53 ******************************************************************************/
55static void destroy_links(struct core_dc *dc) 54static void destroy_links(struct dc *dc)
56{ 55{
57 uint32_t i; 56 uint32_t i;
58 57
@@ -63,7 +62,7 @@ static void destroy_links(struct core_dc *dc)
63} 62}
64 63
65static bool create_links( 64static bool create_links(
66 struct core_dc *dc, 65 struct dc *dc,
67 uint32_t num_virtual_links) 66 uint32_t num_virtual_links)
68{ 67{
69 int i; 68 int i;
@@ -153,7 +152,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc,
153 int vmin, int vmax) 152 int vmin, int vmax)
154{ 153{
155 /* TODO: Support multiple streams */ 154 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc); 155 struct dc *core_dc = dc;
157 struct dc_stream_state *stream = streams[0]; 156 struct dc_stream_state *stream = streams[0];
158 int i = 0; 157 int i = 0;
159 bool ret = false; 158 bool ret = false;
@@ -179,7 +178,7 @@ static bool stream_get_crtc_position(struct dc *dc,
179 unsigned int *v_pos, unsigned int *nom_v_pos) 178 unsigned int *v_pos, unsigned int *nom_v_pos)
180{ 179{
181 /* TODO: Support multiple streams */ 180 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc); 181 struct dc *core_dc = dc;
183 struct dc_stream_state *stream = streams[0]; 182 struct dc_stream_state *stream = streams[0];
184 int i = 0; 183 int i = 0;
185 bool ret = false; 184 bool ret = false;
@@ -202,7 +201,7 @@ static bool stream_get_crtc_position(struct dc *dc,
202 201
203static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) 202static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
204{ 203{
205 struct core_dc *core_dc = DC_TO_CORE(dc); 204 struct dc *core_dc = dc;
206 int i = 0; 205 int i = 0;
207 bool ret = false; 206 bool ret = false;
208 struct pipe_ctx *pipes; 207 struct pipe_ctx *pipes;
@@ -220,7 +219,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
220 219
221static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) 220static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
222{ 221{
223 struct core_dc *core_dc = DC_TO_CORE(dc); 222 struct dc *core_dc = dc;
224 int i = 0; 223 int i = 0;
225 bool ret = false; 224 bool ret = false;
226 struct pipe_ctx *pipes; 225 struct pipe_ctx *pipes;
@@ -245,7 +244,7 @@ static void set_static_screen_events(struct dc *dc,
245 int num_streams, 244 int num_streams,
246 const struct dc_static_screen_events *events) 245 const struct dc_static_screen_events *events)
247{ 246{
248 struct core_dc *core_dc = DC_TO_CORE(dc); 247 struct dc *core_dc = dc;
249 int i = 0; 248 int i = 0;
250 int j = 0; 249 int j = 0;
251 struct pipe_ctx *pipes_affected[MAX_PIPES]; 250 struct pipe_ctx *pipes_affected[MAX_PIPES];
@@ -270,7 +269,7 @@ static void set_drive_settings(struct dc *dc,
270 struct link_training_settings *lt_settings, 269 struct link_training_settings *lt_settings,
271 const struct dc_link *link) 270 const struct dc_link *link)
272{ 271{
273 struct core_dc *core_dc = DC_TO_CORE(dc); 272 struct dc *core_dc = dc;
274 int i; 273 int i;
275 274
276 for (i = 0; i < core_dc->link_count; i++) { 275 for (i = 0; i < core_dc->link_count; i++) {
@@ -288,7 +287,7 @@ static void perform_link_training(struct dc *dc,
288 struct dc_link_settings *link_setting, 287 struct dc_link_settings *link_setting,
289 bool skip_video_pattern) 288 bool skip_video_pattern)
290{ 289{
291 struct core_dc *core_dc = DC_TO_CORE(dc); 290 struct dc *core_dc = dc;
292 int i; 291 int i;
293 292
294 for (i = 0; i < core_dc->link_count; i++) 293 for (i = 0; i < core_dc->link_count; i++)
@@ -369,48 +368,48 @@ void set_dither_option(struct dc_stream_state *stream,
369 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params); 368 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
370} 369}
371 370
372static void allocate_dc_stream_funcs(struct core_dc *core_dc) 371static void allocate_dc_stream_funcs(struct dc *core_dc)
373{ 372{
374 if (core_dc->hwss.set_drr != NULL) { 373 if (core_dc->hwss.set_drr != NULL) {
375 core_dc->public.stream_funcs.adjust_vmin_vmax = 374 core_dc->stream_funcs.adjust_vmin_vmax =
376 stream_adjust_vmin_vmax; 375 stream_adjust_vmin_vmax;
377 } 376 }
378 377
379 core_dc->public.stream_funcs.set_static_screen_events = 378 core_dc->stream_funcs.set_static_screen_events =
380 set_static_screen_events; 379 set_static_screen_events;
381 380
382 core_dc->public.stream_funcs.get_crtc_position = 381 core_dc->stream_funcs.get_crtc_position =
383 stream_get_crtc_position; 382 stream_get_crtc_position;
384 383
385 core_dc->public.stream_funcs.set_gamut_remap = 384 core_dc->stream_funcs.set_gamut_remap =
386 set_gamut_remap; 385 set_gamut_remap;
387 386
388 core_dc->public.stream_funcs.program_csc_matrix = 387 core_dc->stream_funcs.program_csc_matrix =
389 program_csc_matrix; 388 program_csc_matrix;
390 389
391 core_dc->public.stream_funcs.set_dither_option = 390 core_dc->stream_funcs.set_dither_option =
392 set_dither_option; 391 set_dither_option;
393 392
394 core_dc->public.link_funcs.set_drive_settings = 393 core_dc->link_funcs.set_drive_settings =
395 set_drive_settings; 394 set_drive_settings;
396 395
397 core_dc->public.link_funcs.perform_link_training = 396 core_dc->link_funcs.perform_link_training =
398 perform_link_training; 397 perform_link_training;
399 398
400 core_dc->public.link_funcs.set_preferred_link_settings = 399 core_dc->link_funcs.set_preferred_link_settings =
401 set_preferred_link_settings; 400 set_preferred_link_settings;
402 401
403 core_dc->public.link_funcs.enable_hpd = 402 core_dc->link_funcs.enable_hpd =
404 enable_hpd; 403 enable_hpd;
405 404
406 core_dc->public.link_funcs.disable_hpd = 405 core_dc->link_funcs.disable_hpd =
407 disable_hpd; 406 disable_hpd;
408 407
409 core_dc->public.link_funcs.set_test_pattern = 408 core_dc->link_funcs.set_test_pattern =
410 set_test_pattern; 409 set_test_pattern;
411} 410}
412 411
413static void destruct(struct core_dc *dc) 412static void destruct(struct dc *dc)
414{ 413{
415 dc_release_validate_context(dc->current_context); 414 dc_release_validate_context(dc->current_context);
416 dc->current_context = NULL; 415 dc->current_context = NULL;
@@ -446,10 +445,11 @@ static void destruct(struct core_dc *dc)
446 445
447 dm_free(dc->dcn_ip); 446 dm_free(dc->dcn_ip);
448 dc->dcn_ip = NULL; 447 dc->dcn_ip = NULL;
448
449#endif 449#endif
450} 450}
451 451
452static bool construct(struct core_dc *dc, 452static bool construct(struct dc *dc,
453 const struct dc_init_data *init_params) 453 const struct dc_init_data *init_params)
454{ 454{
455 struct dal_logger *logger; 455 struct dal_logger *logger;
@@ -508,7 +508,7 @@ static bool construct(struct core_dc *dc,
508 508
509 dc_ctx->cgs_device = init_params->cgs_device; 509 dc_ctx->cgs_device = init_params->cgs_device;
510 dc_ctx->driver_context = init_params->driver; 510 dc_ctx->driver_context = init_params->driver;
511 dc_ctx->dc = &dc->public; 511 dc_ctx->dc = dc;
512 dc_ctx->asic_id = init_params->asic_id; 512 dc_ctx->asic_id = init_params->asic_id;
513 513
514 /* Create logger */ 514 /* Create logger */
@@ -621,7 +621,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz )
621 621
622struct dc *dc_create(const struct dc_init_data *init_params) 622struct dc *dc_create(const struct dc_init_data *init_params)
623 { 623 {
624 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); 624 struct dc *core_dc = dm_alloc(sizeof(*core_dc));
625 unsigned int full_pipe_count; 625 unsigned int full_pipe_count;
626 626
627 if (NULL == core_dc) 627 if (NULL == core_dc)
@@ -636,23 +636,23 @@ struct dc *dc_create(const struct dc_init_data *init_params)
636 full_pipe_count = core_dc->res_pool->pipe_count; 636 full_pipe_count = core_dc->res_pool->pipe_count;
637 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) 637 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
638 full_pipe_count--; 638 full_pipe_count--;
639 core_dc->public.caps.max_streams = min( 639 core_dc->caps.max_streams = min(
640 full_pipe_count, 640 full_pipe_count,
641 core_dc->res_pool->stream_enc_count); 641 core_dc->res_pool->stream_enc_count);
642 642
643 core_dc->public.caps.max_links = core_dc->link_count; 643 core_dc->caps.max_links = core_dc->link_count;
644 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; 644 core_dc->caps.max_audios = core_dc->res_pool->audio_count;
645 645
646 core_dc->public.config = init_params->flags; 646 core_dc->config = init_params->flags;
647 647
648 dm_logger_write(core_dc->ctx->logger, LOG_DC, 648 dm_logger_write(core_dc->ctx->logger, LOG_DC,
649 "Display Core initialized\n"); 649 "Display Core initialized\n");
650 650
651 651
652 /* TODO: missing feature to be enabled */ 652 /* TODO: missing feature to be enabled */
653 core_dc->public.debug.disable_dfs_bypass = true; 653 core_dc->debug.disable_dfs_bypass = true;
654 654
655 return &core_dc->public; 655 return core_dc;
656 656
657construct_fail: 657construct_fail:
658 dm_free(core_dc); 658 dm_free(core_dc);
@@ -663,14 +663,14 @@ alloc_fail:
663 663
664void dc_destroy(struct dc **dc) 664void dc_destroy(struct dc **dc)
665{ 665{
666 struct core_dc *core_dc = DC_TO_CORE(*dc); 666 struct dc *core_dc = *dc;
667 destruct(core_dc); 667 destruct(core_dc);
668 dm_free(core_dc); 668 dm_free(core_dc);
669 *dc = NULL; 669 *dc = NULL;
670} 670}
671 671
672static bool is_validation_required( 672static bool is_validation_required(
673 const struct core_dc *dc, 673 const struct dc *dc,
674 const struct dc_validation_set set[], 674 const struct dc_validation_set set[],
675 int set_count) 675 int set_count)
676{ 676{
@@ -705,7 +705,7 @@ static bool is_validation_required(
705} 705}
706 706
707static bool validate_streams ( 707static bool validate_streams (
708 const struct dc *dc, 708 struct dc *dc,
709 const struct dc_validation_set set[], 709 const struct dc_validation_set set[],
710 int set_count) 710 int set_count)
711{ 711{
@@ -719,7 +719,7 @@ static bool validate_streams (
719} 719}
720 720
721static bool validate_surfaces( 721static bool validate_surfaces(
722 const struct dc *dc, 722 struct dc *dc,
723 const struct dc_validation_set set[], 723 const struct dc_validation_set set[],
724 int set_count) 724 int set_count)
725{ 725{
@@ -734,11 +734,11 @@ static bool validate_surfaces(
734} 734}
735 735
736struct validate_context *dc_get_validate_context( 736struct validate_context *dc_get_validate_context(
737 const struct dc *dc, 737 struct dc *dc,
738 const struct dc_validation_set set[], 738 const struct dc_validation_set set[],
739 uint8_t set_count) 739 uint8_t set_count)
740{ 740{
741 struct core_dc *core_dc = DC_TO_CORE(dc); 741 struct dc *core_dc = dc;
742 enum dc_status result = DC_ERROR_UNEXPECTED; 742 enum dc_status result = DC_ERROR_UNEXPECTED;
743 struct validate_context *context; 743 struct validate_context *context;
744 744
@@ -773,11 +773,11 @@ context_alloc_fail:
773} 773}
774 774
775bool dc_validate_resources( 775bool dc_validate_resources(
776 const struct dc *dc, 776 struct dc *dc,
777 const struct dc_validation_set set[], 777 const struct dc_validation_set set[],
778 uint8_t set_count) 778 uint8_t set_count)
779{ 779{
780 struct core_dc *core_dc = DC_TO_CORE(dc); 780 struct dc *core_dc = dc;
781 enum dc_status result = DC_ERROR_UNEXPECTED; 781 enum dc_status result = DC_ERROR_UNEXPECTED;
782 struct validate_context *context; 782 struct validate_context *context;
783 783
@@ -811,10 +811,10 @@ context_alloc_fail:
811} 811}
812 812
813bool dc_validate_guaranteed( 813bool dc_validate_guaranteed(
814 const struct dc *dc, 814 struct dc *dc,
815 struct dc_stream_state *stream) 815 struct dc_stream_state *stream)
816{ 816{
817 struct core_dc *core_dc = DC_TO_CORE(dc); 817 struct dc *core_dc = dc;
818 enum dc_status result = DC_ERROR_UNEXPECTED; 818 enum dc_status result = DC_ERROR_UNEXPECTED;
819 struct validate_context *context; 819 struct validate_context *context;
820 820
@@ -844,7 +844,7 @@ context_alloc_fail:
844} 844}
845 845
846static void program_timing_sync( 846static void program_timing_sync(
847 struct core_dc *core_dc, 847 struct dc *core_dc,
848 struct validate_context *ctx) 848 struct validate_context *ctx)
849{ 849{
850 int i, j; 850 int i, j;
@@ -918,7 +918,7 @@ static void program_timing_sync(
918} 918}
919 919
920static bool context_changed( 920static bool context_changed(
921 struct core_dc *dc, 921 struct dc *dc,
922 struct validate_context *context) 922 struct validate_context *context)
923{ 923{
924 uint8_t i; 924 uint8_t i;
@@ -935,7 +935,7 @@ static bool context_changed(
935} 935}
936 936
937static bool streams_changed( 937static bool streams_changed(
938 struct core_dc *dc, 938 struct dc *dc,
939 struct dc_stream_state *streams[], 939 struct dc_stream_state *streams[],
940 uint8_t stream_count) 940 uint8_t stream_count)
941{ 941{
@@ -961,7 +961,7 @@ bool dc_enable_stereo(
961 bool ret = true; 961 bool ret = true;
962 int i, j; 962 int i, j;
963 struct pipe_ctx *pipe; 963 struct pipe_ctx *pipe;
964 struct core_dc *core_dc = DC_TO_CORE(dc); 964 struct dc *core_dc = dc;
965 965
966#ifdef ENABLE_FBC 966#ifdef ENABLE_FBC
967 struct compressor *fbc_compressor = core_dc->fbc_compressor; 967 struct compressor *fbc_compressor = core_dc->fbc_compressor;
@@ -996,7 +996,7 @@ bool dc_enable_stereo(
996 */ 996 */
997static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) 997static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
998{ 998{
999 struct core_dc *core_dc = DC_TO_CORE(dc); 999 struct dc *core_dc = dc;
1000 struct dc_bios *dcb = core_dc->ctx->dc_bios; 1000 struct dc_bios *dcb = core_dc->ctx->dc_bios;
1001 enum dc_status result = DC_ERROR_UNEXPECTED; 1001 enum dc_status result = DC_ERROR_UNEXPECTED;
1002 struct pipe_ctx *pipe; 1002 struct pipe_ctx *pipe;
@@ -1064,7 +1064,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c
1064bool dc_commit_context(struct dc *dc, struct validate_context *context) 1064bool dc_commit_context(struct dc *dc, struct validate_context *context)
1065{ 1065{
1066 enum dc_status result = DC_ERROR_UNEXPECTED; 1066 enum dc_status result = DC_ERROR_UNEXPECTED;
1067 struct core_dc *core_dc = DC_TO_CORE(dc); 1067 struct dc *core_dc = dc;
1068 int i; 1068 int i;
1069 1069
1070 if (false == context_changed(core_dc, context)) 1070 if (false == context_changed(core_dc, context))
@@ -1092,7 +1092,7 @@ bool dc_commit_streams(
1092 struct dc_stream_state *streams[], 1092 struct dc_stream_state *streams[],
1093 uint8_t stream_count) 1093 uint8_t stream_count)
1094{ 1094{
1095 struct core_dc *core_dc = DC_TO_CORE(dc); 1095 struct dc *core_dc = dc;
1096 enum dc_status result = DC_ERROR_UNEXPECTED; 1096 enum dc_status result = DC_ERROR_UNEXPECTED;
1097 struct validate_context *context; 1097 struct validate_context *context;
1098 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; 1098 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
@@ -1158,7 +1158,7 @@ context_alloc_fail:
1158bool dc_post_update_surfaces_to_stream(struct dc *dc) 1158bool dc_post_update_surfaces_to_stream(struct dc *dc)
1159{ 1159{
1160 int i; 1160 int i;
1161 struct core_dc *core_dc = DC_TO_CORE(dc); 1161 struct dc *core_dc = dc;
1162 struct validate_context *context = core_dc->current_context; 1162 struct validate_context *context = core_dc->current_context;
1163 1163
1164 post_surface_trace(dc); 1164 post_surface_trace(dc);
@@ -1375,7 +1375,7 @@ static enum surface_update_type get_scaling_info_update_type(
1375} 1375}
1376 1376
1377static enum surface_update_type det_surface_update( 1377static enum surface_update_type det_surface_update(
1378 const struct core_dc *dc, 1378 const struct dc *dc,
1379 const struct dc_surface_update *u, 1379 const struct dc_surface_update *u,
1380 int surface_index) 1380 int surface_index)
1381{ 1381{
@@ -1410,7 +1410,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
1410 struct dc_stream_update *stream_update, 1410 struct dc_stream_update *stream_update,
1411 const struct dc_stream_status *stream_status) 1411 const struct dc_stream_status *stream_status)
1412{ 1412{
1413 struct core_dc *core_dc = DC_TO_CORE(dc); 1413 struct dc *core_dc = dc;
1414 int i; 1414 int i;
1415 enum surface_update_type overall_type = UPDATE_TYPE_FAST; 1415 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1416 1416
@@ -1456,7 +1456,7 @@ void dc_update_planes_and_stream(struct dc *dc,
1456 struct dc_stream_state *stream, 1456 struct dc_stream_state *stream,
1457 struct dc_stream_update *stream_update) 1457 struct dc_stream_update *stream_update)
1458{ 1458{
1459 struct core_dc *core_dc = DC_TO_CORE(dc); 1459 struct dc *core_dc = dc;
1460 struct validate_context *context; 1460 struct validate_context *context;
1461 int i, j; 1461 int i, j;
1462 enum surface_update_type update_type; 1462 enum surface_update_type update_type;
@@ -1781,29 +1781,29 @@ context_alloc_fail:
1781 DC_ERROR("Failed to allocate new validate context!\n"); 1781 DC_ERROR("Failed to allocate new validate context!\n");
1782} 1782}
1783 1783
1784uint8_t dc_get_current_stream_count(const struct dc *dc) 1784uint8_t dc_get_current_stream_count(struct dc *dc)
1785{ 1785{
1786 struct core_dc *core_dc = DC_TO_CORE(dc); 1786 struct dc *core_dc = dc;
1787 return core_dc->current_context->stream_count; 1787 return core_dc->current_context->stream_count;
1788} 1788}
1789 1789
1790struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) 1790struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
1791{ 1791{
1792 struct core_dc *core_dc = DC_TO_CORE(dc); 1792 struct dc *core_dc = dc;
1793 if (i < core_dc->current_context->stream_count) 1793 if (i < core_dc->current_context->stream_count)
1794 return core_dc->current_context->streams[i]; 1794 return core_dc->current_context->streams[i];
1795 return NULL; 1795 return NULL;
1796} 1796}
1797 1797
1798struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) 1798struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
1799{ 1799{
1800 struct core_dc *core_dc = DC_TO_CORE(dc); 1800 struct dc *core_dc = dc;
1801 return core_dc->links[link_index]; 1801 return core_dc->links[link_index];
1802} 1802}
1803 1803
1804struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) 1804struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe)
1805{ 1805{
1806 struct core_dc *core_dc = DC_TO_CORE(dc); 1806 struct dc *core_dc = dc;
1807 if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { 1807 if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) {
1808 return core_dc->res_pool->dwbc[(int)pipe]; 1808 return core_dc->res_pool->dwbc[(int)pipe];
1809 } else { 1809 } else {
@@ -1814,20 +1814,20 @@ struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe)
1814const struct graphics_object_id dc_get_link_id_at_index( 1814const struct graphics_object_id dc_get_link_id_at_index(
1815 struct dc *dc, uint32_t link_index) 1815 struct dc *dc, uint32_t link_index)
1816{ 1816{
1817 struct core_dc *core_dc = DC_TO_CORE(dc); 1817 struct dc *core_dc = dc;
1818 return core_dc->links[link_index]->link_id; 1818 return core_dc->links[link_index]->link_id;
1819} 1819}
1820 1820
1821enum dc_irq_source dc_get_hpd_irq_source_at_index( 1821enum dc_irq_source dc_get_hpd_irq_source_at_index(
1822 struct dc *dc, uint32_t link_index) 1822 struct dc *dc, uint32_t link_index)
1823{ 1823{
1824 struct core_dc *core_dc = DC_TO_CORE(dc); 1824 struct dc *core_dc = dc;
1825 return core_dc->links[link_index]->irq_source_hpd; 1825 return core_dc->links[link_index]->irq_source_hpd;
1826} 1826}
1827 1827
1828const struct audio **dc_get_audios(struct dc *dc) 1828const struct audio **dc_get_audios(struct dc *dc)
1829{ 1829{
1830 struct core_dc *core_dc = DC_TO_CORE(dc); 1830 struct dc *core_dc = dc;
1831 return (const struct audio **)core_dc->res_pool->audios; 1831 return (const struct audio **)core_dc->res_pool->audios;
1832} 1832}
1833 1833
@@ -1836,24 +1836,24 @@ enum dc_irq_source dc_interrupt_to_irq_source(
1836 uint32_t src_id, 1836 uint32_t src_id,
1837 uint32_t ext_id) 1837 uint32_t ext_id)
1838{ 1838{
1839 struct core_dc *core_dc = DC_TO_CORE(dc); 1839 struct dc *core_dc = dc;
1840 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); 1840 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1841} 1841}
1842 1842
1843void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) 1843void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1844{ 1844{
1845 struct core_dc *core_dc; 1845 struct dc *core_dc;
1846 1846
1847 if (dc == NULL) 1847 if (dc == NULL)
1848 return; 1848 return;
1849 core_dc = DC_TO_CORE(dc); 1849 core_dc = dc;
1850 1850
1851 dal_irq_service_set(core_dc->res_pool->irqs, src, enable); 1851 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1852} 1852}
1853 1853
1854void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) 1854void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1855{ 1855{
1856 struct core_dc *core_dc = DC_TO_CORE(dc); 1856 struct dc *core_dc = dc;
1857 dal_irq_service_ack(core_dc->res_pool->irqs, src); 1857 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1858} 1858}
1859 1859
@@ -1861,7 +1861,7 @@ void dc_set_power_state(
1861 struct dc *dc, 1861 struct dc *dc,
1862 enum dc_acpi_cm_power_state power_state) 1862 enum dc_acpi_cm_power_state power_state)
1863{ 1863{
1864 struct core_dc *core_dc = DC_TO_CORE(dc); 1864 struct dc *core_dc = dc;
1865 atomic_t ref_count; 1865 atomic_t ref_count;
1866 1866
1867 switch (power_state) { 1867 switch (power_state) {
@@ -1889,9 +1889,9 @@ void dc_set_power_state(
1889 1889
1890} 1890}
1891 1891
1892void dc_resume(const struct dc *dc) 1892void dc_resume(struct dc *dc)
1893{ 1893{
1894 struct core_dc *core_dc = DC_TO_CORE(dc); 1894 struct dc *core_dc = dc;
1895 1895
1896 uint32_t i; 1896 uint32_t i;
1897 1897
@@ -1906,7 +1906,7 @@ bool dc_read_aux_dpcd(
1906 uint8_t *data, 1906 uint8_t *data,
1907 uint32_t size) 1907 uint32_t size)
1908{ 1908{
1909 struct core_dc *core_dc = DC_TO_CORE(dc); 1909 struct dc *core_dc = dc;
1910 1910
1911 struct dc_link *link = core_dc->links[link_index]; 1911 struct dc_link *link = core_dc->links[link_index];
1912 enum ddc_result r = dal_ddc_service_read_dpcd_data( 1912 enum ddc_result r = dal_ddc_service_read_dpcd_data(
@@ -1926,7 +1926,7 @@ bool dc_write_aux_dpcd(
1926 const uint8_t *data, 1926 const uint8_t *data,
1927 uint32_t size) 1927 uint32_t size)
1928{ 1928{
1929 struct core_dc *core_dc = DC_TO_CORE(dc); 1929 struct dc *core_dc = dc;
1930 struct dc_link *link = core_dc->links[link_index]; 1930 struct dc_link *link = core_dc->links[link_index];
1931 1931
1932 enum ddc_result r = dal_ddc_service_write_dpcd_data( 1932 enum ddc_result r = dal_ddc_service_write_dpcd_data(
@@ -1947,7 +1947,7 @@ bool dc_read_aux_i2c(
1947 uint8_t *data, 1947 uint8_t *data,
1948 uint32_t size) 1948 uint32_t size)
1949{ 1949{
1950 struct core_dc *core_dc = DC_TO_CORE(dc); 1950 struct dc *core_dc = dc;
1951 1951
1952 struct dc_link *link = core_dc->links[link_index]; 1952 struct dc_link *link = core_dc->links[link_index];
1953 enum ddc_result r = dal_ddc_service_read_dpcd_data( 1953 enum ddc_result r = dal_ddc_service_read_dpcd_data(
@@ -1968,7 +1968,7 @@ bool dc_write_aux_i2c(
1968 const uint8_t *data, 1968 const uint8_t *data,
1969 uint32_t size) 1969 uint32_t size)
1970{ 1970{
1971 struct core_dc *core_dc = DC_TO_CORE(dc); 1971 struct dc *core_dc = dc;
1972 struct dc_link *link = core_dc->links[link_index]; 1972 struct dc_link *link = core_dc->links[link_index];
1973 1973
1974 enum ddc_result r = dal_ddc_service_write_dpcd_data( 1974 enum ddc_result r = dal_ddc_service_write_dpcd_data(
@@ -1990,7 +1990,7 @@ bool dc_query_ddc_data(
1990 uint8_t *read_buf, 1990 uint8_t *read_buf,
1991 uint32_t read_size) { 1991 uint32_t read_size) {
1992 1992
1993 struct core_dc *core_dc = DC_TO_CORE(dc); 1993 struct dc *core_dc = dc;
1994 1994
1995 struct dc_link *link = core_dc->links[link_index]; 1995 struct dc_link *link = core_dc->links[link_index];
1996 1996
@@ -2010,7 +2010,7 @@ bool dc_submit_i2c(
2010 uint32_t link_index, 2010 uint32_t link_index,
2011 struct i2c_command *cmd) 2011 struct i2c_command *cmd)
2012{ 2012{
2013 struct core_dc *core_dc = DC_TO_CORE(dc); 2013 struct dc *core_dc = dc;
2014 2014
2015 struct dc_link *link = core_dc->links[link_index]; 2015 struct dc_link *link = core_dc->links[link_index];
2016 struct ddc_service *ddc = link->ddc; 2016 struct ddc_service *ddc = link->ddc;
@@ -2129,7 +2129,7 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2129bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) 2129bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2130{ 2130{
2131 int i; 2131 int i;
2132 struct core_dc *core_dc = DC_TO_CORE(dc); 2132 struct dc *core_dc = dc;
2133 struct mem_input *mi = NULL; 2133 struct mem_input *mi = NULL;
2134 2134
2135 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 2135 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
@@ -2155,7 +2155,7 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2155 2155
2156void dc_log_hw_state(struct dc *dc) 2156void dc_log_hw_state(struct dc *dc)
2157{ 2157{
2158 struct core_dc *core_dc = DC_TO_CORE(dc); 2158 struct dc *core_dc = dc;
2159 2159
2160 if (core_dc->hwss.log_hw_state) 2160 if (core_dc->hwss.log_hw_state)
2161 core_dc->hwss.log_hw_state(core_dc); 2161 core_dc->hwss.log_hw_state(core_dc);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 21af3bc057c7..d74eed8f9b96 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -37,12 +37,12 @@
37} while (0) 37} while (0)
38 38
39void pre_surface_trace( 39void pre_surface_trace(
40 const struct dc *dc, 40 struct dc *dc,
41 const struct dc_plane_state *const *plane_states, 41 const struct dc_plane_state *const *plane_states,
42 int surface_count) 42 int surface_count)
43{ 43{
44 int i; 44 int i;
45 struct core_dc *core_dc = DC_TO_CORE(dc); 45 struct dc *core_dc = dc;
46 struct dal_logger *logger = core_dc->ctx->logger; 46 struct dal_logger *logger = core_dc->ctx->logger;
47 47
48 for (i = 0; i < surface_count; i++) { 48 for (i = 0; i < surface_count; i++) {
@@ -158,12 +158,12 @@ void pre_surface_trace(
158} 158}
159 159
160void update_surface_trace( 160void update_surface_trace(
161 const struct dc *dc, 161 struct dc *dc,
162 const struct dc_surface_update *updates, 162 const struct dc_surface_update *updates,
163 int surface_count) 163 int surface_count)
164{ 164{
165 int i; 165 int i;
166 struct core_dc *core_dc = DC_TO_CORE(dc); 166 struct dc *core_dc = dc;
167 struct dal_logger *logger = core_dc->ctx->logger; 167 struct dal_logger *logger = core_dc->ctx->logger;
168 168
169 for (i = 0; i < surface_count; i++) { 169 for (i = 0; i < surface_count; i++) {
@@ -279,9 +279,9 @@ void update_surface_trace(
279 SURFACE_TRACE("\n"); 279 SURFACE_TRACE("\n");
280} 280}
281 281
282void post_surface_trace(const struct dc *dc) 282void post_surface_trace(struct dc *dc)
283{ 283{
284 struct core_dc *core_dc = DC_TO_CORE(dc); 284 struct dc *core_dc = dc;
285 struct dal_logger *logger = core_dc->ctx->logger; 285 struct dal_logger *logger = core_dc->ctx->logger;
286 286
287 SURFACE_TRACE("post surface process.\n"); 287 SURFACE_TRACE("post surface process.\n");
@@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc)
289} 289}
290 290
291void context_timing_trace( 291void context_timing_trace(
292 const struct dc *dc, 292 struct dc *dc,
293 struct resource_context *res_ctx) 293 struct resource_context *res_ctx)
294{ 294{
295 int i; 295 int i;
296 struct core_dc *core_dc = DC_TO_CORE(dc); 296 struct dc *core_dc = dc;
297 struct dal_logger *logger = core_dc->ctx->logger; 297 struct dal_logger *logger = core_dc->ctx->logger;
298 int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; 298 int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
299 struct crtc_position position; 299 struct crtc_position position;
@@ -328,11 +328,11 @@ void context_timing_trace(
328} 328}
329 329
330void context_clock_trace( 330void context_clock_trace(
331 const struct dc *dc, 331 struct dc *dc,
332 struct validate_context *context) 332 struct validate_context *context)
333{ 333{
334#if defined(CONFIG_DRM_AMD_DC_DCN1_0) 334#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
335 struct core_dc *core_dc = DC_TO_CORE(dc); 335 struct dc *core_dc = dc;
336 struct dal_logger *logger = core_dc->ctx->logger; 336 struct dal_logger *logger = core_dc->ctx->logger;
337 337
338 CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" 338 CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 7b1f2493cbc9..71993d5983bf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -25,7 +25,6 @@
25 25
26#include "dm_services.h" 26#include "dm_services.h"
27#include "core_types.h" 27#include "core_types.h"
28#include "core_dc.h"
29#include "timing_generator.h" 28#include "timing_generator.h"
30#include "hw_sequencer.h" 29#include "hw_sequencer.h"
31 30
@@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = {
55}; 54};
56 55
57void color_space_to_black_color( 56void color_space_to_black_color(
58 const struct core_dc *dc, 57 const struct dc *dc,
59 enum dc_color_space colorspace, 58 enum dc_color_space colorspace,
60 struct tg_color *black_color) 59 struct tg_color *black_color)
61{ 60{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b858fec72bd7..1888bf4d2c3f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -26,14 +26,13 @@
26#include "dm_services.h" 26#include "dm_services.h"
27#include "dm_helpers.h" 27#include "dm_helpers.h"
28#include "dc.h" 28#include "dc.h"
29#include "core_dc.h"
30#include "grph_object_id.h" 29#include "grph_object_id.h"
31#include "gpio_service_interface.h" 30#include "gpio_service_interface.h"
32#include "core_status.h" 31#include "core_status.h"
33#include "dc_link_dp.h" 32#include "dc_link_dp.h"
34#include "dc_link_ddc.h" 33#include "dc_link_ddc.h"
35#include "link_hwss.h" 34#include "link_hwss.h"
36#include "stream_encoder.h" 35
37#include "link_encoder.h" 36#include "link_encoder.h"
38#include "hw_sequencer.h" 37#include "hw_sequencer.h"
39#include "resource.h" 38#include "resource.h"
@@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing(
1392bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, 1391bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
1393 uint32_t frame_ramp, const struct dc_stream_state *stream) 1392 uint32_t frame_ramp, const struct dc_stream_state *stream)
1394{ 1393{
1395 struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); 1394 struct dc *core_dc = link->ctx->dc;
1396 struct abm *abm = core_dc->res_pool->abm; 1395 struct abm *abm = core_dc->res_pool->abm;
1397 unsigned int controller_id = 0; 1396 unsigned int controller_id = 0;
1398 int i; 1397 int i;
@@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
1431 1430
1432bool dc_link_set_abm_disable(const struct dc_link *link) 1431bool dc_link_set_abm_disable(const struct dc_link *link)
1433{ 1432{
1434 struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); 1433 struct dc *core_dc = link->ctx->dc;
1435 struct abm *abm = core_dc->res_pool->abm; 1434 struct abm *abm = core_dc->res_pool->abm;
1436 1435
1437 if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) 1436 if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
@@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
1445 1444
1446bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) 1445bool dc_link_set_psr_enable(const struct dc_link *link, bool enable)
1447{ 1446{
1448 struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); 1447 struct dc *core_dc = link->ctx->dc;
1449 struct dmcu *dmcu = core_dc->res_pool->dmcu; 1448 struct dmcu *dmcu = core_dc->res_pool->dmcu;
1450 1449
1451 if (dmcu != NULL && link->psr_enabled) 1450 if (dmcu != NULL && link->psr_enabled)
@@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable)
1456 1455
1457bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) 1456bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
1458{ 1457{
1459 struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); 1458 struct dc *core_dc = link->ctx->dc;
1460 struct dmcu *dmcu = core_dc->res_pool->dmcu; 1459 struct dmcu *dmcu = core_dc->res_pool->dmcu;
1461 1460
1462 if (dmcu != NULL && link->psr_enabled) 1461 if (dmcu != NULL && link->psr_enabled)
@@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link,
1469 const struct dc_stream_state *stream, struct psr_config *psr_config, 1468 const struct dc_stream_state *stream, struct psr_config *psr_config,
1470 struct psr_context *psr_context) 1469 struct psr_context *psr_context)
1471{ 1470{
1472 struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); 1471 struct dc *core_dc = link->ctx->dc;
1473 struct dmcu *dmcu = core_dc->res_pool->dmcu; 1472 struct dmcu *dmcu = core_dc->res_pool->dmcu;
1474 int i; 1473 int i;
1475 1474
@@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
1874 1873
1875void core_link_enable_stream(struct pipe_ctx *pipe_ctx) 1874void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
1876{ 1875{
1877 struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); 1876 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
1878 1877
1879 enum dc_status status = enable_link(pipe_ctx); 1878 enum dc_status status = enable_link(pipe_ctx);
1880 1879
@@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
1907 1906
1908void core_link_disable_stream(struct pipe_ctx *pipe_ctx) 1907void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
1909{ 1908{
1910 struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); 1909 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
1911 1910
1912 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1911 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1913 deallocate_mst_payload(pipe_ctx); 1912 deallocate_mst_payload(pipe_ctx);
@@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
1919 1918
1920void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1919void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1921{ 1920{
1922 struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); 1921 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
1923 1922
1924 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 1923 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1925 return; 1924 return;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9d5fe658d14c..0144c98fd0d5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -10,7 +10,6 @@
10#include "core_status.h" 10#include "core_status.h"
11#include "dpcd_defs.h" 11#include "dpcd_defs.h"
12 12
13#include "core_dc.h"
14#include "resource.h" 13#include "resource.h"
15 14
16/* maximum pre emphasis level allowed for each voltage swing level*/ 15/* maximum pre emphasis level allowed for each voltage swing level*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index d19c663c257f..da880bd02ad7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -3,7 +3,7 @@
3 3
4#include "dm_services.h" 4#include "dm_services.h"
5#include "dc.h" 5#include "dc.h"
6#include "inc/core_dc.h" 6#include "inc/core_types.h"
7#include "include/ddc_service_types.h" 7#include "include/ddc_service_types.h"
8#include "include/i2caux_interface.h" 8#include "include/i2caux_interface.h"
9#include "link_hwss.h" 9#include "link_hwss.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d2b8f27416d6..2b357318f945 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
92} 92}
93 93
94struct resource_pool *dc_create_resource_pool( 94struct resource_pool *dc_create_resource_pool(
95 struct core_dc *dc, 95 struct dc *dc,
96 int num_virtual_links, 96 int num_virtual_links,
97 enum dce_version dc_version, 97 enum dce_version dc_version,
98 struct hw_asic_id asic_id) 98 struct hw_asic_id asic_id)
@@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool(
153 return res_pool; 153 return res_pool;
154} 154}
155 155
156void dc_destroy_resource_pool(struct core_dc *dc) 156void dc_destroy_resource_pool(struct dc *dc)
157{ 157{
158 if (dc) { 158 if (dc) {
159 if (dc->res_pool) 159 if (dc->res_pool)
@@ -193,7 +193,7 @@ static void update_num_audio(
193 193
194bool resource_construct( 194bool resource_construct(
195 unsigned int num_virtual_links, 195 unsigned int num_virtual_links,
196 struct core_dc *dc, 196 struct dc *dc,
197 struct resource_pool *pool, 197 struct resource_pool *pool,
198 const struct resource_create_funcs *create_funcs) 198 const struct resource_create_funcs *create_funcs)
199{ 199{
@@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
892 892
893 893
894enum dc_status resource_build_scaling_params_for_context( 894enum dc_status resource_build_scaling_params_for_context(
895 const struct core_dc *dc, 895 const struct dc *dc,
896 struct validate_context *context) 896 struct validate_context *context)
897{ 897{
898 int i; 898 int i;
@@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
1438} 1438}
1439 1439
1440enum dc_status resource_map_pool_resources( 1440enum dc_status resource_map_pool_resources(
1441 const struct core_dc *dc, 1441 const struct dc *dc,
1442 struct validate_context *context, 1442 struct validate_context *context,
1443 struct validate_context *old_context) 1443 struct validate_context *old_context)
1444{ 1444{
@@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2316} 2316}
2317 2317
2318enum dc_status resource_map_clock_resources( 2318enum dc_status resource_map_clock_resources(
2319 const struct core_dc *dc, 2319 const struct dc *dc,
2320 struct validate_context *context, 2320 struct validate_context *context,
2321 struct validate_context *old_context) 2321 struct validate_context *old_context)
2322{ 2322{
@@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources(
2343 else { 2343 else {
2344 pipe_ctx->clock_source = NULL; 2344 pipe_ctx->clock_source = NULL;
2345 2345
2346 if (!dc->public.config.disable_disp_pll_sharing) 2346 if (!dc->config.disable_disp_pll_sharing)
2347 resource_find_used_clk_src_for_sharing( 2347 resource_find_used_clk_src_for_sharing(
2348 &context->res_ctx, 2348 &context->res_ctx,
2349 pipe_ctx); 2349 pipe_ctx);
@@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2515 fmt_bit_depth->pixel_encoding = pixel_encoding; 2515 fmt_bit_depth->pixel_encoding = pixel_encoding;
2516} 2516}
2517 2517
2518bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) 2518bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
2519{ 2519{
2520 struct core_dc *core_dc = DC_TO_CORE(dc); 2520 struct dc *core_dc = dc;
2521 struct dc_context *dc_ctx = core_dc->ctx; 2521 struct dc_context *dc_ctx = core_dc->ctx;
2522 struct dc_link *link = stream->sink->link; 2522 struct dc_link *link = stream->sink->link;
2523 struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; 2523 struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
@@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream)
2547 return res == DC_OK; 2547 return res == DC_OK;
2548} 2548}
2549 2549
2550bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) 2550bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
2551{ 2551{
2552 struct core_dc *core_dc = DC_TO_CORE(dc); 2552 struct dc *core_dc = dc;
2553 2553
2554 /* TODO For now validates pixel format only */ 2554 /* TODO For now validates pixel format only */
2555 if (core_dc->res_pool->funcs->validate_plane) 2555 if (core_dc->res_pool->funcs->validate_plane)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 47e407dab4a3..5e4f7f08e3db 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status(
144 struct dc_stream_state *stream) 144 struct dc_stream_state *stream)
145{ 145{
146 uint8_t i; 146 uint8_t i;
147 struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); 147 struct dc *dc = stream->ctx->dc;
148 148
149 for (i = 0; i < dc->current_context->stream_count; i++) { 149 for (i = 0; i < dc->current_context->stream_count; i++) {
150 if (stream == dc->current_context->streams[i]) { 150 if (stream == dc->current_context->streams[i]) {
@@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes(
163 const struct dc_cursor_attributes *attributes) 163 const struct dc_cursor_attributes *attributes)
164{ 164{
165 int i; 165 int i;
166 struct core_dc *core_dc; 166 struct dc *core_dc;
167 struct resource_context *res_ctx; 167 struct resource_context *res_ctx;
168 168
169 if (NULL == stream) { 169 if (NULL == stream) {
@@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes(
175 return false; 175 return false;
176 } 176 }
177 177
178 core_dc = DC_TO_CORE(stream->ctx->dc); 178 core_dc = stream->ctx->dc;
179 res_ctx = &core_dc->current_context->res_ctx; 179 res_ctx = &core_dc->current_context->res_ctx;
180 180
181 for (i = 0; i < MAX_PIPES; i++) { 181 for (i = 0; i < MAX_PIPES; i++) {
@@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position(
198 const struct dc_cursor_position *position) 198 const struct dc_cursor_position *position)
199{ 199{
200 int i; 200 int i;
201 struct core_dc *core_dc; 201 struct dc *core_dc;
202 struct resource_context *res_ctx; 202 struct resource_context *res_ctx;
203 203
204 if (NULL == stream) { 204 if (NULL == stream) {
@@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position(
211 return false; 211 return false;
212 } 212 }
213 213
214 core_dc = DC_TO_CORE(stream->ctx->dc); 214 core_dc = stream->ctx->dc;
215 res_ctx = &core_dc->current_context->res_ctx; 215 res_ctx = &core_dc->current_context->res_ctx;
216 216
217 for (i = 0; i < MAX_PIPES; i++) { 217 for (i = 0; i < MAX_PIPES; i++) {
@@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position(
246uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 246uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
247{ 247{
248 uint8_t i; 248 uint8_t i;
249 struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); 249 struct dc *core_dc = stream->ctx->dc;
250 struct resource_context *res_ctx = 250 struct resource_context *res_ctx =
251 &core_dc->current_context->res_ctx; 251 &core_dc->current_context->res_ctx;
252 252
@@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
270{ 270{
271 uint8_t i; 271 uint8_t i;
272 bool ret = false; 272 bool ret = false;
273 struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); 273 struct dc *core_dc = stream->ctx->dc;
274 struct resource_context *res_ctx = 274 struct resource_context *res_ctx =
275 &core_dc->current_context->res_ctx; 275 &core_dc->current_context->res_ctx;
276 276
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index da19c7fa5151..0b6410fb2f3e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -28,7 +28,7 @@
28#include "dc.h" 28#include "dc.h"
29 29
30/* DC core (private) */ 30/* DC core (private) */
31#include "core_dc.h" 31#include "core_types.h"
32#include "transform.h" 32#include "transform.h"
33 33
34/******************************************************************************* 34/*******************************************************************************
@@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
64 /*register_flip_interrupt(surface);*/ 64 /*register_flip_interrupt(surface);*/
65} 65}
66 66
67struct dc_plane_state *dc_create_plane_state(const struct dc *dc) 67struct dc_plane_state *dc_create_plane_state(struct dc *dc)
68{ 68{
69 struct core_dc *core_dc = DC_TO_CORE(dc); 69 struct dc *core_dc = dc;
70 70
71 struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); 71 struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state));
72 72
@@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status(
91 const struct dc_plane_state *plane_state) 91 const struct dc_plane_state *plane_state)
92{ 92{
93 const struct dc_plane_status *plane_status; 93 const struct dc_plane_status *plane_status;
94 struct core_dc *core_dc; 94 struct dc *core_dc;
95 int i; 95 int i;
96 96
97 if (!plane_state || 97 if (!plane_state ||
@@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status(
102 } 102 }
103 103
104 plane_status = &plane_state->status; 104 plane_status = &plane_state->status;
105 core_dc = DC_TO_CORE(plane_state->ctx->dc); 105 core_dc = plane_state->ctx->dc;
106 106
107 if (core_dc->current_context == NULL) 107 if (core_dc->current_context == NULL)
108 return NULL; 108 return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e62d15d90fdb..68056d888def 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -34,14 +34,19 @@
34#include "grph_object_ctrl_defs.h" 34#include "grph_object_ctrl_defs.h"
35#include <inc/hw/opp.h> 35#include <inc/hw/opp.h>
36 36
37#include "inc/hw_sequencer.h"
38#include "dml/display_mode_lib.h"
39
40
41
37#define MAX_SURFACES 3 42#define MAX_SURFACES 3
38#define MAX_STREAMS 6 43#define MAX_STREAMS 6
39#define MAX_SINKS_PER_LINK 4 44#define MAX_SINKS_PER_LINK 4
40 45
46
41/******************************************************************************* 47/*******************************************************************************
42 * Display Core Interfaces 48 * Display Core Interfaces
43 ******************************************************************************/ 49 ******************************************************************************/
44
45struct dc_caps { 50struct dc_caps {
46 uint32_t max_streams; 51 uint32_t max_streams;
47 uint32_t max_links; 52 uint32_t max_links;
@@ -186,7 +191,9 @@ struct dc_debug {
186 bool disable_psr; 191 bool disable_psr;
187 bool force_abm_enable; 192 bool force_abm_enable;
188}; 193};
189 194struct validate_context;
195struct resource_pool;
196struct dce_hwseq;
190struct dc { 197struct dc {
191 struct dc_caps caps; 198 struct dc_caps caps;
192 struct dc_cap_funcs cap_funcs; 199 struct dc_cap_funcs cap_funcs;
@@ -194,6 +201,40 @@ struct dc {
194 struct dc_link_funcs link_funcs; 201 struct dc_link_funcs link_funcs;
195 struct dc_config config; 202 struct dc_config config;
196 struct dc_debug debug; 203 struct dc_debug debug;
204
205 struct dc_context *ctx;
206
207 uint8_t link_count;
208 struct dc_link *links[MAX_PIPES * 2];
209
210 struct validate_context *current_context;
211 struct resource_pool *res_pool;
212
213 /* Display Engine Clock levels */
214 struct dm_pp_clock_levels sclk_lvls;
215
216 /* Inputs into BW and WM calculations. */
217 struct bw_calcs_dceip *bw_dceip;
218 struct bw_calcs_vbios *bw_vbios;
219#ifdef CONFIG_DRM_AMD_DC_DCN1_0
220 struct dcn_soc_bounding_box *dcn_soc;
221 struct dcn_ip_params *dcn_ip;
222 struct display_mode_lib dml;
223#endif
224
225 /* HW functions */
226 struct hw_sequencer_funcs hwss;
227 struct dce_hwseq *hwseq;
228
229 /* temp store of dm_pp_display_configuration
230 * to compare to see if display config changed
231 */
232 struct dm_pp_display_configuration prev_display_config;
233
234 /* FBC compressor */
235#ifdef ENABLE_FBC
236 struct compressor *fbc_compressor;
237#endif
197}; 238};
198 239
199enum frame_buffer_mode { 240enum frame_buffer_mode {
@@ -384,7 +425,7 @@ struct dc_surface_update {
384/* 425/*
385 * Create a new surface with default parameters; 426 * Create a new surface with default parameters;
386 */ 427 */
387struct dc_plane_state *dc_create_plane_state(const struct dc *dc); 428struct dc_plane_state *dc_create_plane_state(struct dc *dc);
388const struct dc_plane_status *dc_plane_get_status( 429const struct dc_plane_status *dc_plane_get_status(
389 const struct dc_plane_state *plane_state); 430 const struct dc_plane_state *plane_state);
390 431
@@ -558,8 +599,8 @@ void dc_stream_log(
558 struct dal_logger *dc_logger, 599 struct dal_logger *dc_logger,
559 enum dc_log_type log_type); 600 enum dc_log_type log_type);
560 601
561uint8_t dc_get_current_stream_count(const struct dc *dc); 602uint8_t dc_get_current_stream_count(struct dc *dc);
562struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); 603struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
563 604
564/* 605/*
565 * Return the current frame counter. 606 * Return the current frame counter.
@@ -585,9 +626,9 @@ struct dc_validation_set {
585 uint8_t plane_count; 626 uint8_t plane_count;
586}; 627};
587 628
588bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); 629bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
589 630
590bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); 631bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
591/* 632/*
592 * This function takes a set of resources and checks that they are cofunctional. 633 * This function takes a set of resources and checks that they are cofunctional.
593 * 634 *
@@ -595,12 +636,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s
595 * No hardware is programmed for call. Only validation is done. 636 * No hardware is programmed for call. Only validation is done.
596 */ 637 */
597struct validate_context *dc_get_validate_context( 638struct validate_context *dc_get_validate_context(
598 const struct dc *dc, 639 struct dc *dc,
599 const struct dc_validation_set set[], 640 const struct dc_validation_set set[],
600 uint8_t set_count); 641 uint8_t set_count);
601 642
602bool dc_validate_resources( 643bool dc_validate_resources(
603 const struct dc *dc, 644 struct dc *dc,
604 const struct dc_validation_set set[], 645 const struct dc_validation_set set[],
605 uint8_t set_count); 646 uint8_t set_count);
606 647
@@ -613,7 +654,7 @@ bool dc_validate_resources(
613 */ 654 */
614 655
615bool dc_validate_guaranteed( 656bool dc_validate_guaranteed(
616 const struct dc *dc, 657 struct dc *dc,
617 struct dc_stream_state *stream); 658 struct dc_stream_state *stream);
618 659
619void dc_resource_validate_ctx_copy_construct( 660void dc_resource_validate_ctx_copy_construct(
@@ -764,7 +805,7 @@ struct dc_link {
764 805
765 /* Private to DC core */ 806 /* Private to DC core */
766 807
767 const struct core_dc *dc; 808 const struct dc *dc;
768 809
769 struct dc_context *ctx; 810 struct dc_context *ctx;
770 811
@@ -795,9 +836,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
795 * boot time. They cannot be created or destroyed. 836 * boot time. They cannot be created or destroyed.
796 * Use dc_get_caps() to get number of links. 837 * Use dc_get_caps() to get number of links.
797 */ 838 */
798struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); 839struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
799 840
800struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe); 841struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe);
801 842
802/* Return id of physical connector represented by a dc_link at link_index.*/ 843/* Return id of physical connector represented by a dc_link at link_index.*/
803const struct graphics_object_id dc_get_link_id_at_index( 844const struct graphics_object_id dc_get_link_id_at_index(
@@ -948,7 +989,7 @@ enum dc_irq_source dc_interrupt_to_irq_source(
948 struct dc *dc, 989 struct dc *dc,
949 uint32_t src_id, 990 uint32_t src_id,
950 uint32_t ext_id); 991 uint32_t ext_id);
951void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); 992void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
952void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 993void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
953enum dc_irq_source dc_get_hpd_irq_source_at_index( 994enum dc_irq_source dc_get_hpd_irq_source_at_index(
954 struct dc *dc, uint32_t link_index); 995 struct dc *dc, uint32_t link_index);
@@ -960,7 +1001,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index(
960void dc_set_power_state( 1001void dc_set_power_state(
961 struct dc *dc, 1002 struct dc *dc,
962 enum dc_acpi_cm_power_state power_state); 1003 enum dc_acpi_cm_power_state power_state);
963void dc_resume(const struct dc *dc); 1004void dc_resume(struct dc *dc);
964 1005
965/* 1006/*
966 * DPCD access interfaces 1007 * DPCD access interfaces
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 922af2d1b91a..0654fe34627c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -34,7 +34,6 @@
34 34
35#include "dce_clock_source.h" 35#include "dce_clock_source.h"
36 36
37#include "core_dc.h"
38#include "reg_helper.h" 37#include "reg_helper.h"
39 38
40#define REG(reg)\ 39#define REG(reg)\
@@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz(
609 struct pll_settings *pll_settings) 608 struct pll_settings *pll_settings)
610{ 609{
611 uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 610 uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
612 struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); 611 struct dc *dc_core = cs->ctx->dc;
613 struct validate_context *context = dc_core->current_context; 612 struct validate_context *context = dc_core->current_context;
614 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; 613 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
615 614
@@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
624 struct pll_settings *pll_settings) 623 struct pll_settings *pll_settings)
625{ 624{
626 uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 625 uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
627 struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); 626 struct dc *dc_core = cs->ctx->dc;
628 struct validate_context *context = dc_core->current_context; 627 struct validate_context *context = dc_core->current_context;
629 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; 628 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
630 629
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 7bb2eaf07da5..9d67340a6b8b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -29,14 +29,12 @@
29#include "fixed32_32.h" 29#include "fixed32_32.h"
30#include "bios_parser_interface.h" 30#include "bios_parser_interface.h"
31#include "dc.h" 31#include "dc.h"
32#include "core_dc.h"
33#include "dce_abm.h" 32#include "dce_abm.h"
34#include "dmcu.h" 33#include "dmcu.h"
35#if defined(CONFIG_DRM_AMD_DC_DCN1_0) 34#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
36#include "dcn_calcs.h" 35#include "dcn_calcs.h"
37#include "core_dc.h"
38#endif 36#endif
39 37#include "core_types.h"
40 38
41 39
42#define TO_DCE_CLOCKS(clocks)\ 40#define TO_DCE_CLOCKS(clocks)\
@@ -368,7 +366,7 @@ static int dce_psr_set_clock(
368{ 366{
369 struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); 367 struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
370 struct dc_context *ctx = clk_dce->base.ctx; 368 struct dc_context *ctx = clk_dce->base.ctx;
371 struct core_dc *core_dc = DC_TO_CORE(ctx->dc); 369 struct dc *core_dc = ctx->dc;
372 struct dmcu *dmcu = core_dc->res_pool->dmcu; 370 struct dmcu *dmcu = core_dc->res_pool->dmcu;
373 int actual_clk_khz = requested_clk_khz; 371 int actual_clk_khz = requested_clk_khz;
374 372
@@ -385,7 +383,7 @@ static int dce112_set_clock(
385 struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); 383 struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
386 struct bp_set_dce_clock_parameters dce_clk_params; 384 struct bp_set_dce_clock_parameters dce_clk_params;
387 struct dc_bios *bp = clk->ctx->dc_bios; 385 struct dc_bios *bp = clk->ctx->dc_bios;
388 struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); 386 struct dc *core_dc = clk->ctx->dc;
389 struct abm *abm = core_dc->res_pool->abm; 387 struct abm *abm = core_dc->res_pool->abm;
390 struct dmcu *dmcu = core_dc->res_pool->dmcu; 388 struct dmcu *dmcu = core_dc->res_pool->dmcu;
391 int actual_clock = requested_clk_khz; 389 int actual_clock = requested_clk_khz;
@@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request(
621 if (send_request) { 619 if (send_request) {
622#if defined(CONFIG_DRM_AMD_DC_DCN1_0) 620#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
623 if (clk->ctx->dce_version >= DCN_VERSION_1_0) { 621 if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
624 struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); 622 struct dc *core_dc = clk->ctx->dc;
625 /*use dcfclk request voltage*/ 623 /*use dcfclk request voltage*/
626 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 624 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
627 clock_voltage_req.clocks_in_khz = 625 clock_voltage_req.clocks_in_khz =
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 4894e1755d84..d2e66b1bc0ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -26,7 +26,7 @@
26#include "dce_hwseq.h" 26#include "dce_hwseq.h"
27#include "reg_helper.h" 27#include "reg_helper.h"
28#include "hw_sequencer.h" 28#include "hw_sequencer.h"
29#include "core_dc.h" 29#include "core_types.h"
30 30
31#define CTX \ 31#define CTX \
32 hws->ctx 32 hws->ctx
@@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
44 DCFE_CLOCK_ENABLE, enable); 44 DCFE_CLOCK_ENABLE, enable);
45} 45}
46 46
47void dce_pipe_control_lock(struct core_dc *dc, 47void dce_pipe_control_lock(struct dc *dc,
48 struct pipe_ctx *pipe, 48 struct pipe_ctx *pipe,
49 bool lock) 49 bool lock)
50{ 50{
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 9a97d8ee7971..3a1eb6a79d66 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -528,7 +528,7 @@ enum blnd_mode {
528void dce_enable_fe_clock(struct dce_hwseq *hwss, 528void dce_enable_fe_clock(struct dce_hwseq *hwss,
529 unsigned int inst, bool enable); 529 unsigned int inst, bool enable);
530 530
531void dce_pipe_control_lock(struct core_dc *dc, 531void dce_pipe_control_lock(struct dc *dc,
532 struct pipe_ctx *pipe, 532 struct pipe_ctx *pipe,
533 bool lock); 533 bool lock);
534 534
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index c638f47acefc..b7e51c5ed1b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -24,7 +24,6 @@
24 */ 24 */
25#include "dm_services.h" 25#include "dm_services.h"
26#include "dc.h" 26#include "dc.h"
27#include "core_dc.h"
28#include "core_types.h" 27#include "core_types.h"
29#include "hw_sequencer.h" 28#include "hw_sequencer.h"
30#include "dce100_hw_sequencer.h" 29#include "dce100_hw_sequencer.h"
@@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
71/***************************PIPE_CONTROL***********************************/ 70/***************************PIPE_CONTROL***********************************/
72 71
73static bool dce100_enable_display_power_gating( 72static bool dce100_enable_display_power_gating(
74 struct core_dc *dc, 73 struct dc *dc,
75 uint8_t controller_id, 74 uint8_t controller_id,
76 struct dc_bios *dcb, 75 struct dc_bios *dcb,
77 enum pipe_gating_control power_gating) 76 enum pipe_gating_control power_gating)
@@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating(
107} 106}
108 107
109static void dce100_pplib_apply_display_requirements( 108static void dce100_pplib_apply_display_requirements(
110 struct core_dc *dc, 109 struct dc *dc,
111 struct validate_context *context) 110 struct validate_context *context)
112{ 111{
113 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 112 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
@@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements(
127} 126}
128 127
129void dce100_set_bandwidth( 128void dce100_set_bandwidth(
130 struct core_dc *dc, 129 struct dc *dc,
131 struct validate_context *context, 130 struct validate_context *context,
132 bool decrease_allowed) 131 bool decrease_allowed)
133{ 132{
@@ -143,7 +142,7 @@ void dce100_set_bandwidth(
143 142
144/**************************************************************************/ 143/**************************************************************************/
145 144
146bool dce100_hw_sequencer_construct(struct core_dc *dc) 145bool dce100_hw_sequencer_construct(struct dc *dc)
147{ 146{
148 dce110_hw_sequencer_construct(dc); 147 dce110_hw_sequencer_construct(dc);
149 148
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
index 24433f0e770b..c04aa15cd656 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
@@ -28,13 +28,13 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32struct validate_context; 32struct validate_context;
33 33
34bool dce100_hw_sequencer_construct(struct core_dc *dc); 34bool dce100_hw_sequencer_construct(struct dc *dc);
35 35
36void dce100_set_bandwidth( 36void dce100_set_bandwidth(
37 struct core_dc *dc, 37 struct dc *dc,
38 struct validate_context *context, 38 struct validate_context *context,
39 bool decrease_allowed); 39 bool decrease_allowed);
40 40
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 46f0c71fbac4..b2b03633eb4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool)
652} 652}
653 653
654static enum dc_status build_mapped_resource( 654static enum dc_status build_mapped_resource(
655 const struct core_dc *dc, 655 const struct dc *dc,
656 struct validate_context *context, 656 struct validate_context *context,
657 struct validate_context *old_context) 657 struct validate_context *old_context)
658{ 658{
@@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource(
688} 688}
689 689
690bool dce100_validate_bandwidth( 690bool dce100_validate_bandwidth(
691 const struct core_dc *dc, 691 struct dc *dc,
692 struct validate_context *context) 692 struct validate_context *context)
693{ 693{
694 /* TODO implement when needed but for now hardcode max value*/ 694 /* TODO implement when needed but for now hardcode max value*/
@@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets(
720} 720}
721 721
722enum dc_status dce100_validate_with_context( 722enum dc_status dce100_validate_with_context(
723 const struct core_dc *dc, 723 struct dc *dc,
724 const struct dc_validation_set set[], 724 const struct dc_validation_set set[],
725 int set_count, 725 int set_count,
726 struct validate_context *context, 726 struct validate_context *context,
@@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context(
764} 764}
765 765
766enum dc_status dce100_validate_guaranteed( 766enum dc_status dce100_validate_guaranteed(
767 const struct core_dc *dc, 767 struct dc *dc,
768 struct dc_stream_state *dc_stream, 768 struct dc_stream_state *dc_stream,
769 struct validate_context *context) 769 struct validate_context *context)
770{ 770{
@@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed(
784 784
785 if (result == DC_OK) { 785 if (result == DC_OK) {
786 validate_guaranteed_copy_streams( 786 validate_guaranteed_copy_streams(
787 context, dc->public.caps.max_streams); 787 context, dc->caps.max_streams);
788 result = resource_build_scaling_params_for_context(dc, context); 788 result = resource_build_scaling_params_for_context(dc, context);
789 } 789 }
790 790
@@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = {
824 824
825static bool construct( 825static bool construct(
826 uint8_t num_virtual_links, 826 uint8_t num_virtual_links,
827 struct core_dc *dc, 827 struct dc *dc,
828 struct dce110_resource_pool *pool) 828 struct dce110_resource_pool *pool)
829{ 829{
830 unsigned int i; 830 unsigned int i;
@@ -909,9 +909,9 @@ static bool construct(
909 *************************************************/ 909 *************************************************/
910 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 910 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
911 pool->base.pipe_count = res_cap.num_timing_generator; 911 pool->base.pipe_count = res_cap.num_timing_generator;
912 dc->public.caps.max_downscale_ratio = 200; 912 dc->caps.max_downscale_ratio = 200;
913 dc->public.caps.i2c_speed_in_khz = 40; 913 dc->caps.i2c_speed_in_khz = 40;
914 dc->public.caps.max_cursor_size = 128; 914 dc->caps.max_cursor_size = 128;
915 915
916 for (i = 0; i < pool->base.pipe_count; i++) { 916 for (i = 0; i < pool->base.pipe_count; i++) {
917 pool->base.timing_generators[i] = 917 pool->base.timing_generators[i] =
@@ -958,7 +958,7 @@ static bool construct(
958 } 958 }
959 } 959 }
960 960
961 dc->public.caps.max_planes = pool->base.pipe_count; 961 dc->caps.max_planes = pool->base.pipe_count;
962 962
963 if (!resource_construct(num_virtual_links, dc, &pool->base, 963 if (!resource_construct(num_virtual_links, dc, &pool->base,
964 &res_create_funcs)) 964 &res_create_funcs))
@@ -978,7 +978,7 @@ res_create_fail:
978 978
979struct resource_pool *dce100_create_resource_pool( 979struct resource_pool *dce100_create_resource_pool(
980 uint8_t num_virtual_links, 980 uint8_t num_virtual_links,
981 struct core_dc *dc) 981 struct dc *dc)
982{ 982{
983 struct dce110_resource_pool *pool = 983 struct dce110_resource_pool *pool =
984 dm_alloc(sizeof(struct dce110_resource_pool)); 984 dm_alloc(sizeof(struct dce110_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h
index edc50caf04d1..ca7b2b7c1a48 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h
@@ -8,13 +8,13 @@
8#ifndef DCE100_RESOURCE_H_ 8#ifndef DCE100_RESOURCE_H_
9#define DCE100_RESOURCE_H_ 9#define DCE100_RESOURCE_H_
10 10
11struct core_dc; 11struct dc;
12struct resource_pool; 12struct resource_pool;
13struct dc_validation_set; 13struct dc_validation_set;
14 14
15struct resource_pool *dce100_create_resource_pool( 15struct resource_pool *dce100_create_resource_pool(
16 uint8_t num_virtual_links, 16 uint8_t num_virtual_links,
17 struct core_dc *dc); 17 struct dc *dc);
18 18
19enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); 19enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state);
20 20
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ccde7c80d658..e6c6f1108078 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating(
164} 164}
165 165
166static bool dce110_enable_display_power_gating( 166static bool dce110_enable_display_power_gating(
167 struct core_dc *dc, 167 struct dc *dc,
168 uint8_t controller_id, 168 uint8_t controller_id,
169 struct dc_bios *dcb, 169 struct dc_bios *dcb,
170 enum pipe_gating_control power_gating) 170 enum pipe_gating_control power_gating)
@@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
944 } 944 }
945} 945}
946 946
947static void program_scaler(const struct core_dc *dc, 947static void program_scaler(const struct dc *dc,
948 const struct pipe_ctx *pipe_ctx) 948 const struct pipe_ctx *pipe_ctx)
949{ 949{
950 struct tg_color color = {0}; 950 struct tg_color color = {0};
@@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc,
955 return; 955 return;
956#endif 956#endif
957 957
958 if (dc->public.debug.surface_visual_confirm) 958 if (dc->debug.surface_visual_confirm)
959 get_surface_visual_confirm_color(pipe_ctx, &color); 959 get_surface_visual_confirm_color(pipe_ctx, &color);
960 else 960 else
961 color_space_to_black_color(dc, 961 color_space_to_black_color(dc,
@@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc,
979static enum dc_status dce110_prog_pixclk_crtc_otg( 979static enum dc_status dce110_prog_pixclk_crtc_otg(
980 struct pipe_ctx *pipe_ctx, 980 struct pipe_ctx *pipe_ctx,
981 struct validate_context *context, 981 struct validate_context *context,
982 struct core_dc *dc) 982 struct dc *dc)
983{ 983{
984 struct dc_stream_state *stream = pipe_ctx->stream; 984 struct dc_stream_state *stream = pipe_ctx->stream;
985 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 985 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
@@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
1035static enum dc_status apply_single_controller_ctx_to_hw( 1035static enum dc_status apply_single_controller_ctx_to_hw(
1036 struct pipe_ctx *pipe_ctx, 1036 struct pipe_ctx *pipe_ctx,
1037 struct validate_context *context, 1037 struct validate_context *context,
1038 struct core_dc *dc) 1038 struct dc *dc)
1039{ 1039{
1040 struct dc_stream_state *stream = pipe_ctx->stream; 1040 struct dc_stream_state *stream = pipe_ctx->stream;
1041 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. 1041 struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
@@ -1146,7 +1146,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
1146 1146
1147/******************************************************************************/ 1147/******************************************************************************/
1148 1148
1149static void power_down_encoders(struct core_dc *dc) 1149static void power_down_encoders(struct dc *dc)
1150{ 1150{
1151 int i; 1151 int i;
1152 1152
@@ -1156,7 +1156,7 @@ static void power_down_encoders(struct core_dc *dc)
1156 } 1156 }
1157} 1157}
1158 1158
1159static void power_down_controllers(struct core_dc *dc) 1159static void power_down_controllers(struct dc *dc)
1160{ 1160{
1161 int i; 1161 int i;
1162 1162
@@ -1166,7 +1166,7 @@ static void power_down_controllers(struct core_dc *dc)
1166 } 1166 }
1167} 1167}
1168 1168
1169static void power_down_clock_sources(struct core_dc *dc) 1169static void power_down_clock_sources(struct dc *dc)
1170{ 1170{
1171 int i; 1171 int i;
1172 1172
@@ -1181,7 +1181,7 @@ static void power_down_clock_sources(struct core_dc *dc)
1181 } 1181 }
1182} 1182}
1183 1183
1184static void power_down_all_hw_blocks(struct core_dc *dc) 1184static void power_down_all_hw_blocks(struct dc *dc)
1185{ 1185{
1186 power_down_encoders(dc); 1186 power_down_encoders(dc);
1187 1187
@@ -1196,7 +1196,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc)
1196} 1196}
1197 1197
1198static void disable_vga_and_power_gate_all_controllers( 1198static void disable_vga_and_power_gate_all_controllers(
1199 struct core_dc *dc) 1199 struct dc *dc)
1200{ 1200{
1201 int i; 1201 int i;
1202 struct timing_generator *tg; 1202 struct timing_generator *tg;
@@ -1224,7 +1224,7 @@ static void disable_vga_and_power_gate_all_controllers(
1224 * 3. Enable power gating for controller 1224 * 3. Enable power gating for controller
1225 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1225 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1226 */ 1226 */
1227void dce110_enable_accelerated_mode(struct core_dc *dc) 1227void dce110_enable_accelerated_mode(struct dc *dc)
1228{ 1228{
1229 power_down_all_hw_blocks(dc); 1229 power_down_all_hw_blocks(dc);
1230 1230
@@ -1250,7 +1250,7 @@ static uint32_t compute_pstate_blackout_duration(
1250} 1250}
1251 1251
1252void dce110_set_displaymarks( 1252void dce110_set_displaymarks(
1253 const struct core_dc *dc, 1253 const struct dc *dc,
1254 struct validate_context *context) 1254 struct validate_context *context)
1255{ 1255{
1256 uint8_t i, num_pipes; 1256 uint8_t i, num_pipes;
@@ -1316,7 +1316,7 @@ static void set_safe_displaymarks(
1316} 1316}
1317 1317
1318static void switch_dp_clock_sources( 1318static void switch_dp_clock_sources(
1319 const struct core_dc *dc, 1319 const struct dc *dc,
1320 struct resource_context *res_ctx) 1320 struct resource_context *res_ctx)
1321{ 1321{
1322 uint8_t i; 1322 uint8_t i;
@@ -1408,7 +1408,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1408 * may read PLL register to get pixel clock 1408 * may read PLL register to get pixel clock
1409 */ 1409 */
1410static uint32_t get_max_pixel_clock_for_all_paths( 1410static uint32_t get_max_pixel_clock_for_all_paths(
1411 struct core_dc *dc, 1411 struct dc *dc,
1412 struct validate_context *context, 1412 struct validate_context *context,
1413 bool pre_mode_set) 1413 bool pre_mode_set)
1414{ 1414{
@@ -1449,7 +1449,7 @@ static uint32_t get_max_pixel_clock_for_all_paths(
1449 * etc support for dcn1.0 1449 * etc support for dcn1.0
1450 */ 1450 */
1451static void apply_min_clocks( 1451static void apply_min_clocks(
1452 struct core_dc *dc, 1452 struct dc *dc,
1453 struct validate_context *context, 1453 struct validate_context *context,
1454 enum dm_pp_clocks_state *clocks_state, 1454 enum dm_pp_clocks_state *clocks_state,
1455 bool pre_mode_set) 1455 bool pre_mode_set)
@@ -1538,7 +1538,7 @@ static void apply_min_clocks(
1538/* 1538/*
1539 * Check if FBC can be enabled 1539 * Check if FBC can be enabled
1540 */ 1540 */
1541static enum dc_status validate_fbc(struct core_dc *dc, 1541static enum dc_status validate_fbc(struct dc *dc,
1542 struct validate_context *context) 1542 struct validate_context *context)
1543{ 1543{
1544 struct pipe_ctx *pipe_ctx = 1544 struct pipe_ctx *pipe_ctx =
@@ -1568,7 +1568,7 @@ static enum dc_status validate_fbc(struct core_dc *dc,
1568/* 1568/*
1569 * Enable FBC 1569 * Enable FBC
1570 */ 1570 */
1571static enum dc_status enable_fbc(struct core_dc *dc, 1571static enum dc_status enable_fbc(struct dc *dc,
1572 struct validate_context *context) 1572 struct validate_context *context)
1573{ 1573{
1574 enum dc_status status = validate_fbc(dc, context); 1574 enum dc_status status = validate_fbc(dc, context);
@@ -1597,7 +1597,7 @@ static enum dc_status enable_fbc(struct core_dc *dc,
1597#endif 1597#endif
1598 1598
1599static enum dc_status apply_ctx_to_hw_fpga( 1599static enum dc_status apply_ctx_to_hw_fpga(
1600 struct core_dc *dc, 1600 struct dc *dc,
1601 struct validate_context *context) 1601 struct validate_context *context)
1602{ 1602{
1603 enum dc_status status = DC_ERROR_UNEXPECTED; 1603 enum dc_status status = DC_ERROR_UNEXPECTED;
@@ -1627,7 +1627,7 @@ static enum dc_status apply_ctx_to_hw_fpga(
1627} 1627}
1628 1628
1629static void dce110_reset_hw_ctx_wrap( 1629static void dce110_reset_hw_ctx_wrap(
1630 struct core_dc *dc, 1630 struct dc *dc,
1631 struct validate_context *context) 1631 struct validate_context *context)
1632{ 1632{
1633 int i; 1633 int i;
@@ -1672,7 +1672,7 @@ static void dce110_reset_hw_ctx_wrap(
1672 1672
1673 1673
1674enum dc_status dce110_apply_ctx_to_hw( 1674enum dc_status dce110_apply_ctx_to_hw(
1675 struct core_dc *dc, 1675 struct dc *dc,
1676 struct validate_context *context) 1676 struct validate_context *context)
1677{ 1677{
1678 struct dc_bios *dcb = dc->ctx->dc_bios; 1678 struct dc_bios *dcb = dc->ctx->dc_bios;
@@ -1965,7 +1965,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
1965 * -------------------------------------------------| 1965 * -------------------------------------------------|
1966 * 1966 *
1967 ******************************************************************************/ 1967 ******************************************************************************/
1968static void program_surface_visibility(const struct core_dc *dc, 1968static void program_surface_visibility(const struct dc *dc,
1969 struct pipe_ctx *pipe_ctx) 1969 struct pipe_ctx *pipe_ctx)
1970{ 1970{
1971 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 1971 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
@@ -2038,7 +2038,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2038 * TODO REMOVE, USE UPDATE INSTEAD 2038 * TODO REMOVE, USE UPDATE INSTEAD
2039 */ 2039 */
2040static void set_plane_config( 2040static void set_plane_config(
2041 const struct core_dc *dc, 2041 const struct dc *dc,
2042 struct pipe_ctx *pipe_ctx, 2042 struct pipe_ctx *pipe_ctx,
2043 struct resource_context *res_ctx) 2043 struct resource_context *res_ctx)
2044{ 2044{
@@ -2117,7 +2117,7 @@ static void set_plane_config(
2117 if (mi->funcs->set_blank) 2117 if (mi->funcs->set_blank)
2118 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2118 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2119 2119
2120 if (dc->public.config.gpu_vm_support) 2120 if (dc->config.gpu_vm_support)
2121 mi->funcs->mem_input_program_pte_vm( 2121 mi->funcs->mem_input_program_pte_vm(
2122 pipe_ctx->plane_res.mi, 2122 pipe_ctx->plane_res.mi,
2123 plane_state->format, 2123 plane_state->format,
@@ -2125,7 +2125,7 @@ static void set_plane_config(
2125 plane_state->rotation); 2125 plane_state->rotation);
2126} 2126}
2127 2127
2128static void update_plane_addr(const struct core_dc *dc, 2128static void update_plane_addr(const struct dc *dc,
2129 struct pipe_ctx *pipe_ctx) 2129 struct pipe_ctx *pipe_ctx)
2130{ 2130{
2131 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2131 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
@@ -2163,7 +2163,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2163 } 2163 }
2164} 2164}
2165 2165
2166void dce110_power_down(struct core_dc *dc) 2166void dce110_power_down(struct dc *dc)
2167{ 2167{
2168 power_down_all_hw_blocks(dc); 2168 power_down_all_hw_blocks(dc);
2169 disable_vga_and_power_gate_all_controllers(dc); 2169 disable_vga_and_power_gate_all_controllers(dc);
@@ -2208,7 +2208,7 @@ static bool wait_for_reset_trigger_to_occur(
2208 2208
2209/* Enable timing synchronization for a group of Timing Generators. */ 2209/* Enable timing synchronization for a group of Timing Generators. */
2210static void dce110_enable_timing_synchronization( 2210static void dce110_enable_timing_synchronization(
2211 struct core_dc *dc, 2211 struct dc *dc,
2212 int group_index, 2212 int group_index,
2213 int group_size, 2213 int group_size,
2214 struct pipe_ctx *grouped_pipes[]) 2214 struct pipe_ctx *grouped_pipes[])
@@ -2257,7 +2257,7 @@ static void dce110_enable_timing_synchronization(
2257 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2257 DC_SYNC_INFO("GSL: Set-up complete.\n");
2258} 2258}
2259 2259
2260static void init_hw(struct core_dc *dc) 2260static void init_hw(struct dc *dc)
2261{ 2261{
2262 int i; 2262 int i;
2263 struct dc_bios *bp; 2263 struct dc_bios *bp;
@@ -2394,7 +2394,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
2394} 2394}
2395 2395
2396static int determine_sclk_from_bounding_box( 2396static int determine_sclk_from_bounding_box(
2397 const struct core_dc *dc, 2397 const struct dc *dc,
2398 int required_sclk) 2398 int required_sclk)
2399{ 2399{
2400 int i; 2400 int i;
@@ -2420,7 +2420,7 @@ static int determine_sclk_from_bounding_box(
2420} 2420}
2421 2421
2422static void pplib_apply_display_requirements( 2422static void pplib_apply_display_requirements(
2423 struct core_dc *dc, 2423 struct dc *dc,
2424 struct validate_context *context) 2424 struct validate_context *context)
2425{ 2425{
2426 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2426 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
@@ -2474,7 +2474,7 @@ static void pplib_apply_display_requirements(
2474} 2474}
2475 2475
2476static void dce110_set_bandwidth( 2476static void dce110_set_bandwidth(
2477 struct core_dc *dc, 2477 struct dc *dc,
2478 struct validate_context *context, 2478 struct validate_context *context,
2479 bool decrease_allowed) 2479 bool decrease_allowed)
2480{ 2480{
@@ -2491,7 +2491,7 @@ static void dce110_set_bandwidth(
2491} 2491}
2492 2492
2493static void dce110_program_front_end_for_pipe( 2493static void dce110_program_front_end_for_pipe(
2494 struct core_dc *dc, struct pipe_ctx *pipe_ctx) 2494 struct dc *dc, struct pipe_ctx *pipe_ctx)
2495{ 2495{
2496 struct mem_input *mi = pipe_ctx->plane_res.mi; 2496 struct mem_input *mi = pipe_ctx->plane_res.mi;
2497 struct pipe_ctx *old_pipe = NULL; 2497 struct pipe_ctx *old_pipe = NULL;
@@ -2572,7 +2572,7 @@ static void dce110_program_front_end_for_pipe(
2572 if (mi->funcs->set_blank) 2572 if (mi->funcs->set_blank)
2573 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2573 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2574 2574
2575 if (dc->public.config.gpu_vm_support) 2575 if (dc->config.gpu_vm_support)
2576 mi->funcs->mem_input_program_pte_vm( 2576 mi->funcs->mem_input_program_pte_vm(
2577 pipe_ctx->plane_res.mi, 2577 pipe_ctx->plane_res.mi,
2578 plane_state->format, 2578 plane_state->format,
@@ -2618,7 +2618,7 @@ static void dce110_program_front_end_for_pipe(
2618} 2618}
2619 2619
2620static void dce110_apply_ctx_for_surface( 2620static void dce110_apply_ctx_for_surface(
2621 struct core_dc *dc, 2621 struct dc *dc,
2622 const struct dc_stream_state *stream, 2622 const struct dc_stream_state *stream,
2623 int num_planes, 2623 int num_planes,
2624 struct validate_context *context) 2624 struct validate_context *context)
@@ -2648,7 +2648,7 @@ static void dce110_apply_ctx_for_surface(
2648 } 2648 }
2649} 2649}
2650 2650
2651static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) 2651static void dce110_power_down_fe(struct dc *dc, int fe_idx)
2652{ 2652{
2653 /* Do not power down fe when stream is active on dce*/ 2653 /* Do not power down fe when stream is active on dce*/
2654 if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) 2654 if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream)
@@ -2662,7 +2662,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
2662} 2662}
2663 2663
2664static void dce110_wait_for_mpcc_disconnect( 2664static void dce110_wait_for_mpcc_disconnect(
2665 struct core_dc *dc, 2665 struct dc *dc,
2666 struct resource_pool *res_pool, 2666 struct resource_pool *res_pool,
2667 struct pipe_ctx *pipe_ctx) 2667 struct pipe_ctx *pipe_ctx)
2668{ 2668{
@@ -2724,7 +2724,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
2724 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect 2724 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect
2725}; 2725};
2726 2726
2727bool dce110_hw_sequencer_construct(struct core_dc *dc) 2727bool dce110_hw_sequencer_construct(struct dc *dc)
2728{ 2728{
2729 dc->hwss = dce110_funcs; 2729 dc->hwss = dce110_funcs;
2730 2730
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index 89782ca1917f..d710f6e6dc07 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -29,20 +29,20 @@
29#include "core_types.h" 29#include "core_types.h"
30 30
31#define GAMMA_HW_POINTS_NUM 256 31#define GAMMA_HW_POINTS_NUM 256
32struct core_dc; 32struct dc;
33struct validate_context; 33struct validate_context;
34struct dm_pp_display_configuration; 34struct dm_pp_display_configuration;
35 35
36bool dce110_hw_sequencer_construct(struct core_dc *dc); 36bool dce110_hw_sequencer_construct(struct dc *dc);
37 37
38enum dc_status dce110_apply_ctx_to_hw( 38enum dc_status dce110_apply_ctx_to_hw(
39 struct core_dc *dc, 39 struct dc *dc,
40 struct validate_context *context); 40 struct validate_context *context);
41 41
42void dce110_set_display_clock(struct validate_context *context); 42void dce110_set_display_clock(struct validate_context *context);
43 43
44void dce110_set_displaymarks( 44void dce110_set_displaymarks(
45 const struct core_dc *dc, 45 const struct dc *dc,
46 struct validate_context *context); 46 struct validate_context *context);
47 47
48void dce110_enable_stream(struct pipe_ctx *pipe_ctx); 48void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
@@ -55,9 +55,9 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
55void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); 55void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
56 56
57void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 57void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
58void dce110_enable_accelerated_mode(struct core_dc *dc); 58void dce110_enable_accelerated_mode(struct dc *dc);
59 59
60void dce110_power_down(struct core_dc *dc); 60void dce110_power_down(struct dc *dc);
61 61
62void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); 62void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
63 63
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 56be84ce5a0d..2154c2e567f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -772,7 +772,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne
772} 772}
773 773
774static enum dc_status build_mapped_resource( 774static enum dc_status build_mapped_resource(
775 const struct core_dc *dc, 775 const struct dc *dc,
776 struct validate_context *context, 776 struct validate_context *context,
777 struct validate_context *old_context) 777 struct validate_context *old_context)
778{ 778{
@@ -814,7 +814,7 @@ static enum dc_status build_mapped_resource(
814} 814}
815 815
816static bool dce110_validate_bandwidth( 816static bool dce110_validate_bandwidth(
817 const struct core_dc *dc, 817 struct dc *dc,
818 struct validate_context *context) 818 struct validate_context *context)
819{ 819{
820 bool result = false; 820 bool result = false;
@@ -928,7 +928,7 @@ static bool dce110_validate_surface_sets(
928} 928}
929 929
930static enum dc_status dce110_validate_with_context( 930static enum dc_status dce110_validate_with_context(
931 const struct core_dc *dc, 931 struct dc *dc,
932 const struct dc_validation_set set[], 932 const struct dc_validation_set set[],
933 int set_count, 933 int set_count,
934 struct validate_context *context, 934 struct validate_context *context,
@@ -972,7 +972,7 @@ static enum dc_status dce110_validate_with_context(
972} 972}
973 973
974static enum dc_status dce110_validate_guaranteed( 974static enum dc_status dce110_validate_guaranteed(
975 const struct core_dc *dc, 975 struct dc *dc,
976 struct dc_stream_state *dc_stream, 976 struct dc_stream_state *dc_stream,
977 struct validate_context *context) 977 struct validate_context *context)
978{ 978{
@@ -992,7 +992,7 @@ static enum dc_status dce110_validate_guaranteed(
992 992
993 if (result == DC_OK) { 993 if (result == DC_OK) {
994 validate_guaranteed_copy_streams( 994 validate_guaranteed_copy_streams(
995 context, dc->public.caps.max_streams); 995 context, dc->caps.max_streams);
996 result = resource_build_scaling_params_for_context(dc, context); 996 result = resource_build_scaling_params_for_context(dc, context);
997 } 997 }
998 998
@@ -1008,7 +1008,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
1008 const struct resource_pool *pool, 1008 const struct resource_pool *pool,
1009 struct dc_stream_state *stream) 1009 struct dc_stream_state *stream)
1010{ 1010{
1011 struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); 1011 struct dc *dc = stream->ctx->dc;
1012 struct resource_context *res_ctx = &context->res_ctx; 1012 struct resource_context *res_ctx = &context->res_ctx;
1013 unsigned int underlay_idx = pool->underlay_pipe_index; 1013 unsigned int underlay_idx = pool->underlay_pipe_index;
1014 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1014 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
@@ -1117,7 +1117,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1117 return true; 1117 return true;
1118} 1118}
1119 1119
1120static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 1120static void bw_calcs_data_update_from_pplib(struct dc *dc)
1121{ 1121{
1122 struct dm_pp_clock_levels clks = {0}; 1122 struct dm_pp_clock_levels clks = {0};
1123 1123
@@ -1184,7 +1184,7 @@ const struct resource_caps *dce110_resource_cap(
1184 1184
1185static bool construct( 1185static bool construct(
1186 uint8_t num_virtual_links, 1186 uint8_t num_virtual_links,
1187 struct core_dc *dc, 1187 struct dc *dc,
1188 struct dce110_resource_pool *pool, 1188 struct dce110_resource_pool *pool,
1189 struct hw_asic_id asic_id) 1189 struct hw_asic_id asic_id)
1190{ 1190{
@@ -1206,9 +1206,9 @@ static bool construct(
1206 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1206 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1207 pool->base.underlay_pipe_index = pool->base.pipe_count; 1207 pool->base.underlay_pipe_index = pool->base.pipe_count;
1208 1208
1209 dc->public.caps.max_downscale_ratio = 150; 1209 dc->caps.max_downscale_ratio = 150;
1210 dc->public.caps.i2c_speed_in_khz = 100; 1210 dc->caps.i2c_speed_in_khz = 100;
1211 dc->public.caps.max_cursor_size = 128; 1211 dc->caps.max_cursor_size = 128;
1212 1212
1213 /************************************************* 1213 /*************************************************
1214 * Create resources * 1214 * Create resources *
@@ -1351,7 +1351,7 @@ static bool construct(
1351 if (!dce110_hw_sequencer_construct(dc)) 1351 if (!dce110_hw_sequencer_construct(dc))
1352 goto res_create_fail; 1352 goto res_create_fail;
1353 1353
1354 dc->public.caps.max_planes = pool->base.pipe_count; 1354 dc->caps.max_planes = pool->base.pipe_count;
1355 1355
1356 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1356 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1357 1357
@@ -1366,7 +1366,7 @@ res_create_fail:
1366 1366
1367struct resource_pool *dce110_create_resource_pool( 1367struct resource_pool *dce110_create_resource_pool(
1368 uint8_t num_virtual_links, 1368 uint8_t num_virtual_links,
1369 struct core_dc *dc, 1369 struct dc *dc,
1370 struct hw_asic_id asic_id) 1370 struct hw_asic_id asic_id)
1371{ 1371{
1372 struct dce110_resource_pool *pool = 1372 struct dce110_resource_pool *pool =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
index 8e2e85dd30b9..5bb692d037d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
@@ -28,7 +28,7 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32struct resource_pool; 32struct resource_pool;
33 33
34#define TO_DCE110_RES_POOL(pool)\ 34#define TO_DCE110_RES_POOL(pool)\
@@ -42,7 +42,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
42 42
43struct resource_pool *dce110_create_resource_pool( 43struct resource_pool *dce110_create_resource_pool(
44 uint8_t num_virtual_links, 44 uint8_t num_virtual_links,
45 struct core_dc *dc, 45 struct dc *dc,
46 struct hw_asic_id asic_id); 46 struct hw_asic_id asic_id);
47 47
48#endif /* __DC_RESOURCE_DCE110_H__ */ 48#endif /* __DC_RESOURCE_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
index 204f613467b7..8816e09110e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
@@ -25,7 +25,6 @@
25 25
26#include "dm_services.h" 26#include "dm_services.h"
27#include "dc.h" 27#include "dc.h"
28#include "core_dc.h"
29#include "core_types.h" 28#include "core_types.h"
30#include "dce112_hw_sequencer.h" 29#include "dce112_hw_sequencer.h"
31 30
@@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx)
112} 111}
113 112
114static bool dce112_enable_display_power_gating( 113static bool dce112_enable_display_power_gating(
115 struct core_dc *dc, 114 struct dc *dc,
116 uint8_t controller_id, 115 uint8_t controller_id,
117 struct dc_bios *dcb, 116 struct dc_bios *dcb,
118 enum pipe_gating_control power_gating) 117 enum pipe_gating_control power_gating)
@@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating(
153 return false; 152 return false;
154} 153}
155 154
156bool dce112_hw_sequencer_construct(struct core_dc *dc) 155bool dce112_hw_sequencer_construct(struct dc *dc)
157{ 156{
158 /* All registers used by dce11.2 match those in dce11 in offset and 157 /* All registers used by dce11.2 match those in dce11 in offset and
159 * structure 158 * structure
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
index d96c582da45c..37bd60cc93f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
@@ -28,9 +28,9 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32 32
33bool dce112_hw_sequencer_construct(struct core_dc *dc); 33bool dce112_hw_sequencer_construct(struct dc *dc);
34 34
35#endif /* __DC_HWSS_DCE112_H__ */ 35#endif /* __DC_HWSS_DCE112_H__ */
36 36
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index d6e58a25f3d0..89a8dfa68c01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll(
723} 723}
724 724
725static enum dc_status build_mapped_resource( 725static enum dc_status build_mapped_resource(
726 const struct core_dc *dc, 726 const struct dc *dc,
727 struct validate_context *context, 727 struct validate_context *context,
728 struct validate_context *old_context) 728 struct validate_context *old_context)
729{ 729{
@@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource(
759} 759}
760 760
761bool dce112_validate_bandwidth( 761bool dce112_validate_bandwidth(
762 const struct core_dc *dc, 762 struct dc *dc,
763 struct validate_context *context) 763 struct validate_context *context)
764{ 764{
765 bool result = false; 765 bool result = false;
@@ -837,7 +837,7 @@ bool dce112_validate_bandwidth(
837} 837}
838 838
839enum dc_status resource_map_phy_clock_resources( 839enum dc_status resource_map_phy_clock_resources(
840 const struct core_dc *dc, 840 const struct dc *dc,
841 struct validate_context *context, 841 struct validate_context *context,
842 struct validate_context *old_context) 842 struct validate_context *old_context)
843{ 843{
@@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets(
904} 904}
905 905
906enum dc_status dce112_validate_with_context( 906enum dc_status dce112_validate_with_context(
907 const struct core_dc *dc, 907 struct dc *dc,
908 const struct dc_validation_set set[], 908 const struct dc_validation_set set[],
909 int set_count, 909 int set_count,
910 struct validate_context *context, 910 struct validate_context *context,
@@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context(
948} 948}
949 949
950enum dc_status dce112_validate_guaranteed( 950enum dc_status dce112_validate_guaranteed(
951 const struct core_dc *dc, 951 struct dc *dc,
952 struct dc_stream_state *stream, 952 struct dc_stream_state *stream,
953 struct validate_context *context) 953 struct validate_context *context)
954{ 954{
@@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed(
968 968
969 if (result == DC_OK) { 969 if (result == DC_OK) {
970 validate_guaranteed_copy_streams( 970 validate_guaranteed_copy_streams(
971 context, dc->public.caps.max_streams); 971 context, dc->caps.max_streams);
972 result = resource_build_scaling_params_for_context(dc, context); 972 result = resource_build_scaling_params_for_context(dc, context);
973 } 973 }
974 974
@@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = {
997 .validate_plane = dce100_validate_plane 997 .validate_plane = dce100_validate_plane
998}; 998};
999 999
1000static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 1000static void bw_calcs_data_update_from_pplib(struct dc *dc)
1001{ 1001{
1002 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 1002 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1003 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 1003 struct dm_pp_clock_levels_with_latency mem_clks = {0};
@@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap(
1153 1153
1154static bool construct( 1154static bool construct(
1155 uint8_t num_virtual_links, 1155 uint8_t num_virtual_links,
1156 struct core_dc *dc, 1156 struct dc *dc,
1157 struct dce110_resource_pool *pool) 1157 struct dce110_resource_pool *pool)
1158{ 1158{
1159 unsigned int i; 1159 unsigned int i;
@@ -1170,9 +1170,9 @@ static bool construct(
1170 *************************************************/ 1170 *************************************************/
1171 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1171 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1172 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1172 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1173 dc->public.caps.max_downscale_ratio = 200; 1173 dc->caps.max_downscale_ratio = 200;
1174 dc->public.caps.i2c_speed_in_khz = 100; 1174 dc->caps.i2c_speed_in_khz = 100;
1175 dc->public.caps.max_cursor_size = 128; 1175 dc->caps.max_cursor_size = 128;
1176 1176
1177 /************************************************* 1177 /*************************************************
1178 * Create resources * 1178 * Create resources *
@@ -1319,7 +1319,7 @@ static bool construct(
1319 &res_create_funcs)) 1319 &res_create_funcs))
1320 goto res_create_fail; 1320 goto res_create_fail;
1321 1321
1322 dc->public.caps.max_planes = pool->base.pipe_count; 1322 dc->caps.max_planes = pool->base.pipe_count;
1323 1323
1324 /* Create hardware sequencer */ 1324 /* Create hardware sequencer */
1325 if (!dce112_hw_sequencer_construct(dc)) 1325 if (!dce112_hw_sequencer_construct(dc))
@@ -1338,7 +1338,7 @@ res_create_fail:
1338 1338
1339struct resource_pool *dce112_create_resource_pool( 1339struct resource_pool *dce112_create_resource_pool(
1340 uint8_t num_virtual_links, 1340 uint8_t num_virtual_links,
1341 struct core_dc *dc) 1341 struct dc *dc)
1342{ 1342{
1343 struct dce110_resource_pool *pool = 1343 struct dce110_resource_pool *pool =
1344 dm_alloc(sizeof(struct dce110_resource_pool)); 1344 dm_alloc(sizeof(struct dce110_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
index feef559f1ecd..69f8f689196d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
@@ -28,27 +28,27 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32struct resource_pool; 32struct resource_pool;
33 33
34struct resource_pool *dce112_create_resource_pool( 34struct resource_pool *dce112_create_resource_pool(
35 uint8_t num_virtual_links, 35 uint8_t num_virtual_links,
36 struct core_dc *dc); 36 struct dc *dc);
37 37
38enum dc_status dce112_validate_with_context( 38enum dc_status dce112_validate_with_context(
39 const struct core_dc *dc, 39 struct dc *dc,
40 const struct dc_validation_set set[], 40 const struct dc_validation_set set[],
41 int set_count, 41 int set_count,
42 struct validate_context *context, 42 struct validate_context *context,
43 struct validate_context *old_context); 43 struct validate_context *old_context);
44 44
45enum dc_status dce112_validate_guaranteed( 45enum dc_status dce112_validate_guaranteed(
46 const struct core_dc *dc, 46 struct dc *dc,
47 struct dc_stream_state *dc_stream, 47 struct dc_stream_state *dc_stream,
48 struct validate_context *context); 48 struct validate_context *context);
49 49
50bool dce112_validate_bandwidth( 50bool dce112_validate_bandwidth(
51 const struct core_dc *dc, 51 struct dc *dc,
52 struct validate_context *context); 52 struct validate_context *context);
53 53
54 54
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
index 91301b412aa0..d6225f332431 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -25,7 +25,6 @@
25 25
26#include "dm_services.h" 26#include "dm_services.h"
27#include "dc.h" 27#include "dc.h"
28#include "core_dc.h"
29#include "core_types.h" 28#include "core_types.h"
30#include "dce120_hw_sequencer.h" 29#include "dce120_hw_sequencer.h"
31#include "dce/dce_hwseq.h" 30#include "dce/dce_hwseq.h"
@@ -149,7 +148,7 @@ static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
149#endif 148#endif
150 149
151static bool dce120_enable_display_power_gating( 150static bool dce120_enable_display_power_gating(
152 struct core_dc *dc, 151 struct dc *dc,
153 uint8_t controller_id, 152 uint8_t controller_id,
154 struct dc_bios *dcb, 153 struct dc_bios *dcb,
155 enum pipe_gating_control power_gating) 154 enum pipe_gating_control power_gating)
@@ -247,7 +246,7 @@ static void dce120_update_dchub(
247 246
248 247
249 248
250bool dce120_hw_sequencer_construct(struct core_dc *dc) 249bool dce120_hw_sequencer_construct(struct dc *dc)
251{ 250{
252 /* All registers used by dce11.2 match those in dce11 in offset and 251 /* All registers used by dce11.2 match those in dce11 in offset and
253 * structure 252 * structure
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
index 3402413c7156..6448a17c2fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
@@ -28,9 +28,9 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32 32
33bool dce120_hw_sequencer_construct(struct core_dc *dc); 33bool dce120_hw_sequencer_construct(struct dc *dc);
34 34
35#endif /* __DC_HWSS_DCE112_H__ */ 35#endif /* __DC_HWSS_DCE112_H__ */
36 36
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 562ae2205a90..b8fcdff40db3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -410,7 +410,7 @@ void dce120_clock_source_destroy(struct clock_source **clk_src)
410} 410}
411 411
412 412
413bool dce120_hw_sequencer_create(struct core_dc *dc) 413bool dce120_hw_sequencer_create(struct dc *dc)
414{ 414{
415 /* All registers used by dce11.2 match those in dce11 in offset and 415 /* All registers used by dce11.2 match those in dce11 in offset and
416 * structure 416 * structure
@@ -704,7 +704,7 @@ static const struct resource_funcs dce120_res_pool_funcs = {
704 .validate_plane = dce100_validate_plane 704 .validate_plane = dce100_validate_plane
705}; 705};
706 706
707static void bw_calcs_data_update_from_pplib(struct core_dc *dc) 707static void bw_calcs_data_update_from_pplib(struct dc *dc)
708{ 708{
709 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 709 struct dm_pp_clock_levels_with_latency eng_clks = {0};
710 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 710 struct dm_pp_clock_levels_with_latency mem_clks = {0};
@@ -831,7 +831,7 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
831 831
832static bool construct( 832static bool construct(
833 uint8_t num_virtual_links, 833 uint8_t num_virtual_links,
834 struct core_dc *dc, 834 struct dc *dc,
835 struct dce110_resource_pool *pool) 835 struct dce110_resource_pool *pool)
836{ 836{
837 unsigned int i; 837 unsigned int i;
@@ -847,10 +847,10 @@ static bool construct(
847 pool->base.pipe_count = res_cap.num_timing_generator; 847 pool->base.pipe_count = res_cap.num_timing_generator;
848 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 848 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
849 849
850 dc->public.caps.max_downscale_ratio = 200; 850 dc->caps.max_downscale_ratio = 200;
851 dc->public.caps.i2c_speed_in_khz = 100; 851 dc->caps.i2c_speed_in_khz = 100;
852 dc->public.caps.max_cursor_size = 128; 852 dc->caps.max_cursor_size = 128;
853 dc->public.debug = debug_defaults; 853 dc->debug = debug_defaults;
854 854
855 /************************************************* 855 /*************************************************
856 * Create resources * 856 * Create resources *
@@ -982,7 +982,7 @@ static bool construct(
982 if (!dce120_hw_sequencer_create(dc)) 982 if (!dce120_hw_sequencer_create(dc))
983 goto controller_create_fail; 983 goto controller_create_fail;
984 984
985 dc->public.caps.max_planes = pool->base.pipe_count; 985 dc->caps.max_planes = pool->base.pipe_count;
986 986
987 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 987 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
988 988
@@ -1003,7 +1003,7 @@ res_create_fail:
1003 1003
1004struct resource_pool *dce120_create_resource_pool( 1004struct resource_pool *dce120_create_resource_pool(
1005 uint8_t num_virtual_links, 1005 uint8_t num_virtual_links,
1006 struct core_dc *dc) 1006 struct dc *dc)
1007{ 1007{
1008 struct dce110_resource_pool *pool = 1008 struct dce110_resource_pool *pool =
1009 dm_alloc(sizeof(struct dce110_resource_pool)); 1009 dm_alloc(sizeof(struct dce110_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
index 038c78dcc247..3d1f3cf012f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
@@ -28,12 +28,12 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32struct resource_pool; 32struct resource_pool;
33 33
34struct resource_pool *dce120_create_resource_pool( 34struct resource_pool *dce120_create_resource_pool(
35 uint8_t num_virtual_links, 35 uint8_t num_virtual_links,
36 struct core_dc *dc); 36 struct dc *dc);
37 37
38#endif /* __DC_RESOURCE_DCE120_H__ */ 38#endif /* __DC_RESOURCE_DCE120_H__ */
39 39
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
index 4cba80ff6ca4..28fe3824441f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
@@ -25,7 +25,6 @@
25 25
26#include "dm_services.h" 26#include "dm_services.h"
27#include "dc.h" 27#include "dc.h"
28#include "core_dc.h"
29#include "core_types.h" 28#include "core_types.h"
30#include "dce80_hw_sequencer.h" 29#include "dce80_hw_sequencer.h"
31 30
@@ -72,7 +71,7 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
72/***************************PIPE_CONTROL***********************************/ 71/***************************PIPE_CONTROL***********************************/
73 72
74static bool dce80_enable_display_power_gating( 73static bool dce80_enable_display_power_gating(
75 struct core_dc *dc, 74 struct dc *dc,
76 uint8_t controller_id, 75 uint8_t controller_id,
77 struct dc_bios *dcb, 76 struct dc_bios *dcb,
78 enum pipe_gating_control power_gating) 77 enum pipe_gating_control power_gating)
@@ -107,7 +106,7 @@ static bool dce80_enable_display_power_gating(
107 return false; 106 return false;
108} 107}
109 108
110bool dce80_hw_sequencer_construct(struct core_dc *dc) 109bool dce80_hw_sequencer_construct(struct dc *dc)
111{ 110{
112 dce110_hw_sequencer_construct(dc); 111 dce110_hw_sequencer_construct(dc);
113 112
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
index 7cc203f433d3..9d6dd05bd596 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
@@ -28,9 +28,9 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32 32
33bool dce80_hw_sequencer_construct(struct core_dc *dc); 33bool dce80_hw_sequencer_construct(struct dc *dc);
34 34
35#endif /* __DC_HWSS_DCE80_H__ */ 35#endif /* __DC_HWSS_DCE80_H__ */
36 36
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 132117e8bb77..838bfdaee009 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -684,7 +684,7 @@ static void destruct(struct dce110_resource_pool *pool)
684} 684}
685 685
686static enum dc_status build_mapped_resource( 686static enum dc_status build_mapped_resource(
687 const struct core_dc *dc, 687 const struct dc *dc,
688 struct validate_context *context, 688 struct validate_context *context,
689 struct validate_context *old_context) 689 struct validate_context *old_context)
690{ 690{
@@ -720,7 +720,7 @@ static enum dc_status build_mapped_resource(
720} 720}
721 721
722bool dce80_validate_bandwidth( 722bool dce80_validate_bandwidth(
723 const struct core_dc *dc, 723 struct dc *dc,
724 struct validate_context *context) 724 struct validate_context *context)
725{ 725{
726 /* TODO implement when needed but for now hardcode max value*/ 726 /* TODO implement when needed but for now hardcode max value*/
@@ -752,7 +752,7 @@ static bool dce80_validate_surface_sets(
752} 752}
753 753
754enum dc_status dce80_validate_with_context( 754enum dc_status dce80_validate_with_context(
755 const struct core_dc *dc, 755 struct dc *dc,
756 const struct dc_validation_set set[], 756 const struct dc_validation_set set[],
757 int set_count, 757 int set_count,
758 struct validate_context *context, 758 struct validate_context *context,
@@ -795,7 +795,7 @@ enum dc_status dce80_validate_with_context(
795} 795}
796 796
797enum dc_status dce80_validate_guaranteed( 797enum dc_status dce80_validate_guaranteed(
798 const struct core_dc *dc, 798 struct dc *dc,
799 struct dc_stream_state *dc_stream, 799 struct dc_stream_state *dc_stream,
800 struct validate_context *context) 800 struct validate_context *context)
801{ 801{
@@ -815,7 +815,7 @@ enum dc_status dce80_validate_guaranteed(
815 815
816 if (result == DC_OK) { 816 if (result == DC_OK) {
817 validate_guaranteed_copy_streams( 817 validate_guaranteed_copy_streams(
818 context, dc->public.caps.max_streams); 818 context, dc->caps.max_streams);
819 result = resource_build_scaling_params_for_context(dc, context); 819 result = resource_build_scaling_params_for_context(dc, context);
820 } 820 }
821 821
@@ -845,7 +845,7 @@ static const struct resource_funcs dce80_res_pool_funcs = {
845 845
846static bool dce80_construct( 846static bool dce80_construct(
847 uint8_t num_virtual_links, 847 uint8_t num_virtual_links,
848 struct core_dc *dc, 848 struct dc *dc,
849 struct dce110_resource_pool *pool) 849 struct dce110_resource_pool *pool)
850{ 850{
851 unsigned int i; 851 unsigned int i;
@@ -865,9 +865,9 @@ static bool dce80_construct(
865 *************************************************/ 865 *************************************************/
866 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 866 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
867 pool->base.pipe_count = res_cap.num_timing_generator; 867 pool->base.pipe_count = res_cap.num_timing_generator;
868 dc->public.caps.max_downscale_ratio = 200; 868 dc->caps.max_downscale_ratio = 200;
869 dc->public.caps.i2c_speed_in_khz = 40; 869 dc->caps.i2c_speed_in_khz = 40;
870 dc->public.caps.max_cursor_size = 128; 870 dc->caps.max_cursor_size = 128;
871 871
872 /************************************************* 872 /*************************************************
873 * Create resources * 873 * Create resources *
@@ -974,7 +974,7 @@ static bool dce80_construct(
974 } 974 }
975 } 975 }
976 976
977 dc->public.caps.max_planes = pool->base.pipe_count; 977 dc->caps.max_planes = pool->base.pipe_count;
978 978
979 if (!resource_construct(num_virtual_links, dc, &pool->base, 979 if (!resource_construct(num_virtual_links, dc, &pool->base,
980 &res_create_funcs)) 980 &res_create_funcs))
@@ -993,7 +993,7 @@ res_create_fail:
993 993
994struct resource_pool *dce80_create_resource_pool( 994struct resource_pool *dce80_create_resource_pool(
995 uint8_t num_virtual_links, 995 uint8_t num_virtual_links,
996 struct core_dc *dc) 996 struct dc *dc)
997{ 997{
998 struct dce110_resource_pool *pool = 998 struct dce110_resource_pool *pool =
999 dm_alloc(sizeof(struct dce110_resource_pool)); 999 dm_alloc(sizeof(struct dce110_resource_pool));
@@ -1010,7 +1010,7 @@ struct resource_pool *dce80_create_resource_pool(
1010 1010
1011static bool dce81_construct( 1011static bool dce81_construct(
1012 uint8_t num_virtual_links, 1012 uint8_t num_virtual_links,
1013 struct core_dc *dc, 1013 struct dc *dc,
1014 struct dce110_resource_pool *pool) 1014 struct dce110_resource_pool *pool)
1015{ 1015{
1016 unsigned int i; 1016 unsigned int i;
@@ -1030,9 +1030,9 @@ static bool dce81_construct(
1030 *************************************************/ 1030 *************************************************/
1031 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1031 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1032 pool->base.pipe_count = res_cap_81.num_timing_generator; 1032 pool->base.pipe_count = res_cap_81.num_timing_generator;
1033 dc->public.caps.max_downscale_ratio = 200; 1033 dc->caps.max_downscale_ratio = 200;
1034 dc->public.caps.i2c_speed_in_khz = 40; 1034 dc->caps.i2c_speed_in_khz = 40;
1035 dc->public.caps.max_cursor_size = 128; 1035 dc->caps.max_cursor_size = 128;
1036 1036
1037 /************************************************* 1037 /*************************************************
1038 * Create resources * 1038 * Create resources *
@@ -1139,7 +1139,7 @@ static bool dce81_construct(
1139 } 1139 }
1140 } 1140 }
1141 1141
1142 dc->public.caps.max_planes = pool->base.pipe_count; 1142 dc->caps.max_planes = pool->base.pipe_count;
1143 1143
1144 if (!resource_construct(num_virtual_links, dc, &pool->base, 1144 if (!resource_construct(num_virtual_links, dc, &pool->base,
1145 &res_create_funcs)) 1145 &res_create_funcs))
@@ -1158,7 +1158,7 @@ res_create_fail:
1158 1158
1159struct resource_pool *dce81_create_resource_pool( 1159struct resource_pool *dce81_create_resource_pool(
1160 uint8_t num_virtual_links, 1160 uint8_t num_virtual_links,
1161 struct core_dc *dc) 1161 struct dc *dc)
1162{ 1162{
1163 struct dce110_resource_pool *pool = 1163 struct dce110_resource_pool *pool =
1164 dm_alloc(sizeof(struct dce110_resource_pool)); 1164 dm_alloc(sizeof(struct dce110_resource_pool));
@@ -1175,7 +1175,7 @@ struct resource_pool *dce81_create_resource_pool(
1175 1175
1176static bool dce83_construct( 1176static bool dce83_construct(
1177 uint8_t num_virtual_links, 1177 uint8_t num_virtual_links,
1178 struct core_dc *dc, 1178 struct dc *dc,
1179 struct dce110_resource_pool *pool) 1179 struct dce110_resource_pool *pool)
1180{ 1180{
1181 unsigned int i; 1181 unsigned int i;
@@ -1195,9 +1195,9 @@ static bool dce83_construct(
1195 *************************************************/ 1195 *************************************************/
1196 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1196 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1197 pool->base.pipe_count = res_cap_83.num_timing_generator; 1197 pool->base.pipe_count = res_cap_83.num_timing_generator;
1198 dc->public.caps.max_downscale_ratio = 200; 1198 dc->caps.max_downscale_ratio = 200;
1199 dc->public.caps.i2c_speed_in_khz = 40; 1199 dc->caps.i2c_speed_in_khz = 40;
1200 dc->public.caps.max_cursor_size = 128; 1200 dc->caps.max_cursor_size = 128;
1201 1201
1202 /************************************************* 1202 /*************************************************
1203 * Create resources * 1203 * Create resources *
@@ -1300,7 +1300,7 @@ static bool dce83_construct(
1300 } 1300 }
1301 } 1301 }
1302 1302
1303 dc->public.caps.max_planes = pool->base.pipe_count; 1303 dc->caps.max_planes = pool->base.pipe_count;
1304 1304
1305 if (!resource_construct(num_virtual_links, dc, &pool->base, 1305 if (!resource_construct(num_virtual_links, dc, &pool->base,
1306 &res_create_funcs)) 1306 &res_create_funcs))
@@ -1319,7 +1319,7 @@ res_create_fail:
1319 1319
1320struct resource_pool *dce83_create_resource_pool( 1320struct resource_pool *dce83_create_resource_pool(
1321 uint8_t num_virtual_links, 1321 uint8_t num_virtual_links,
1322 struct core_dc *dc) 1322 struct dc *dc)
1323{ 1323{
1324 struct dce110_resource_pool *pool = 1324 struct dce110_resource_pool *pool =
1325 dm_alloc(sizeof(struct dce110_resource_pool)); 1325 dm_alloc(sizeof(struct dce110_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h
index 04f0cfe24ef2..eff31ab83a39 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h
@@ -28,20 +28,20 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32struct resource_pool; 32struct resource_pool;
33 33
34struct resource_pool *dce80_create_resource_pool( 34struct resource_pool *dce80_create_resource_pool(
35 uint8_t num_virtual_links, 35 uint8_t num_virtual_links,
36 struct core_dc *dc); 36 struct dc *dc);
37 37
38struct resource_pool *dce81_create_resource_pool( 38struct resource_pool *dce81_create_resource_pool(
39 uint8_t num_virtual_links, 39 uint8_t num_virtual_links,
40 struct core_dc *dc); 40 struct dc *dc);
41 41
42struct resource_pool *dce83_create_resource_pool( 42struct resource_pool *dce83_create_resource_pool(
43 uint8_t num_virtual_links, 43 uint8_t num_virtual_links,
44 struct core_dc *dc); 44 struct dc *dc);
45 45
46#endif /* __DC_RESOURCE_DCE80_H__ */ 46#endif /* __DC_RESOURCE_DCE80_H__ */
47 47
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
index 11386121f8ed..684241cb40d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
@@ -26,7 +26,6 @@
26#if defined(CONFIG_DRM_AMD_DC_DCN1_0) 26#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
27 27
28#include "reg_helper.h" 28#include "reg_helper.h"
29#include "core_dc.h"
30#include "resource.h" 29#include "resource.h"
31#include "dwb.h" 30#include "dwb.h"
32#include "dcn10_dwb.h" 31#include "dcn10_dwb.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 184627c8685e..d5d2398d92b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -52,7 +52,7 @@
52#define FN(reg_name, field_name) \ 52#define FN(reg_name, field_name) \
53 hws->shifts->field_name, hws->masks->field_name 53 hws->shifts->field_name, hws->masks->field_name
54 54
55static void log_mpc_crc(struct core_dc *dc) 55static void log_mpc_crc(struct dc *dc)
56{ 56{
57 struct dc_context *dc_ctx = dc->ctx; 57 struct dc_context *dc_ctx = dc->ctx;
58 struct dce_hwseq *hws = dc->hwseq; 58 struct dce_hwseq *hws = dc->hwseq;
@@ -130,7 +130,7 @@ static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,
130 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 130 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
131} 131}
132 132
133static void dcn10_log_hubbub_state(struct core_dc *dc) 133static void dcn10_log_hubbub_state(struct dc *dc)
134{ 134{
135 struct dc_context *dc_ctx = dc->ctx; 135 struct dc_context *dc_ctx = dc->ctx;
136 struct dcn_hubbub_wm wm; 136 struct dcn_hubbub_wm wm;
@@ -157,7 +157,7 @@ static void dcn10_log_hubbub_state(struct core_dc *dc)
157 DTN_INFO("\n"); 157 DTN_INFO("\n");
158} 158}
159 159
160static void dcn10_log_hw_state(struct core_dc *dc) 160static void dcn10_log_hw_state(struct dc *dc)
161{ 161{
162 struct dc_context *dc_ctx = dc->ctx; 162 struct dc_context *dc_ctx = dc->ctx;
163 struct resource_pool *pool = dc->res_pool; 163 struct resource_pool *pool = dc->res_pool;
@@ -273,7 +273,7 @@ static void verify_allow_pstate_change_high(
273 forced_pstate_allow = true; 273 forced_pstate_allow = true;
274 274
275 if (should_log_hw_state) { 275 if (should_log_hw_state) {
276 dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); 276 dcn10_log_hw_state(hws->ctx->dc);
277 } 277 }
278 278
279 BREAK_TO_DEBUGGER(); 279 BREAK_TO_DEBUGGER();
@@ -746,7 +746,7 @@ static void power_on_plane(
746 "Un-gated front end for pipe %d\n", plane_id); 746 "Un-gated front end for pipe %d\n", plane_id);
747} 747}
748 748
749static void bios_golden_init(struct core_dc *dc) 749static void bios_golden_init(struct dc *dc)
750{ 750{
751 struct dc_bios *bp = dc->ctx->dc_bios; 751 struct dc_bios *bp = dc->ctx->dc_bios;
752 int i; 752 int i;
@@ -762,7 +762,7 @@ static void bios_golden_init(struct core_dc *dc)
762 } 762 }
763} 763}
764 764
765static void dcn10_init_hw(struct core_dc *dc) 765static void dcn10_init_hw(struct dc *dc)
766{ 766{
767 int i; 767 int i;
768 struct abm *abm = dc->res_pool->abm; 768 struct abm *abm = dc->res_pool->abm;
@@ -773,7 +773,7 @@ static void dcn10_init_hw(struct core_dc *dc)
773 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 773 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
774 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 774 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
775 775
776 if (!dc->public.debug.disable_clock_gate) { 776 if (!dc->debug.disable_clock_gate) {
777 /* enable all DCN clock gating */ 777 /* enable all DCN clock gating */
778 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 778 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
779 779
@@ -830,7 +830,7 @@ static void dcn10_init_hw(struct core_dc *dc)
830 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 830 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
831 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 831 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
832 832
833 if (!dc->public.debug.disable_clock_gate) { 833 if (!dc->debug.disable_clock_gate) {
834 /* enable all DCN clock gating */ 834 /* enable all DCN clock gating */
835 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 835 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
836 836
@@ -845,7 +845,7 @@ static void dcn10_init_hw(struct core_dc *dc)
845static enum dc_status dcn10_prog_pixclk_crtc_otg( 845static enum dc_status dcn10_prog_pixclk_crtc_otg(
846 struct pipe_ctx *pipe_ctx, 846 struct pipe_ctx *pipe_ctx,
847 struct validate_context *context, 847 struct validate_context *context,
848 struct core_dc *dc) 848 struct dc *dc)
849{ 849{
850 struct dc_stream_state *stream = pipe_ctx->stream; 850 struct dc_stream_state *stream = pipe_ctx->stream;
851 enum dc_color_space color_space; 851 enum dc_color_space color_space;
@@ -932,7 +932,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
932} 932}
933 933
934static void reset_back_end_for_pipe( 934static void reset_back_end_for_pipe(
935 struct core_dc *dc, 935 struct dc *dc,
936 struct pipe_ctx *pipe_ctx, 936 struct pipe_ctx *pipe_ctx,
937 struct validate_context *context) 937 struct validate_context *context)
938{ 938{
@@ -979,7 +979,7 @@ static void reset_back_end_for_pipe(
979} 979}
980 980
981/* trigger HW to start disconnect plane from stream on the next vsync */ 981/* trigger HW to start disconnect plane from stream on the next vsync */
982static void plane_atomic_disconnect(struct core_dc *dc, 982static void plane_atomic_disconnect(struct dc *dc,
983 int fe_idx) 983 int fe_idx)
984{ 984{
985 struct mem_input *mi = dc->res_pool->mis[fe_idx]; 985 struct mem_input *mi = dc->res_pool->mis[fe_idx];
@@ -1004,10 +1004,10 @@ static void plane_atomic_disconnect(struct core_dc *dc,
1004 if (opp_id == dc->res_pool->pipe_count) 1004 if (opp_id == dc->res_pool->pipe_count)
1005 return; 1005 return;
1006 1006
1007 if (dc->public.debug.sanity_checks) 1007 if (dc->debug.sanity_checks)
1008 verify_allow_pstate_change_high(dc->hwseq); 1008 verify_allow_pstate_change_high(dc->hwseq);
1009 mi->funcs->dcc_control(mi, false, false); 1009 mi->funcs->dcc_control(mi, false, false);
1010 if (dc->public.debug.sanity_checks) 1010 if (dc->debug.sanity_checks)
1011 verify_allow_pstate_change_high(dc->hwseq); 1011 verify_allow_pstate_change_high(dc->hwseq);
1012 1012
1013 mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx); 1013 mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx);
@@ -1015,7 +1015,7 @@ static void plane_atomic_disconnect(struct core_dc *dc,
1015 1015
1016/* disable HW used by plane. 1016/* disable HW used by plane.
1017 * note: cannot disable until disconnect is complete */ 1017 * note: cannot disable until disconnect is complete */
1018static void plane_atomic_disable(struct core_dc *dc, 1018static void plane_atomic_disable(struct dc *dc,
1019 int fe_idx) 1019 int fe_idx)
1020{ 1020{
1021 struct dce_hwseq *hws = dc->hwseq; 1021 struct dce_hwseq *hws = dc->hwseq;
@@ -1037,7 +1037,7 @@ static void plane_atomic_disable(struct core_dc *dc,
1037 mi->opp_id = 0xf; 1037 mi->opp_id = 0xf;
1038 mi->mpcc_id = 0xf; 1038 mi->mpcc_id = 0xf;
1039 1039
1040 if (dc->public.debug.sanity_checks) 1040 if (dc->debug.sanity_checks)
1041 verify_allow_pstate_change_high(dc->hwseq); 1041 verify_allow_pstate_change_high(dc->hwseq);
1042 1042
1043 REG_UPDATE(HUBP_CLK_CNTL[fe_idx], 1043 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
@@ -1049,7 +1049,7 @@ static void plane_atomic_disable(struct core_dc *dc,
1049 REG_UPDATE(OPP_PIPE_CONTROL[opp_id], 1049 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
1050 OPP_PIPE_CLOCK_EN, 0); 1050 OPP_PIPE_CLOCK_EN, 0);
1051 1051
1052 if (dc->public.debug.sanity_checks) 1052 if (dc->debug.sanity_checks)
1053 verify_allow_pstate_change_high(dc->hwseq); 1053 verify_allow_pstate_change_high(dc->hwseq);
1054} 1054}
1055 1055
@@ -1057,7 +1057,7 @@ static void plane_atomic_disable(struct core_dc *dc,
1057 * kill power to plane hw 1057 * kill power to plane hw
1058 * note: cannot power down until plane is disable 1058 * note: cannot power down until plane is disable
1059 */ 1059 */
1060static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) 1060static void plane_atomic_power_down(struct dc *dc, int fe_idx)
1061{ 1061{
1062 struct dce_hwseq *hws = dc->hwseq; 1062 struct dce_hwseq *hws = dc->hwseq;
1063 struct transform *xfm = dc->res_pool->transforms[fe_idx]; 1063 struct transform *xfm = dc->res_pool->transforms[fe_idx];
@@ -1072,13 +1072,13 @@ static void plane_atomic_power_down(struct core_dc *dc, int fe_idx)
1072 dm_logger_write(dc->ctx->logger, LOG_DC, 1072 dm_logger_write(dc->ctx->logger, LOG_DC,
1073 "Power gated front end %d\n", fe_idx); 1073 "Power gated front end %d\n", fe_idx);
1074 1074
1075 if (dc->public.debug.sanity_checks) 1075 if (dc->debug.sanity_checks)
1076 verify_allow_pstate_change_high(dc->hwseq); 1076 verify_allow_pstate_change_high(dc->hwseq);
1077} 1077}
1078 1078
1079 1079
1080static void reset_front_end( 1080static void reset_front_end(
1081 struct core_dc *dc, 1081 struct dc *dc,
1082 int fe_idx) 1082 int fe_idx)
1083{ 1083{
1084 struct dce_hwseq *hws = dc->hwseq; 1084 struct dce_hwseq *hws = dc->hwseq;
@@ -1097,7 +1097,7 @@ static void reset_front_end(
1097 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); 1097 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
1098 tg->funcs->unlock(tg); 1098 tg->funcs->unlock(tg);
1099 1099
1100 if (dc->public.debug.sanity_checks) 1100 if (dc->debug.sanity_checks)
1101 verify_allow_pstate_change_high(hws); 1101 verify_allow_pstate_change_high(hws);
1102 1102
1103 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 1103 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
@@ -1112,7 +1112,7 @@ static void reset_front_end(
1112 fe_idx); 1112 fe_idx);
1113} 1113}
1114 1114
1115static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) 1115static void dcn10_power_down_fe(struct dc *dc, int fe_idx)
1116{ 1116{
1117 struct dce_hwseq *hws = dc->hwseq; 1117 struct dce_hwseq *hws = dc->hwseq;
1118 struct transform *xfm = dc->res_pool->transforms[fe_idx]; 1118 struct transform *xfm = dc->res_pool->transforms[fe_idx];
@@ -1129,12 +1129,12 @@ static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx)
1129 dm_logger_write(dc->ctx->logger, LOG_DC, 1129 dm_logger_write(dc->ctx->logger, LOG_DC,
1130 "Power gated front end %d\n", fe_idx); 1130 "Power gated front end %d\n", fe_idx);
1131 1131
1132 if (dc->public.debug.sanity_checks) 1132 if (dc->debug.sanity_checks)
1133 verify_allow_pstate_change_high(dc->hwseq); 1133 verify_allow_pstate_change_high(dc->hwseq);
1134} 1134}
1135 1135
1136static void reset_hw_ctx_wrap( 1136static void reset_hw_ctx_wrap(
1137 struct core_dc *dc, 1137 struct dc *dc,
1138 struct validate_context *context) 1138 struct validate_context *context)
1139{ 1139{
1140 int i; 1140 int i;
@@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws)
1246 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); 1246 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
1247} 1247}
1248 1248
1249static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) 1249static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1250{ 1250{
1251 bool addr_patched = false; 1251 bool addr_patched = false;
1252 PHYSICAL_ADDRESS_LOC addr; 1252 PHYSICAL_ADDRESS_LOC addr;
@@ -1657,7 +1657,7 @@ static bool dcn10_set_output_transfer_func(
1657} 1657}
1658 1658
1659static void dcn10_pipe_control_lock( 1659static void dcn10_pipe_control_lock(
1660 struct core_dc *dc, 1660 struct dc *dc,
1661 struct pipe_ctx *pipe, 1661 struct pipe_ctx *pipe,
1662 bool lock) 1662 bool lock)
1663{ 1663{
@@ -1669,7 +1669,7 @@ static void dcn10_pipe_control_lock(
1669 if (pipe->top_pipe) 1669 if (pipe->top_pipe)
1670 return; 1670 return;
1671 1671
1672 if (dc->public.debug.sanity_checks) 1672 if (dc->debug.sanity_checks)
1673 verify_allow_pstate_change_high(dc->hwseq); 1673 verify_allow_pstate_change_high(dc->hwseq);
1674 1674
1675 if (lock) 1675 if (lock)
@@ -1677,7 +1677,7 @@ static void dcn10_pipe_control_lock(
1677 else 1677 else
1678 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1678 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1679 1679
1680 if (dc->public.debug.sanity_checks) 1680 if (dc->debug.sanity_checks)
1681 verify_allow_pstate_change_high(dc->hwseq); 1681 verify_allow_pstate_change_high(dc->hwseq);
1682} 1682}
1683 1683
@@ -1719,7 +1719,7 @@ static bool wait_for_reset_trigger_to_occur(
1719} 1719}
1720 1720
1721static void dcn10_enable_timing_synchronization( 1721static void dcn10_enable_timing_synchronization(
1722 struct core_dc *dc, 1722 struct dc *dc,
1723 int group_index, 1723 int group_index,
1724 int group_size, 1724 int group_size,
1725 struct pipe_ctx *grouped_pipes[]) 1725 struct pipe_ctx *grouped_pipes[])
@@ -1748,7 +1748,7 @@ static void dcn10_enable_timing_synchronization(
1748} 1748}
1749 1749
1750static void print_rq_dlg_ttu( 1750static void print_rq_dlg_ttu(
1751 struct core_dc *core_dc, 1751 struct dc *core_dc,
1752 struct pipe_ctx *pipe_ctx) 1752 struct pipe_ctx *pipe_ctx)
1753{ 1753{
1754 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, 1754 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
@@ -1870,14 +1870,14 @@ static void print_rq_dlg_ttu(
1870} 1870}
1871 1871
1872static void dcn10_power_on_fe( 1872static void dcn10_power_on_fe(
1873 struct core_dc *dc, 1873 struct dc *dc,
1874 struct pipe_ctx *pipe_ctx, 1874 struct pipe_ctx *pipe_ctx,
1875 struct validate_context *context) 1875 struct validate_context *context)
1876{ 1876{
1877 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1877 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1878 struct dce_hwseq *hws = dc->hwseq; 1878 struct dce_hwseq *hws = dc->hwseq;
1879 1879
1880 if (dc->public.debug.sanity_checks) { 1880 if (dc->debug.sanity_checks) {
1881 verify_allow_pstate_change_high(dc->hwseq); 1881 verify_allow_pstate_change_high(dc->hwseq);
1882 } 1882 }
1883 1883
@@ -1928,7 +1928,7 @@ static void dcn10_power_on_fe(
1928 print_rq_dlg_ttu(dc, pipe_ctx); 1928 print_rq_dlg_ttu(dc, pipe_ctx);
1929 } 1929 }
1930 1930
1931 if (dc->public.debug.sanity_checks) { 1931 if (dc->debug.sanity_checks) {
1932 verify_allow_pstate_change_high(dc->hwseq); 1932 verify_allow_pstate_change_high(dc->hwseq);
1933 } 1933 }
1934} 1934}
@@ -2084,7 +2084,7 @@ static void dcn10_get_surface_visual_confirm_color(
2084} 2084}
2085 2085
2086static void update_dchubp_dpp( 2086static void update_dchubp_dpp(
2087 struct core_dc *dc, 2087 struct dc *dc,
2088 struct pipe_ctx *pipe_ctx, 2088 struct pipe_ctx *pipe_ctx,
2089 struct validate_context *context) 2089 struct validate_context *context)
2090{ 2090{
@@ -2126,7 +2126,7 @@ static void update_dchubp_dpp(
2126 2126
2127 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; 2127 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2128 2128
2129 if (dc->public.config.gpu_vm_support) 2129 if (dc->config.gpu_vm_support)
2130 mi->funcs->mem_input_program_pte_vm( 2130 mi->funcs->mem_input_program_pte_vm(
2131 pipe_ctx->plane_res.mi, 2131 pipe_ctx->plane_res.mi,
2132 plane_state->format, 2132 plane_state->format,
@@ -2142,7 +2142,7 @@ static void update_dchubp_dpp(
2142 mpcc_cfg.opp = pipe_ctx->stream_res.opp; 2142 mpcc_cfg.opp = pipe_ctx->stream_res.opp;
2143 for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) 2143 for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
2144 mpcc_cfg.z_index++; 2144 mpcc_cfg.z_index++;
2145 if (dc->public.debug.surface_visual_confirm) 2145 if (dc->debug.surface_visual_confirm)
2146 dcn10_get_surface_visual_confirm_color( 2146 dcn10_get_surface_visual_confirm_color(
2147 pipe_ctx, &mpcc_cfg.black_color); 2147 pipe_ctx, &mpcc_cfg.black_color);
2148 else 2148 else
@@ -2187,7 +2187,7 @@ static void update_dchubp_dpp(
2187 2187
2188 2188
2189static void program_all_pipe_in_tree( 2189static void program_all_pipe_in_tree(
2190 struct core_dc *dc, 2190 struct dc *dc,
2191 struct pipe_ctx *pipe_ctx, 2191 struct pipe_ctx *pipe_ctx,
2192 struct validate_context *context) 2192 struct validate_context *context)
2193{ 2193{
@@ -2201,7 +2201,7 @@ static void program_all_pipe_in_tree(
2201 /* watermark is for all pipes */ 2201 /* watermark is for all pipes */
2202 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); 2202 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
2203 2203
2204 if (dc->public.debug.sanity_checks) { 2204 if (dc->debug.sanity_checks) {
2205 /* pstate stuck check after watermark update */ 2205 /* pstate stuck check after watermark update */
2206 verify_allow_pstate_change_high(dc->hwseq); 2206 verify_allow_pstate_change_high(dc->hwseq);
2207 } 2207 }
@@ -2236,7 +2236,7 @@ static void program_all_pipe_in_tree(
2236 update_dchubp_dpp(dc, pipe_ctx, context); 2236 update_dchubp_dpp(dc, pipe_ctx, context);
2237 } 2237 }
2238 2238
2239 if (dc->public.debug.sanity_checks) { 2239 if (dc->debug.sanity_checks) {
2240 /* pstate stuck check after each pipe is programmed */ 2240 /* pstate stuck check after each pipe is programmed */
2241 verify_allow_pstate_change_high(dc->hwseq); 2241 verify_allow_pstate_change_high(dc->hwseq);
2242 } 2242 }
@@ -2246,7 +2246,7 @@ static void program_all_pipe_in_tree(
2246} 2246}
2247 2247
2248static void dcn10_pplib_apply_display_requirements( 2248static void dcn10_pplib_apply_display_requirements(
2249 struct core_dc *dc, 2249 struct dc *dc,
2250 struct validate_context *context) 2250 struct validate_context *context)
2251{ 2251{
2252 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2252 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
@@ -2273,14 +2273,14 @@ static void dcn10_pplib_apply_display_requirements(
2273} 2273}
2274 2274
2275static void dcn10_apply_ctx_for_surface( 2275static void dcn10_apply_ctx_for_surface(
2276 struct core_dc *dc, 2276 struct dc *dc,
2277 const struct dc_stream_state *stream, 2277 const struct dc_stream_state *stream,
2278 int num_planes, 2278 int num_planes,
2279 struct validate_context *context) 2279 struct validate_context *context)
2280{ 2280{
2281 int i, be_idx; 2281 int i, be_idx;
2282 2282
2283 if (dc->public.debug.sanity_checks) 2283 if (dc->debug.sanity_checks)
2284 verify_allow_pstate_change_high(dc->hwseq); 2284 verify_allow_pstate_change_high(dc->hwseq);
2285 2285
2286 be_idx = -1; 2286 be_idx = -1;
@@ -2351,7 +2351,7 @@ static void dcn10_apply_ctx_for_surface(
2351 "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", 2351 "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n",
2352 old_pipe_ctx->mpcc->inst);*/ 2352 old_pipe_ctx->mpcc->inst);*/
2353 2353
2354 if (dc->public.debug.sanity_checks) 2354 if (dc->debug.sanity_checks)
2355 verify_allow_pstate_change_high(dc->hwseq); 2355 verify_allow_pstate_change_high(dc->hwseq);
2356 2356
2357 old_pipe_ctx->top_pipe = NULL; 2357 old_pipe_ctx->top_pipe = NULL;
@@ -2422,18 +2422,18 @@ static void dcn10_apply_ctx_for_surface(
2422 context->bw.dcn.watermarks.d.pte_meta_urgent_ns 2422 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2423 ); 2423 );
2424 2424
2425 if (dc->public.debug.sanity_checks) 2425 if (dc->debug.sanity_checks)
2426 verify_allow_pstate_change_high(dc->hwseq); 2426 verify_allow_pstate_change_high(dc->hwseq);
2427} 2427}
2428 2428
2429static void dcn10_set_bandwidth( 2429static void dcn10_set_bandwidth(
2430 struct core_dc *dc, 2430 struct dc *dc,
2431 struct validate_context *context, 2431 struct validate_context *context,
2432 bool decrease_allowed) 2432 bool decrease_allowed)
2433{ 2433{
2434 struct dm_pp_clock_for_voltage_req clock; 2434 struct dm_pp_clock_for_voltage_req clock;
2435 2435
2436 if (dc->public.debug.sanity_checks) { 2436 if (dc->debug.sanity_checks) {
2437 verify_allow_pstate_change_high(dc->hwseq); 2437 verify_allow_pstate_change_high(dc->hwseq);
2438 } 2438 }
2439 2439
@@ -2488,7 +2488,7 @@ static void dcn10_set_bandwidth(
2488 } 2488 }
2489 dcn10_pplib_apply_display_requirements(dc, context); 2489 dcn10_pplib_apply_display_requirements(dc, context);
2490 2490
2491 if (dc->public.debug.sanity_checks) { 2491 if (dc->debug.sanity_checks) {
2492 verify_allow_pstate_change_high(dc->hwseq); 2492 verify_allow_pstate_change_high(dc->hwseq);
2493 } 2493 }
2494 2494
@@ -2541,7 +2541,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2541} 2541}
2542 2542
2543static void set_plane_config( 2543static void set_plane_config(
2544 const struct core_dc *dc, 2544 const struct dc *dc,
2545 struct pipe_ctx *pipe_ctx, 2545 struct pipe_ctx *pipe_ctx,
2546 struct resource_context *res_ctx) 2546 struct resource_context *res_ctx)
2547{ 2547{
@@ -2586,7 +2586,7 @@ static void dcn10_config_stereo_parameters(
2586 return; 2586 return;
2587} 2587}
2588 2588
2589static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) 2589static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2590{ 2590{
2591 struct crtc_stereo_flags flags = { 0 }; 2591 struct crtc_stereo_flags flags = { 0 };
2592 struct dc_stream_state *stream = pipe_ctx->stream; 2592 struct dc_stream_state *stream = pipe_ctx->stream;
@@ -2607,13 +2607,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
2607} 2607}
2608 2608
2609static void dcn10_wait_for_mpcc_disconnect( 2609static void dcn10_wait_for_mpcc_disconnect(
2610 struct core_dc *dc, 2610 struct dc *dc,
2611 struct resource_pool *res_pool, 2611 struct resource_pool *res_pool,
2612 struct pipe_ctx *pipe_ctx) 2612 struct pipe_ctx *pipe_ctx)
2613{ 2613{
2614 int i; 2614 int i;
2615 2615
2616 if (dc->public.debug.sanity_checks) { 2616 if (dc->debug.sanity_checks) {
2617 verify_allow_pstate_change_high(dc->hwseq); 2617 verify_allow_pstate_change_high(dc->hwseq);
2618 } 2618 }
2619 2619
@@ -2631,14 +2631,14 @@ static void dcn10_wait_for_mpcc_disconnect(
2631 } 2631 }
2632 } 2632 }
2633 2633
2634 if (dc->public.debug.sanity_checks) { 2634 if (dc->debug.sanity_checks) {
2635 verify_allow_pstate_change_high(dc->hwseq); 2635 verify_allow_pstate_change_high(dc->hwseq);
2636 } 2636 }
2637 2637
2638} 2638}
2639 2639
2640static bool dcn10_dummy_display_power_gating( 2640static bool dcn10_dummy_display_power_gating(
2641 struct core_dc *dc, 2641 struct dc *dc,
2642 uint8_t controller_id, 2642 uint8_t controller_id,
2643 struct dc_bios *dcb, 2643 struct dc_bios *dcb,
2644 enum pipe_gating_control power_gating) 2644 enum pipe_gating_control power_gating)
@@ -2652,7 +2652,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2652 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2652 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2653 2653
2654 if (plane_state->ctx->dc->debug.sanity_checks) { 2654 if (plane_state->ctx->dc->debug.sanity_checks) {
2655 struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); 2655 struct dc *dc = plane_state->ctx->dc;
2656 2656
2657 verify_allow_pstate_change_high(dc->hwseq); 2657 verify_allow_pstate_change_high(dc->hwseq);
2658 } 2658 }
@@ -2716,7 +2716,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
2716}; 2716};
2717 2717
2718 2718
2719void dcn10_hw_sequencer_construct(struct core_dc *dc) 2719void dcn10_hw_sequencer_construct(struct dc *dc)
2720{ 2720{
2721 dc->hwss = dcn10_funcs; 2721 dc->hwss = dcn10_funcs;
2722} 2722}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 28218dc43522..8bb09de8dcd7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -28,9 +28,9 @@
28 28
29#include "core_types.h" 29#include "core_types.h"
30 30
31struct core_dc; 31struct dc;
32 32
33void dcn10_hw_sequencer_construct(struct core_dc *dc); 33void dcn10_hw_sequencer_construct(struct dc *dc);
34extern void fill_display_configs( 34extern void fill_display_configs(
35 const struct validate_context *context, 35 const struct validate_context *context,
36 struct dm_pp_display_configuration *pp_display_cfg); 36 struct dm_pp_display_configuration *pp_display_cfg);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index c36843d497ac..2d9e88f08abb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -825,7 +825,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
825} 825}
826 826
827static enum dc_status build_mapped_resource( 827static enum dc_status build_mapped_resource(
828 const struct core_dc *dc, 828 const struct dc *dc,
829 struct validate_context *context, 829 struct validate_context *context,
830 struct validate_context *old_context) 830 struct validate_context *old_context)
831{ 831{
@@ -872,7 +872,7 @@ static enum dc_status build_mapped_resource(
872} 872}
873 873
874enum dc_status dcn10_validate_with_context( 874enum dc_status dcn10_validate_with_context(
875 const struct core_dc *dc, 875 struct dc *dc,
876 const struct dc_validation_set set[], 876 const struct dc_validation_set set[],
877 int set_count, 877 int set_count,
878 struct validate_context *context, 878 struct validate_context *context,
@@ -917,7 +917,7 @@ enum dc_status dcn10_validate_with_context(
917} 917}
918 918
919enum dc_status dcn10_validate_guaranteed( 919enum dc_status dcn10_validate_guaranteed(
920 const struct core_dc *dc, 920 struct dc *dc,
921 struct dc_stream_state *dc_stream, 921 struct dc_stream_state *dc_stream,
922 struct validate_context *context) 922 struct validate_context *context)
923{ 923{
@@ -937,7 +937,7 @@ enum dc_status dcn10_validate_guaranteed(
937 937
938 if (result == DC_OK) { 938 if (result == DC_OK) {
939 validate_guaranteed_copy_streams( 939 validate_guaranteed_copy_streams(
940 context, dc->public.caps.max_streams); 940 context, dc->caps.max_streams);
941 result = resource_build_scaling_params_for_context(dc, context); 941 result = resource_build_scaling_params_for_context(dc, context);
942 } 942 }
943 if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) 943 if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
@@ -1221,7 +1221,7 @@ static struct resource_funcs dcn10_res_pool_funcs = {
1221 1221
1222static bool construct( 1222static bool construct(
1223 uint8_t num_virtual_links, 1223 uint8_t num_virtual_links,
1224 struct core_dc *dc, 1224 struct dc *dc,
1225 struct dcn10_resource_pool *pool) 1225 struct dcn10_resource_pool *pool)
1226{ 1226{
1227 int i; 1227 int i;
@@ -1244,16 +1244,16 @@ static bool construct(
1244 1244
1245 /* TODO: Hardcode to correct number of functional controllers */ 1245 /* TODO: Hardcode to correct number of functional controllers */
1246 pool->base.pipe_count = 4; 1246 pool->base.pipe_count = 4;
1247 dc->public.caps.max_downscale_ratio = 200; 1247 dc->caps.max_downscale_ratio = 200;
1248 dc->public.caps.i2c_speed_in_khz = 100; 1248 dc->caps.i2c_speed_in_khz = 100;
1249 dc->public.caps.max_cursor_size = 256; 1249 dc->caps.max_cursor_size = 256;
1250 1250
1251 dc->public.caps.max_slave_planes = 1; 1251 dc->caps.max_slave_planes = 1;
1252 1252
1253 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1253 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1254 dc->public.debug = debug_defaults_drv; 1254 dc->debug = debug_defaults_drv;
1255 else 1255 else
1256 dc->public.debug = debug_defaults_diags; 1256 dc->debug = debug_defaults_diags;
1257 1257
1258 /************************************************* 1258 /*************************************************
1259 * Create resources * 1259 * Create resources *
@@ -1327,7 +1327,7 @@ static bool construct(
1327 1327
1328 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1328 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1329 dc->dcn_soc->urgent_latency = 3; 1329 dc->dcn_soc->urgent_latency = 3;
1330 dc->public.debug.disable_dmcu = true; 1330 dc->debug.disable_dmcu = true;
1331 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1331 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1332 } 1332 }
1333 1333
@@ -1347,10 +1347,10 @@ static bool construct(
1347 } 1347 }
1348 } 1348 }
1349 1349
1350 if (!dc->public.debug.disable_pplib_clock_request) 1350 if (!dc->debug.disable_pplib_clock_request)
1351 dcn_bw_update_from_pplib(dc); 1351 dcn_bw_update_from_pplib(dc);
1352 dcn_bw_sync_calcs_and_dml(dc); 1352 dcn_bw_sync_calcs_and_dml(dc);
1353 if (!dc->public.debug.disable_pplib_wm_range) 1353 if (!dc->debug.disable_pplib_wm_range)
1354 dcn_bw_notify_pplib_of_wm_ranges(dc); 1354 dcn_bw_notify_pplib_of_wm_ranges(dc);
1355 1355
1356 { 1356 {
@@ -1424,9 +1424,9 @@ static bool construct(
1424 goto res_create_fail; 1424 goto res_create_fail;
1425 1425
1426 dcn10_hw_sequencer_construct(dc); 1426 dcn10_hw_sequencer_construct(dc);
1427 dc->public.caps.max_planes = pool->base.pipe_count; 1427 dc->caps.max_planes = pool->base.pipe_count;
1428 1428
1429 dc->public.cap_funcs = cap_funcs; 1429 dc->cap_funcs = cap_funcs;
1430 1430
1431 return true; 1431 return true;
1432 1432
@@ -1449,7 +1449,7 @@ dwbc_create_fail:
1449 1449
1450struct resource_pool *dcn10_create_resource_pool( 1450struct resource_pool *dcn10_create_resource_pool(
1451 uint8_t num_virtual_links, 1451 uint8_t num_virtual_links,
1452 struct core_dc *dc) 1452 struct dc *dc)
1453{ 1453{
1454 struct dcn10_resource_pool *pool = 1454 struct dcn10_resource_pool *pool =
1455 dm_alloc(sizeof(struct dcn10_resource_pool)); 1455 dm_alloc(sizeof(struct dcn10_resource_pool));
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
index 5f84dbd0bdea..8f71225bc61b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
@@ -31,7 +31,7 @@
31#define TO_DCN10_RES_POOL(pool)\ 31#define TO_DCN10_RES_POOL(pool)\
32 container_of(pool, struct dcn10_resource_pool, base) 32 container_of(pool, struct dcn10_resource_pool, base)
33 33
34struct core_dc; 34struct dc;
35struct resource_pool; 35struct resource_pool;
36struct _vcs_dpi_display_pipe_params_st; 36struct _vcs_dpi_display_pipe_params_st;
37 37
@@ -40,7 +40,7 @@ struct dcn10_resource_pool {
40}; 40};
41struct resource_pool *dcn10_create_resource_pool( 41struct resource_pool *dcn10_create_resource_pool(
42 uint8_t num_virtual_links, 42 uint8_t num_virtual_links,
43 struct core_dc *dc); 43 struct dc *dc);
44 44
45 45
46#endif /* __DC_RESOURCE_DCN10_H__ */ 46#endif /* __DC_RESOURCE_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
deleted file mode 100644
index ebe1fd78a92a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * core_dc.h
3 *
4 * Created on: Nov 13, 2015
5 * Author: yonsun
6 */
7
8#ifndef __CORE_DC_H__
9#define __CORE_DC_H__
10
11#include "core_types.h"
12#include "hw_sequencer.h"
13#include "compressor.h"
14
15#define DC_TO_CORE(dc)\
16 container_of(dc, struct core_dc, public)
17
18struct core_dc {
19 struct dc public;
20 struct dc_context *ctx;
21
22 uint8_t link_count;
23 struct dc_link *links[MAX_PIPES * 2];
24
25 struct validate_context *current_context;
26 struct resource_pool *res_pool;
27
28 /* Display Engine Clock levels */
29 struct dm_pp_clock_levels sclk_lvls;
30
31 /* Inputs into BW and WM calculations. */
32 struct bw_calcs_dceip *bw_dceip;
33 struct bw_calcs_vbios *bw_vbios;
34#ifdef CONFIG_DRM_AMD_DC_DCN1_0
35 struct dcn_soc_bounding_box *dcn_soc;
36 struct dcn_ip_params *dcn_ip;
37 struct display_mode_lib dml;
38#endif
39
40 /* HW functions */
41 struct hw_sequencer_funcs hwss;
42 struct dce_hwseq *hwseq;
43
44 /* temp store of dm_pp_display_configuration
45 * to compare to see if display config changed
46 */
47 struct dm_pp_display_configuration prev_display_config;
48
49 /* FBC compressor */
50#ifdef ENABLE_FBC
51 struct compressor *fbc_compressor;
52#endif
53};
54
55#endif /* __CORE_DC_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 28454028434c..f8ade552c595 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -52,7 +52,7 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
52 52
53/************ link *****************/ 53/************ link *****************/
54struct link_init_data { 54struct link_init_data {
55 const struct core_dc *dc; 55 const struct dc *dc;
56 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 56 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
57 uint32_t connector_index; /* this will be mapped to the HPD pins */ 57 uint32_t connector_index; /* this will be mapped to the HPD pins */
58 uint32_t link_index; /* this is mapped to DAL display_index 58 uint32_t link_index; /* this is mapped to DAL display_index
@@ -87,19 +87,19 @@ struct resource_funcs {
87 struct link_encoder *(*link_enc_create)( 87 struct link_encoder *(*link_enc_create)(
88 const struct encoder_init_data *init); 88 const struct encoder_init_data *init);
89 enum dc_status (*validate_with_context)( 89 enum dc_status (*validate_with_context)(
90 const struct core_dc *dc, 90 struct dc *dc,
91 const struct dc_validation_set set[], 91 const struct dc_validation_set set[],
92 int set_count, 92 int set_count,
93 struct validate_context *context, 93 struct validate_context *context,
94 struct validate_context *old_context); 94 struct validate_context *old_context);
95 95
96 enum dc_status (*validate_guaranteed)( 96 enum dc_status (*validate_guaranteed)(
97 const struct core_dc *dc, 97 struct dc *dc,
98 struct dc_stream_state *stream, 98 struct dc_stream_state *stream,
99 struct validate_context *context); 99 struct validate_context *context);
100 100
101 bool (*validate_bandwidth)( 101 bool (*validate_bandwidth)(
102 const struct core_dc *dc, 102 struct dc *dc,
103 struct validate_context *context); 103 struct validate_context *context);
104 104
105 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 105 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
index 36c48f7d3f56..6a205b010084 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
@@ -33,7 +33,7 @@
33#include "bw_fixed.h" 33#include "bw_fixed.h"
34 34
35struct pipe_ctx; 35struct pipe_ctx;
36struct core_dc; 36struct dc;
37struct validate_context; 37struct validate_context;
38struct dce_bw_output; 38struct dce_bw_output;
39 39
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 7e8abcd60d12..58744fe87ed8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -34,7 +34,7 @@
34#include "display_clock.h" 34#include "display_clock.h"
35#include "../dml/display_mode_lib.h" 35#include "../dml/display_mode_lib.h"
36 36
37struct core_dc; 37struct dc;
38struct validate_context; 38struct validate_context;
39 39
40/******************************************************************************* 40/*******************************************************************************
@@ -620,16 +620,16 @@ struct dcn_ip_params {
620extern const struct dcn_ip_params dcn10_ip_defaults; 620extern const struct dcn_ip_params dcn10_ip_defaults;
621 621
622bool dcn_validate_bandwidth( 622bool dcn_validate_bandwidth(
623 const struct core_dc *dc, 623 struct dc *dc,
624 struct validate_context *context); 624 struct validate_context *context);
625 625
626unsigned int dcn_find_dcfclk_suits_all( 626unsigned int dcn_find_dcfclk_suits_all(
627 const struct core_dc *dc, 627 const struct dc *dc,
628 struct clocks_value *clocks); 628 struct clocks_value *clocks);
629 629
630void dcn_bw_update_from_pplib(struct core_dc *dc); 630void dcn_bw_update_from_pplib(struct dc *dc);
631void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); 631void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
632void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); 632void dcn_bw_sync_calcs_and_dml(struct dc *dc);
633 633
634#endif /* __DCN_CALCS_H__ */ 634#endif /* __DCN_CALCS_H__ */
635 635
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index a02f18ae527d..f876a11c903f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -30,6 +30,7 @@
30 30
31#include "dml/display_mode_structs.h" 31#include "dml/display_mode_structs.h"
32 32
33struct dchub_init_data;
33struct cstate_pstate_watermarks_st { 34struct cstate_pstate_watermarks_st {
34 uint32_t cstate_exit_ns; 35 uint32_t cstate_exit_ns;
35 uint32_t cstate_enter_plus_exit_ns; 36 uint32_t cstate_enter_plus_exit_ns;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7689e372b9da..c73dca9f6d46 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -25,8 +25,10 @@
25 25
26#ifndef __DC_HW_SEQUENCER_H__ 26#ifndef __DC_HW_SEQUENCER_H__
27#define __DC_HW_SEQUENCER_H__ 27#define __DC_HW_SEQUENCER_H__
28#include "core_types.h" 28#include "dc_types.h"
29#include "timing_generator.h" 29#include "clock_source.h"
30#include "inc/hw/timing_generator.h"
31#include "core_status.h"
30 32
31enum pipe_gating_control { 33enum pipe_gating_control {
32 PIPE_GATING_CONTROL_DISABLE = 0, 34 PIPE_GATING_CONTROL_DISABLE = 0,
@@ -46,25 +48,31 @@ struct dce_hwseq {
46 struct dce_hwseq_wa wa; 48 struct dce_hwseq_wa wa;
47}; 49};
48 50
51struct pipe_ctx;
52struct validate_context;
53struct dchub_init_data;
54struct dc_static_screen_events;
55struct resource_pool;
56struct resource_context;
49 57
50struct hw_sequencer_funcs { 58struct hw_sequencer_funcs {
51 59
52 void (*init_hw)(struct core_dc *dc); 60 void (*init_hw)(struct dc *dc);
53 61
54 enum dc_status (*apply_ctx_to_hw)( 62 enum dc_status (*apply_ctx_to_hw)(
55 struct core_dc *dc, struct validate_context *context); 63 struct dc *dc, struct validate_context *context);
56 64
57 void (*reset_hw_ctx_wrap)( 65 void (*reset_hw_ctx_wrap)(
58 struct core_dc *dc, struct validate_context *context); 66 struct dc *dc, struct validate_context *context);
59 67
60 void (*apply_ctx_for_surface)( 68 void (*apply_ctx_for_surface)(
61 struct core_dc *dc, 69 struct dc *dc,
62 const struct dc_stream_state *stream, 70 const struct dc_stream_state *stream,
63 int num_planes, 71 int num_planes,
64 struct validate_context *context); 72 struct validate_context *context);
65 73
66 void (*set_plane_config)( 74 void (*set_plane_config)(
67 const struct core_dc *dc, 75 const struct dc *dc,
68 struct pipe_ctx *pipe_ctx, 76 struct pipe_ctx *pipe_ctx,
69 struct resource_context *res_ctx); 77 struct resource_context *res_ctx);
70 78
@@ -77,7 +85,7 @@ struct hw_sequencer_funcs {
77 uint16_t *matrix); 85 uint16_t *matrix);
78 86
79 void (*update_plane_addr)( 87 void (*update_plane_addr)(
80 const struct core_dc *dc, 88 const struct dc *dc,
81 struct pipe_ctx *pipe_ctx); 89 struct pipe_ctx *pipe_ctx);
82 90
83 void (*update_dchub)( 91 void (*update_dchub)(
@@ -95,12 +103,12 @@ struct hw_sequencer_funcs {
95 struct pipe_ctx *pipe_ctx, 103 struct pipe_ctx *pipe_ctx,
96 const struct dc_stream_state *stream); 104 const struct dc_stream_state *stream);
97 105
98 void (*power_down)(struct core_dc *dc); 106 void (*power_down)(struct dc *dc);
99 107
100 void (*enable_accelerated_mode)(struct core_dc *dc); 108 void (*enable_accelerated_mode)(struct dc *dc);
101 109
102 void (*enable_timing_synchronization)( 110 void (*enable_timing_synchronization)(
103 struct core_dc *dc, 111 struct dc *dc,
104 int group_index, 112 int group_index,
105 int group_size, 113 int group_size,
106 struct pipe_ctx *grouped_pipes[]); 114 struct pipe_ctx *grouped_pipes[]);
@@ -110,14 +118,14 @@ struct hw_sequencer_funcs {
110 bool clock_gating); 118 bool clock_gating);
111 119
112 bool (*enable_display_power_gating)( 120 bool (*enable_display_power_gating)(
113 struct core_dc *dc, 121 struct dc *dc,
114 uint8_t controller_id, 122 uint8_t controller_id,
115 struct dc_bios *dcb, 123 struct dc_bios *dcb,
116 enum pipe_gating_control power_gating); 124 enum pipe_gating_control power_gating);
117 125
118 void (*power_down_front_end)(struct core_dc *dc, int fe_idx); 126 void (*power_down_front_end)(struct dc *dc, int fe_idx);
119 127
120 void (*power_on_front_end)(struct core_dc *dc, 128 void (*power_on_front_end)(struct dc *dc,
121 struct pipe_ctx *pipe, 129 struct pipe_ctx *pipe,
122 struct validate_context *context); 130 struct validate_context *context);
123 131
@@ -131,12 +139,12 @@ struct hw_sequencer_funcs {
131 struct dc_link_settings *link_settings); 139 struct dc_link_settings *link_settings);
132 140
133 void (*pipe_control_lock)( 141 void (*pipe_control_lock)(
134 struct core_dc *dc, 142 struct dc *dc,
135 struct pipe_ctx *pipe, 143 struct pipe_ctx *pipe,
136 bool lock); 144 bool lock);
137 145
138 void (*set_bandwidth)( 146 void (*set_bandwidth)(
139 struct core_dc *dc, 147 struct dc *dc,
140 struct validate_context *context, 148 struct validate_context *context,
141 bool decrease_allowed); 149 bool decrease_allowed);
142 150
@@ -152,23 +160,23 @@ struct hw_sequencer_funcs {
152 enum dc_status (*prog_pixclk_crtc_otg)( 160 enum dc_status (*prog_pixclk_crtc_otg)(
153 struct pipe_ctx *pipe_ctx, 161 struct pipe_ctx *pipe_ctx,
154 struct validate_context *context, 162 struct validate_context *context,
155 struct core_dc *dc); 163 struct dc *dc);
156 164
157 void (*setup_stereo)( 165 void (*setup_stereo)(
158 struct pipe_ctx *pipe_ctx, 166 struct pipe_ctx *pipe_ctx,
159 struct core_dc *dc); 167 struct dc *dc);
160 168
161 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 169 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
162 170
163 void (*log_hw_state)(struct core_dc *dc); 171 void (*log_hw_state)(struct dc *dc);
164 172
165 void (*wait_for_mpcc_disconnect)(struct core_dc *dc, 173 void (*wait_for_mpcc_disconnect)(struct dc *dc,
166 struct resource_pool *res_pool, 174 struct resource_pool *res_pool,
167 struct pipe_ctx *pipe_ctx); 175 struct pipe_ctx *pipe_ctx);
168}; 176};
169 177
170void color_space_to_black_color( 178void color_space_to_black_color(
171 const struct core_dc *dc, 179 const struct dc *dc,
172 enum dc_color_space colorspace, 180 enum dc_color_space colorspace,
173 struct tg_color *black_color); 181 struct tg_color *black_color);
174 182
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 7f30d9937d10..13218a52e2fa 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -27,7 +27,6 @@
27 27
28#include "core_types.h" 28#include "core_types.h"
29#include "core_status.h" 29#include "core_status.h"
30#include "core_dc.h"
31#include "dal_asic_id.h" 30#include "dal_asic_id.h"
32 31
33/* TODO unhardcode, 4 for CZ*/ 32/* TODO unhardcode, 4 for CZ*/
@@ -67,27 +66,27 @@ struct resource_create_funcs {
67 66
68bool resource_construct( 67bool resource_construct(
69 unsigned int num_virtual_links, 68 unsigned int num_virtual_links,
70 struct core_dc *dc, 69 struct dc *dc,
71 struct resource_pool *pool, 70 struct resource_pool *pool,
72 const struct resource_create_funcs *create_funcs); 71 const struct resource_create_funcs *create_funcs);
73 72
74struct resource_pool *dc_create_resource_pool( 73struct resource_pool *dc_create_resource_pool(
75 struct core_dc *dc, 74 struct dc *dc,
76 int num_virtual_links, 75 int num_virtual_links,
77 enum dce_version dc_version, 76 enum dce_version dc_version,
78 struct hw_asic_id asic_id); 77 struct hw_asic_id asic_id);
79 78
80void dc_destroy_resource_pool(struct core_dc *dc); 79void dc_destroy_resource_pool(struct dc *dc);
81 80
82enum dc_status resource_map_pool_resources( 81enum dc_status resource_map_pool_resources(
83 const struct core_dc *dc, 82 const struct dc *dc,
84 struct validate_context *context, 83 struct validate_context *context,
85 struct validate_context *old_context); 84 struct validate_context *old_context);
86 85
87bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); 86bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
88 87
89enum dc_status resource_build_scaling_params_for_context( 88enum dc_status resource_build_scaling_params_for_context(
90 const struct core_dc *dc, 89 const struct dc *dc,
91 struct validate_context *context); 90 struct validate_context *context);
92 91
93void resource_build_info_frame(struct pipe_ctx *pipe_ctx); 92void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
@@ -148,12 +147,12 @@ void resource_validate_ctx_update_pointer_after_copy(
148 struct validate_context *dst_ctx); 147 struct validate_context *dst_ctx);
149 148
150enum dc_status resource_map_clock_resources( 149enum dc_status resource_map_clock_resources(
151 const struct core_dc *dc, 150 const struct dc *dc,
152 struct validate_context *context, 151 struct validate_context *context,
153 struct validate_context *old_context); 152 struct validate_context *old_context);
154 153
155enum dc_status resource_map_phy_clock_resources( 154enum dc_status resource_map_phy_clock_resources(
156 const struct core_dc *dc, 155 const struct dc *dc,
157 struct validate_context *context, 156 struct validate_context *context,
158 struct validate_context *old_context); 157 struct validate_context *old_context);
159 158
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 24e47eb8cf3f..e3a12f3e0642 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -34,8 +34,8 @@
34 34
35#include "ivsrcid/ivsrcid_vislands30.h" 35#include "ivsrcid/ivsrcid_vislands30.h"
36 36
37#include "core_dc.h" 37#include "dc.h"
38 38#include "core_types.h"
39static bool hpd_ack( 39static bool hpd_ack(
40 struct irq_service *irq_service, 40 struct irq_service *irq_service,
41 const struct irq_source_info *info) 41 const struct irq_source_info *info)
@@ -206,7 +206,7 @@ bool dce110_vblank_set(
206 bool enable) 206 bool enable)
207{ 207{
208 struct dc_context *dc_ctx = irq_service->ctx; 208 struct dc_context *dc_ctx = irq_service->ctx;
209 struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); 209 struct dc *core_dc = irq_service->ctx->dc;
210 enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( 210 enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source(
211 irq_service->ctx->dc, 211 irq_service->ctx->dc,
212 info->src_id, 212 info->src_id,
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
index 7e8cb22f280f..f458ef8e4c57 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
@@ -36,7 +36,6 @@
36#include "ivsrcid/ivsrcid_vislands30.h" 36#include "ivsrcid/ivsrcid_vislands30.h"
37 37
38#include "dc_types.h" 38#include "dc_types.h"
39#include "inc/core_dc.h"
40 39
41static bool hpd_ack( 40static bool hpd_ack(
42 struct irq_service *irq_service, 41 struct irq_service *irq_service,
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index beb790937769..93c8556358f0 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -76,23 +76,23 @@ void logger_write(struct dal_logger *logger,
76 void *paralist); 76 void *paralist);
77 77
78void pre_surface_trace( 78void pre_surface_trace(
79 const struct dc *dc, 79 struct dc *dc,
80 const struct dc_plane_state *const *plane_states, 80 const struct dc_plane_state *const *plane_states,
81 int surface_count); 81 int surface_count);
82 82
83void update_surface_trace( 83void update_surface_trace(
84 const struct dc *dc, 84 struct dc *dc,
85 const struct dc_surface_update *updates, 85 const struct dc_surface_update *updates,
86 int surface_count); 86 int surface_count);
87 87
88void post_surface_trace(const struct dc *dc); 88void post_surface_trace(struct dc *dc);
89 89
90void context_timing_trace( 90void context_timing_trace(
91 const struct dc *dc, 91 struct dc *dc,
92 struct resource_context *res_ctx); 92 struct resource_context *res_ctx);
93 93
94void context_clock_trace( 94void context_clock_trace(
95 const struct dc *dc, 95 struct dc *dc,
96 struct validate_context *context); 96 struct validate_context *context);
97 97
98/* Any function which is empty or have incomplete implementation should be 98/* Any function which is empty or have incomplete implementation should be
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index f0a3e4332a09..f49203b3eb94 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -27,7 +27,6 @@
27#include "dc.h" 27#include "dc.h"
28#include "mod_freesync.h" 28#include "mod_freesync.h"
29#include "core_types.h" 29#include "core_types.h"
30#include "core_dc.h"
31 30
32#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 31#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
33 32
@@ -146,7 +145,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
146 struct core_freesync *core_freesync = 145 struct core_freesync *core_freesync =
147 dm_alloc(sizeof(struct core_freesync)); 146 dm_alloc(sizeof(struct core_freesync));
148 147
149 struct core_dc *core_dc = DC_TO_CORE(dc); 148 struct dc *core_dc = dc;
150 149
151 struct persistent_data_flag flag; 150 struct persistent_data_flag flag;
152 151
@@ -246,7 +245,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
246bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, 245bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
247 struct dc_stream_state *stream, struct mod_freesync_caps *caps) 246 struct dc_stream_state *stream, struct mod_freesync_caps *caps)
248{ 247{
249 struct core_dc *core_dc = NULL; 248 struct dc *core_dc = NULL;
250 struct core_freesync *core_freesync = NULL; 249 struct core_freesync *core_freesync = NULL;
251 int persistent_freesync_enable = 0; 250 int persistent_freesync_enable = 0;
252 struct persistent_data_flag flag; 251 struct persistent_data_flag flag;
@@ -257,7 +256,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
257 return false; 256 return false;
258 257
259 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 258 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
260 core_dc = DC_TO_CORE(core_freesync->dc); 259 core_dc = core_freesync->dc;
261 260
262 flag.save_per_edid = true; 261 flag.save_per_edid = true;
263 flag.save_per_link = false; 262 flag.save_per_link = false;
@@ -971,14 +970,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
971 unsigned int stream_index, map_index; 970 unsigned int stream_index, map_index;
972 int persistent_data = 0; 971 int persistent_data = 0;
973 struct persistent_data_flag flag; 972 struct persistent_data_flag flag;
974 struct core_dc *core_dc = NULL; 973 struct dc *core_dc = NULL;
975 struct core_freesync *core_freesync = NULL; 974 struct core_freesync *core_freesync = NULL;
976 975
977 if (mod_freesync == NULL) 976 if (mod_freesync == NULL)
978 return false; 977 return false;
979 978
980 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 979 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
981 core_dc = DC_TO_CORE(core_freesync->dc); 980 core_dc = core_freesync->dc;
982 981
983 flag.save_per_edid = true; 982 flag.save_per_edid = true;
984 flag.save_per_link = false; 983 flag.save_per_link = false;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 07:19:28 -0400