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authorDave Airlie <airlied@redhat.com>2017-02-16 20:55:12 -0500
committerDave Airlie <airlied@redhat.com>2017-02-16 20:55:12 -0500
commitdec13c8ba2f5be8839ba5505b57b22ab0d2a287e (patch)
tree4a5b0c2ed1c2cd0f653ffa6185cc98a0b3f80750 /drivers/gpu/drm/amd
parentbe3c9f5eed3be89d17b5dcffc38412932214fbae (diff)
parente8411302b44b844b4f619e8064735c70b7490ee8 (diff)
Merge branch 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
Fixes for 4.11. Highlights: - fix >2 displays on asics with 3 or 5 crtcs - fix SI headless asics - powerplay fixes for new polaris variants - misc fixes * 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: fix warning on older gcc releases drm/ttm: make TTM_MAX_BO_PRIORITY unsigned drm/amd/amdgpu: Fix flow control in uvd_v4_2_stop() drm/amd/powerplay: add didt config table for polaris kicker drm/amd/powerplay: modify VddcPhase value for polaris kicker drm/amd/powerplay: add kicker flag into smumgr drm/amdgpu: Initialize pipe priority order on graphic initialization drm/amdgpu: read hw register to check pg status. drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register drm/amdgpu/pm: check for headless before calling compute_clocks drm/amdgpu: use amdgpu_gem_va_check() in amdgpu_gem_va_update_vm() drm/amdgpu: add more cases to DCE11 possible crtc mask setup
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c7
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h1
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h1
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h3
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c150
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c2
23 files changed, 227 insertions, 37 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96ad79627dbb..e9af03113fc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1037,7 +1037,6 @@ struct amdgpu_uvd {
1037 bool use_ctx_buf; 1037 bool use_ctx_buf;
1038 struct amd_sched_entity entity; 1038 struct amd_sched_entity entity;
1039 uint32_t srbm_soft_reset; 1039 uint32_t srbm_soft_reset;
1040 bool is_powergated;
1041}; 1040};
1042 1041
1043/* 1042/*
@@ -1066,7 +1065,6 @@ struct amdgpu_vce {
1066 struct amd_sched_entity entity; 1065 struct amd_sched_entity entity;
1067 uint32_t srbm_soft_reset; 1066 uint32_t srbm_soft_reset;
1068 unsigned num_rings; 1067 unsigned num_rings;
1069 bool is_powergated;
1070}; 1068};
1071 1069
1072/* 1070/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index fa34dcae392f..d9e5aa4a79ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -834,16 +834,18 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
834 case CHIP_TOPAZ: 834 case CHIP_TOPAZ:
835 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || 835 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
836 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || 836 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
837 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) 837 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
838 info->is_kicker = true;
838 strcpy(fw_name, "amdgpu/topaz_k_smc.bin"); 839 strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
839 else 840 } else
840 strcpy(fw_name, "amdgpu/topaz_smc.bin"); 841 strcpy(fw_name, "amdgpu/topaz_smc.bin");
841 break; 842 break;
842 case CHIP_TONGA: 843 case CHIP_TONGA:
843 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || 844 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
844 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) 845 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
846 info->is_kicker = true;
845 strcpy(fw_name, "amdgpu/tonga_k_smc.bin"); 847 strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
846 else 848 } else
847 strcpy(fw_name, "amdgpu/tonga_smc.bin"); 849 strcpy(fw_name, "amdgpu/tonga_smc.bin");
848 break; 850 break;
849 case CHIP_FIJI: 851 case CHIP_FIJI:
@@ -858,9 +860,10 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
858 ((adev->pdev->device == 0x67ff) && 860 ((adev->pdev->device == 0x67ff) &&
859 ((adev->pdev->revision == 0xcf) || 861 ((adev->pdev->revision == 0xcf) ||
860 (adev->pdev->revision == 0xef) || 862 (adev->pdev->revision == 0xef) ||
861 (adev->pdev->revision == 0xff)))) 863 (adev->pdev->revision == 0xff)))) {
864 info->is_kicker = true;
862 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin"); 865 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
863 else 866 } else
864 strcpy(fw_name, "amdgpu/polaris11_smc.bin"); 867 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
865 } else if (type == CGS_UCODE_ID_SMU_SK) { 868 } else if (type == CGS_UCODE_ID_SMU_SK) {
866 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); 869 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
@@ -874,9 +877,10 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
874 (adev->pdev->revision == 0xe4) || 877 (adev->pdev->revision == 0xe4) ||
875 (adev->pdev->revision == 0xe5) || 878 (adev->pdev->revision == 0xe5) ||
876 (adev->pdev->revision == 0xe7) || 879 (adev->pdev->revision == 0xe7) ||
877 (adev->pdev->revision == 0xef))) 880 (adev->pdev->revision == 0xef))) {
881 info->is_kicker = true;
878 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin"); 882 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
879 else 883 } else
880 strcpy(fw_name, "amdgpu/polaris10_smc.bin"); 884 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
881 } else if (type == CGS_UCODE_ID_SMU_SK) { 885 } else if (type == CGS_UCODE_ID_SMU_SK) {
882 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); 886 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ec7037a48b6e..51d759463384 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -504,13 +504,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
504 list_for_each_entry(entry, list, head) { 504 list_for_each_entry(entry, list, head) {
505 struct amdgpu_bo *bo = 505 struct amdgpu_bo *bo =
506 container_of(entry->bo, struct amdgpu_bo, tbo); 506 container_of(entry->bo, struct amdgpu_bo, tbo);
507 507 if (amdgpu_gem_va_check(NULL, bo))
508 /* if anything is swapped out don't swap it in here,
509 just abort and wait for the next CS */
510 if (!amdgpu_bo_gpu_accessible(bo))
511 goto error;
512
513 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
514 goto error; 508 goto error;
515 } 509 }
516 510
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 95e026a4a2de..346e80a7119b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1296,7 +1296,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1296 if (!adev->pm.dpm_enabled) 1296 if (!adev->pm.dpm_enabled)
1297 return; 1297 return;
1298 1298
1299 amdgpu_display_bandwidth_update(adev); 1299 if (adev->mode_info.num_crtc)
1300 amdgpu_display_bandwidth_update(adev);
1300 1301
1301 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1302 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1302 struct amdgpu_ring *ring = adev->rings[i]; 1303 struct amdgpu_ring *ring = adev->rings[i];
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 1cf1d9d1aec1..5b24e89552ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3737,9 +3737,15 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3737 default: 3737 default:
3738 encoder->possible_crtcs = 0x3; 3738 encoder->possible_crtcs = 0x3;
3739 break; 3739 break;
3740 case 3:
3741 encoder->possible_crtcs = 0x7;
3742 break;
3740 case 4: 3743 case 4:
3741 encoder->possible_crtcs = 0xf; 3744 encoder->possible_crtcs = 0xf;
3742 break; 3745 break;
3746 case 5:
3747 encoder->possible_crtcs = 0x1f;
3748 break;
3743 case 6: 3749 case 6:
3744 encoder->possible_crtcs = 0x3f; 3750 encoder->possible_crtcs = 0x3f;
3745 break; 3751 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e3589b55a1e1..1f9354541f29 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1983,6 +1983,14 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1986
1987 tmp = RREG32(mmSPI_ARB_PRIORITY);
1988 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1989 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
1990 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
1991 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
1992 WREG32(mmSPI_ARB_PRIORITY, tmp);
1993
1986 mutex_unlock(&adev->grbm_idx_mutex); 1994 mutex_unlock(&adev->grbm_idx_mutex);
1987 1995
1988 udelay(50); 1996 udelay(50);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 35f9cd83b821..67afc901905c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3898,6 +3898,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3898 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 3898 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3899 (adev->gfx.config.sc_earlyz_tile_fifo_size << 3899 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3900 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 3900 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3901
3902 tmp = RREG32(mmSPI_ARB_PRIORITY);
3903 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3904 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3905 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3906 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3907 WREG32(mmSPI_ARB_PRIORITY, tmp);
3908
3901 mutex_unlock(&adev->grbm_idx_mutex); 3909 mutex_unlock(&adev->grbm_idx_mutex);
3902 3910
3903} 3911}
@@ -7260,7 +7268,7 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c
7260 static union { 7268 static union {
7261 struct amdgpu_ce_ib_state regular; 7269 struct amdgpu_ce_ib_state regular;
7262 struct amdgpu_ce_ib_state_chained_ib chained; 7270 struct amdgpu_ce_ib_state_chained_ib chained;
7263 } ce_payload = {0}; 7271 } ce_payload = {};
7264 7272
7265 if (ring->adev->virt.chained_ib_support) { 7273 if (ring->adev->virt.chained_ib_support) {
7266 ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, ce_payload); 7274 ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, ce_payload);
@@ -7287,7 +7295,7 @@ static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t c
7287 static union { 7295 static union {
7288 struct amdgpu_de_ib_state regular; 7296 struct amdgpu_de_ib_state regular;
7289 struct amdgpu_de_ib_state_chained_ib chained; 7297 struct amdgpu_de_ib_state_chained_ib chained;
7290 } de_payload = {0}; 7298 } de_payload = {};
7291 7299
7292 gds_addr = csa_addr + 4096; 7300 gds_addr = csa_addr + 4096;
7293 if (ring->adev->virt.chained_ib_support) { 7301 if (ring->adev->virt.chained_ib_support) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index f15df99f0a06..b34cefc7ebd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -401,7 +401,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
401 break; 401 break;
402 mdelay(1); 402 mdelay(1);
403 } 403 }
404 break; 404 if (status & 2)
405 break;
405 } 406 }
406 407
407 for (i = 0; i < 10; ++i) { 408 for (i = 0; i < 10; ++i) {
@@ -411,7 +412,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
411 break; 412 break;
412 mdelay(1); 413 mdelay(1);
413 } 414 }
414 break; 415 if (status & 0xf)
416 break;
415 } 417 }
416 418
417 /* Stall UMC and register bus before resetting VCPU */ 419 /* Stall UMC and register bus before resetting VCPU */
@@ -424,7 +426,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
424 break; 426 break;
425 mdelay(1); 427 mdelay(1);
426 } 428 }
427 break; 429 if (status & 0x240)
430 break;
428 } 431 }
429 432
430 WREG32_P(0x3D49, 0, ~(1 << 2)); 433 WREG32_P(0x3D49, 0, ~(1 << 2));
@@ -723,7 +726,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
723 if (state == AMD_PG_STATE_GATE) { 726 if (state == AMD_PG_STATE_GATE) {
724 uvd_v4_2_stop(adev); 727 uvd_v4_2_stop(adev);
725 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) { 728 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
726 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) { 729 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
730 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
727 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 731 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
728 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 732 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
729 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 733 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
@@ -733,7 +737,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
733 return 0; 737 return 0;
734 } else { 738 } else {
735 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) { 739 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
736 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) { 740 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
741 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
737 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 742 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
738 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 743 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
739 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 744 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 46e715193924..ad8c02e423d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -825,12 +825,10 @@ static int uvd_v5_0_set_powergating_state(void *handle,
825 825
826 if (state == AMD_PG_STATE_GATE) { 826 if (state == AMD_PG_STATE_GATE) {
827 uvd_v5_0_stop(adev); 827 uvd_v5_0_stop(adev);
828 adev->uvd.is_powergated = true;
829 } else { 828 } else {
830 ret = uvd_v5_0_start(adev); 829 ret = uvd_v5_0_start(adev);
831 if (ret) 830 if (ret)
832 goto out; 831 goto out;
833 adev->uvd.is_powergated = false;
834 } 832 }
835 833
836out: 834out:
@@ -844,7 +842,8 @@ static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
844 842
845 mutex_lock(&adev->pm.mutex); 843 mutex_lock(&adev->pm.mutex);
846 844
847 if (adev->uvd.is_powergated) { 845 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
846 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
848 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 847 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
849 goto out; 848 goto out;
850 } 849 }
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index af83ab8c1250..18a6de4e1512 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1051,12 +1051,10 @@ static int uvd_v6_0_set_powergating_state(void *handle,
1051 1051
1052 if (state == AMD_PG_STATE_GATE) { 1052 if (state == AMD_PG_STATE_GATE) {
1053 uvd_v6_0_stop(adev); 1053 uvd_v6_0_stop(adev);
1054 adev->uvd.is_powergated = true;
1055 } else { 1054 } else {
1056 ret = uvd_v6_0_start(adev); 1055 ret = uvd_v6_0_start(adev);
1057 if (ret) 1056 if (ret)
1058 goto out; 1057 goto out;
1059 adev->uvd.is_powergated = false;
1060 } 1058 }
1061 1059
1062out: 1060out:
@@ -1070,7 +1068,8 @@ static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1070 1068
1071 mutex_lock(&adev->pm.mutex); 1069 mutex_lock(&adev->pm.mutex);
1072 1070
1073 if (adev->uvd.is_powergated) { 1071 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
1072 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1074 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 1073 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1075 goto out; 1074 goto out;
1076 } 1075 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index a8c40eebdd78..93ec8815bb13 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -510,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
510 WREG32(mmVCE_LMI_SWAP_CNTL, 0); 510 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
511 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); 511 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
512 WREG32(mmVCE_LMI_VM_CTRL, 0); 512 WREG32(mmVCE_LMI_VM_CTRL, 0);
513 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
514
513 if (adev->asic_type >= CHIP_STONEY) { 515 if (adev->asic_type >= CHIP_STONEY) {
514 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); 516 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
515 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); 517 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
@@ -766,12 +768,10 @@ static int vce_v3_0_set_powergating_state(void *handle,
766 ret = vce_v3_0_stop(adev); 768 ret = vce_v3_0_stop(adev);
767 if (ret) 769 if (ret)
768 goto out; 770 goto out;
769 adev->vce.is_powergated = true;
770 } else { 771 } else {
771 ret = vce_v3_0_start(adev); 772 ret = vce_v3_0_start(adev);
772 if (ret) 773 if (ret)
773 goto out; 774 goto out;
774 adev->vce.is_powergated = false;
775 } 775 }
776 776
777out: 777out:
@@ -785,7 +785,8 @@ static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
785 785
786 mutex_lock(&adev->pm.mutex); 786 mutex_lock(&adev->pm.mutex);
787 787
788 if (adev->vce.is_powergated) { 788 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
789 CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
789 DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); 790 DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
790 goto out; 791 goto out;
791 } 792 }
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
index 25882a4dea5d..34c6ff52710e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
@@ -5452,5 +5452,7 @@
5452#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 5452#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
5453#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 5453#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
5454#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 5454#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
5455#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
5456#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
5455 5457
5456#endif /* SMU_7_0_1_SH_MASK_H */ 5458#endif /* SMU_7_0_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
index a9ef1562f43b..66597c64f525 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
@@ -1121,5 +1121,6 @@
1121#define ixROM_SW_DATA_62 0xc060011c 1121#define ixROM_SW_DATA_62 0xc060011c
1122#define ixROM_SW_DATA_63 0xc0600120 1122#define ixROM_SW_DATA_63 0xc0600120
1123#define ixROM_SW_DATA_64 0xc0600124 1123#define ixROM_SW_DATA_64 0xc0600124
1124#define ixCURRENT_PG_STATUS 0xc020029c
1124 1125
1125#endif /* SMU_7_1_1_D_H */ 1126#endif /* SMU_7_1_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
index 2c997f7b5d13..fb06f2e2f6e6 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
@@ -4860,5 +4860,7 @@
4860#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 4860#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
4861#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 4861#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
4862#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 4862#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
4863#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
4864#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
4863 4865
4864#endif /* SMU_7_1_1_SH_MASK_H */ 4866#endif /* SMU_7_1_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
index 22dd4c2b7290..4446d43d2a8f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
@@ -1271,5 +1271,6 @@
1271#define ixROM_SW_DATA_62 0xc060011c 1271#define ixROM_SW_DATA_62 0xc060011c
1272#define ixROM_SW_DATA_63 0xc0600120 1272#define ixROM_SW_DATA_63 0xc0600120
1273#define ixROM_SW_DATA_64 0xc0600124 1273#define ixROM_SW_DATA_64 0xc0600124
1274#define ixCURRENT_PG_STATUS 0xc020029c
1274 1275
1275#endif /* SMU_7_1_2_D_H */ 1276#endif /* SMU_7_1_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
index 518fd02e9d35..627906674fe8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
@@ -5830,5 +5830,7 @@
5830#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 5830#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
5831#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 5831#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
5832#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 5832#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
5833#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
5834#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
5833 5835
5834#endif /* SMU_7_1_2_SH_MASK_H */ 5836#endif /* SMU_7_1_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
index eca2b851f25f..0333d880bc9e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
@@ -1244,5 +1244,5 @@
1244#define ixGC_CAC_ACC_CU14 0xc8 1244#define ixGC_CAC_ACC_CU14 0xc8
1245#define ixGC_CAC_ACC_CU15 0xc9 1245#define ixGC_CAC_ACC_CU15 0xc9
1246#define ixGC_CAC_OVRD_CU 0xe7 1246#define ixGC_CAC_OVRD_CU 0xe7
1247 1247#define ixCURRENT_PG_STATUS 0xc020029c
1248#endif /* SMU_7_1_3_D_H */ 1248#endif /* SMU_7_1_3_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
index 1ede9e274714..654c1093d362 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
@@ -6076,5 +6076,8 @@
6076#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 6076#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
6077#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000 6077#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000
6078#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 6078#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
6079#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
6080#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
6081
6079 6082
6080#endif /* SMU_7_1_3_SH_MASK_H */ 6083#endif /* SMU_7_1_3_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 1d26ae768147..17b9d41f3e87 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -171,6 +171,7 @@ struct cgs_firmware_info {
171 uint32_t ucode_start_address; 171 uint32_t ucode_start_address;
172 172
173 void *kptr; 173 void *kptr;
174 bool is_kicker;
174}; 175};
175 176
176struct cgs_mode_info { 177struct cgs_mode_info {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 3341c0fbd069..1dc31aa72781 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -477,6 +477,151 @@ static const struct gpu_pt_config_reg DIDTConfig_Polaris12[] = {
477 { 0xFFFFFFFF } 477 { 0xFFFFFFFF }
478}; 478};
479 479
480static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =
481{
482/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
483 * Offset Mask Shift Value Type
484 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
485 */
486 /* DIDT_SQ */
487 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT, 0x004c, GPU_CONFIGREG_DIDT_IND },
488 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT, 0x00d0, GPU_CONFIGREG_DIDT_IND },
489 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT, 0x0069, GPU_CONFIGREG_DIDT_IND },
490 { ixDIDT_SQ_WEIGHT0_3, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT, 0x0048, GPU_CONFIGREG_DIDT_IND },
491
492 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT, 0x005f, GPU_CONFIGREG_DIDT_IND },
493 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT, 0x007a, GPU_CONFIGREG_DIDT_IND },
494 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT, 0x001f, GPU_CONFIGREG_DIDT_IND },
495 { ixDIDT_SQ_WEIGHT4_7, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT, 0x002d, GPU_CONFIGREG_DIDT_IND },
496
497 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT, 0x0088, GPU_CONFIGREG_DIDT_IND },
498 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
499 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
500 { ixDIDT_SQ_WEIGHT8_11, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
501
502 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
503 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
504
505 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
506 { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
507
508 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
509 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
510 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
511 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
512 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
513 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
514
515 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
516 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
517 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
518 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
519 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
520
521 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
522 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
523 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
524 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
525
526 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
527 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
528 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
529 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
530 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
531 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
532 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
533 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
534
535 /* DIDT_TD */
536 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND },
537 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
538 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND },
539 { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND },
540
541 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND },
542 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND },
543 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
544 { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
545
546 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
547 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
548
549 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
550 { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
551
552 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
553 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
554 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
555 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
556 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
557 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
558
559 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
560 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
561 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
562 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa, GPU_CONFIGREG_DIDT_IND },
563 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__UNUSED_0_MASK, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
564
565 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
566 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
567 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde, GPU_CONFIGREG_DIDT_IND },
568 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
569
570 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
571 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
572 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
573 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
574 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
575 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
576 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0008, GPU_CONFIGREG_DIDT_IND },
577 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
578
579 /* DIDT_TCP */
580 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT, 0x0004, GPU_CONFIGREG_DIDT_IND },
581 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT, 0x0037, GPU_CONFIGREG_DIDT_IND },
582 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
583 { ixDIDT_TCP_WEIGHT0_3, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND },
584
585 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT, 0x0054, GPU_CONFIGREG_DIDT_IND },
586 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
587 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
588 { ixDIDT_TCP_WEIGHT4_7, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
589
590 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
591 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
592
593 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
594 { ixDIDT_TCP_CTRL_OCP, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND },
595
596 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
597 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_0_MASK, DIDT_TCP_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
598 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x0032, GPU_CONFIGREG_DIDT_IND },
599 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_1_MASK, DIDT_TCP_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
600 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
601 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__UNUSED_2_MASK, DIDT_TCP_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
602
603 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
604 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
605 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
606 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01aa, GPU_CONFIGREG_DIDT_IND },
607 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
608
609 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
610 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
611 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde, GPU_CONFIGREG_DIDT_IND },
612 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
613
614 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND },
615 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
616 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
617 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
618 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
619 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
620 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND },
621 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__UNUSED_0_MASK, DIDT_TCP_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
622
623 { 0xFFFFFFFF } /* End of list */
624};
480 625
481static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) 626static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
482{ 627{
@@ -630,7 +775,10 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
630 } else if (hwmgr->chip_id == CHIP_POLARIS11) { 775 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
631 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); 776 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
632 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result); 777 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
633 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11); 778 if (hwmgr->smumgr->is_kicker)
779 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
780 else
781 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
634 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result); 782 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
635 } else if (hwmgr->chip_id == CHIP_POLARIS12) { 783 } else if (hwmgr->chip_id == CHIP_POLARIS12) {
636 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); 784 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 9b6531bd6350..7c318a95e0c2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -137,6 +137,7 @@ struct pp_smumgr {
137 uint32_t usec_timeout; 137 uint32_t usec_timeout;
138 bool reload_fw; 138 bool reload_fw;
139 const struct pp_smumgr_func *smumgr_funcs; 139 const struct pp_smumgr_func *smumgr_funcs;
140 bool is_kicker;
140}; 141};
141 142
142extern int smum_early_init(struct pp_instance *handle); 143extern int smum_early_init(struct pp_instance *handle);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index 0e26900e459e..c6c3c5751ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -494,6 +494,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
494 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 494 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
495 struct phm_ppt_v1_information *table_info = 495 struct phm_ppt_v1_information *table_info =
496 (struct phm_ppt_v1_information *)(hwmgr->pptable); 496 (struct phm_ppt_v1_information *)(hwmgr->pptable);
497 struct pp_smumgr *smumgr = hwmgr->smumgr;
497 498
498 state->CcPwrDynRm = 0; 499 state->CcPwrDynRm = 0;
499 state->CcPwrDynRm1 = 0; 500 state->CcPwrDynRm1 = 0;
@@ -502,7 +503,10 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
502 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 503 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
503 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 504 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
504 505
505 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; 506 if (smumgr->is_kicker)
507 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
508 else
509 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
506 510
507 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); 511 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
508 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); 512 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 6749fbe26c74..35ac27681415 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -533,6 +533,8 @@ int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr)
533 cgs_get_firmware_info(smumgr->device, 533 cgs_get_firmware_info(smumgr->device,
534 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); 534 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
535 535
536 smumgr->is_kicker = info.is_kicker;
537
536 result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); 538 result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
537 539
538 return result; 540 return result;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 21:33:51 -0400