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authorDavid S. Miller <davem@davemloft.net>2015-07-23 03:41:16 -0400
committerDavid S. Miller <davem@davemloft.net>2015-07-23 03:41:16 -0400
commitc5e40ee287db61a79af1746954ee03ebbf1ff8a3 (patch)
tree007da00e75e9b84766ac4868421705300e1e2e14 /drivers/gpu/drm/amd
parent052831879945be0d9fad2216b127147c565ec1b1 (diff)
parentc5dfd654d0ec0a28fe81e7bd4d4fd984a9855e09 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: net/bridge/br_mdb.c br_mdb.c conflict was a function call being removed to fix a bug in 'net' but whose signature was changed in 'net-next'. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c35
6 files changed, 73 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d63135bf29c0..1f040d85ac47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -669,6 +669,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
669static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 669static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
670 struct amdgpu_cs_parser *p) 670 struct amdgpu_cs_parser *p)
671{ 671{
672 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
672 struct amdgpu_ib *ib; 673 struct amdgpu_ib *ib;
673 int i, j, r; 674 int i, j, r;
674 675
@@ -694,6 +695,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
694 for (j = 0; j < num_deps; ++j) { 695 for (j = 0; j < num_deps; ++j) {
695 struct amdgpu_fence *fence; 696 struct amdgpu_fence *fence;
696 struct amdgpu_ring *ring; 697 struct amdgpu_ring *ring;
698 struct amdgpu_ctx *ctx;
697 699
698 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 700 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
699 deps[j].ip_instance, 701 deps[j].ip_instance,
@@ -701,14 +703,21 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
701 if (r) 703 if (r)
702 return r; 704 return r;
703 705
706 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
707 if (ctx == NULL)
708 return -EINVAL;
709
704 r = amdgpu_fence_recreate(ring, p->filp, 710 r = amdgpu_fence_recreate(ring, p->filp,
705 deps[j].handle, 711 deps[j].handle,
706 &fence); 712 &fence);
707 if (r) 713 if (r) {
714 amdgpu_ctx_put(ctx);
708 return r; 715 return r;
716 }
709 717
710 amdgpu_sync_fence(&ib->sync, fence); 718 amdgpu_sync_fence(&ib->sync, fence);
711 amdgpu_fence_unref(&fence); 719 amdgpu_fence_unref(&fence);
720 amdgpu_ctx_put(ctx);
712 } 721 }
713 } 722 }
714 723
@@ -808,12 +817,16 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
808 817
809 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 818 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
810 wait->in.ring, &ring); 819 wait->in.ring, &ring);
811 if (r) 820 if (r) {
821 amdgpu_ctx_put(ctx);
812 return r; 822 return r;
823 }
813 824
814 r = amdgpu_fence_recreate(ring, filp, wait->in.handle, &fence); 825 r = amdgpu_fence_recreate(ring, filp, wait->in.handle, &fence);
815 if (r) 826 if (r) {
827 amdgpu_ctx_put(ctx);
816 return r; 828 return r;
829 }
817 830
818 r = fence_wait_timeout(&fence->base, true, timeout); 831 r = fence_wait_timeout(&fence->base, true, timeout);
819 amdgpu_fence_unref(&fence); 832 amdgpu_fence_unref(&fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ba46be361c9b..d79009b65867 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1207,10 +1207,15 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1207 } else { 1207 } else {
1208 if (adev->ip_blocks[i].funcs->early_init) { 1208 if (adev->ip_blocks[i].funcs->early_init) {
1209 r = adev->ip_blocks[i].funcs->early_init((void *)adev); 1209 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1210 if (r) 1210 if (r == -ENOENT)
1211 adev->ip_block_enabled[i] = false;
1212 else if (r)
1211 return r; 1213 return r;
1214 else
1215 adev->ip_block_enabled[i] = true;
1216 } else {
1217 adev->ip_block_enabled[i] = true;
1212 } 1218 }
1213 adev->ip_block_enabled[i] = true;
1214 } 1219 }
1215 } 1220 }
1216 1221
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index f75a31df30bd..1a2d419cbf16 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -1679,25 +1679,31 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1679 if (ret) 1679 if (ret)
1680 return ret; 1680 return ret;
1681 1681
1682 DRM_INFO("DPM unforce state min=%d, max=%d.\n", 1682 DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1683 pi->sclk_dpm.soft_min_clk, 1683 pi->sclk_dpm.soft_min_clk,
1684 pi->sclk_dpm.soft_max_clk); 1684 pi->sclk_dpm.soft_max_clk);
1685 1685
1686 return 0; 1686 return 0;
1687} 1687}
1688 1688
1689static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, 1689static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1690 enum amdgpu_dpm_forced_level level) 1690 enum amdgpu_dpm_forced_level level)
1691{ 1691{
1692 int ret = 0; 1692 int ret = 0;
1693 1693
1694 switch (level) { 1694 switch (level) {
1695 case AMDGPU_DPM_FORCED_LEVEL_HIGH: 1695 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1696 ret = cz_dpm_unforce_dpm_levels(adev);
1697 if (ret)
1698 return ret;
1696 ret = cz_dpm_force_highest(adev); 1699 ret = cz_dpm_force_highest(adev);
1697 if (ret) 1700 if (ret)
1698 return ret; 1701 return ret;
1699 break; 1702 break;
1700 case AMDGPU_DPM_FORCED_LEVEL_LOW: 1703 case AMDGPU_DPM_FORCED_LEVEL_LOW:
1704 ret = cz_dpm_unforce_dpm_levels(adev);
1705 if (ret)
1706 return ret;
1701 ret = cz_dpm_force_lowest(adev); 1707 ret = cz_dpm_force_lowest(adev);
1702 if (ret) 1708 if (ret)
1703 return ret; 1709 return ret;
@@ -1711,6 +1717,8 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1711 break; 1717 break;
1712 } 1718 }
1713 1719
1720 adev->pm.dpm.forced_level = level;
1721
1714 return ret; 1722 return ret;
1715} 1723}
1716 1724
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 08387dfd98a7..cc050a329c49 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2566,6 +2566,7 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2566 struct drm_device *dev = crtc->dev; 2566 struct drm_device *dev = crtc->dev;
2567 struct amdgpu_device *adev = dev->dev_private; 2567 struct amdgpu_device *adev = dev->dev_private;
2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2569 unsigned type;
2569 2570
2570 switch (mode) { 2571 switch (mode) {
2571 case DRM_MODE_DPMS_ON: 2572 case DRM_MODE_DPMS_ON:
@@ -2574,6 +2575,9 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2574 dce_v8_0_vga_enable(crtc, true); 2575 dce_v8_0_vga_enable(crtc, true);
2575 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2576 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2576 dce_v8_0_vga_enable(crtc, false); 2577 dce_v8_0_vga_enable(crtc, false);
2578 /* Make sure VBLANK interrupt is still enabled */
2579 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2580 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2577 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2581 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2578 dce_v8_0_crtc_load_lut(crtc); 2582 dce_v8_0_crtc_load_lut(crtc);
2579 break; 2583 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7b683fb2173c..1c7c992dea37 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1813,10 +1813,7 @@ static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1813 u32 data, mask; 1813 u32 data, mask;
1814 1814
1815 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1815 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1816 if (data & 1) 1816 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1817 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1818 else
1819 data = 0;
1820 1817
1821 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1818 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1822 1819
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index fa5a4448531d..68552da40287 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -122,6 +122,32 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
123} 123}
124 124
125/* smu_8_0_d.h */
126#define mmMP0PUB_IND_INDEX 0x180
127#define mmMP0PUB_IND_DATA 0x181
128
129static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
130{
131 unsigned long flags;
132 u32 r;
133
134 spin_lock_irqsave(&adev->smc_idx_lock, flags);
135 WREG32(mmMP0PUB_IND_INDEX, (reg));
136 r = RREG32(mmMP0PUB_IND_DATA);
137 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
138 return r;
139}
140
141static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
142{
143 unsigned long flags;
144
145 spin_lock_irqsave(&adev->smc_idx_lock, flags);
146 WREG32(mmMP0PUB_IND_INDEX, (reg));
147 WREG32(mmMP0PUB_IND_DATA, (v));
148 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
149}
150
125static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 151static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
126{ 152{
127 unsigned long flags; 153 unsigned long flags;
@@ -1222,8 +1248,13 @@ static int vi_common_early_init(void *handle)
1222 bool smc_enabled = false; 1248 bool smc_enabled = false;
1223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224 1250
1225 adev->smc_rreg = &vi_smc_rreg; 1251 if (adev->flags & AMDGPU_IS_APU) {
1226 adev->smc_wreg = &vi_smc_wreg; 1252 adev->smc_rreg = &cz_smc_rreg;
1253 adev->smc_wreg = &cz_smc_wreg;
1254 } else {
1255 adev->smc_rreg = &vi_smc_rreg;
1256 adev->smc_wreg = &vi_smc_wreg;
1257 }
1227 adev->pcie_rreg = &vi_pcie_rreg; 1258 adev->pcie_rreg = &vi_pcie_rreg;
1228 adev->pcie_wreg = &vi_pcie_wreg; 1259 adev->pcie_wreg = &vi_pcie_wreg;
1229 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1260 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;