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authorAlex Deucher <alexander.deucher@amd.com>2017-05-02 16:15:06 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-05-05 18:14:16 -0400
commitad7d0ff3e79a100a24b66e8908a45402c20c3685 (patch)
tree44d426421d82cc584091bb3768c1feb946654482 /drivers/gpu/drm/amd
parentf47b77b4e4baeb7922b5652ae7040d4d5de684a7 (diff)
drm/amdgpu/gfx9: derive tile pipes from golden settings
rather than hardcoding it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 484ead2a20a4..741b56f996c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -771,7 +771,6 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
771 switch (adev->asic_type) { 771 switch (adev->asic_type) {
772 case CHIP_VEGA10: 772 case CHIP_VEGA10:
773 adev->gfx.config.max_shader_engines = 4; 773 adev->gfx.config.max_shader_engines = 4;
774 adev->gfx.config.max_tile_pipes = 8; //??
775 adev->gfx.config.max_cu_per_sh = 16; 774 adev->gfx.config.max_cu_per_sh = 16;
776 adev->gfx.config.max_sh_per_se = 1; 775 adev->gfx.config.max_sh_per_se = 1;
777 adev->gfx.config.max_backends_per_se = 4; 776 adev->gfx.config.max_backends_per_se = 4;
@@ -800,6 +799,10 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
800 adev->gfx.config.gb_addr_config, 799 adev->gfx.config.gb_addr_config,
801 GB_ADDR_CONFIG, 800 GB_ADDR_CONFIG,
802 NUM_PIPES); 801 NUM_PIPES);
802
803 adev->gfx.config.max_tile_pipes =
804 adev->gfx.config.gb_addr_config_fields.num_pipes;
805
803 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 806 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
804 REG_GET_FIELD( 807 REG_GET_FIELD(
805 adev->gfx.config.gb_addr_config, 808 adev->gfx.config.gb_addr_config,