Merge branch 'next' into for-linus

Prepare input updates for 4.14 merge window.

10 files changed, 110 insertions, 52 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 1cf78f4dd339..1e8e1123ddf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -693,6 +693,10 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
                                  adev->clock.default_dispclk / 100);
                         adev->clock.default_dispclk = 60000;
+                } else if (adev->clock.default_dispclk <= 60000) {
+                        DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
+                                 adev->clock.default_dispclk / 100);
+                        adev->clock.default_dispclk = 62500;
                 }
                 adev->clock.dp_extclk =
                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f2d705e6a75a..ab6b0d0febab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -449,6 +449,7 @@ static const struct pci_device_id pciidlist[] = {
         {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
         {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
         {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
+        {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
         {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
         /* Vega 10 */
         {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index a4831fe0223b..a2c59a08b2bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -220,9 +220,9 @@ static void amdgpu_vram_mgr_debug(struct ttm_mem_type_manager *man,
 }
 
 const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = {
-        amdgpu_vram_mgr_init,
-        amdgpu_vram_mgr_fini,
-        amdgpu_vram_mgr_new,
-        amdgpu_vram_mgr_del,
-        amdgpu_vram_mgr_debug
+        .init           = amdgpu_vram_mgr_init,
+        .takedown       = amdgpu_vram_mgr_fini,
+        .get_node       = amdgpu_vram_mgr_new,
+        .put_node       = amdgpu_vram_mgr_del,
+        .debug          = amdgpu_vram_mgr_debug
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
index 8c9bc75a9c2d..8a0818b23ea4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
@@ -165,7 +165,7 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
         struct drm_device *dev = crtc->dev;
         struct amdgpu_device *adev = dev->dev_private;
         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
-        ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+        ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
 
         memset(&args, 0, sizeof(args));
 
@@ -178,7 +178,7 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
 void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
 {
         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
-        ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+        ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
 
         memset(&args, 0, sizeof(args));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 0cdeb6a2e4a0..5dffa27afa45 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1207,8 +1207,11 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 773654a19749..47bbc87f96d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1176,8 +1176,11 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 1f3552967ba3..d8c9a959493e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -983,8 +983,11 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
         fixed20_12 a, b, c;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
                 priority_a_cnt = 0;
                 priority_b_cnt = 0;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 3c558c170e5e..db30c6ba563a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1091,8 +1091,11 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
-                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+                active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
+                                            (u32)mode->clock);
+                line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
+                                          (u32)mode->clock);
+                line_time = min(line_time, (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index fb0819359909..90332f55cfba 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -77,13 +77,26 @@ static int vce_v3_0_set_clockgating_state(void *handle,
 static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
+        u32 v;
+
+        mutex_lock(&adev->grbm_idx_mutex);
+        if (adev->vce.harvest_config == 0 ||
+                adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+        else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 
         if (ring == &adev->vce.ring[0])
-                return RREG32(mmVCE_RB_RPTR);
+                v = RREG32(mmVCE_RB_RPTR);
         else if (ring == &adev->vce.ring[1])
-                return RREG32(mmVCE_RB_RPTR2);
+                v = RREG32(mmVCE_RB_RPTR2);
         else
-                return RREG32(mmVCE_RB_RPTR3);
+                v = RREG32(mmVCE_RB_RPTR3);
+
+        WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+        mutex_unlock(&adev->grbm_idx_mutex);
+
+        return v;
 }
 
 /**
@@ -96,13 +109,26 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
+        u32 v;
+
+        mutex_lock(&adev->grbm_idx_mutex);
+        if (adev->vce.harvest_config == 0 ||
+                adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+        else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 
         if (ring == &adev->vce.ring[0])
-                return RREG32(mmVCE_RB_WPTR);
+                v = RREG32(mmVCE_RB_WPTR);
         else if (ring == &adev->vce.ring[1])
-                return RREG32(mmVCE_RB_WPTR2);
+                v = RREG32(mmVCE_RB_WPTR2);
         else
-                return RREG32(mmVCE_RB_WPTR3);
+                v = RREG32(mmVCE_RB_WPTR3);
+
+        WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+        mutex_unlock(&adev->grbm_idx_mutex);
+
+        return v;
 }
 
 /**
@@ -116,12 +142,22 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
+        mutex_lock(&adev->grbm_idx_mutex);
+        if (adev->vce.harvest_config == 0 ||
+                adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
+        else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
+                WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
+
         if (ring == &adev->vce.ring[0])
                 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
         else if (ring == &adev->vce.ring[1])
                 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
         else
                 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
+
+        WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
+        mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
@@ -231,33 +267,38 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
         struct amdgpu_ring *ring;
         int idx, r;
 
-        ring = &adev->vce.ring[0];
-        WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
-        WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-        WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
-
-        ring = &adev->vce.ring[1];
-        WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
-        WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-        WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
-
-        ring = &adev->vce.ring[2];
-        WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
-        WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
-        WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
-        WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
-
         mutex_lock(&adev->grbm_idx_mutex);
         for (idx = 0; idx < 2; ++idx) {
                 if (adev->vce.harvest_config & (1 << idx))
                         continue;
 
                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
+
+                /* Program instance 0 reg space for two instances or instance 0 case
+                program instance 1 reg space for only instance 1 available case */
+                if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) {
+                        ring = &adev->vce.ring[0];
+                        WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
+                        WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+                        WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
+
+                        ring = &adev->vce.ring[1];
+                        WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
+                        WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+                        WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
+
+                        ring = &adev->vce.ring[2];
+                        WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
+                        WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
+                        WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
+                        WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
+                }
+
                 vce_v3_0_mc_resume(adev, idx);
                 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index d5f53d04fa08..83e40fe51b62 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -709,17 +709,17 @@ static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
 
 static struct phm_master_table_item
 vega10_thermal_start_thermal_controller_master_list[] = {
-        {NULL, tf_vega10_thermal_initialize},
-        {NULL, tf_vega10_thermal_set_temperature_range},
-        {NULL, tf_vega10_thermal_enable_alert},
+        { .tableFunction = tf_vega10_thermal_initialize },
+        { .tableFunction = tf_vega10_thermal_set_temperature_range },
+        { .tableFunction = tf_vega10_thermal_enable_alert },
 /* We should restrict performance levels to low before we halt the SMC.
  * On the other hand we are still in boot state when we do this
  * so it would be pointless.
  * If this assumption changes we have to revisit this table.
  */
-        {NULL, tf_vega10_thermal_setup_fan_table},
-        {NULL, tf_vega10_thermal_start_smc_fan_control},
-        {NULL, NULL}
+        { .tableFunction = tf_vega10_thermal_setup_fan_table },
+        { .tableFunction = tf_vega10_thermal_start_smc_fan_control },
+        { }
 };
 
 static struct phm_master_table_header
@@ -731,10 +731,10 @@ vega10_thermal_start_thermal_controller_master = {
 
 static struct phm_master_table_item
 vega10_thermal_set_temperature_range_master_list[] = {
-        {NULL, tf_vega10_thermal_disable_alert},
-        {NULL, tf_vega10_thermal_set_temperature_range},
-        {NULL, tf_vega10_thermal_enable_alert},
-        {NULL, NULL}
+        { .tableFunction = tf_vega10_thermal_disable_alert },
+        { .tableFunction = tf_vega10_thermal_set_temperature_range },
+        { .tableFunction = tf_vega10_thermal_enable_alert },
+        { }
 };
 
 struct phm_master_table_header