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authorFelix Kuehling <Felix.Kuehling@amd.com>2018-01-04 17:17:47 -0500
committerOded Gabbay <oded.gabbay@gmail.com>2018-01-04 17:17:47 -0500
commita3084e6c522f94130c9dfc26fe6458c353dbc0c9 (patch)
tree16f9394aeccc3d07342dd79bec19b48c9d111fd3 /drivers/gpu/drm/amd
parent1d63669885ebc8fca13e44864f7199c3ff50cea3 (diff)
drm/amdkfd: Add dGPU device IDs and device info
v2: remove needs_iommu field as it doesn't exists CC: linux-pci@vger.kernel.org Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device.c145
1 files changed, 143 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index e8ff4eab63e7..83d6f410890e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -57,12 +57,110 @@ static const struct kfd_device_info carrizo_device_info = {
57 .needs_pci_atomics = false, 57 .needs_pci_atomics = false,
58}; 58};
59 59
60static const struct kfd_device_info hawaii_device_info = {
61 .asic_family = CHIP_HAWAII,
62 .max_pasid_bits = 16,
63 /* max num of queues for KV.TODO should be a dynamic value */
64 .max_no_of_hqd = 24,
65 .ih_ring_entry_size = 4 * sizeof(uint32_t),
66 .event_interrupt_class = &event_interrupt_class_cik,
67 .num_of_watch_points = 4,
68 .mqd_size_aligned = MQD_SIZE_ALIGNED,
69 .supports_cwsr = false,
70 .needs_pci_atomics = false,
71};
72
73static const struct kfd_device_info tonga_device_info = {
74 .asic_family = CHIP_TONGA,
75 .max_pasid_bits = 16,
76 .max_no_of_hqd = 24,
77 .ih_ring_entry_size = 4 * sizeof(uint32_t),
78 .event_interrupt_class = &event_interrupt_class_cik,
79 .num_of_watch_points = 4,
80 .mqd_size_aligned = MQD_SIZE_ALIGNED,
81 .supports_cwsr = false,
82 .needs_pci_atomics = true,
83};
84
85static const struct kfd_device_info tonga_vf_device_info = {
86 .asic_family = CHIP_TONGA,
87 .max_pasid_bits = 16,
88 .max_no_of_hqd = 24,
89 .ih_ring_entry_size = 4 * sizeof(uint32_t),
90 .event_interrupt_class = &event_interrupt_class_cik,
91 .num_of_watch_points = 4,
92 .mqd_size_aligned = MQD_SIZE_ALIGNED,
93 .supports_cwsr = false,
94 .needs_pci_atomics = false,
95};
96
97static const struct kfd_device_info fiji_device_info = {
98 .asic_family = CHIP_FIJI,
99 .max_pasid_bits = 16,
100 .max_no_of_hqd = 24,
101 .ih_ring_entry_size = 4 * sizeof(uint32_t),
102 .event_interrupt_class = &event_interrupt_class_cik,
103 .num_of_watch_points = 4,
104 .mqd_size_aligned = MQD_SIZE_ALIGNED,
105 .supports_cwsr = true,
106 .needs_pci_atomics = true,
107};
108
109static const struct kfd_device_info fiji_vf_device_info = {
110 .asic_family = CHIP_FIJI,
111 .max_pasid_bits = 16,
112 .max_no_of_hqd = 24,
113 .ih_ring_entry_size = 4 * sizeof(uint32_t),
114 .event_interrupt_class = &event_interrupt_class_cik,
115 .num_of_watch_points = 4,
116 .mqd_size_aligned = MQD_SIZE_ALIGNED,
117 .supports_cwsr = true,
118 .needs_pci_atomics = false,
119};
120
121
122static const struct kfd_device_info polaris10_device_info = {
123 .asic_family = CHIP_POLARIS10,
124 .max_pasid_bits = 16,
125 .max_no_of_hqd = 24,
126 .ih_ring_entry_size = 4 * sizeof(uint32_t),
127 .event_interrupt_class = &event_interrupt_class_cik,
128 .num_of_watch_points = 4,
129 .mqd_size_aligned = MQD_SIZE_ALIGNED,
130 .supports_cwsr = true,
131 .needs_pci_atomics = true,
132};
133
134static const struct kfd_device_info polaris10_vf_device_info = {
135 .asic_family = CHIP_POLARIS10,
136 .max_pasid_bits = 16,
137 .max_no_of_hqd = 24,
138 .ih_ring_entry_size = 4 * sizeof(uint32_t),
139 .event_interrupt_class = &event_interrupt_class_cik,
140 .num_of_watch_points = 4,
141 .mqd_size_aligned = MQD_SIZE_ALIGNED,
142 .supports_cwsr = true,
143 .needs_pci_atomics = false,
144};
145
146static const struct kfd_device_info polaris11_device_info = {
147 .asic_family = CHIP_POLARIS11,
148 .max_pasid_bits = 16,
149 .max_no_of_hqd = 24,
150 .ih_ring_entry_size = 4 * sizeof(uint32_t),
151 .event_interrupt_class = &event_interrupt_class_cik,
152 .num_of_watch_points = 4,
153 .mqd_size_aligned = MQD_SIZE_ALIGNED,
154 .supports_cwsr = true,
155 .needs_pci_atomics = true,
156};
157
158
60struct kfd_deviceid { 159struct kfd_deviceid {
61 unsigned short did; 160 unsigned short did;
62 const struct kfd_device_info *device_info; 161 const struct kfd_device_info *device_info;
63}; 162};
64 163
65/* Please keep this sorted by increasing device id. */
66static const struct kfd_deviceid supported_devices[] = { 164static const struct kfd_deviceid supported_devices[] = {
67 { 0x1304, &kaveri_device_info }, /* Kaveri */ 165 { 0x1304, &kaveri_device_info }, /* Kaveri */
68 { 0x1305, &kaveri_device_info }, /* Kaveri */ 166 { 0x1305, &kaveri_device_info }, /* Kaveri */
@@ -90,7 +188,50 @@ static const struct kfd_deviceid supported_devices[] = {
90 { 0x9874, &carrizo_device_info }, /* Carrizo */ 188 { 0x9874, &carrizo_device_info }, /* Carrizo */
91 { 0x9875, &carrizo_device_info }, /* Carrizo */ 189 { 0x9875, &carrizo_device_info }, /* Carrizo */
92 { 0x9876, &carrizo_device_info }, /* Carrizo */ 190 { 0x9876, &carrizo_device_info }, /* Carrizo */
93 { 0x9877, &carrizo_device_info } /* Carrizo */ 191 { 0x9877, &carrizo_device_info }, /* Carrizo */
192 { 0x67A0, &hawaii_device_info }, /* Hawaii */
193 { 0x67A1, &hawaii_device_info }, /* Hawaii */
194 { 0x67A2, &hawaii_device_info }, /* Hawaii */
195 { 0x67A8, &hawaii_device_info }, /* Hawaii */
196 { 0x67A9, &hawaii_device_info }, /* Hawaii */
197 { 0x67AA, &hawaii_device_info }, /* Hawaii */
198 { 0x67B0, &hawaii_device_info }, /* Hawaii */
199 { 0x67B1, &hawaii_device_info }, /* Hawaii */
200 { 0x67B8, &hawaii_device_info }, /* Hawaii */
201 { 0x67B9, &hawaii_device_info }, /* Hawaii */
202 { 0x67BA, &hawaii_device_info }, /* Hawaii */
203 { 0x67BE, &hawaii_device_info }, /* Hawaii */
204 { 0x6920, &tonga_device_info }, /* Tonga */
205 { 0x6921, &tonga_device_info }, /* Tonga */
206 { 0x6928, &tonga_device_info }, /* Tonga */
207 { 0x6929, &tonga_device_info }, /* Tonga */
208 { 0x692B, &tonga_device_info }, /* Tonga */
209 { 0x692F, &tonga_vf_device_info }, /* Tonga vf */
210 { 0x6938, &tonga_device_info }, /* Tonga */
211 { 0x6939, &tonga_device_info }, /* Tonga */
212 { 0x7300, &fiji_device_info }, /* Fiji */
213 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/
214 { 0x67C0, &polaris10_device_info }, /* Polaris10 */
215 { 0x67C1, &polaris10_device_info }, /* Polaris10 */
216 { 0x67C2, &polaris10_device_info }, /* Polaris10 */
217 { 0x67C4, &polaris10_device_info }, /* Polaris10 */
218 { 0x67C7, &polaris10_device_info }, /* Polaris10 */
219 { 0x67C8, &polaris10_device_info }, /* Polaris10 */
220 { 0x67C9, &polaris10_device_info }, /* Polaris10 */
221 { 0x67CA, &polaris10_device_info }, /* Polaris10 */
222 { 0x67CC, &polaris10_device_info }, /* Polaris10 */
223 { 0x67CF, &polaris10_device_info }, /* Polaris10 */
224 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/
225 { 0x67DF, &polaris10_device_info }, /* Polaris10 */
226 { 0x67E0, &polaris11_device_info }, /* Polaris11 */
227 { 0x67E1, &polaris11_device_info }, /* Polaris11 */
228 { 0x67E3, &polaris11_device_info }, /* Polaris11 */
229 { 0x67E7, &polaris11_device_info }, /* Polaris11 */
230 { 0x67E8, &polaris11_device_info }, /* Polaris11 */
231 { 0x67E9, &polaris11_device_info }, /* Polaris11 */
232 { 0x67EB, &polaris11_device_info }, /* Polaris11 */
233 { 0x67EF, &polaris11_device_info }, /* Polaris11 */
234 { 0x67FF, &polaris11_device_info }, /* Polaris11 */
94}; 235};
95 236
96static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 237static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,