aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd
diff options
context:
space:
mode:
authorAnthony Koo <Anthony.Koo@amd.com>2018-08-21 15:40:28 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 12:10:51 -0400
commit98e6436d3af5fef7ca9b59d865dd5807ede36fb9 (patch)
tree1ece2c3ff69196a3b22b001da1b6d1a8b58cac7e /drivers/gpu/drm/amd
parent8c3db1284a016dc670fe0a98afec33e001d363bc (diff)
drm/amd/display: Refactor FreeSync module
Remove dependency on internal sink map and instead use existing stream and plane state Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c288
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h18
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c60
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c3
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_resource.c110
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_hw_types.h6
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_stream.h29
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_types.h22
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c34
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c27
-rw-r--r--drivers/gpu/drm/amd/display/include/set_mode_types.h12
-rw-r--r--drivers/gpu/drm/amd/display/modules/freesync/freesync.c1837
-rw-r--r--drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h144
14 files changed, 930 insertions, 1670 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0c805be054a1..5f5e5ea20d78 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -839,8 +839,7 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
839 839
840 if (sink) { 840 if (sink) {
841 if (aconnector->dc_sink) { 841 if (aconnector->dc_sink) {
842 amdgpu_dm_remove_sink_from_freesync_module( 842 amdgpu_dm_update_freesync_caps(connector, NULL);
843 connector);
844 /* retain and release bellow are used for 843 /* retain and release bellow are used for
845 * bump up refcount for sink because the link don't point 844 * bump up refcount for sink because the link don't point
846 * to it anymore after disconnect so on next crtc to connector 845 * to it anymore after disconnect so on next crtc to connector
@@ -850,10 +849,10 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
850 dc_sink_release(aconnector->dc_sink); 849 dc_sink_release(aconnector->dc_sink);
851 } 850 }
852 aconnector->dc_sink = sink; 851 aconnector->dc_sink = sink;
853 amdgpu_dm_add_sink_to_freesync_module( 852 amdgpu_dm_update_freesync_caps(connector,
854 connector, aconnector->edid); 853 aconnector->edid);
855 } else { 854 } else {
856 amdgpu_dm_remove_sink_from_freesync_module(connector); 855 amdgpu_dm_update_freesync_caps(connector, NULL);
857 if (!aconnector->dc_sink) 856 if (!aconnector->dc_sink)
858 aconnector->dc_sink = aconnector->dc_em_sink; 857 aconnector->dc_sink = aconnector->dc_em_sink;
859 else if (aconnector->dc_sink != aconnector->dc_em_sink) 858 else if (aconnector->dc_sink != aconnector->dc_em_sink)
@@ -890,8 +889,7 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
890 /* TODO: check if we still need the S3 mode update workaround. 889 /* TODO: check if we still need the S3 mode update workaround.
891 * If yes, put it here. */ 890 * If yes, put it here. */
892 if (aconnector->dc_sink) 891 if (aconnector->dc_sink)
893 amdgpu_dm_remove_sink_from_freesync_module( 892 amdgpu_dm_update_freesync_caps(connector, NULL);
894 connector);
895 893
896 aconnector->dc_sink = sink; 894 aconnector->dc_sink = sink;
897 if (sink->dc_edid.length == 0) { 895 if (sink->dc_edid.length == 0) {
@@ -904,10 +902,10 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
904 drm_connector_update_edid_property(connector, 902 drm_connector_update_edid_property(connector,
905 aconnector->edid); 903 aconnector->edid);
906 } 904 }
907 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid); 905 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
908 906
909 } else { 907 } else {
910 amdgpu_dm_remove_sink_from_freesync_module(connector); 908 amdgpu_dm_update_freesync_caps(connector, NULL);
911 drm_connector_update_edid_property(connector, NULL); 909 drm_connector_update_edid_property(connector, NULL);
912 aconnector->num_modes = 0; 910 aconnector->num_modes = 0;
913 aconnector->dc_sink = NULL; 911 aconnector->dc_sink = NULL;
@@ -1580,26 +1578,68 @@ static void dm_bandwidth_update(struct amdgpu_device *adev)
1580static int amdgpu_notify_freesync(struct drm_device *dev, void *data, 1578static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1581 struct drm_file *filp) 1579 struct drm_file *filp)
1582{ 1580{
1583 struct mod_freesync_params freesync_params; 1581 struct drm_atomic_state *state;
1584 uint8_t num_streams; 1582 struct drm_modeset_acquire_ctx ctx;
1583 struct drm_crtc *crtc;
1584 struct drm_connector *connector;
1585 struct drm_connector_state *old_con_state, *new_con_state;
1586 int ret = 0;
1585 uint8_t i; 1587 uint8_t i;
1588 bool enable = false;
1586 1589
1587 struct amdgpu_device *adev = dev->dev_private; 1590 drm_modeset_acquire_init(&ctx, 0);
1588 int r = 0; 1591
1592 state = drm_atomic_state_alloc(dev);
1593 if (!state) {
1594 ret = -ENOMEM;
1595 goto out;
1596 }
1597 state->acquire_ctx = &ctx;
1598
1599retry:
1600 drm_for_each_crtc(crtc, dev) {
1601 ret = drm_atomic_add_affected_connectors(state, crtc);
1602 if (ret)
1603 goto fail;
1604
1605 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
1606 ret = drm_atomic_add_affected_planes(state, crtc);
1607 if (ret)
1608 goto fail;
1609 }
1589 1610
1590 /* Get freesync enable flag from DRM */ 1611 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
1612 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
1613 struct drm_crtc_state *new_crtc_state;
1614 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
1615 struct dm_crtc_state *dm_new_crtc_state;
1591 1616
1592 num_streams = dc_get_current_stream_count(adev->dm.dc); 1617 if (!acrtc) {
1618 ASSERT(0);
1619 continue;
1620 }
1593 1621
1594 for (i = 0; i < num_streams; i++) { 1622 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
1595 struct dc_stream_state *stream; 1623 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1596 stream = dc_get_stream_at_index(adev->dm.dc, i);
1597 1624
1598 mod_freesync_update_state(adev->dm.freesync_module, 1625 dm_new_crtc_state->freesync_enabled = enable;
1599 &stream, 1, &freesync_params);
1600 } 1626 }
1601 1627
1602 return r; 1628 ret = drm_atomic_commit(state);
1629
1630fail:
1631 if (ret == -EDEADLK) {
1632 drm_atomic_state_clear(state);
1633 drm_modeset_backoff(&ctx);
1634 goto retry;
1635 }
1636
1637 drm_atomic_state_put(state);
1638
1639out:
1640 drm_modeset_drop_locks(&ctx);
1641 drm_modeset_acquire_fini(&ctx);
1642 return ret;
1603} 1643}
1604 1644
1605static const struct amdgpu_display_funcs dm_display_funcs = { 1645static const struct amdgpu_display_funcs dm_display_funcs = {
@@ -2563,6 +2603,10 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
2563 dc_stream_retain(state->stream); 2603 dc_stream_retain(state->stream);
2564 } 2604 }
2565 2605
2606 state->adjust = cur->adjust;
2607 state->vrr_infopacket = cur->vrr_infopacket;
2608 state->freesync_enabled = cur->freesync_enabled;
2609
2566 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 2610 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2567 2611
2568 return &state->base; 2612 return &state->base;
@@ -2770,13 +2814,15 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2770 struct dm_connector_state *new_state = 2814 struct dm_connector_state *new_state =
2771 kmemdup(state, sizeof(*state), GFP_KERNEL); 2815 kmemdup(state, sizeof(*state), GFP_KERNEL);
2772 2816
2773 if (new_state) { 2817 if (!new_state)
2774 __drm_atomic_helper_connector_duplicate_state(connector, 2818 return NULL;
2775 &new_state->base);
2776 return &new_state->base;
2777 }
2778 2819
2779 return NULL; 2820 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
2821
2822 new_state->freesync_capable = state->freesync_capable;
2823 new_state->freesync_enable = state->freesync_enable;
2824
2825 return &new_state->base;
2780} 2826}
2781 2827
2782static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 2828static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
@@ -3786,8 +3832,6 @@ static void remove_stream(struct amdgpu_device *adev,
3786 struct dc_stream_state *stream) 3832 struct dc_stream_state *stream)
3787{ 3833{
3788 /* this is the update mode case */ 3834 /* this is the update mode case */
3789 if (adev->dm.freesync_module)
3790 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3791 3835
3792 acrtc->otg_inst = -1; 3836 acrtc->otg_inst = -1;
3793 acrtc->enabled = false; 3837 acrtc->enabled = false;
@@ -4055,6 +4099,11 @@ static bool commit_planes_to_stream(
4055 stream_update->dst = dc_stream->dst; 4099 stream_update->dst = dc_stream->dst;
4056 stream_update->out_transfer_func = dc_stream->out_transfer_func; 4100 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4057 4101
4102 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4103 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4104 stream_update->adjust = &dc_stream->adjust;
4105 }
4106
4058 for (i = 0; i < new_plane_count; i++) { 4107 for (i = 0; i < new_plane_count; i++) {
4059 updates[i].surface = plane_states[i]; 4108 updates[i].surface = plane_states[i];
4060 updates[i].gamma = 4109 updates[i].gamma =
@@ -4190,6 +4239,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4190 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4239 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4191 } 4240 }
4192 4241
4242 dc_stream_attach->adjust = acrtc_state->adjust;
4243 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
4193 4244
4194 if (false == commit_planes_to_stream(dm->dc, 4245 if (false == commit_planes_to_stream(dm->dc,
4195 plane_states_constructed, 4246 plane_states_constructed,
@@ -4339,62 +4390,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4339 } 4390 }
4340 } /* for_each_crtc_in_state() */ 4391 } /* for_each_crtc_in_state() */
4341 4392
4342 /*
4343 * Add streams after required streams from new and replaced streams
4344 * are removed from freesync module
4345 */
4346 if (adev->dm.freesync_module) {
4347 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4348 new_crtc_state, i) {
4349 struct amdgpu_dm_connector *aconnector = NULL;
4350 struct dm_connector_state *dm_new_con_state = NULL;
4351 struct amdgpu_crtc *acrtc = NULL;
4352 bool modeset_needed;
4353
4354 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4355 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4356 modeset_needed = modeset_required(
4357 new_crtc_state,
4358 dm_new_crtc_state->stream,
4359 dm_old_crtc_state->stream);
4360 /* We add stream to freesync if:
4361 * 1. Said stream is not null, and
4362 * 2. A modeset is requested. This means that the
4363 * stream was removed previously, and needs to be
4364 * replaced.
4365 */
4366 if (dm_new_crtc_state->stream == NULL ||
4367 !modeset_needed)
4368 continue;
4369
4370 acrtc = to_amdgpu_crtc(crtc);
4371
4372 aconnector =
4373 amdgpu_dm_find_first_crtc_matching_connector(
4374 state, crtc);
4375 if (!aconnector) {
4376 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4377 "find connector for acrtc "
4378 "id:%d skipping freesync "
4379 "init\n",
4380 acrtc->crtc_id);
4381 continue;
4382 }
4383
4384 mod_freesync_add_stream(adev->dm.freesync_module,
4385 dm_new_crtc_state->stream,
4386 &aconnector->caps);
4387 new_con_state = drm_atomic_get_new_connector_state(
4388 state, &aconnector->base);
4389 dm_new_con_state = to_dm_connector_state(new_con_state);
4390
4391 mod_freesync_set_user_enable(adev->dm.freesync_module,
4392 &dm_new_crtc_state->stream,
4393 1,
4394 &dm_new_con_state->user_enable);
4395 }
4396 }
4397
4398 if (dm_state->context) { 4393 if (dm_state->context) {
4399 dm_enable_per_frame_crtc_master_sync(dm_state->context); 4394 dm_enable_per_frame_crtc_master_sync(dm_state->context);
4400 WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); 4395 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
@@ -4448,6 +4443,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4448 WARN_ON(!status); 4443 WARN_ON(!status);
4449 WARN_ON(!status->plane_count); 4444 WARN_ON(!status->plane_count);
4450 4445
4446 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4447 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
4448
4451 /*TODO How it works with MPO ?*/ 4449 /*TODO How it works with MPO ?*/
4452 if (!commit_planes_to_stream( 4450 if (!commit_planes_to_stream(
4453 dm->dc, 4451 dm->dc,
@@ -4480,11 +4478,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4480 if (dm_new_crtc_state->stream == NULL || !modeset_needed) 4478 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4481 continue; 4479 continue;
4482 4480
4483 if (adev->dm.freesync_module)
4484 mod_freesync_notify_mode_change(
4485 adev->dm.freesync_module,
4486 &dm_new_crtc_state->stream, 1);
4487
4488 manage_dm_interrupts(adev, acrtc, true); 4481 manage_dm_interrupts(adev, acrtc, true);
4489 } 4482 }
4490 4483
@@ -4667,7 +4660,42 @@ static int do_aquire_global_lock(struct drm_device *dev,
4667 return ret < 0 ? ret : 0; 4660 return ret < 0 ? ret : 0;
4668} 4661}
4669 4662
4670static int dm_update_crtcs_state(struct dc *dc, 4663void set_freesync_on_stream(struct amdgpu_display_manager *dm,
4664 struct dm_crtc_state *new_crtc_state,
4665 struct dm_connector_state *new_con_state,
4666 struct dc_stream_state *new_stream)
4667{
4668 struct mod_freesync_config config = {0};
4669 struct mod_vrr_params vrr = {0};
4670 struct dc_info_packet vrr_infopacket = {0};
4671 struct amdgpu_dm_connector *aconnector =
4672 to_amdgpu_dm_connector(new_con_state->base.connector);
4673
4674 if (new_con_state->freesync_capable &&
4675 new_con_state->freesync_enable) {
4676 config.state = new_crtc_state->freesync_enabled ?
4677 VRR_STATE_ACTIVE_VARIABLE :
4678 VRR_STATE_INACTIVE;
4679 config.min_refresh_in_uhz =
4680 aconnector->min_vfreq * 1000000;
4681 config.max_refresh_in_uhz =
4682 aconnector->max_vfreq * 1000000;
4683 }
4684
4685 mod_freesync_build_vrr_params(dm->freesync_module,
4686 new_stream,
4687 &config, &vrr);
4688
4689 mod_freesync_build_vrr_infopacket(dm->freesync_module,
4690 new_stream,
4691 &vrr,
4692 &vrr_infopacket);
4693
4694 new_crtc_state->adjust = vrr.adjust;
4695 new_crtc_state->vrr_infopacket = vrr_infopacket;
4696}
4697
4698static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
4671 struct drm_atomic_state *state, 4699 struct drm_atomic_state *state,
4672 bool enable, 4700 bool enable,
4673 bool *lock_and_validation_needed) 4701 bool *lock_and_validation_needed)
@@ -4737,6 +4765,9 @@ static int dm_update_crtcs_state(struct dc *dc,
4737 break; 4765 break;
4738 } 4766 }
4739 4767
4768 set_freesync_on_stream(dm, dm_new_crtc_state,
4769 dm_new_conn_state, new_stream);
4770
4740 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 4771 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4741 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 4772 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4742 new_crtc_state->mode_changed = false; 4773 new_crtc_state->mode_changed = false;
@@ -4745,6 +4776,9 @@ static int dm_update_crtcs_state(struct dc *dc,
4745 } 4776 }
4746 } 4777 }
4747 4778
4779 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
4780 new_crtc_state->mode_changed = true;
4781
4748 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4782 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4749 goto next_crtc; 4783 goto next_crtc;
4750 4784
@@ -4771,7 +4805,7 @@ static int dm_update_crtcs_state(struct dc *dc,
4771 4805
4772 /* i.e. reset mode */ 4806 /* i.e. reset mode */
4773 if (dc_remove_stream_from_ctx( 4807 if (dc_remove_stream_from_ctx(
4774 dc, 4808 dm->dc,
4775 dm_state->context, 4809 dm_state->context,
4776 dm_old_crtc_state->stream) != DC_OK) { 4810 dm_old_crtc_state->stream) != DC_OK) {
4777 ret = -EINVAL; 4811 ret = -EINVAL;
@@ -4808,7 +4842,7 @@ static int dm_update_crtcs_state(struct dc *dc,
4808 crtc->base.id); 4842 crtc->base.id);
4809 4843
4810 if (dc_add_stream_to_ctx( 4844 if (dc_add_stream_to_ctx(
4811 dc, 4845 dm->dc,
4812 dm_state->context, 4846 dm_state->context,
4813 dm_new_crtc_state->stream) != DC_OK) { 4847 dm_new_crtc_state->stream) != DC_OK) {
4814 ret = -EINVAL; 4848 ret = -EINVAL;
@@ -4857,6 +4891,8 @@ next_crtc:
4857 goto fail; 4891 goto fail;
4858 amdgpu_dm_set_ctm(dm_new_crtc_state); 4892 amdgpu_dm_set_ctm(dm_new_crtc_state);
4859 } 4893 }
4894
4895
4860 } 4896 }
4861 4897
4862 return ret; 4898 return ret;
@@ -5024,8 +5060,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
5024 goto fail; 5060 goto fail;
5025 5061
5026 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5062 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5063 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5064 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5065
5027 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 5066 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
5028 !new_crtc_state->color_mgmt_changed) 5067 !new_crtc_state->color_mgmt_changed &&
5068 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
5029 continue; 5069 continue;
5030 5070
5031 if (!new_crtc_state->enable) 5071 if (!new_crtc_state->enable)
@@ -5051,13 +5091,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
5051 } 5091 }
5052 5092
5053 /* Disable all crtcs which require disable */ 5093 /* Disable all crtcs which require disable */
5054 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed); 5094 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
5055 if (ret) { 5095 if (ret) {
5056 goto fail; 5096 goto fail;
5057 } 5097 }
5058 5098
5059 /* Enable all crtcs which require enable */ 5099 /* Enable all crtcs which require enable */
5060 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed); 5100 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
5061 if (ret) { 5101 if (ret) {
5062 goto fail; 5102 goto fail;
5063 } 5103 }
@@ -5150,8 +5190,8 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc,
5150 5190
5151 return capable; 5191 return capable;
5152} 5192}
5153void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 5193void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5154 struct edid *edid) 5194 struct edid *edid)
5155{ 5195{
5156 int i; 5196 int i;
5157 bool edid_check_required; 5197 bool edid_check_required;
@@ -5170,6 +5210,18 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5170 return; 5210 return;
5171 } 5211 }
5172 5212
5213 if (!edid) {
5214 dm_con_state = to_dm_connector_state(connector->state);
5215
5216 amdgpu_dm_connector->min_vfreq = 0;
5217 amdgpu_dm_connector->max_vfreq = 0;
5218 amdgpu_dm_connector->pixel_clock_mhz = 0;
5219
5220 dm_con_state->freesync_capable = false;
5221 dm_con_state->freesync_enable = false;
5222 return;
5223 }
5224
5173 dm_con_state = to_dm_connector_state(connector->state); 5225 dm_con_state = to_dm_connector_state(connector->state);
5174 5226
5175 edid_check_required = false; 5227 edid_check_required = false;
@@ -5220,46 +5272,10 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5220 } 5272 }
5221 5273
5222 if (amdgpu_dm_connector->max_vfreq - 5274 if (amdgpu_dm_connector->max_vfreq -
5223 amdgpu_dm_connector->min_vfreq > 10) { 5275 amdgpu_dm_connector->min_vfreq > 10) {
5224 amdgpu_dm_connector->caps.supported = true; 5276
5225 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5226 amdgpu_dm_connector->min_vfreq * 1000000;
5227 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5228 amdgpu_dm_connector->max_vfreq * 1000000;
5229 dm_con_state->freesync_capable = true; 5277 dm_con_state->freesync_capable = true;
5230 } 5278 }
5231 } 5279 }
5232} 5280}
5233 5281
5234void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
5235{
5236 struct amdgpu_dm_connector *amdgpu_dm_connector =
5237 to_amdgpu_dm_connector(connector);
5238 struct dm_connector_state *dm_con_state;
5239 struct drm_device *dev = connector->dev;
5240 struct amdgpu_device *adev = dev->dev_private;
5241
5242 if (!amdgpu_dm_connector->dc_sink || !adev->dm.freesync_module) {
5243 DRM_ERROR("dc_sink NULL or no free_sync module.\n");
5244 return;
5245 }
5246
5247 if (!connector->state) {
5248 DRM_ERROR("%s - Connector has no state", __func__);
5249 return;
5250 }
5251
5252 dm_con_state = to_dm_connector_state(connector->state);
5253
5254 amdgpu_dm_connector->min_vfreq = 0;
5255 amdgpu_dm_connector->max_vfreq = 0;
5256 amdgpu_dm_connector->pixel_clock_mhz = 0;
5257
5258 memset(&amdgpu_dm_connector->caps, 0, sizeof(amdgpu_dm_connector->caps));
5259
5260 dm_con_state->freesync_capable = false;
5261
5262 dm_con_state->user_enable.enable_for_gaming = false;
5263 dm_con_state->user_enable.enable_for_static = false;
5264 dm_con_state->user_enable.enable_for_video = false;
5265}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index a29dc35954c9..c159584c04f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -167,9 +167,6 @@ struct amdgpu_dm_connector {
167 int max_vfreq ; 167 int max_vfreq ;
168 int pixel_clock_mhz; 168 int pixel_clock_mhz;
169 169
170 /*freesync caps*/
171 struct mod_freesync_caps caps;
172
173 struct mutex hpd_lock; 170 struct mutex hpd_lock;
174 171
175 bool fake_enable; 172 bool fake_enable;
@@ -197,9 +194,13 @@ struct dm_crtc_state {
197 194
198 int crc_skip_count; 195 int crc_skip_count;
199 bool crc_enabled; 196 bool crc_enabled;
197
198 bool freesync_enabled;
199 struct dc_crtc_timing_adjust adjust;
200 struct dc_info_packet vrr_infopacket;
200}; 201};
201 202
202#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 203#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
203 204
204struct dm_atomic_state { 205struct dm_atomic_state {
205 struct drm_atomic_state base; 206 struct drm_atomic_state base;
@@ -216,7 +217,7 @@ struct dm_connector_state {
216 uint8_t underscan_vborder; 217 uint8_t underscan_vborder;
217 uint8_t underscan_hborder; 218 uint8_t underscan_hborder;
218 bool underscan_enable; 219 bool underscan_enable;
219 struct mod_freesync_user_enable user_enable; 220 bool freesync_enable;
220 bool freesync_capable; 221 bool freesync_capable;
221}; 222};
222 223
@@ -250,11 +251,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
250void dm_restore_drm_connector_state(struct drm_device *dev, 251void dm_restore_drm_connector_state(struct drm_device *dev,
251 struct drm_connector *connector); 252 struct drm_connector *connector);
252 253
253void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 254void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
254 struct edid *edid); 255 struct edid *edid);
255
256void
257amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
258 256
259/* amdgpu_dm_crc.c */ 257/* amdgpu_dm_crc.c */
260#ifdef CONFIG_DEBUG_FS 258#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9a300732ba37..67683645ce2c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -234,8 +234,9 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
234 dc_sink->priv = aconnector; 234 dc_sink->priv = aconnector;
235 aconnector->dc_sink = dc_sink; 235 aconnector->dc_sink = dc_sink;
236 236
237 amdgpu_dm_add_sink_to_freesync_module( 237 if (aconnector->dc_sink)
238 connector, aconnector->edid); 238 amdgpu_dm_update_freesync_caps(
239 connector, aconnector->edid);
239} 240}
240 241
241static int dm_dp_mst_get_modes(struct drm_connector *connector) 242static int dm_dp_mst_get_modes(struct drm_connector *connector)
@@ -275,8 +276,9 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
275 aconnector->dc_sink = dc_sink; 276 aconnector->dc_sink = dc_sink;
276 277
277 if (aconnector->dc_sink) 278 if (aconnector->dc_sink)
278 amdgpu_dm_add_sink_to_freesync_module( 279 amdgpu_dm_update_freesync_caps(
279 connector, aconnector->edid); 280 connector, aconnector->edid);
281
280 } 282 }
281 283
282 drm_connector_update_edid_property( 284 drm_connector_update_edid_property(
@@ -439,7 +441,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
439 441
440 aconnector->port = NULL; 442 aconnector->port = NULL;
441 if (aconnector->dc_sink) { 443 if (aconnector->dc_sink) {
442 amdgpu_dm_remove_sink_from_freesync_module(connector); 444 amdgpu_dm_update_freesync_caps(connector, NULL);
443 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 445 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
444 dc_sink_release(aconnector->dc_sink); 446 dc_sink_release(aconnector->dc_sink);
445 aconnector->dc_sink = NULL; 447 aconnector->dc_sink = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 71742635e797..a4df627d6936 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -188,11 +188,9 @@ failed_alloc:
188 ***************************************************************************** 188 *****************************************************************************
189 */ 189 */
190bool dc_stream_adjust_vmin_vmax(struct dc *dc, 190bool dc_stream_adjust_vmin_vmax(struct dc *dc,
191 struct dc_stream_state **streams, int num_streams, 191 struct dc_stream_state *stream,
192 int vmin, int vmax) 192 struct dc_crtc_timing_adjust *adjust)
193{ 193{
194 /* TODO: Support multiple streams */
195 struct dc_stream_state *stream = streams[0];
196 int i = 0; 194 int i = 0;
197 bool ret = false; 195 bool ret = false;
198 196
@@ -200,11 +198,11 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
200 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 198 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
201 199
202 if (pipe->stream == stream && pipe->stream_res.stream_enc) { 200 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
203 dc->hwss.set_drr(&pipe, 1, vmin, vmax); 201 pipe->stream->adjust = *adjust;
204 202 dc->hwss.set_drr(&pipe,
205 /* build and update the info frame */ 203 1,
206 resource_build_info_frame(pipe); 204 adjust->v_total_min,
207 dc->hwss.update_info_frame(pipe); 205 adjust->v_total_max);
208 206
209 ret = true; 207 ret = true;
210 } 208 }
@@ -217,7 +215,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
217 unsigned int *v_pos, unsigned int *nom_v_pos) 215 unsigned int *v_pos, unsigned int *nom_v_pos)
218{ 216{
219 /* TODO: Support multiple streams */ 217 /* TODO: Support multiple streams */
220 struct dc_stream_state *stream = streams[0]; 218 const struct dc_stream_state *stream = streams[0];
221 int i = 0; 219 int i = 0;
222 bool ret = false; 220 bool ret = false;
223 struct crtc_position position; 221 struct crtc_position position;
@@ -1257,8 +1255,25 @@ static enum surface_update_type check_update_surfaces_for_stream(
1257 if (stream_status == NULL || stream_status->plane_count != surface_count) 1255 if (stream_status == NULL || stream_status->plane_count != surface_count)
1258 return UPDATE_TYPE_FULL; 1256 return UPDATE_TYPE_FULL;
1259 1257
1260 if (stream_update) 1258 /* some stream updates require passive update */
1261 return UPDATE_TYPE_FULL; 1259 if (stream_update) {
1260 if ((stream_update->src.height != 0) &&
1261 (stream_update->src.width != 0))
1262 return UPDATE_TYPE_FULL;
1263
1264 if ((stream_update->dst.height != 0) &&
1265 (stream_update->dst.width != 0))
1266 return UPDATE_TYPE_FULL;
1267
1268 if (stream_update->out_transfer_func)
1269 return UPDATE_TYPE_FULL;
1270
1271 if (stream_update->hdr_static_metadata)
1272 return UPDATE_TYPE_FULL;
1273
1274 if (stream_update->abm_level)
1275 return UPDATE_TYPE_FULL;
1276 }
1262 1277
1263 for (i = 0 ; i < surface_count; i++) { 1278 for (i = 0 ; i < surface_count; i++) {
1264 enum surface_update_type type = 1279 enum surface_update_type type =
@@ -1337,7 +1352,6 @@ static void commit_planes_for_stream(struct dc *dc,
1337 return; 1352 return;
1338 } 1353 }
1339 1354
1340 /* Full fe update*/
1341 for (j = 0; j < dc->res_pool->pipe_count; j++) { 1355 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1342 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; 1356 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1343 1357
@@ -1348,11 +1362,22 @@ static void commit_planes_for_stream(struct dc *dc,
1348 1362
1349 top_pipe_to_program = pipe_ctx; 1363 top_pipe_to_program = pipe_ctx;
1350 1364
1351 if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state) 1365 if (!pipe_ctx->plane_state)
1366 continue;
1367
1368 /* Fast update*/
1369 // VRR program can be done as part of FAST UPDATE
1370 if (stream_update && stream_update->adjust)
1371 dc->hwss.set_drr(&pipe_ctx, 1,
1372 stream_update->adjust->v_total_min,
1373 stream_update->adjust->v_total_max);
1374
1375 /* Full fe update*/
1376 if (update_type == UPDATE_TYPE_FAST)
1352 continue; 1377 continue;
1353 1378
1354 stream_status = 1379 stream_status =
1355 stream_get_status(context, pipe_ctx->stream); 1380 stream_get_status(context, pipe_ctx->stream);
1356 1381
1357 dc->hwss.apply_ctx_for_surface( 1382 dc->hwss.apply_ctx_for_surface(
1358 dc, pipe_ctx->stream, stream_status->plane_count, context); 1383 dc, pipe_ctx->stream, stream_status->plane_count, context);
@@ -1407,7 +1432,7 @@ static void commit_planes_for_stream(struct dc *dc,
1407 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); 1432 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
1408 } 1433 }
1409 1434
1410 if (stream && stream_update && update_type > UPDATE_TYPE_FAST) 1435 if (stream && stream_update)
1411 for (j = 0; j < dc->res_pool->pipe_count; j++) { 1436 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1412 struct pipe_ctx *pipe_ctx = 1437 struct pipe_ctx *pipe_ctx =
1413 &context->res_ctx.pipe_ctx[j]; 1438 &context->res_ctx.pipe_ctx[j];
@@ -1415,7 +1440,8 @@ static void commit_planes_for_stream(struct dc *dc,
1415 if (pipe_ctx->stream != stream) 1440 if (pipe_ctx->stream != stream)
1416 continue; 1441 continue;
1417 1442
1418 if (stream_update->hdr_static_metadata) { 1443 if (stream_update->hdr_static_metadata ||
1444 (stream_update->vrr_infopacket)) {
1419 resource_build_info_frame(pipe_ctx); 1445 resource_build_info_frame(pipe_ctx);
1420 dc->hwss.update_info_frame(pipe_ctx); 1446 dc->hwss.update_info_frame(pipe_ctx);
1421 } 1447 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index a7553b6d59c2..d91df5ef0cb3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2389,6 +2389,9 @@ static bool retrieve_link_cap(struct dc_link *link)
2389 2389
2390 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); 2390 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2391 2391
2392 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
2393 DP_DPCD_REV];
2394
2392 link->dpcd_caps.allow_invalid_MSA_timing_param = 2395 link->dpcd_caps.allow_invalid_MSA_timing_param =
2393 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 2396 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2394 2397
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2c348b11b9a5..4468b240929a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2475,119 +2475,13 @@ static void set_spd_info_packet(
2475{ 2475{
2476 /* SPD info packet for FreeSync */ 2476 /* SPD info packet for FreeSync */
2477 2477
2478 unsigned char checksum = 0;
2479 unsigned int idx, payload_size = 0;
2480
2481 /* Check if Freesync is supported. Return if false. If true, 2478 /* Check if Freesync is supported. Return if false. If true,
2482 * set the corresponding bit in the info packet 2479 * set the corresponding bit in the info packet
2483 */ 2480 */
2484 if (stream->freesync_ctx.supported == false) 2481 if (!stream->vrr_infopacket.valid)
2485 return; 2482 return;
2486 2483
2487 if (dc_is_hdmi_signal(stream->signal)) { 2484 *info_packet = stream->vrr_infopacket;
2488
2489 /* HEADER */
2490
2491 /* HB0 = Packet Type = 0x83 (Source Product
2492 * Descriptor InfoFrame)
2493 */
2494 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
2495
2496 /* HB1 = Version = 0x01 */
2497 info_packet->hb1 = 0x01;
2498
2499 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
2500 info_packet->hb2 = 0x08;
2501
2502 payload_size = 0x08;
2503
2504 } else if (dc_is_dp_signal(stream->signal)) {
2505
2506 /* HEADER */
2507
2508 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
2509 * when used to associate audio related info packets
2510 */
2511 info_packet->hb0 = 0x00;
2512
2513 /* HB1 = Packet Type = 0x83 (Source Product
2514 * Descriptor InfoFrame)
2515 */
2516 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
2517
2518 /* HB2 = [Bits 7:0 = Least significant eight bits -
2519 * For INFOFRAME, the value must be 1Bh]
2520 */
2521 info_packet->hb2 = 0x1B;
2522
2523 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
2524 * [Bits 1:0 = Most significant two bits = 0x00]
2525 */
2526 info_packet->hb3 = 0x04;
2527
2528 payload_size = 0x1B;
2529 }
2530
2531 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
2532 info_packet->sb[1] = 0x1A;
2533
2534 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
2535 info_packet->sb[2] = 0x00;
2536
2537 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
2538 info_packet->sb[3] = 0x00;
2539
2540 /* PB4 = Reserved */
2541 info_packet->sb[4] = 0x00;
2542
2543 /* PB5 = Reserved */
2544 info_packet->sb[5] = 0x00;
2545
2546 /* PB6 = [Bits 7:3 = Reserved] */
2547 info_packet->sb[6] = 0x00;
2548
2549 if (stream->freesync_ctx.supported == true)
2550 /* PB6 = [Bit 0 = FreeSync Supported] */
2551 info_packet->sb[6] |= 0x01;
2552
2553 if (stream->freesync_ctx.enabled == true)
2554 /* PB6 = [Bit 1 = FreeSync Enabled] */
2555 info_packet->sb[6] |= 0x02;
2556
2557 if (stream->freesync_ctx.active == true)
2558 /* PB6 = [Bit 2 = FreeSync Active] */
2559 info_packet->sb[6] |= 0x04;
2560
2561 /* PB7 = FreeSync Minimum refresh rate (Hz) */
2562 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
2563 min_refresh_in_micro_hz / 1000000);
2564
2565 /* PB8 = FreeSync Maximum refresh rate (Hz)
2566 *
2567 * Note: We do not use the maximum capable refresh rate
2568 * of the panel, because we should never go above the field
2569 * rate of the mode timing set.
2570 */
2571 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
2572 nominal_refresh_in_micro_hz / 1000000);
2573
2574 /* PB9 - PB27 = Reserved */
2575 for (idx = 9; idx <= 27; idx++)
2576 info_packet->sb[idx] = 0x00;
2577
2578 /* Calculate checksum */
2579 checksum += info_packet->hb0;
2580 checksum += info_packet->hb1;
2581 checksum += info_packet->hb2;
2582 checksum += info_packet->hb3;
2583
2584 for (idx = 1; idx <= payload_size; idx++)
2585 checksum += info_packet->sb[idx];
2586
2587 /* PB0 = Checksum (one byte complement) */
2588 info_packet->sb[0] = (unsigned char) (0x100 - checksum);
2589
2590 info_packet->valid = true;
2591} 2485}
2592 2486
2593static void set_hdr_static_info_packet( 2487static void set_hdr_static_info_packet(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b789cb2b354b..57f57cf0fe2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -708,12 +708,6 @@ struct crtc_trigger_info {
708 enum trigger_delay delay; 708 enum trigger_delay delay;
709}; 709};
710 710
711enum vrr_state {
712 VRR_STATE_OFF = 0,
713 VRR_STATE_VARIABLE,
714 VRR_STATE_FIXED,
715};
716
717struct dc_crtc_timing_adjust { 711struct dc_crtc_timing_adjust {
718 uint32_t v_total_min; 712 uint32_t v_total_min;
719 uint32_t v_total_max; 713 uint32_t v_total_max;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index cbfe418006cb..67101a525e3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -45,19 +45,25 @@ struct dc_stream_status {
45 struct dc_link *link; 45 struct dc_link *link;
46}; 46};
47 47
48// TODO: References to this needs to be removed..
49struct freesync_context {
50 bool dummy;
51};
52
48struct dc_stream_state { 53struct dc_stream_state {
49 struct dc_sink *sink; 54 struct dc_sink *sink;
50 struct dc_crtc_timing timing; 55 struct dc_crtc_timing timing;
51 struct dc_crtc_timing_adjust timing_adjust; 56 struct dc_crtc_timing_adjust adjust;
52 struct vrr_params vrr_params; 57 struct dc_info_packet vrr_infopacket;
53 58
54 struct rect src; /* composition area */ 59 struct rect src; /* composition area */
55 struct rect dst; /* stream addressable area */ 60 struct rect dst; /* stream addressable area */
56 61
57 struct audio_info audio_info; 62 // TODO: References to this needs to be removed..
58
59 struct freesync_context freesync_ctx; 63 struct freesync_context freesync_ctx;
60 64
65 struct audio_info audio_info;
66
61 struct dc_info_packet hdr_static_metadata; 67 struct dc_info_packet hdr_static_metadata;
62 PHYSICAL_ADDRESS_LOC dmdata_address; 68 PHYSICAL_ADDRESS_LOC dmdata_address;
63 bool use_dynamic_meta; 69 bool use_dynamic_meta;
@@ -120,6 +126,8 @@ struct dc_stream_update {
120 unsigned int *abm_level; 126 unsigned int *abm_level;
121 127
122 unsigned long long *periodic_fn_vsync_delta; 128 unsigned long long *periodic_fn_vsync_delta;
129 struct dc_crtc_timing_adjust *adjust;
130 struct dc_info_packet *vrr_infopacket;
123}; 131};
124 132
125bool dc_is_stream_unchanged( 133bool dc_is_stream_unchanged(
@@ -258,10 +266,8 @@ bool dc_stream_set_cursor_position(
258 266
259 267
260bool dc_stream_adjust_vmin_vmax(struct dc *dc, 268bool dc_stream_adjust_vmin_vmax(struct dc *dc,
261 struct dc_stream_state **stream, 269 struct dc_stream_state *stream,
262 int num_streams, 270 struct dc_crtc_timing_adjust *adjust);
263 int vmin,
264 int vmax);
265 271
266bool dc_stream_get_crtc_position(struct dc *dc, 272bool dc_stream_get_crtc_position(struct dc *dc,
267 struct dc_stream_state **stream, 273 struct dc_stream_state **stream,
@@ -288,13 +294,6 @@ void dc_stream_set_static_screen_events(struct dc *dc,
288void dc_stream_set_dither_option(struct dc_stream_state *stream, 294void dc_stream_set_dither_option(struct dc_stream_state *stream,
289 enum dc_dither_option option); 295 enum dc_dither_option option);
290 296
291
292bool dc_stream_adjust_vmin_vmax(struct dc *dc,
293 struct dc_stream_state **stream,
294 int num_streams,
295 int vmin,
296 int vmax);
297
298bool dc_stream_get_crtc_position(struct dc *dc, 297bool dc_stream_get_crtc_position(struct dc *dc,
299 struct dc_stream_state **stream, 298 struct dc_stream_state **stream,
300 int num_streams, 299 int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 8c6eb78b0c3b..58a6ef80a60e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -513,13 +513,11 @@ struct audio_info {
513 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 513 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
514}; 514};
515 515
516struct vrr_params { 516enum dc_infoframe_type {
517 enum vrr_state state; 517 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
518 uint32_t window_min; 518 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
519 uint32_t window_max; 519 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
520 uint32_t inserted_frame_duration_in_us; 520 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
521 uint32_t frames_to_insert;
522 uint32_t frame_counter;
523}; 521};
524 522
525struct dc_info_packet { 523struct dc_info_packet {
@@ -539,16 +537,6 @@ struct dc_plane_flip_time {
539 unsigned int prev_update_time_in_us; 537 unsigned int prev_update_time_in_us;
540}; 538};
541 539
542// Will combine with vrr_params at some point.
543struct freesync_context {
544 bool supported;
545 bool enabled;
546 bool active;
547
548 unsigned int min_refresh_in_micro_hz;
549 unsigned int nominal_refresh_in_micro_hz;
550};
551
552struct psr_config { 540struct psr_config {
553 unsigned char psr_version; 541 unsigned char psr_version;
554 unsigned int psr_rfb_setup_time; 542 unsigned int psr_rfb_setup_time;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2f2c5155c5aa..ae4792494fe7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1286,6 +1286,8 @@ static enum dc_status dce110_enable_stream_timing(
1286 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1286 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1287 pipe_ctx[pipe_ctx->pipe_idx]; 1287 pipe_ctx[pipe_ctx->pipe_idx];
1288 struct tg_color black_color = {0}; 1288 struct tg_color black_color = {0};
1289 struct drr_params params = {0};
1290 unsigned int event_triggers = 0;
1289 1291
1290 if (!pipe_ctx_old->stream) { 1292 if (!pipe_ctx_old->stream) {
1291 1293
@@ -1315,9 +1317,19 @@ static enum dc_status dce110_enable_stream_timing(
1315 &stream->timing, 1317 &stream->timing,
1316 true); 1318 true);
1317 1319
1318 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1320 params.vertical_total_min = stream->adjust.v_total_min;
1319 pipe_ctx->stream_res.tg, 1321 params.vertical_total_max = stream->adjust.v_total_max;
1320 0x182); 1322 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1323 pipe_ctx->stream_res.tg->funcs->set_drr(
1324 pipe_ctx->stream_res.tg, &params);
1325
1326 // DRR should set trigger event to monitor surface update event
1327 if (stream->adjust.v_total_min != 0 &&
1328 stream->adjust.v_total_max != 0)
1329 event_triggers = 0x80;
1330 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1331 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1332 pipe_ctx->stream_res.tg, event_triggers);
1321 } 1333 }
1322 1334
1323 if (!pipe_ctx_old->stream) { 1335 if (!pipe_ctx_old->stream) {
@@ -1328,8 +1340,6 @@ static enum dc_status dce110_enable_stream_timing(
1328 } 1340 }
1329 } 1341 }
1330 1342
1331
1332
1333 return DC_OK; 1343 return DC_OK;
1334} 1344}
1335 1345
@@ -1719,16 +1729,24 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
1719{ 1729{
1720 int i = 0; 1730 int i = 0;
1721 struct drr_params params = {0}; 1731 struct drr_params params = {0};
1732 // DRR should set trigger event to monitor surface update event
1733 unsigned int event_triggers = 0x80;
1722 1734
1723 params.vertical_total_max = vmax; 1735 params.vertical_total_max = vmax;
1724 params.vertical_total_min = vmin; 1736 params.vertical_total_min = vmin;
1725 1737
1726 /* TODO: If multiple pipes are to be supported, you need 1738 /* TODO: If multiple pipes are to be supported, you need
1727 * some GSL stuff 1739 * some GSL stuff. Static screen triggers may be programmed differently
1740 * as well.
1728 */ 1741 */
1729
1730 for (i = 0; i < num_pipes; i++) { 1742 for (i = 0; i < num_pipes; i++) {
1731 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params); 1743 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1744 pipe_ctx[i]->stream_res.tg, &params);
1745
1746 if (vmax != 0 && vmin != 0)
1747 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1748 pipe_ctx[i]->stream_res.tg,
1749 event_triggers);
1732 } 1750 }
1733} 1751}
1734 1752
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6d27f1db3c69..4b8bedb625b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -631,6 +631,8 @@ static enum dc_status dcn10_enable_stream_timing(
631 struct dc_stream_state *stream = pipe_ctx->stream; 631 struct dc_stream_state *stream = pipe_ctx->stream;
632 enum dc_color_space color_space; 632 enum dc_color_space color_space;
633 struct tg_color black_color = {0}; 633 struct tg_color black_color = {0};
634 struct drr_params params = {0};
635 unsigned int event_triggers = 0;
634 636
635 /* by upper caller loop, pipe0 is parent pipe and be called first. 637 /* by upper caller loop, pipe0 is parent pipe and be called first.
636 * back end is set up by for pipe0. Other children pipe share back end 638 * back end is set up by for pipe0. Other children pipe share back end
@@ -698,6 +700,19 @@ static enum dc_status dcn10_enable_stream_timing(
698 return DC_ERROR_UNEXPECTED; 700 return DC_ERROR_UNEXPECTED;
699 } 701 }
700 702
703 params.vertical_total_min = stream->adjust.v_total_min;
704 params.vertical_total_max = stream->adjust.v_total_max;
705 if (pipe_ctx->stream_res.tg->funcs->set_drr)
706 pipe_ctx->stream_res.tg->funcs->set_drr(
707 pipe_ctx->stream_res.tg, &params);
708
709 // DRR should set trigger event to monitor surface update event
710 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
711 event_triggers = 0x80;
712 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
713 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
714 pipe_ctx->stream_res.tg, event_triggers);
715
701 /* TODO program crtc source select for non-virtual signal*/ 716 /* TODO program crtc source select for non-virtual signal*/
702 /* TODO program FMT */ 717 /* TODO program FMT */
703 /* TODO setup link_enc */ 718 /* TODO setup link_enc */
@@ -2399,15 +2414,23 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
2399{ 2414{
2400 int i = 0; 2415 int i = 0;
2401 struct drr_params params = {0}; 2416 struct drr_params params = {0};
2417 // DRR should set trigger event to monitor surface update event
2418 unsigned int event_triggers = 0x80;
2402 2419
2403 params.vertical_total_max = vmax; 2420 params.vertical_total_max = vmax;
2404 params.vertical_total_min = vmin; 2421 params.vertical_total_min = vmin;
2405 2422
2406 /* TODO: If multiple pipes are to be supported, you need 2423 /* TODO: If multiple pipes are to be supported, you need
2407 * some GSL stuff 2424 * some GSL stuff. Static screen triggers may be programmed differently
2425 * as well.
2408 */ 2426 */
2409 for (i = 0; i < num_pipes; i++) { 2427 for (i = 0; i < num_pipes; i++) {
2410 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params); 2428 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2429 pipe_ctx[i]->stream_res.tg, &params);
2430 if (vmax != 0 && vmin != 0)
2431 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2432 pipe_ctx[i]->stream_res.tg,
2433 event_triggers);
2411 } 2434 }
2412} 2435}
2413 2436
diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h b/drivers/gpu/drm/amd/display/include/set_mode_types.h
index fee2b6ffcfc1..2b836e582c08 100644
--- a/drivers/gpu/drm/amd/display/include/set_mode_types.h
+++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h
@@ -90,18 +90,6 @@ union hdmi_info_packet {
90 struct info_packet_raw_data packet_raw_data; 90 struct info_packet_raw_data packet_raw_data;
91}; 91};
92 92
93struct info_packet {
94 enum info_frame_flag flags;
95 union hdmi_info_packet info_packet_hdmi;
96};
97
98struct info_frame {
99 struct info_packet avi_info_packet;
100 struct info_packet gamut_packet;
101 struct info_packet vendor_info_packet;
102 struct info_packet spd_info_packet;
103};
104
105#pragma pack(pop) 93#pragma pack(pop)
106 94
107#endif /* __DAL_SET_MODE_TYPES_H__ */ 95#endif /* __DAL_SET_MODE_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index fa344ceafc17..5e12e463c06a 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -30,6 +30,7 @@
30 30
31#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 31#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
32 32
33#define MIN_REFRESH_RANGE_IN_US 10000000
33/* Refresh rate ramp at a fixed rate of 65 Hz/second */ 34/* Refresh rate ramp at a fixed rate of 65 Hz/second */
34#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65) 35#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
35/* Number of elements in the render times cache array */ 36/* Number of elements in the render times cache array */
@@ -40,103 +41,9 @@
40#define FIXED_REFRESH_ENTER_FRAME_COUNT 5 41#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
41#define FIXED_REFRESH_EXIT_FRAME_COUNT 5 42#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
42 43
43#define FREESYNC_REGISTRY_NAME "freesync_v1"
44
45#define FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY "DalFreeSyncNoStaticForExternalDp"
46
47#define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal"
48
49#define FREESYNC_DEFAULT_REGKEY "LCDFreeSyncDefault"
50
51struct gradual_static_ramp {
52 bool ramp_is_active;
53 bool ramp_direction_is_up;
54 unsigned int ramp_current_frame_duration_in_ns;
55};
56
57struct freesync_time {
58 /* video (48Hz feature) related */
59 unsigned int update_duration_in_ns;
60
61 /* BTR/fixed refresh related */
62 unsigned int prev_time_stamp_in_us;
63
64 unsigned int min_render_time_in_us;
65 unsigned int max_render_time_in_us;
66
67 unsigned int render_times_index;
68 unsigned int render_times[RENDER_TIMES_MAX_COUNT];
69
70 unsigned int min_window;
71 unsigned int max_window;
72};
73
74struct below_the_range {
75 bool btr_active;
76 bool program_btr;
77
78 unsigned int mid_point_in_us;
79
80 unsigned int inserted_frame_duration_in_us;
81 unsigned int frames_to_insert;
82 unsigned int frame_counter;
83};
84
85struct fixed_refresh {
86 bool fixed_active;
87 bool program_fixed;
88 unsigned int frame_counter;
89};
90
91struct freesync_range {
92 unsigned int min_refresh;
93 unsigned int max_frame_duration;
94 unsigned int vmax;
95
96 unsigned int max_refresh;
97 unsigned int min_frame_duration;
98 unsigned int vmin;
99};
100
101struct freesync_state {
102 bool fullscreen;
103 bool static_screen;
104 bool video;
105
106 unsigned int vmin;
107 unsigned int vmax;
108
109 struct freesync_time time;
110
111 unsigned int nominal_refresh_rate_in_micro_hz;
112 bool windowed_fullscreen;
113
114 struct gradual_static_ramp static_ramp;
115 struct below_the_range btr;
116 struct fixed_refresh fixed_refresh;
117 struct freesync_range freesync_range;
118};
119
120struct freesync_entity {
121 struct dc_stream_state *stream;
122 struct mod_freesync_caps *caps;
123 struct freesync_state state;
124 struct mod_freesync_user_enable user_enable;
125};
126
127struct freesync_registry_options {
128 bool drr_external_supported;
129 bool drr_internal_supported;
130 bool lcd_freesync_default_set;
131 int lcd_freesync_default_value;
132};
133
134struct core_freesync { 44struct core_freesync {
135 struct mod_freesync public; 45 struct mod_freesync public;
136 struct dc *dc; 46 struct dc *dc;
137 struct freesync_registry_options opts;
138 struct freesync_entity *map;
139 int num_entities;
140}; 47};
141 48
142#define MOD_FREESYNC_TO_CORE(mod_freesync)\ 49#define MOD_FREESYNC_TO_CORE(mod_freesync)\
@@ -147,69 +54,16 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
147 struct core_freesync *core_freesync = 54 struct core_freesync *core_freesync =
148 kzalloc(sizeof(struct core_freesync), GFP_KERNEL); 55 kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
149 56
150
151 struct persistent_data_flag flag;
152
153 int i, data = 0;
154
155 if (core_freesync == NULL) 57 if (core_freesync == NULL)
156 goto fail_alloc_context; 58 goto fail_alloc_context;
157 59
158 core_freesync->map = kcalloc(MOD_FREESYNC_MAX_CONCURRENT_STREAMS,
159 sizeof(struct freesync_entity),
160 GFP_KERNEL);
161
162 if (core_freesync->map == NULL)
163 goto fail_alloc_map;
164
165 for (i = 0; i < MOD_FREESYNC_MAX_CONCURRENT_STREAMS; i++)
166 core_freesync->map[i].stream = NULL;
167
168 core_freesync->num_entities = 0;
169
170 if (dc == NULL) 60 if (dc == NULL)
171 goto fail_construct; 61 goto fail_construct;
172 62
173 core_freesync->dc = dc; 63 core_freesync->dc = dc;
174
175 /* Create initial module folder in registry for freesync enable data */
176 flag.save_per_edid = true;
177 flag.save_per_link = false;
178 dm_write_persistent_data(dc->ctx, NULL, FREESYNC_REGISTRY_NAME,
179 NULL, NULL, 0, &flag);
180 flag.save_per_edid = false;
181 flag.save_per_link = false;
182
183 if (dm_read_persistent_data(dc->ctx, NULL, NULL,
184 FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY,
185 &data, sizeof(data), &flag)) {
186 core_freesync->opts.drr_internal_supported =
187 (data & 1) ? false : true;
188 }
189
190 if (dm_read_persistent_data(dc->ctx, NULL, NULL,
191 FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY,
192 &data, sizeof(data), &flag)) {
193 core_freesync->opts.drr_external_supported =
194 (data & 1) ? false : true;
195 }
196
197 if (dm_read_persistent_data(dc->ctx, NULL, NULL,
198 FREESYNC_DEFAULT_REGKEY,
199 &data, sizeof(data), &flag)) {
200 core_freesync->opts.lcd_freesync_default_set = true;
201 core_freesync->opts.lcd_freesync_default_value = data;
202 } else {
203 core_freesync->opts.lcd_freesync_default_set = false;
204 core_freesync->opts.lcd_freesync_default_value = 0;
205 }
206
207 return &core_freesync->public; 64 return &core_freesync->public;
208 65
209fail_construct: 66fail_construct:
210 kfree(core_freesync->map);
211
212fail_alloc_map:
213 kfree(core_freesync); 67 kfree(core_freesync);
214 68
215fail_alloc_context: 69fail_alloc_context:
@@ -218,968 +72,396 @@ fail_alloc_context:
218 72
219void mod_freesync_destroy(struct mod_freesync *mod_freesync) 73void mod_freesync_destroy(struct mod_freesync *mod_freesync)
220{ 74{
221 if (mod_freesync != NULL) {
222 int i;
223 struct core_freesync *core_freesync =
224 MOD_FREESYNC_TO_CORE(mod_freesync);
225
226 for (i = 0; i < core_freesync->num_entities; i++)
227 if (core_freesync->map[i].stream)
228 dc_stream_release(core_freesync->map[i].stream);
229
230 kfree(core_freesync->map);
231
232 kfree(core_freesync);
233 }
234}
235
236/* Given a specific dc_stream* this function finds its equivalent
237 * on the core_freesync->map and returns the corresponding index
238 */
239static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
240 struct dc_stream_state *stream)
241{
242 unsigned int index = 0;
243
244 for (index = 0; index < core_freesync->num_entities; index++) {
245 if (core_freesync->map[index].stream == stream) {
246 return index;
247 }
248 }
249 /* Could not find stream requested */
250 ASSERT(false);
251 return index;
252}
253
254bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
255 struct dc_stream_state *stream, struct mod_freesync_caps *caps)
256{
257 struct dc *dc = NULL;
258 struct core_freesync *core_freesync = NULL; 75 struct core_freesync *core_freesync = NULL;
259 int persistent_freesync_enable = 0;
260 struct persistent_data_flag flag;
261 unsigned int nom_refresh_rate_uhz;
262 unsigned long long temp;
263
264 if (mod_freesync == NULL) 76 if (mod_freesync == NULL)
265 return false; 77 return;
266
267 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 78 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
268 dc = core_freesync->dc; 79 kfree(core_freesync);
269
270 flag.save_per_edid = true;
271 flag.save_per_link = false;
272
273 if (core_freesync->num_entities < MOD_FREESYNC_MAX_CONCURRENT_STREAMS) {
274
275 dc_stream_retain(stream);
276
277 temp = stream->timing.pix_clk_khz;
278 temp *= 1000ULL * 1000ULL * 1000ULL;
279 temp = div_u64(temp, stream->timing.h_total);
280 temp = div_u64(temp, stream->timing.v_total);
281
282 nom_refresh_rate_uhz = (unsigned int) temp;
283
284 core_freesync->map[core_freesync->num_entities].stream = stream;
285 core_freesync->map[core_freesync->num_entities].caps = caps;
286
287 core_freesync->map[core_freesync->num_entities].state.
288 fullscreen = false;
289 core_freesync->map[core_freesync->num_entities].state.
290 static_screen = false;
291 core_freesync->map[core_freesync->num_entities].state.
292 video = false;
293 core_freesync->map[core_freesync->num_entities].state.time.
294 update_duration_in_ns = 0;
295 core_freesync->map[core_freesync->num_entities].state.
296 static_ramp.ramp_is_active = false;
297
298 /* get persistent data from registry */
299 if (dm_read_persistent_data(dc->ctx, stream->sink,
300 FREESYNC_REGISTRY_NAME,
301 "userenable", &persistent_freesync_enable,
302 sizeof(int), &flag)) {
303 core_freesync->map[core_freesync->num_entities].user_enable.
304 enable_for_gaming =
305 (persistent_freesync_enable & 1) ? true : false;
306 core_freesync->map[core_freesync->num_entities].user_enable.
307 enable_for_static =
308 (persistent_freesync_enable & 2) ? true : false;
309 core_freesync->map[core_freesync->num_entities].user_enable.
310 enable_for_video =
311 (persistent_freesync_enable & 4) ? true : false;
312 /* If FreeSync display and LCDFreeSyncDefault is set, use as default values write back to userenable */
313 } else if (caps->supported && (core_freesync->opts.lcd_freesync_default_set)) {
314 core_freesync->map[core_freesync->num_entities].user_enable.enable_for_gaming =
315 (core_freesync->opts.lcd_freesync_default_value & 1) ? true : false;
316 core_freesync->map[core_freesync->num_entities].user_enable.enable_for_static =
317 (core_freesync->opts.lcd_freesync_default_value & 2) ? true : false;
318 core_freesync->map[core_freesync->num_entities].user_enable.enable_for_video =
319 (core_freesync->opts.lcd_freesync_default_value & 4) ? true : false;
320 dm_write_persistent_data(dc->ctx, stream->sink,
321 FREESYNC_REGISTRY_NAME,
322 "userenable", &core_freesync->opts.lcd_freesync_default_value,
323 sizeof(int), &flag);
324 } else {
325 core_freesync->map[core_freesync->num_entities].user_enable.
326 enable_for_gaming = false;
327 core_freesync->map[core_freesync->num_entities].user_enable.
328 enable_for_static = false;
329 core_freesync->map[core_freesync->num_entities].user_enable.
330 enable_for_video = false;
331 }
332
333 if (caps->supported &&
334 nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz &&
335 nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz)
336 stream->ignore_msa_timing_param = 1;
337
338 core_freesync->num_entities++;
339 return true;
340 }
341 return false;
342} 80}
343 81
344bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, 82#if 0 /* unused currently */
345 struct dc_stream_state *stream) 83static unsigned int calc_refresh_in_uhz_from_duration(
84 unsigned int duration_in_ns)
346{ 85{
347 int i = 0; 86 unsigned int refresh_in_uhz =
348 struct core_freesync *core_freesync = NULL; 87 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
349 unsigned int index = 0; 88 duration_in_ns)));
350 89 return refresh_in_uhz;
351 if (mod_freesync == NULL) 90}
352 return false; 91#endif
353 92
354 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 93static unsigned int calc_duration_in_us_from_refresh_in_uhz(
355 index = map_index_from_stream(core_freesync, stream); 94 unsigned int refresh_in_uhz)
356 95{
357 dc_stream_release(core_freesync->map[index].stream); 96 unsigned int duration_in_us =
358 core_freesync->map[index].stream = NULL; 97 ((unsigned int)(div64_u64((1000000000ULL * 1000),
359 /* To remove this entity, shift everything after down */ 98 refresh_in_uhz)));
360 for (i = index; i < core_freesync->num_entities - 1; i++) 99 return duration_in_us;
361 core_freesync->map[i] = core_freesync->map[i + 1];
362 core_freesync->num_entities--;
363 return true;
364} 100}
365 101
366static void adjust_vmin_vmax(struct core_freesync *core_freesync, 102static unsigned int calc_duration_in_us_from_v_total(
367 struct dc_stream_state **streams, 103 const struct dc_stream_state *stream,
368 int num_streams, 104 const struct mod_vrr_params *in_vrr,
369 int map_index, 105 unsigned int v_total)
370 unsigned int v_total_min,
371 unsigned int v_total_max)
372{ 106{
373 if (num_streams == 0 || streams == NULL || num_streams > 1) 107 unsigned int duration_in_us =
374 return; 108 (unsigned int)(div64_u64(((unsigned long long)(v_total)
109 * 1000) * stream->timing.h_total,
110 stream->timing.pix_clk_khz));
375 111
376 core_freesync->map[map_index].state.vmin = v_total_min; 112 if (duration_in_us < in_vrr->min_duration_in_us)
377 core_freesync->map[map_index].state.vmax = v_total_max; 113 duration_in_us = in_vrr->min_duration_in_us;
378 114
379 dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, 115 if (duration_in_us > in_vrr->max_duration_in_us)
380 num_streams, v_total_min, 116 duration_in_us = in_vrr->max_duration_in_us;
381 v_total_max);
382}
383 117
118 return duration_in_us;
119}
384 120
385static void update_stream_freesync_context(struct core_freesync *core_freesync, 121static unsigned int calc_v_total_from_refresh(
386 struct dc_stream_state *stream) 122 const struct dc_stream_state *stream,
123 unsigned int refresh_in_uhz)
387{ 124{
388 unsigned int index; 125 unsigned int v_total = stream->timing.v_total;
389 struct freesync_context *ctx; 126 unsigned int frame_duration_in_ns;
390 127
391 ctx = &stream->freesync_ctx; 128 frame_duration_in_ns =
129 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
130 refresh_in_uhz)));
392 131
393 index = map_index_from_stream(core_freesync, stream); 132 v_total = div64_u64(div64_u64(((unsigned long long)(
133 frame_duration_in_ns) * stream->timing.pix_clk_khz),
134 stream->timing.h_total), 1000000);
394 135
395 ctx->supported = core_freesync->map[index].caps->supported; 136 /* v_total cannot be less than nominal */
396 ctx->enabled = (core_freesync->map[index].user_enable.enable_for_gaming || 137 if (v_total < stream->timing.v_total) {
397 core_freesync->map[index].user_enable.enable_for_video || 138 ASSERT(v_total < stream->timing.v_total);
398 core_freesync->map[index].user_enable.enable_for_static); 139 v_total = stream->timing.v_total;
399 ctx->active = (core_freesync->map[index].state.fullscreen || 140 }
400 core_freesync->map[index].state.video ||
401 core_freesync->map[index].state.static_ramp.ramp_is_active);
402 ctx->min_refresh_in_micro_hz =
403 core_freesync->map[index].caps->min_refresh_in_micro_hz;
404 ctx->nominal_refresh_in_micro_hz = core_freesync->
405 map[index].state.nominal_refresh_rate_in_micro_hz;
406 141
142 return v_total;
407} 143}
408 144
409static void update_stream(struct core_freesync *core_freesync, 145static unsigned int calc_v_total_from_duration(
410 struct dc_stream_state *stream) 146 const struct dc_stream_state *stream,
147 const struct mod_vrr_params *vrr,
148 unsigned int duration_in_us)
411{ 149{
412 unsigned int index = map_index_from_stream(core_freesync, stream); 150 unsigned int v_total = 0;
413 if (core_freesync->map[index].caps->supported) {
414 stream->ignore_msa_timing_param = 1;
415 update_stream_freesync_context(core_freesync, stream);
416 }
417}
418 151
419static void calc_freesync_range(struct core_freesync *core_freesync, 152 if (duration_in_us < vrr->min_duration_in_us)
420 struct dc_stream_state *stream, 153 duration_in_us = vrr->min_duration_in_us;
421 struct freesync_state *state,
422 unsigned int min_refresh_in_uhz,
423 unsigned int max_refresh_in_uhz)
424{
425 unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0;
426 unsigned int index = map_index_from_stream(core_freesync, stream);
427 uint32_t vtotal = stream->timing.v_total;
428
429 if ((min_refresh_in_uhz == 0) || (max_refresh_in_uhz == 0)) {
430 state->freesync_range.min_refresh =
431 state->nominal_refresh_rate_in_micro_hz;
432 state->freesync_range.max_refresh =
433 state->nominal_refresh_rate_in_micro_hz;
434 154
435 state->freesync_range.max_frame_duration = 0; 155 if (duration_in_us > vrr->max_duration_in_us)
436 state->freesync_range.min_frame_duration = 0; 156 duration_in_us = vrr->max_duration_in_us;
437 157
438 state->freesync_range.vmax = vtotal; 158 v_total = div64_u64(div64_u64(((unsigned long long)(
439 state->freesync_range.vmin = vtotal; 159 duration_in_us) * stream->timing.pix_clk_khz),
440 160 stream->timing.h_total), 1000);
441 return;
442 }
443 161
444 min_frame_duration_in_ns = ((unsigned int) (div64_u64( 162 /* v_total cannot be less than nominal */
445 (1000000000ULL * 1000000), 163 if (v_total < stream->timing.v_total) {
446 max_refresh_in_uhz))); 164 ASSERT(v_total < stream->timing.v_total);
447 max_frame_duration_in_ns = ((unsigned int) (div64_u64( 165 v_total = stream->timing.v_total;
448 (1000000000ULL * 1000000),
449 min_refresh_in_uhz)));
450
451 state->freesync_range.min_refresh = min_refresh_in_uhz;
452 state->freesync_range.max_refresh = max_refresh_in_uhz;
453
454 state->freesync_range.max_frame_duration = max_frame_duration_in_ns;
455 state->freesync_range.min_frame_duration = min_frame_duration_in_ns;
456
457 state->freesync_range.vmax = div64_u64(div64_u64(((unsigned long long)(
458 max_frame_duration_in_ns) * stream->timing.pix_clk_khz),
459 stream->timing.h_total), 1000000);
460 state->freesync_range.vmin = div64_u64(div64_u64(((unsigned long long)(
461 min_frame_duration_in_ns) * stream->timing.pix_clk_khz),
462 stream->timing.h_total), 1000000);
463
464 /* vmin/vmax cannot be less than vtotal */
465 if (state->freesync_range.vmin < vtotal) {
466 /* Error of 1 is permissible */
467 ASSERT((state->freesync_range.vmin + 1) >= vtotal);
468 state->freesync_range.vmin = vtotal;
469 } 166 }
470 167
471 if (state->freesync_range.vmax < vtotal) { 168 return v_total;
472 /* Error of 1 is permissible */
473 ASSERT((state->freesync_range.vmax + 1) >= vtotal);
474 state->freesync_range.vmax = vtotal;
475 }
476
477 /* Determine whether BTR can be supported */
478 if (max_frame_duration_in_ns >=
479 2 * min_frame_duration_in_ns)
480 core_freesync->map[index].caps->btr_supported = true;
481 else
482 core_freesync->map[index].caps->btr_supported = false;
483
484 /* Cache the time variables */
485 state->time.max_render_time_in_us =
486 max_frame_duration_in_ns / 1000;
487 state->time.min_render_time_in_us =
488 min_frame_duration_in_ns / 1000;
489 state->btr.mid_point_in_us =
490 (max_frame_duration_in_ns +
491 min_frame_duration_in_ns) / 2000;
492} 169}
493 170
494static void calc_v_total_from_duration(struct dc_stream_state *stream, 171static void update_v_total_for_static_ramp(
495 unsigned int duration_in_ns, int *v_total_nominal) 172 struct core_freesync *core_freesync,
173 const struct dc_stream_state *stream,
174 struct mod_vrr_params *in_out_vrr)
496{ 175{
497 *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( 176 unsigned int v_total = 0;
498 duration_in_ns) * stream->timing.pix_clk_khz), 177 unsigned int current_duration_in_us =
499 stream->timing.h_total), 1000000); 178 calc_duration_in_us_from_v_total(
500} 179 stream, in_out_vrr,
501 180 in_out_vrr->adjust.v_total_max);
502static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, 181 unsigned int target_duration_in_us =
503 struct dc_stream_state *stream, 182 calc_duration_in_us_from_refresh_in_uhz(
504 unsigned int index, int *v_total) 183 in_out_vrr->fixed.target_refresh_in_uhz);
505{ 184 bool ramp_direction_is_up = (current_duration_in_us >
506 unsigned int frame_duration = 0; 185 target_duration_in_us) ? true : false;
507
508 struct gradual_static_ramp *static_ramp_variables =
509 &core_freesync->map[index].state.static_ramp;
510 186
511 /* Calc ratio between new and current frame duration with 3 digit */ 187 /* Calc ratio between new and current frame duration with 3 digit */
512 unsigned int frame_duration_ratio = div64_u64(1000000, 188 unsigned int frame_duration_ratio = div64_u64(1000000,
513 (1000 + div64_u64(((unsigned long long)( 189 (1000 + div64_u64(((unsigned long long)(
514 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) * 190 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
515 static_ramp_variables->ramp_current_frame_duration_in_ns), 191 current_duration_in_us),
516 1000000000))); 192 1000000)));
517 193
518 /* Calculate delta between new and current frame duration in ns */ 194 /* Calculate delta between new and current frame duration in us */
519 unsigned int frame_duration_delta = div64_u64(((unsigned long long)( 195 unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
520 static_ramp_variables->ramp_current_frame_duration_in_ns) * 196 current_duration_in_us) *
521 (1000 - frame_duration_ratio)), 1000); 197 (1000 - frame_duration_ratio)), 1000);
522 198
523 /* Adjust frame duration delta based on ratio between current and 199 /* Adjust frame duration delta based on ratio between current and
524 * standard frame duration (frame duration at 60 Hz refresh rate). 200 * standard frame duration (frame duration at 60 Hz refresh rate).
525 */ 201 */
526 unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)( 202 unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
527 frame_duration_delta) * static_ramp_variables-> 203 frame_duration_delta) * current_duration_in_us), 16666);
528 ramp_current_frame_duration_in_ns), 16666666);
529 204
530 /* Going to a higher refresh rate (lower frame duration) */ 205 /* Going to a higher refresh rate (lower frame duration) */
531 if (static_ramp_variables->ramp_direction_is_up) { 206 if (ramp_direction_is_up) {
532 /* reduce frame duration */ 207 /* reduce frame duration */
533 static_ramp_variables->ramp_current_frame_duration_in_ns -= 208 current_duration_in_us -= ramp_rate_interpolated;
534 ramp_rate_interpolated;
535
536 /* min frame duration */
537 frame_duration = ((unsigned int) (div64_u64(
538 (1000000000ULL * 1000000),
539 core_freesync->map[index].state.
540 nominal_refresh_rate_in_micro_hz)));
541 209
542 /* adjust for frame duration below min */ 210 /* adjust for frame duration below min */
543 if (static_ramp_variables->ramp_current_frame_duration_in_ns <= 211 if (current_duration_in_us <= target_duration_in_us) {
544 frame_duration) { 212 in_out_vrr->fixed.ramping_active = false;
545 213 in_out_vrr->fixed.ramping_done = true;
546 static_ramp_variables->ramp_is_active = false; 214 current_duration_in_us =
547 static_ramp_variables-> 215 calc_duration_in_us_from_refresh_in_uhz(
548 ramp_current_frame_duration_in_ns = 216 in_out_vrr->fixed.target_refresh_in_uhz);
549 frame_duration;
550 } 217 }
551 /* Going to a lower refresh rate (larger frame duration) */ 218 /* Going to a lower refresh rate (larger frame duration) */
552 } else { 219 } else {
553 /* increase frame duration */ 220 /* increase frame duration */
554 static_ramp_variables->ramp_current_frame_duration_in_ns += 221 current_duration_in_us += ramp_rate_interpolated;
555 ramp_rate_interpolated;
556
557 /* max frame duration */
558 frame_duration = ((unsigned int) (div64_u64(
559 (1000000000ULL * 1000000),
560 core_freesync->map[index].caps->min_refresh_in_micro_hz)));
561 222
562 /* adjust for frame duration above max */ 223 /* adjust for frame duration above max */
563 if (static_ramp_variables->ramp_current_frame_duration_in_ns >= 224 if (current_duration_in_us >= target_duration_in_us) {
564 frame_duration) { 225 in_out_vrr->fixed.ramping_active = false;
565 226 in_out_vrr->fixed.ramping_done = true;
566 static_ramp_variables->ramp_is_active = false; 227 current_duration_in_us =
567 static_ramp_variables-> 228 calc_duration_in_us_from_refresh_in_uhz(
568 ramp_current_frame_duration_in_ns = 229 in_out_vrr->fixed.target_refresh_in_uhz);
569 frame_duration;
570 } 230 }
571 } 231 }
572 232
573 calc_v_total_from_duration(stream, static_ramp_variables-> 233 v_total = calc_v_total_from_duration(stream,
574 ramp_current_frame_duration_in_ns, v_total); 234 in_out_vrr,
575} 235 current_duration_in_us);
576
577static void reset_freesync_state_variables(struct freesync_state* state)
578{
579 state->static_ramp.ramp_is_active = false;
580 if (state->nominal_refresh_rate_in_micro_hz)
581 state->static_ramp.ramp_current_frame_duration_in_ns =
582 ((unsigned int) (div64_u64(
583 (1000000000ULL * 1000000),
584 state->nominal_refresh_rate_in_micro_hz)));
585
586 state->btr.btr_active = false;
587 state->btr.frame_counter = 0;
588 state->btr.frames_to_insert = 0;
589 state->btr.inserted_frame_duration_in_us = 0;
590 state->btr.program_btr = false;
591
592 state->fixed_refresh.fixed_active = false;
593 state->fixed_refresh.program_fixed = false;
594}
595/*
596 * Sets freesync mode on a stream depending on current freesync state.
597 */
598static bool set_freesync_on_streams(struct core_freesync *core_freesync,
599 struct dc_stream_state **streams, int num_streams)
600{
601 int v_total_nominal = 0, v_total_min = 0, v_total_max = 0;
602 unsigned int stream_idx, map_index = 0;
603 struct freesync_state *state;
604 236
605 if (num_streams == 0 || streams == NULL || num_streams > 1)
606 return false;
607 237
608 for (stream_idx = 0; stream_idx < num_streams; stream_idx++) { 238 in_out_vrr->adjust.v_total_min = v_total;
609 239 in_out_vrr->adjust.v_total_max = v_total;
610 map_index = map_index_from_stream(core_freesync,
611 streams[stream_idx]);
612
613 state = &core_freesync->map[map_index].state;
614
615 if (core_freesync->map[map_index].caps->supported) {
616
617 /* Fullscreen has the topmost priority. If the
618 * fullscreen bit is set, we are in a fullscreen
619 * application where it should not matter if it is
620 * static screen. We should not check the static_screen
621 * or video bit.
622 *
623 * Special cases of fullscreen include btr and fixed
624 * refresh. We program btr on every flip and involves
625 * programming full range right before the last inserted frame.
626 * However, we do not want to program the full freesync range
627 * when fixed refresh is active, because we only program
628 * that logic once and this will override it.
629 */
630 if (core_freesync->map[map_index].user_enable.
631 enable_for_gaming == true &&
632 state->fullscreen == true &&
633 state->fixed_refresh.fixed_active == false) {
634 /* Enable freesync */
635
636 v_total_min = state->freesync_range.vmin;
637 v_total_max = state->freesync_range.vmax;
638
639 /* Update the freesync context for the stream */
640 update_stream_freesync_context(core_freesync,
641 streams[stream_idx]);
642
643 adjust_vmin_vmax(core_freesync, streams,
644 num_streams, map_index,
645 v_total_min,
646 v_total_max);
647
648 return true;
649
650 } else if (core_freesync->map[map_index].user_enable.
651 enable_for_video && state->video == true) {
652 /* Enable 48Hz feature */
653
654 calc_v_total_from_duration(streams[stream_idx],
655 state->time.update_duration_in_ns,
656 &v_total_nominal);
657
658 /* Program only if v_total_nominal is in range*/
659 if (v_total_nominal >=
660 streams[stream_idx]->timing.v_total) {
661
662 /* Update the freesync context for
663 * the stream
664 */
665 update_stream_freesync_context(
666 core_freesync,
667 streams[stream_idx]);
668
669 adjust_vmin_vmax(
670 core_freesync, streams,
671 num_streams, map_index,
672 v_total_nominal,
673 v_total_nominal);
674 }
675 return true;
676
677 } else {
678 /* Disable freesync */
679 v_total_nominal = streams[stream_idx]->
680 timing.v_total;
681
682 /* Update the freesync context for
683 * the stream
684 */
685 update_stream_freesync_context(
686 core_freesync,
687 streams[stream_idx]);
688
689 adjust_vmin_vmax(core_freesync, streams,
690 num_streams, map_index,
691 v_total_nominal,
692 v_total_nominal);
693
694 /* Reset the cached variables */
695 reset_freesync_state_variables(state);
696
697 return true;
698 }
699 } else {
700 /* Disable freesync */
701 v_total_nominal = streams[stream_idx]->
702 timing.v_total;
703 /*
704 * we have to reset drr always even sink does
705 * not support freesync because a former stream has
706 * be programmed
707 */
708 adjust_vmin_vmax(core_freesync, streams,
709 num_streams, map_index,
710 v_total_nominal,
711 v_total_nominal);
712 /* Reset the cached variables */
713 reset_freesync_state_variables(state);
714 }
715
716 }
717
718 return false;
719} 240}
720 241
721static void set_static_ramp_variables(struct core_freesync *core_freesync, 242static void apply_below_the_range(struct core_freesync *core_freesync,
722 unsigned int index, bool enable_static_screen) 243 const struct dc_stream_state *stream,
723{ 244 unsigned int last_render_time_in_us,
724 unsigned int frame_duration = 0; 245 struct mod_vrr_params *in_out_vrr)
725 unsigned int nominal_refresh_rate = core_freesync->map[index].state.
726 nominal_refresh_rate_in_micro_hz;
727 unsigned int min_refresh_rate= core_freesync->map[index].caps->
728 min_refresh_in_micro_hz;
729 struct gradual_static_ramp *static_ramp_variables =
730 &core_freesync->map[index].state.static_ramp;
731
732 /* If we are ENABLING static screen, refresh rate should go DOWN.
733 * If we are DISABLING static screen, refresh rate should go UP.
734 */
735 if (enable_static_screen)
736 static_ramp_variables->ramp_direction_is_up = false;
737 else
738 static_ramp_variables->ramp_direction_is_up = true;
739
740 /* If ramp is not active, set initial frame duration depending on
741 * whether we are enabling/disabling static screen mode. If the ramp is
742 * already active, ramp should continue in the opposite direction
743 * starting with the current frame duration
744 */
745 if (!static_ramp_variables->ramp_is_active) {
746 if (enable_static_screen == true) {
747 /* Going to lower refresh rate, so start from max
748 * refresh rate (min frame duration)
749 */
750 frame_duration = ((unsigned int) (div64_u64(
751 (1000000000ULL * 1000000),
752 nominal_refresh_rate)));
753 } else {
754 /* Going to higher refresh rate, so start from min
755 * refresh rate (max frame duration)
756 */
757 frame_duration = ((unsigned int) (div64_u64(
758 (1000000000ULL * 1000000),
759 min_refresh_rate)));
760 }
761 static_ramp_variables->
762 ramp_current_frame_duration_in_ns = frame_duration;
763
764 static_ramp_variables->ramp_is_active = true;
765 }
766}
767
768void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
769 struct dc_stream_state **streams, int num_streams)
770{ 246{
771 unsigned int index, v_total, inserted_frame_v_total = 0; 247 unsigned int inserted_frame_duration_in_us = 0;
772 unsigned int min_frame_duration_in_ns, vmax, vmin = 0; 248 unsigned int mid_point_frames_ceil = 0;
773 struct freesync_state *state; 249 unsigned int mid_point_frames_floor = 0;
774 struct core_freesync *core_freesync = NULL; 250 unsigned int frame_time_in_us = 0;
775 struct dc_static_screen_events triggers = {0}; 251 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
776 252 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
777 if (mod_freesync == NULL) 253 unsigned int frames_to_insert = 0;
778 return; 254 unsigned int min_frame_duration_in_ns = 0;
779 255 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
780 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
781
782 if (core_freesync->num_entities == 0)
783 return;
784
785 index = map_index_from_stream(core_freesync,
786 streams[0]);
787
788 if (core_freesync->map[index].caps->supported == false)
789 return;
790
791 state = &core_freesync->map[index].state;
792
793 /* Below the Range Logic */
794
795 /* Only execute if in fullscreen mode */
796 if (state->fullscreen == true &&
797 core_freesync->map[index].user_enable.enable_for_gaming &&
798 core_freesync->map[index].caps->btr_supported &&
799 state->btr.btr_active) {
800 256
801 /* TODO: pass in flag for Pre-DCE12 ASIC 257 min_frame_duration_in_ns = ((unsigned int) (div64_u64(
802 * in order for frame variable duration to take affect, 258 (1000000000ULL * 1000000),
803 * it needs to be done one VSYNC early, which is at 259 in_out_vrr->max_refresh_in_uhz)));
804 * frameCounter == 1.
805 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
806 * will take affect on current frame
807 */
808 if (state->btr.frames_to_insert == state->btr.frame_counter) {
809 260
810 min_frame_duration_in_ns = ((unsigned int) (div64_u64( 261 /* Program BTR */
811 (1000000000ULL * 1000000), 262 if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
812 state->nominal_refresh_rate_in_micro_hz))); 263 /* Exit Below the Range */
264 if (in_out_vrr->btr.btr_active) {
265 in_out_vrr->btr.frame_counter = 0;
266 in_out_vrr->btr.btr_active = false;
813 267
814 vmin = state->freesync_range.vmin; 268 /* Exit Fixed Refresh mode */
269 } else if (in_out_vrr->fixed.fixed_active) {
815 270
816 inserted_frame_v_total = vmin; 271 in_out_vrr->fixed.frame_counter++;
817 272
818 if (min_frame_duration_in_ns / 1000) 273 if (in_out_vrr->fixed.frame_counter >
819 inserted_frame_v_total = 274 FIXED_REFRESH_EXIT_FRAME_COUNT) {
820 state->btr.inserted_frame_duration_in_us * 275 in_out_vrr->fixed.frame_counter = 0;
821 vmin / (min_frame_duration_in_ns / 1000); 276 in_out_vrr->fixed.fixed_active = false;
277 }
278 }
279 } else if (last_render_time_in_us > max_render_time_in_us) {
280 /* Enter Below the Range */
281 if (!in_out_vrr->btr.btr_active &&
282 in_out_vrr->btr.btr_enabled) {
283 in_out_vrr->btr.btr_active = true;
822 284
823 /* Set length of inserted frames as v_total_max*/ 285 /* Enter Fixed Refresh mode */
824 vmax = inserted_frame_v_total; 286 } else if (!in_out_vrr->fixed.fixed_active &&
825 vmin = inserted_frame_v_total; 287 !in_out_vrr->btr.btr_enabled) {
288 in_out_vrr->fixed.frame_counter++;
826 289
827 /* Program V_TOTAL */ 290 if (in_out_vrr->fixed.frame_counter >
828 adjust_vmin_vmax(core_freesync, streams, 291 FIXED_REFRESH_ENTER_FRAME_COUNT) {
829 num_streams, index, 292 in_out_vrr->fixed.frame_counter = 0;
830 vmin, vmax); 293 in_out_vrr->fixed.fixed_active = true;
294 }
831 } 295 }
296 }
832 297
833 if (state->btr.frame_counter > 0) 298 /* BTR set to "not active" so disengage */
834 state->btr.frame_counter--; 299 if (!in_out_vrr->btr.btr_active) {
300 in_out_vrr->btr.btr_active = false;
301 in_out_vrr->btr.inserted_duration_in_us = 0;
302 in_out_vrr->btr.frames_to_insert = 0;
303 in_out_vrr->btr.frame_counter = 0;
835 304
836 /* Restore FreeSync */ 305 /* Restore FreeSync */
837 if (state->btr.frame_counter == 0) 306 in_out_vrr->adjust.v_total_min =
838 set_freesync_on_streams(core_freesync, streams, num_streams); 307 calc_v_total_from_refresh(stream,
839 } 308 in_out_vrr->max_refresh_in_uhz);
840 309 in_out_vrr->adjust.v_total_max =
841 /* If in fullscreen freesync mode or in video, do not program 310 calc_v_total_from_refresh(stream,
842 * static screen ramp values 311 in_out_vrr->min_refresh_in_uhz);
843 */ 312 /* BTR set to "active" so engage */
844 if (state->fullscreen == true || state->video == true) { 313 } else {
845 314
846 state->static_ramp.ramp_is_active = false; 315 /* Calculate number of midPoint frames that could fit within
316 * the render time interval- take ceil of this value
317 */
318 mid_point_frames_ceil = (last_render_time_in_us +
319 in_out_vrr->btr.mid_point_in_us - 1) /
320 in_out_vrr->btr.mid_point_in_us;
847 321
848 return; 322 if (mid_point_frames_ceil > 0) {
849 } 323 frame_time_in_us = last_render_time_in_us /
324 mid_point_frames_ceil;
325 delta_from_mid_point_in_us_1 =
326 (in_out_vrr->btr.mid_point_in_us >
327 frame_time_in_us) ?
328 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
329 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
330 }
850 331
851 /* Gradual Static Screen Ramping Logic */ 332 /* Calculate number of midPoint frames that could fit within
333 * the render time interval- take floor of this value
334 */
335 mid_point_frames_floor = last_render_time_in_us /
336 in_out_vrr->btr.mid_point_in_us;
852 337
853 /* Execute if ramp is active and user enabled freesync static screen*/ 338 if (mid_point_frames_floor > 0) {
854 if (state->static_ramp.ramp_is_active &&
855 core_freesync->map[index].user_enable.enable_for_static) {
856 339
857 calc_v_total_for_static_ramp(core_freesync, streams[0], 340 frame_time_in_us = last_render_time_in_us /
858 index, &v_total); 341 mid_point_frames_floor;
342 delta_from_mid_point_in_us_2 =
343 (in_out_vrr->btr.mid_point_in_us >
344 frame_time_in_us) ?
345 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
346 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
347 }
859 348
860 /* Update the freesync context for the stream */ 349 /* Choose number of frames to insert based on how close it
861 update_stream_freesync_context(core_freesync, streams[0]); 350 * can get to the mid point of the variable range.
351 */
352 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2)
353 frames_to_insert = mid_point_frames_ceil;
354 else
355 frames_to_insert = mid_point_frames_floor;
862 356
863 /* Program static screen ramp values */ 357 /* Either we've calculated the number of frames to insert,
864 adjust_vmin_vmax(core_freesync, streams, 358 * or we need to insert min duration frames
865 num_streams, index, 359 */
866 v_total, 360 if (frames_to_insert > 0)
867 v_total); 361 inserted_frame_duration_in_us = last_render_time_in_us /
362 frames_to_insert;
868 363
869 triggers.overlay_update = true; 364 if (inserted_frame_duration_in_us <
870 triggers.surface_update = true; 365 (1000000 / in_out_vrr->max_refresh_in_uhz))
366 inserted_frame_duration_in_us =
367 (1000000 / in_out_vrr->max_refresh_in_uhz);
871 368
872 dc_stream_set_static_screen_events(core_freesync->dc, streams, 369 /* Cache the calculated variables */
873 num_streams, &triggers); 370 in_out_vrr->btr.inserted_duration_in_us =
371 inserted_frame_duration_in_us;
372 in_out_vrr->btr.frames_to_insert = frames_to_insert;
373 in_out_vrr->btr.frame_counter = frames_to_insert;
374
375 in_out_vrr->adjust.v_total_min =
376 calc_v_total_from_duration(stream, in_out_vrr,
377 in_out_vrr->btr.inserted_duration_in_us);
378 in_out_vrr->adjust.v_total_max =
379 in_out_vrr->adjust.v_total_min;
874 } 380 }
875} 381}
876 382
877void mod_freesync_update_state(struct mod_freesync *mod_freesync, 383static void apply_fixed_refresh(struct core_freesync *core_freesync,
878 struct dc_stream_state **streams, int num_streams, 384 const struct dc_stream_state *stream,
879 struct mod_freesync_params *freesync_params) 385 unsigned int last_render_time_in_us,
386 struct mod_vrr_params *in_out_vrr)
880{ 387{
881 bool freesync_program_required = false; 388 bool update = false;
882 unsigned int stream_index; 389 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
883 struct freesync_state *state;
884 struct core_freesync *core_freesync = NULL;
885 struct dc_static_screen_events triggers = {0};
886 390
887 if (mod_freesync == NULL) 391 if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
888 return; 392 /* Exit Fixed Refresh mode */
889 393 if (in_out_vrr->fixed.fixed_active) {
890 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 394 in_out_vrr->fixed.frame_counter++;
891
892 if (core_freesync->num_entities == 0)
893 return;
894 395
895 for(stream_index = 0; stream_index < num_streams; stream_index++) { 396 if (in_out_vrr->fixed.frame_counter >
896 397 FIXED_REFRESH_EXIT_FRAME_COUNT) {
897 unsigned int map_index = map_index_from_stream(core_freesync, 398 in_out_vrr->fixed.frame_counter = 0;
898 streams[stream_index]); 399 in_out_vrr->fixed.fixed_active = false;
899 400 in_out_vrr->fixed.target_refresh_in_uhz = 0;
900 bool is_embedded = dc_is_embedded_signal( 401 update = true;
901 streams[stream_index]->sink->sink_signal);
902
903 struct freesync_registry_options *opts = &core_freesync->opts;
904
905 state = &core_freesync->map[map_index].state;
906
907 switch (freesync_params->state){
908 case FREESYNC_STATE_FULLSCREEN:
909 state->fullscreen = freesync_params->enable;
910 freesync_program_required = true;
911 state->windowed_fullscreen =
912 freesync_params->windowed_fullscreen;
913 break;
914 case FREESYNC_STATE_STATIC_SCREEN:
915 /* Static screen ramp is disabled by default, but can
916 * be enabled through regkey.
917 */
918 if ((is_embedded && opts->drr_internal_supported) ||
919 (!is_embedded && opts->drr_external_supported))
920
921 if (state->static_screen !=
922 freesync_params->enable) {
923
924 /* Change the state flag */
925 state->static_screen =
926 freesync_params->enable;
927
928 /* Update static screen ramp */
929 set_static_ramp_variables(core_freesync,
930 map_index,
931 freesync_params->enable);
932 }
933 /* We program the ramp starting next VUpdate */
934 break;
935 case FREESYNC_STATE_VIDEO:
936 /* Change core variables only if there is a change*/
937 if(freesync_params->update_duration_in_ns !=
938 state->time.update_duration_in_ns) {
939
940 state->video = freesync_params->enable;
941 state->time.update_duration_in_ns =
942 freesync_params->update_duration_in_ns;
943
944 freesync_program_required = true;
945 } 402 }
946 break;
947 case FREESYNC_STATE_NONE:
948 /* handle here to avoid warning */
949 break;
950 } 403 }
951 } 404 } else if (last_render_time_in_us > max_render_time_in_us) {
952 405 /* Enter Fixed Refresh mode */
953 /* Update mask */ 406 if (!in_out_vrr->fixed.fixed_active) {
954 triggers.overlay_update = true; 407 in_out_vrr->fixed.frame_counter++;
955 triggers.surface_update = true;
956
957 dc_stream_set_static_screen_events(core_freesync->dc, streams,
958 num_streams, &triggers);
959
960 if (freesync_program_required)
961 /* Program freesync according to current state*/
962 set_freesync_on_streams(core_freesync, streams, num_streams);
963}
964
965
966bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
967 struct dc_stream_state *stream,
968 struct mod_freesync_params *freesync_params)
969{
970 unsigned int index = 0;
971 struct core_freesync *core_freesync = NULL;
972
973 if (mod_freesync == NULL)
974 return false;
975 408
976 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 409 if (in_out_vrr->fixed.frame_counter >
977 index = map_index_from_stream(core_freesync, stream); 410 FIXED_REFRESH_ENTER_FRAME_COUNT) {
978 411 in_out_vrr->fixed.frame_counter = 0;
979 if (core_freesync->map[index].state.fullscreen) { 412 in_out_vrr->fixed.fixed_active = true;
980 freesync_params->state = FREESYNC_STATE_FULLSCREEN; 413 in_out_vrr->fixed.target_refresh_in_uhz =
981 freesync_params->enable = true; 414 in_out_vrr->max_refresh_in_uhz;
982 } else if (core_freesync->map[index].state.static_screen) { 415 update = true;
983 freesync_params->state = FREESYNC_STATE_STATIC_SCREEN; 416 }
984 freesync_params->enable = true; 417 }
985 } else if (core_freesync->map[index].state.video) {
986 freesync_params->state = FREESYNC_STATE_VIDEO;
987 freesync_params->enable = true;
988 } else {
989 freesync_params->state = FREESYNC_STATE_NONE;
990 freesync_params->enable = false;
991 } 418 }
992 419
993 freesync_params->update_duration_in_ns = 420 if (update) {
994 core_freesync->map[index].state.time.update_duration_in_ns; 421 if (in_out_vrr->fixed.fixed_active) {
995 422 in_out_vrr->adjust.v_total_min =
996 freesync_params->windowed_fullscreen = 423 calc_v_total_from_refresh(
997 core_freesync->map[index].state.windowed_fullscreen; 424 stream, in_out_vrr->max_refresh_in_uhz);
998 425 in_out_vrr->adjust.v_total_max =
999 return true; 426 in_out_vrr->adjust.v_total_min;
1000} 427 } else {
1001 428 in_out_vrr->adjust.v_total_min =
1002bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, 429 calc_v_total_from_refresh(
1003 struct dc_stream_state **streams, int num_streams, 430 stream, in_out_vrr->max_refresh_in_uhz);
1004 struct mod_freesync_user_enable *user_enable) 431 in_out_vrr->adjust.v_total_max =
1005{ 432 in_out_vrr->adjust.v_total_min;
1006 unsigned int stream_index, map_index; 433 }
1007 int persistent_data = 0;
1008 struct persistent_data_flag flag;
1009 struct dc *dc = NULL;
1010 struct core_freesync *core_freesync = NULL;
1011
1012 if (mod_freesync == NULL)
1013 return false;
1014
1015 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1016 dc = core_freesync->dc;
1017
1018 flag.save_per_edid = true;
1019 flag.save_per_link = false;
1020
1021 for(stream_index = 0; stream_index < num_streams;
1022 stream_index++){
1023
1024 map_index = map_index_from_stream(core_freesync,
1025 streams[stream_index]);
1026
1027 core_freesync->map[map_index].user_enable = *user_enable;
1028
1029 /* Write persistent data in registry*/
1030 if (core_freesync->map[map_index].user_enable.
1031 enable_for_gaming)
1032 persistent_data = persistent_data | 1;
1033 if (core_freesync->map[map_index].user_enable.
1034 enable_for_static)
1035 persistent_data = persistent_data | 2;
1036 if (core_freesync->map[map_index].user_enable.
1037 enable_for_video)
1038 persistent_data = persistent_data | 4;
1039
1040 dm_write_persistent_data(dc->ctx,
1041 streams[stream_index]->sink,
1042 FREESYNC_REGISTRY_NAME,
1043 "userenable",
1044 &persistent_data,
1045 sizeof(int),
1046 &flag);
1047 } 434 }
1048
1049 set_freesync_on_streams(core_freesync, streams, num_streams);
1050
1051 return true;
1052} 435}
1053 436
1054bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, 437static bool vrr_settings_require_update(struct core_freesync *core_freesync,
1055 struct dc_stream_state *stream, 438 struct mod_freesync_config *in_config,
1056 struct mod_freesync_user_enable *user_enable) 439 unsigned int min_refresh_in_uhz,
1057{ 440 unsigned int max_refresh_in_uhz,
1058 unsigned int index = 0; 441 struct mod_vrr_params *in_vrr)
1059 struct core_freesync *core_freesync = NULL;
1060
1061 if (mod_freesync == NULL)
1062 return false;
1063
1064 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1065 index = map_index_from_stream(core_freesync, stream);
1066
1067 *user_enable = core_freesync->map[index].user_enable;
1068
1069 return true;
1070}
1071
1072bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
1073 struct dc_stream_state *stream,
1074 bool *is_ramp_active)
1075{
1076 unsigned int index = 0;
1077 struct core_freesync *core_freesync = NULL;
1078
1079 if (mod_freesync == NULL)
1080 return false;
1081
1082 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1083 index = map_index_from_stream(core_freesync, stream);
1084
1085 *is_ramp_active =
1086 core_freesync->map[index].state.static_ramp.ramp_is_active;
1087
1088 return true;
1089}
1090
1091bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
1092 struct dc_stream_state *streams,
1093 unsigned int min_refresh,
1094 unsigned int max_refresh,
1095 struct mod_freesync_caps *caps)
1096{ 442{
1097 unsigned int index = 0; 443 if (in_vrr->state != in_config->state) {
1098 struct core_freesync *core_freesync; 444 return true;
1099 struct freesync_state *state; 445 } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1100 446 in_vrr->fixed.target_refresh_in_uhz !=
1101 if (mod_freesync == NULL) 447 in_config->min_refresh_in_uhz) {
1102 return false; 448 return true;
1103 449 } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
1104 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 450 return true;
1105 index = map_index_from_stream(core_freesync, streams); 451 } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
1106 state = &core_freesync->map[index].state; 452 return true;
1107
1108 if (max_refresh == 0)
1109 max_refresh = state->nominal_refresh_rate_in_micro_hz;
1110
1111 if (min_refresh == 0) {
1112 /* Restore defaults */
1113 calc_freesync_range(core_freesync, streams, state,
1114 core_freesync->map[index].caps->
1115 min_refresh_in_micro_hz,
1116 state->nominal_refresh_rate_in_micro_hz);
1117 } else {
1118 calc_freesync_range(core_freesync, streams,
1119 state,
1120 min_refresh,
1121 max_refresh);
1122
1123 /* Program vtotal min/max */
1124 adjust_vmin_vmax(core_freesync, &streams, 1, index,
1125 state->freesync_range.vmin,
1126 state->freesync_range.vmax);
1127 }
1128
1129 if (min_refresh != 0 &&
1130 dc_is_embedded_signal(streams->sink->sink_signal) &&
1131 (max_refresh - min_refresh >= 10000000)) {
1132 caps->supported = true;
1133 caps->min_refresh_in_micro_hz = min_refresh;
1134 caps->max_refresh_in_micro_hz = max_refresh;
1135 } 453 }
1136 454
1137 /* Update the stream */ 455 return false;
1138 update_stream(core_freesync, streams);
1139
1140 return true;
1141}
1142
1143bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
1144 struct dc_stream_state *stream,
1145 unsigned int *min_refresh,
1146 unsigned int *max_refresh)
1147{
1148 unsigned int index = 0;
1149 struct core_freesync *core_freesync = NULL;
1150
1151 if (mod_freesync == NULL)
1152 return false;
1153
1154 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1155 index = map_index_from_stream(core_freesync, stream);
1156
1157 *min_refresh =
1158 core_freesync->map[index].state.freesync_range.min_refresh;
1159 *max_refresh =
1160 core_freesync->map[index].state.freesync_range.max_refresh;
1161
1162 return true;
1163} 456}
1164 457
1165bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, 458bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
1166 struct dc_stream_state *stream, 459 const struct dc_stream_state *stream,
1167 unsigned int *vmin, 460 unsigned int *vmin,
1168 unsigned int *vmax) 461 unsigned int *vmax)
1169{ 462{
1170 unsigned int index = 0; 463 *vmin = stream->adjust.v_total_min;
1171 struct core_freesync *core_freesync = NULL; 464 *vmax = stream->adjust.v_total_max;
1172
1173 if (mod_freesync == NULL)
1174 return false;
1175
1176 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1177 index = map_index_from_stream(core_freesync, stream);
1178
1179 *vmin =
1180 core_freesync->map[index].state.freesync_range.vmin;
1181 *vmax =
1182 core_freesync->map[index].state.freesync_range.vmax;
1183 465
1184 return true; 466 return true;
1185} 467}
@@ -1189,7 +471,6 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
1189 unsigned int *nom_v_pos, 471 unsigned int *nom_v_pos,
1190 unsigned int *v_pos) 472 unsigned int *v_pos)
1191{ 473{
1192 unsigned int index = 0;
1193 struct core_freesync *core_freesync = NULL; 474 struct core_freesync *core_freesync = NULL;
1194 struct crtc_position position; 475 struct crtc_position position;
1195 476
@@ -1197,7 +478,6 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
1197 return false; 478 return false;
1198 479
1199 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 480 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1200 index = map_index_from_stream(core_freesync, stream);
1201 481
1202 if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, 482 if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
1203 &position.vertical_count, 483 &position.vertical_count,
@@ -1212,310 +492,368 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
1212 return false; 492 return false;
1213} 493}
1214 494
1215void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, 495void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
1216 struct dc_stream_state **streams, int num_streams) 496 const struct dc_stream_state *stream,
497 const struct mod_vrr_params *vrr,
498 struct dc_info_packet *infopacket)
1217{ 499{
1218 unsigned int stream_index, map_index; 500 /* SPD info packet for FreeSync */
1219 struct freesync_state *state; 501 unsigned char checksum = 0;
1220 struct core_freesync *core_freesync = NULL; 502 unsigned int idx, payload_size = 0;
1221 struct dc_static_screen_events triggers = {0};
1222 unsigned long long temp = 0;
1223 503
1224 if (mod_freesync == NULL) 504 /* Check if Freesync is supported. Return if false. If true,
505 * set the corresponding bit in the info packet
506 */
507 if (!vrr->supported)
1225 return; 508 return;
1226 509
1227 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 510 if (dc_is_hdmi_signal(stream->signal)) {
1228 511
1229 for (stream_index = 0; stream_index < num_streams; stream_index++) { 512 /* HEADER */
1230 map_index = map_index_from_stream(core_freesync,
1231 streams[stream_index]);
1232
1233 state = &core_freesync->map[map_index].state;
1234
1235 /* Update the field rate for new timing */
1236 temp = streams[stream_index]->timing.pix_clk_khz;
1237 temp *= 1000ULL * 1000ULL * 1000ULL;
1238 temp = div_u64(temp,
1239 streams[stream_index]->timing.h_total);
1240 temp = div_u64(temp,
1241 streams[stream_index]->timing.v_total);
1242 state->nominal_refresh_rate_in_micro_hz =
1243 (unsigned int) temp;
1244
1245 if (core_freesync->map[map_index].caps->supported) {
1246
1247 /* Update the stream */
1248 update_stream(core_freesync, streams[stream_index]);
1249
1250 /* Calculate vmin/vmax and refresh rate for
1251 * current mode
1252 */
1253 calc_freesync_range(core_freesync, *streams, state,
1254 core_freesync->map[map_index].caps->
1255 min_refresh_in_micro_hz,
1256 state->nominal_refresh_rate_in_micro_hz);
1257
1258 /* Update mask */
1259 triggers.overlay_update = true;
1260 triggers.surface_update = true;
1261
1262 dc_stream_set_static_screen_events(core_freesync->dc,
1263 streams, num_streams,
1264 &triggers);
1265 }
1266 }
1267 513
1268 /* Program freesync according to current state*/ 514 /* HB0 = Packet Type = 0x83 (Source Product
1269 set_freesync_on_streams(core_freesync, streams, num_streams); 515 * Descriptor InfoFrame)
1270} 516 */
517 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
1271 518
1272/* Add the timestamps to the cache and determine whether BTR programming 519 /* HB1 = Version = 0x01 */
1273 * is required, depending on the times calculated 520 infopacket->hb1 = 0x01;
1274 */
1275static void update_timestamps(struct core_freesync *core_freesync,
1276 const struct dc_stream_state *stream, unsigned int map_index,
1277 unsigned int last_render_time_in_us)
1278{
1279 struct freesync_state *state = &core_freesync->map[map_index].state;
1280 521
1281 state->time.render_times[state->time.render_times_index] = 522 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
1282 last_render_time_in_us; 523 infopacket->hb2 = 0x08;
1283 state->time.render_times_index++;
1284 524
1285 if (state->time.render_times_index >= RENDER_TIMES_MAX_COUNT) 525 payload_size = 0x08;
1286 state->time.render_times_index = 0;
1287 526
1288 if (last_render_time_in_us + BTR_EXIT_MARGIN < 527 } else if (dc_is_dp_signal(stream->signal)) {
1289 state->time.max_render_time_in_us) {
1290 528
1291 /* Exit Below the Range */ 529 /* HEADER */
1292 if (state->btr.btr_active) {
1293 530
1294 state->btr.program_btr = true; 531 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
1295 state->btr.btr_active = false; 532 * when used to associate audio related info packets
1296 state->btr.frame_counter = 0; 533 */
534 infopacket->hb0 = 0x00;
1297 535
1298 /* Exit Fixed Refresh mode */ 536 /* HB1 = Packet Type = 0x83 (Source Product
1299 } else if (state->fixed_refresh.fixed_active) { 537 * Descriptor InfoFrame)
538 */
539 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
1300 540
1301 state->fixed_refresh.frame_counter++; 541 /* HB2 = [Bits 7:0 = Least significant eight bits -
542 * For INFOFRAME, the value must be 1Bh]
543 */
544 infopacket->hb2 = 0x1B;
1302 545
1303 if (state->fixed_refresh.frame_counter > 546 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
1304 FIXED_REFRESH_EXIT_FRAME_COUNT) { 547 * [Bits 1:0 = Most significant two bits = 0x00]
1305 state->fixed_refresh.frame_counter = 0; 548 */
1306 state->fixed_refresh.program_fixed = true; 549 infopacket->hb3 = 0x04;
1307 state->fixed_refresh.fixed_active = false;
1308 }
1309 }
1310 550
1311 } else if (last_render_time_in_us > state->time.max_render_time_in_us) { 551 payload_size = 0x1B;
552 }
1312 553
1313 /* Enter Below the Range */ 554 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
1314 if (!state->btr.btr_active && 555 infopacket->sb[1] = 0x1A;
1315 core_freesync->map[map_index].caps->btr_supported) {
1316 556
1317 state->btr.program_btr = true; 557 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
1318 state->btr.btr_active = true; 558 infopacket->sb[2] = 0x00;
1319 559
1320 /* Enter Fixed Refresh mode */ 560 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
1321 } else if (!state->fixed_refresh.fixed_active && 561 infopacket->sb[3] = 0x00;
1322 !core_freesync->map[map_index].caps->btr_supported) {
1323 562
1324 state->fixed_refresh.frame_counter++; 563 /* PB4 = Reserved */
1325 564
1326 if (state->fixed_refresh.frame_counter > 565 /* PB5 = Reserved */
1327 FIXED_REFRESH_ENTER_FRAME_COUNT) {
1328 state->fixed_refresh.frame_counter = 0;
1329 state->fixed_refresh.program_fixed = true;
1330 state->fixed_refresh.fixed_active = true;
1331 }
1332 }
1333 }
1334 566
1335 /* When Below the Range is active, must react on every frame */ 567 /* PB6 = [Bits 7:3 = Reserved] */
1336 if (state->btr.btr_active)
1337 state->btr.program_btr = true;
1338}
1339 568
1340static void apply_below_the_range(struct core_freesync *core_freesync, 569 /* PB6 = [Bit 0 = FreeSync Supported] */
1341 struct dc_stream_state *stream, unsigned int map_index, 570 if (vrr->state != VRR_STATE_UNSUPPORTED)
1342 unsigned int last_render_time_in_us) 571 infopacket->sb[6] |= 0x01;
1343{
1344 unsigned int inserted_frame_duration_in_us = 0;
1345 unsigned int mid_point_frames_ceil = 0;
1346 unsigned int mid_point_frames_floor = 0;
1347 unsigned int frame_time_in_us = 0;
1348 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
1349 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
1350 unsigned int frames_to_insert = 0;
1351 unsigned int min_frame_duration_in_ns = 0;
1352 struct freesync_state *state = &core_freesync->map[map_index].state;
1353 572
1354 if (!state->btr.program_btr) 573 /* PB6 = [Bit 1 = FreeSync Enabled] */
1355 return; 574 if (vrr->state != VRR_STATE_DISABLED &&
575 vrr->state != VRR_STATE_UNSUPPORTED)
576 infopacket->sb[6] |= 0x02;
1356 577
1357 state->btr.program_btr = false; 578 /* PB6 = [Bit 2 = FreeSync Active] */
579 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
580 vrr->state == VRR_STATE_ACTIVE_FIXED)
581 infopacket->sb[6] |= 0x04;
1358 582
1359 min_frame_duration_in_ns = ((unsigned int) (div64_u64( 583 /* PB7 = FreeSync Minimum refresh rate (Hz) */
1360 (1000000000ULL * 1000000), 584 infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
1361 state->nominal_refresh_rate_in_micro_hz)));
1362 585
1363 /* Program BTR */ 586 /* PB8 = FreeSync Maximum refresh rate (Hz)
587 * Note: We should never go above the field rate of the mode timing set.
588 */
589 infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
1364 590
1365 /* BTR set to "not active" so disengage */ 591 /* PB9 - PB27 = Reserved */
1366 if (!state->btr.btr_active)
1367 592
1368 /* Restore FreeSync */ 593 /* Calculate checksum */
1369 set_freesync_on_streams(core_freesync, &stream, 1); 594 checksum += infopacket->hb0;
595 checksum += infopacket->hb1;
596 checksum += infopacket->hb2;
597 checksum += infopacket->hb3;
1370 598
1371 /* BTR set to "active" so engage */ 599 for (idx = 1; idx <= payload_size; idx++)
1372 else { 600 checksum += infopacket->sb[idx];
1373 601
1374 /* Calculate number of midPoint frames that could fit within 602 /* PB0 = Checksum (one byte complement) */
1375 * the render time interval- take ceil of this value 603 infopacket->sb[0] = (unsigned char)(0x100 - checksum);
1376 */
1377 mid_point_frames_ceil = (last_render_time_in_us +
1378 state->btr.mid_point_in_us- 1) /
1379 state->btr.mid_point_in_us;
1380 604
1381 if (mid_point_frames_ceil > 0) { 605 infopacket->valid = true;
606}
1382 607
1383 frame_time_in_us = last_render_time_in_us / 608void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
1384 mid_point_frames_ceil; 609 const struct dc_stream_state *stream,
1385 delta_from_mid_point_in_us_1 = 610 struct mod_freesync_config *in_config,
1386 (state->btr.mid_point_in_us > 611 struct mod_vrr_params *in_out_vrr)
1387 frame_time_in_us) ? 612{
1388 (state->btr.mid_point_in_us - frame_time_in_us): 613 struct core_freesync *core_freesync = NULL;
1389 (frame_time_in_us - state->btr.mid_point_in_us); 614 unsigned long long nominal_field_rate_in_uhz = 0;
1390 } 615 bool nominal_field_rate_in_range = true;
616 unsigned int refresh_range = 0;
617 unsigned int min_refresh_in_uhz = 0;
618 unsigned int max_refresh_in_uhz = 0;
1391 619
1392 /* Calculate number of midPoint frames that could fit within 620 if (mod_freesync == NULL)
1393 * the render time interval- take floor of this value 621 return;
1394 */
1395 mid_point_frames_floor = last_render_time_in_us /
1396 state->btr.mid_point_in_us;
1397 622
1398 if (mid_point_frames_floor > 0) { 623 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1399 624
1400 frame_time_in_us = last_render_time_in_us / 625 /* Calculate nominal field rate for stream */
1401 mid_point_frames_floor; 626 nominal_field_rate_in_uhz = stream->timing.pix_clk_khz;
1402 delta_from_mid_point_in_us_2 = 627 nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
1403 (state->btr.mid_point_in_us > 628 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
1404 frame_time_in_us) ? 629 stream->timing.h_total);
1405 (state->btr.mid_point_in_us - frame_time_in_us): 630 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
1406 (frame_time_in_us - state->btr.mid_point_in_us); 631 stream->timing.v_total);
1407 } 632
633 min_refresh_in_uhz = in_config->min_refresh_in_uhz;
634 max_refresh_in_uhz = in_config->max_refresh_in_uhz;
635
636 // Don't allow min > max
637 if (min_refresh_in_uhz > max_refresh_in_uhz)
638 min_refresh_in_uhz = max_refresh_in_uhz;
639
640 // Full range may be larger than current video timing, so cap at nominal
641 if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
642 max_refresh_in_uhz = nominal_field_rate_in_uhz;
643
644 /* Allow for some rounding error of actual video timing by taking ceil.
645 * For example, 144 Hz mode timing may actually be 143.xxx Hz when
646 * calculated from pixel rate and vertical/horizontal totals, but
647 * this should be allowed instead of blocking FreeSync.
648 */
649 if ((min_refresh_in_uhz / 1000000) >
650 ((nominal_field_rate_in_uhz + 1000000 - 1) / 1000000))
651 nominal_field_rate_in_range = false;
1408 652
1409 /* Choose number of frames to insert based on how close it 653 // Full range may be larger than current video timing, so cap at nominal
1410 * can get to the mid point of the variable range. 654 if (min_refresh_in_uhz > nominal_field_rate_in_uhz)
1411 */ 655 min_refresh_in_uhz = nominal_field_rate_in_uhz;
1412 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2)
1413 frames_to_insert = mid_point_frames_ceil;
1414 else
1415 frames_to_insert = mid_point_frames_floor;
1416 656
1417 /* Either we've calculated the number of frames to insert, 657 if (!vrr_settings_require_update(core_freesync,
1418 * or we need to insert min duration frames 658 in_config, min_refresh_in_uhz, max_refresh_in_uhz,
1419 */ 659 in_out_vrr))
1420 if (frames_to_insert > 0) 660 return;
1421 inserted_frame_duration_in_us = last_render_time_in_us /
1422 frames_to_insert;
1423 661
1424 if (inserted_frame_duration_in_us < 662 in_out_vrr->state = in_config->state;
1425 state->time.min_render_time_in_us)
1426 663
1427 inserted_frame_duration_in_us = 664 if ((in_config->state == VRR_STATE_UNSUPPORTED) ||
1428 state->time.min_render_time_in_us; 665 (!nominal_field_rate_in_range)) {
666 in_out_vrr->state = VRR_STATE_UNSUPPORTED;
667 in_out_vrr->supported = false;
668 } else {
669 in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
670 in_out_vrr->max_duration_in_us =
671 calc_duration_in_us_from_refresh_in_uhz(
672 min_refresh_in_uhz);
1429 673
1430 /* Cache the calculated variables */ 674 in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
1431 state->btr.inserted_frame_duration_in_us = 675 in_out_vrr->min_duration_in_us =
1432 inserted_frame_duration_in_us; 676 calc_duration_in_us_from_refresh_in_uhz(
1433 state->btr.frames_to_insert = frames_to_insert; 677 max_refresh_in_uhz);
1434 state->btr.frame_counter = frames_to_insert;
1435 678
679 refresh_range = in_out_vrr->max_refresh_in_uhz -
680 in_out_vrr->min_refresh_in_uhz;
681
682 in_out_vrr->supported = true;
683 }
684
685 in_out_vrr->fixed.ramping_active = in_config->ramping;
686
687 in_out_vrr->btr.btr_enabled = in_config->btr;
688 if (in_out_vrr->max_refresh_in_uhz <
689 2 * in_out_vrr->min_refresh_in_uhz)
690 in_out_vrr->btr.btr_enabled = false;
691 in_out_vrr->btr.btr_active = false;
692 in_out_vrr->btr.inserted_duration_in_us = 0;
693 in_out_vrr->btr.frames_to_insert = 0;
694 in_out_vrr->btr.frame_counter = 0;
695 in_out_vrr->btr.mid_point_in_us =
696 in_out_vrr->min_duration_in_us +
697 (in_out_vrr->max_duration_in_us -
698 in_out_vrr->min_duration_in_us) / 2;
699
700 if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
701 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
702 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
703 } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
704 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
705 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
706 } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
707 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
708 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
709 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
710 refresh_range >= MIN_REFRESH_RANGE_IN_US) {
711 in_out_vrr->adjust.v_total_min =
712 calc_v_total_from_refresh(stream,
713 in_out_vrr->max_refresh_in_uhz);
714 in_out_vrr->adjust.v_total_max =
715 calc_v_total_from_refresh(stream,
716 in_out_vrr->min_refresh_in_uhz);
717 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
718 in_out_vrr->fixed.target_refresh_in_uhz =
719 in_out_vrr->min_refresh_in_uhz;
720 if (in_out_vrr->fixed.ramping_active) {
721 in_out_vrr->fixed.fixed_active = true;
722 } else {
723 in_out_vrr->fixed.fixed_active = true;
724 in_out_vrr->adjust.v_total_min =
725 calc_v_total_from_refresh(stream,
726 in_out_vrr->fixed.target_refresh_in_uhz);
727 in_out_vrr->adjust.v_total_max =
728 in_out_vrr->adjust.v_total_min;
729 }
730 } else {
731 in_out_vrr->state = VRR_STATE_INACTIVE;
732 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
733 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1436 } 734 }
1437} 735}
1438 736
1439static void apply_fixed_refresh(struct core_freesync *core_freesync, 737void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1440 struct dc_stream_state *stream, unsigned int map_index) 738 const struct dc_plane_state *plane,
739 const struct dc_stream_state *stream,
740 unsigned int curr_time_stamp_in_us,
741 struct mod_vrr_params *in_out_vrr)
1441{ 742{
1442 unsigned int vmin = 0, vmax = 0; 743 struct core_freesync *core_freesync = NULL;
1443 struct freesync_state *state = &core_freesync->map[map_index].state; 744 unsigned int last_render_time_in_us = 0;
745 unsigned int average_render_time_in_us = 0;
1444 746
1445 if (!state->fixed_refresh.program_fixed) 747 if (mod_freesync == NULL)
1446 return; 748 return;
1447 749
1448 state->fixed_refresh.program_fixed = false; 750 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1449 751
1450 /* Program Fixed Refresh */ 752 if (in_out_vrr->supported &&
753 in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
754 unsigned int i = 0;
755 unsigned int oldest_index = plane->time.index + 1;
1451 756
1452 /* Fixed Refresh set to "not active" so disengage */ 757 if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX)
1453 if (!state->fixed_refresh.fixed_active) { 758 oldest_index = 0;
1454 set_freesync_on_streams(core_freesync, &stream, 1);
1455 759
1456 /* Fixed Refresh set to "active" so engage (fix to max) */ 760 last_render_time_in_us = curr_time_stamp_in_us -
1457 } else { 761 plane->time.prev_update_time_in_us;
762
763 // Sum off all entries except oldest one
764 for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) {
765 average_render_time_in_us +=
766 plane->time.time_elapsed_in_us[i];
767 }
768 average_render_time_in_us -=
769 plane->time.time_elapsed_in_us[oldest_index];
770
771 // Add render time for current flip
772 average_render_time_in_us += last_render_time_in_us;
773 average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX;
774
775 if (in_out_vrr->btr.btr_enabled) {
776 apply_below_the_range(core_freesync,
777 stream,
778 last_render_time_in_us,
779 in_out_vrr);
780 } else {
781 apply_fixed_refresh(core_freesync,
782 stream,
783 last_render_time_in_us,
784 in_out_vrr);
785 }
1458 786
1459 vmin = state->freesync_range.vmin;
1460 vmax = vmin;
1461 adjust_vmin_vmax(core_freesync, &stream, map_index,
1462 1, vmin, vmax);
1463 } 787 }
1464} 788}
1465 789
1466void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, 790void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1467 struct dc_stream_state **streams, int num_streams, 791 const struct dc_stream_state *stream,
1468 unsigned int curr_time_stamp_in_us) 792 struct mod_vrr_params *in_out_vrr)
1469{ 793{
1470 unsigned int stream_index, map_index, last_render_time_in_us = 0;
1471 struct core_freesync *core_freesync = NULL; 794 struct core_freesync *core_freesync = NULL;
1472 795
1473 if (mod_freesync == NULL) 796 if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1474 return; 797 return;
1475 798
1476 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 799 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1477 800
1478 for (stream_index = 0; stream_index < num_streams; stream_index++) { 801 if (in_out_vrr->supported == false)
1479 802 return;
1480 map_index = map_index_from_stream(core_freesync,
1481 streams[stream_index]);
1482
1483 if (core_freesync->map[map_index].caps->supported) {
1484
1485 last_render_time_in_us = curr_time_stamp_in_us -
1486 core_freesync->map[map_index].state.time.
1487 prev_time_stamp_in_us;
1488
1489 /* Add the timestamps to the cache and determine
1490 * whether BTR program is required
1491 */
1492 update_timestamps(core_freesync, streams[stream_index],
1493 map_index, last_render_time_in_us);
1494 803
1495 if (core_freesync->map[map_index].state.fullscreen && 804 /* Below the Range Logic */
1496 core_freesync->map[map_index].user_enable.
1497 enable_for_gaming) {
1498 805
1499 if (core_freesync->map[map_index].caps->btr_supported) { 806 /* Only execute if in fullscreen mode */
807 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
808 in_out_vrr->btr.btr_active) {
809 /* TODO: pass in flag for Pre-DCE12 ASIC
810 * in order for frame variable duration to take affect,
811 * it needs to be done one VSYNC early, which is at
812 * frameCounter == 1.
813 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
814 * will take affect on current frame
815 */
816 if (in_out_vrr->btr.frames_to_insert ==
817 in_out_vrr->btr.frame_counter) {
818 in_out_vrr->adjust.v_total_min =
819 calc_v_total_from_duration(stream,
820 in_out_vrr,
821 in_out_vrr->btr.inserted_duration_in_us);
822 in_out_vrr->adjust.v_total_max =
823 in_out_vrr->adjust.v_total_min;
824 }
1500 825
1501 apply_below_the_range(core_freesync, 826 if (in_out_vrr->btr.frame_counter > 0)
1502 streams[stream_index], map_index, 827 in_out_vrr->btr.frame_counter--;
1503 last_render_time_in_us);
1504 } else {
1505 apply_fixed_refresh(core_freesync,
1506 streams[stream_index], map_index);
1507 }
1508 }
1509 828
1510 core_freesync->map[map_index].state.time. 829 /* Restore FreeSync */
1511 prev_time_stamp_in_us = curr_time_stamp_in_us; 830 if (in_out_vrr->btr.frame_counter == 0) {
831 in_out_vrr->adjust.v_total_min =
832 calc_v_total_from_refresh(stream,
833 in_out_vrr->max_refresh_in_uhz);
834 in_out_vrr->adjust.v_total_max =
835 calc_v_total_from_refresh(stream,
836 in_out_vrr->min_refresh_in_uhz);
1512 } 837 }
838 }
839
840 /* If in fullscreen freesync mode or in video, do not program
841 * static screen ramp values
842 */
843 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
844 in_out_vrr->fixed.ramping_active = false;
1513 845
846 /* Gradual Static Screen Ramping Logic */
847 /* Execute if ramp is active and user enabled freesync static screen*/
848 if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
849 in_out_vrr->fixed.ramping_active) {
850 update_v_total_for_static_ramp(
851 core_freesync, stream, in_out_vrr);
1514 } 852 }
1515} 853}
1516 854
1517void mod_freesync_get_settings(struct mod_freesync *mod_freesync, 855void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
1518 struct dc_stream_state **streams, int num_streams, 856 const struct mod_vrr_params *vrr,
1519 unsigned int *v_total_min, unsigned int *v_total_max, 857 unsigned int *v_total_min, unsigned int *v_total_max,
1520 unsigned int *event_triggers, 858 unsigned int *event_triggers,
1521 unsigned int *window_min, unsigned int *window_max, 859 unsigned int *window_min, unsigned int *window_max,
@@ -1523,7 +861,6 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
1523 unsigned int *inserted_frames, 861 unsigned int *inserted_frames,
1524 unsigned int *inserted_duration_in_us) 862 unsigned int *inserted_duration_in_us)
1525{ 863{
1526 unsigned int stream_index, map_index;
1527 struct core_freesync *core_freesync = NULL; 864 struct core_freesync *core_freesync = NULL;
1528 865
1529 if (mod_freesync == NULL) 866 if (mod_freesync == NULL)
@@ -1531,25 +868,13 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
1531 868
1532 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 869 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1533 870
1534 for (stream_index = 0; stream_index < num_streams; stream_index++) { 871 if (vrr->supported) {
1535 872 *v_total_min = vrr->adjust.v_total_min;
1536 map_index = map_index_from_stream(core_freesync, 873 *v_total_max = vrr->adjust.v_total_max;
1537 streams[stream_index]); 874 *event_triggers = 0;
1538 875 *lfc_mid_point_in_us = vrr->btr.mid_point_in_us;
1539 if (core_freesync->map[map_index].caps->supported) { 876 *inserted_frames = vrr->btr.frames_to_insert;
1540 struct freesync_state state = 877 *inserted_duration_in_us = vrr->btr.inserted_duration_in_us;
1541 core_freesync->map[map_index].state;
1542 *v_total_min = state.vmin;
1543 *v_total_max = state.vmax;
1544 *event_triggers = 0;
1545 *window_min = state.time.min_window;
1546 *window_max = state.time.max_window;
1547 *lfc_mid_point_in_us = state.btr.mid_point_in_us;
1548 *inserted_frames = state.btr.frames_to_insert;
1549 *inserted_duration_in_us =
1550 state.btr.inserted_frame_duration_in_us;
1551 }
1552
1553 } 878 }
1554} 879}
1555 880
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index f083e1619dbe..bd75ca5f1cd3 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -56,96 +56,72 @@
56 56
57#include "dm_services.h" 57#include "dm_services.h"
58 58
59struct mod_freesync *mod_freesync_create(struct dc *dc); 59// Access structures
60void mod_freesync_destroy(struct mod_freesync *mod_freesync);
61
62struct mod_freesync { 60struct mod_freesync {
63 int dummy; 61 int dummy;
64}; 62};
65 63
66enum mod_freesync_state { 64// TODO: References to this should be removed
67 FREESYNC_STATE_NONE,
68 FREESYNC_STATE_FULLSCREEN,
69 FREESYNC_STATE_STATIC_SCREEN,
70 FREESYNC_STATE_VIDEO
71};
72
73enum mod_freesync_user_enable_mask {
74 FREESYNC_USER_ENABLE_STATIC = 0x1,
75 FREESYNC_USER_ENABLE_VIDEO = 0x2,
76 FREESYNC_USER_ENABLE_GAMING = 0x4
77};
78
79struct mod_freesync_user_enable {
80 bool enable_for_static;
81 bool enable_for_video;
82 bool enable_for_gaming;
83};
84
85struct mod_freesync_caps { 65struct mod_freesync_caps {
86 bool supported; 66 bool supported;
87 unsigned int min_refresh_in_micro_hz; 67 unsigned int min_refresh_in_micro_hz;
88 unsigned int max_refresh_in_micro_hz; 68 unsigned int max_refresh_in_micro_hz;
89
90 bool btr_supported;
91}; 69};
92 70
93struct mod_freesync_params { 71enum mod_vrr_state {
94 enum mod_freesync_state state; 72 VRR_STATE_UNSUPPORTED = 0,
95 bool enable; 73 VRR_STATE_DISABLED,
96 unsigned int update_duration_in_ns; 74 VRR_STATE_INACTIVE,
97 bool windowed_fullscreen; 75 VRR_STATE_ACTIVE_VARIABLE,
76 VRR_STATE_ACTIVE_FIXED
98}; 77};
99 78
100/* 79struct mod_freesync_config {
101 * Add stream to be tracked by module 80 enum mod_vrr_state state;
102 */ 81 bool ramping;
103bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, 82 bool btr;
104 struct dc_stream_state *stream, struct mod_freesync_caps *caps); 83 unsigned int min_refresh_in_uhz;
84 unsigned int max_refresh_in_uhz;
85};
105 86
106/* 87struct mod_vrr_params_btr {
107 * Remove stream to be tracked by module 88 bool btr_enabled;
108 */ 89 bool btr_active;
109bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, 90 uint32_t mid_point_in_us;
110 struct dc_stream_state *stream); 91 uint32_t inserted_duration_in_us;
92 uint32_t frames_to_insert;
93 uint32_t frame_counter;
94};
111 95
112/* 96struct mod_vrr_params_fixed_refresh {
113 * Update the freesync state flags for each display and program 97 bool fixed_active;
114 * freesync accordingly 98 bool ramping_active;
115 */ 99 bool ramping_done;
116void mod_freesync_update_state(struct mod_freesync *mod_freesync, 100 uint32_t target_refresh_in_uhz;
117 struct dc_stream_state **streams, int num_streams, 101 uint32_t frame_counter;
118 struct mod_freesync_params *freesync_params); 102};
119 103
120bool mod_freesync_get_state(struct mod_freesync *mod_freesync, 104struct mod_vrr_params {
121 struct dc_stream_state *stream, 105 bool supported;
122 struct mod_freesync_params *freesync_params); 106 enum mod_vrr_state state;
123 107
124bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, 108 uint32_t min_refresh_in_uhz;
125 struct dc_stream_state **streams, int num_streams, 109 uint32_t max_duration_in_us;
126 struct mod_freesync_user_enable *user_enable); 110 uint32_t max_refresh_in_uhz;
111 uint32_t min_duration_in_us;
127 112
128bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, 113 struct dc_crtc_timing_adjust adjust;
129 struct dc_stream_state *stream,
130 struct mod_freesync_user_enable *user_enable);
131 114
132bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, 115 struct mod_vrr_params_fixed_refresh fixed;
133 struct dc_stream_state *stream,
134 bool *is_ramp_active);
135 116
136bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, 117 struct mod_vrr_params_btr btr;
137 struct dc_stream_state *streams, 118};
138 unsigned int min_refresh,
139 unsigned int max_refresh,
140 struct mod_freesync_caps *caps);
141 119
142bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, 120struct mod_freesync *mod_freesync_create(struct dc *dc);
143 struct dc_stream_state *stream, 121void mod_freesync_destroy(struct mod_freesync *mod_freesync);
144 unsigned int *min_refresh,
145 unsigned int *max_refresh);
146 122
147bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, 123bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
148 struct dc_stream_state *stream, 124 const struct dc_stream_state *stream,
149 unsigned int *vmin, 125 unsigned int *vmin,
150 unsigned int *vmax); 126 unsigned int *vmax);
151 127
@@ -154,18 +130,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
154 unsigned int *nom_v_pos, 130 unsigned int *nom_v_pos,
155 unsigned int *v_pos); 131 unsigned int *v_pos);
156 132
157void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
158 struct dc_stream_state **streams, int num_streams);
159
160void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
161 struct dc_stream_state **streams, int num_streams);
162
163void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
164 struct dc_stream_state **streams, int num_streams,
165 unsigned int curr_time_stamp);
166
167void mod_freesync_get_settings(struct mod_freesync *mod_freesync, 133void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
168 struct dc_stream_state **streams, int num_streams, 134 const struct mod_vrr_params *vrr,
169 unsigned int *v_total_min, unsigned int *v_total_max, 135 unsigned int *v_total_min, unsigned int *v_total_max,
170 unsigned int *event_triggers, 136 unsigned int *event_triggers,
171 unsigned int *window_min, unsigned int *window_max, 137 unsigned int *window_min, unsigned int *window_max,
@@ -173,4 +139,24 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
173 unsigned int *inserted_frames, 139 unsigned int *inserted_frames,
174 unsigned int *inserted_duration_in_us); 140 unsigned int *inserted_duration_in_us);
175 141
142void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
143 const struct dc_stream_state *stream,
144 const struct mod_vrr_params *vrr,
145 struct dc_info_packet *infopacket);
146
147void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
148 const struct dc_stream_state *stream,
149 struct mod_freesync_config *in_config,
150 struct mod_vrr_params *in_out_vrr);
151
152void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
153 const struct dc_plane_state *plane,
154 const struct dc_stream_state *stream,
155 unsigned int curr_time_stamp_in_us,
156 struct mod_vrr_params *in_out_vrr);
157
158void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
159 const struct dc_stream_state *stream,
160 struct mod_vrr_params *in_out_vrr);
161
176#endif 162#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 06:01:28 -0400