drm/amdgpu/gfx7: fix pipeline sync

Need to wait on the fence as well.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 13 insertions, 12 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 92d8061efaf4..f4068f753fbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3054,6 +3054,19 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 {
         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
+        uint32_t seq = ring->fence_drv.sync_seq;
+        uint64_t addr = ring->fence_drv.gpu_addr;
+
+        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
+        amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
+                                 WAIT_REG_MEM_FUNCTION(3) | /* equal */
+                                 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
+        amdgpu_ring_write(ring, addr & 0xfffffffc);
+        amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+        amdgpu_ring_write(ring, seq);
+        amdgpu_ring_write(ring, 0xffffffff);
+        amdgpu_ring_write(ring, 4); /* poll interval */
+
         if (usepfp) {
                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
@@ -3081,18 +3094,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                         unsigned vm_id, uint64_t pd_addr)
 {
         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
-        uint32_t seq = ring->fence_drv.sync_seq;
-        uint64_t addr = ring->fence_drv.gpu_addr;
-
-        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
-        amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
-                                 WAIT_REG_MEM_FUNCTION(3) | /* equal */
-                                 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
-        amdgpu_ring_write(ring, addr & 0xfffffffc);
-        amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-        amdgpu_ring_write(ring, seq);
-        amdgpu_ring_write(ring, 0xffffffff);
-        amdgpu_ring_write(ring, 4); /* poll interval */
 
         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |