diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2018-08-17 04:42:35 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 16:11:42 -0400 |
commit | 841cf911fb9e4abd7b8bac2776943c60da9069f4 (patch) | |
tree | 8fdfeb413f86a62988f9b850f0214eaed96c3148 /drivers/gpu/drm/amd | |
parent | a62a49e5b968a58266ee04d63ddaa81a01510b39 (diff) |
drm/amdgpu: Remove duplicate code in gfx_v9_0.c
There are no any logical changes here.
1. if kcq can be enabled via kiq, we don't need to
do kiq ring test.
2. amdgpu_ring_test_ring function can be used to
sync the ring complete, remove the duplicate code.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 |
1 files changed, 12 insertions, 60 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ab5cacea967b..37c95c479002 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |||
@@ -2666,7 +2666,6 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) | |||
2666 | static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) | 2666 | static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) |
2667 | { | 2667 | { |
2668 | struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; | 2668 | struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; |
2669 | uint32_t scratch, tmp = 0; | ||
2670 | uint64_t queue_mask = 0; | 2669 | uint64_t queue_mask = 0; |
2671 | int r, i; | 2670 | int r, i; |
2672 | 2671 | ||
@@ -2685,17 +2684,10 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) | |||
2685 | queue_mask |= (1ull << i); | 2684 | queue_mask |= (1ull << i); |
2686 | } | 2685 | } |
2687 | 2686 | ||
2688 | r = amdgpu_gfx_scratch_get(adev, &scratch); | 2687 | kiq_ring->ready = true; |
2689 | if (r) { | 2688 | r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); |
2690 | DRM_ERROR("Failed to get scratch reg (%d).\n", r); | ||
2691 | return r; | ||
2692 | } | ||
2693 | WREG32(scratch, 0xCAFEDEAD); | ||
2694 | |||
2695 | r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); | ||
2696 | if (r) { | 2689 | if (r) { |
2697 | DRM_ERROR("Failed to lock KIQ (%d).\n", r); | 2690 | DRM_ERROR("Failed to lock KIQ (%d).\n", r); |
2698 | amdgpu_gfx_scratch_free(adev, scratch); | ||
2699 | return r; | 2691 | return r; |
2700 | } | 2692 | } |
2701 | 2693 | ||
@@ -2732,24 +2724,12 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) | |||
2732 | amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); | 2724 | amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); |
2733 | amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); | 2725 | amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); |
2734 | } | 2726 | } |
2735 | /* write to scratch for completion */ | ||
2736 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); | ||
2737 | amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); | ||
2738 | amdgpu_ring_write(kiq_ring, 0xDEADBEEF); | ||
2739 | amdgpu_ring_commit(kiq_ring); | ||
2740 | 2727 | ||
2741 | for (i = 0; i < adev->usec_timeout; i++) { | 2728 | r = amdgpu_ring_test_ring(kiq_ring); |
2742 | tmp = RREG32(scratch); | 2729 | if (r) { |
2743 | if (tmp == 0xDEADBEEF) | 2730 | DRM_ERROR("KCQ enable failed\n"); |
2744 | break; | 2731 | kiq_ring->ready = false; |
2745 | DRM_UDELAY(1); | ||
2746 | } | ||
2747 | if (i >= adev->usec_timeout) { | ||
2748 | DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", | ||
2749 | scratch, tmp); | ||
2750 | r = -EINVAL; | ||
2751 | } | 2732 | } |
2752 | amdgpu_gfx_scratch_free(adev, scratch); | ||
2753 | 2733 | ||
2754 | return r; | 2734 | return r; |
2755 | } | 2735 | } |
@@ -3188,12 +3168,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) | |||
3188 | return r; | 3168 | return r; |
3189 | } | 3169 | } |
3190 | 3170 | ||
3191 | ring = &adev->gfx.kiq.ring; | ||
3192 | ring->ready = true; | ||
3193 | r = amdgpu_ring_test_ring(ring); | ||
3194 | if (r) | ||
3195 | ring->ready = false; | ||
3196 | |||
3197 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | 3171 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
3198 | ring = &adev->gfx.compute_ring[i]; | 3172 | ring = &adev->gfx.compute_ring[i]; |
3199 | 3173 | ||
@@ -3244,21 +3218,11 @@ static int gfx_v9_0_hw_init(void *handle) | |||
3244 | 3218 | ||
3245 | static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) | 3219 | static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) |
3246 | { | 3220 | { |
3247 | struct amdgpu_device *adev = kiq_ring->adev; | 3221 | int r; |
3248 | uint32_t scratch, tmp = 0; | ||
3249 | int r, i; | ||
3250 | |||
3251 | r = amdgpu_gfx_scratch_get(adev, &scratch); | ||
3252 | if (r) { | ||
3253 | DRM_ERROR("Failed to get scratch reg (%d).\n", r); | ||
3254 | return r; | ||
3255 | } | ||
3256 | WREG32(scratch, 0xCAFEDEAD); | ||
3257 | 3222 | ||
3258 | r = amdgpu_ring_alloc(kiq_ring, 10); | 3223 | r = amdgpu_ring_alloc(kiq_ring, 6); |
3259 | if (r) { | 3224 | if (r) { |
3260 | DRM_ERROR("Failed to lock KIQ (%d).\n", r); | 3225 | DRM_ERROR("Failed to lock KIQ (%d).\n", r); |
3261 | amdgpu_gfx_scratch_free(adev, scratch); | ||
3262 | return r; | 3226 | return r; |
3263 | } | 3227 | } |
3264 | 3228 | ||
@@ -3273,23 +3237,11 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring | |||
3273 | amdgpu_ring_write(kiq_ring, 0); | 3237 | amdgpu_ring_write(kiq_ring, 0); |
3274 | amdgpu_ring_write(kiq_ring, 0); | 3238 | amdgpu_ring_write(kiq_ring, 0); |
3275 | amdgpu_ring_write(kiq_ring, 0); | 3239 | amdgpu_ring_write(kiq_ring, 0); |
3276 | /* write to scratch for completion */ | ||
3277 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); | ||
3278 | amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); | ||
3279 | amdgpu_ring_write(kiq_ring, 0xDEADBEEF); | ||
3280 | amdgpu_ring_commit(kiq_ring); | ||
3281 | 3240 | ||
3282 | for (i = 0; i < adev->usec_timeout; i++) { | 3241 | r = amdgpu_ring_test_ring(kiq_ring); |
3283 | tmp = RREG32(scratch); | 3242 | if (r) |
3284 | if (tmp == 0xDEADBEEF) | 3243 | DRM_ERROR("KCQ disable failed\n"); |
3285 | break; | 3244 | |
3286 | DRM_UDELAY(1); | ||
3287 | } | ||
3288 | if (i >= adev->usec_timeout) { | ||
3289 | DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); | ||
3290 | r = -EINVAL; | ||
3291 | } | ||
3292 | amdgpu_gfx_scratch_free(adev, scratch); | ||
3293 | return r; | 3245 | return r; |
3294 | } | 3246 | } |
3295 | 3247 | ||