diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2018-09-13 16:41:57 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-14 10:38:03 -0400 |
commit | 741deade2a704a434bd5939118c43d38e9ddac25 (patch) | |
tree | 403036d4b55161c6d968ff2593e5ddfd47eb81eb /drivers/gpu/drm/amd | |
parent | 23ecdc6187ef74e00b78e889446a309628719b6e (diff) |
drm/amdgpu: simplify Raven, Raven2, and Picasso handling
Treat them all as Raven rather than adding a new picasso
asic type. This simplifies a lot of code and also handles the
case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu
fw handling for picasso.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 66 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 8 |
15 files changed, 60 insertions, 112 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 762dc5f886cd..354f0557d697 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | |||
@@ -91,7 +91,6 @@ static const char *amdgpu_asic_name[] = { | |||
91 | "VEGA12", | 91 | "VEGA12", |
92 | "VEGA20", | 92 | "VEGA20", |
93 | "RAVEN", | 93 | "RAVEN", |
94 | "PICASSO", | ||
95 | "LAST", | 94 | "LAST", |
96 | }; | 95 | }; |
97 | 96 | ||
@@ -1337,12 +1336,11 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) | |||
1337 | case CHIP_RAVEN: | 1336 | case CHIP_RAVEN: |
1338 | if (adev->rev_id >= 8) | 1337 | if (adev->rev_id >= 8) |
1339 | chip_name = "raven2"; | 1338 | chip_name = "raven2"; |
1339 | else if (adev->pdev->device == 0x15d8) | ||
1340 | chip_name = "picasso"; | ||
1340 | else | 1341 | else |
1341 | chip_name = "raven"; | 1342 | chip_name = "raven"; |
1342 | break; | 1343 | break; |
1343 | case CHIP_PICASSO: | ||
1344 | chip_name = "picasso"; | ||
1345 | break; | ||
1346 | } | 1344 | } |
1347 | 1345 | ||
1348 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | 1346 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); |
@@ -1468,8 +1466,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) | |||
1468 | case CHIP_VEGA12: | 1466 | case CHIP_VEGA12: |
1469 | case CHIP_VEGA20: | 1467 | case CHIP_VEGA20: |
1470 | case CHIP_RAVEN: | 1468 | case CHIP_RAVEN: |
1471 | case CHIP_PICASSO: | 1469 | if (adev->asic_type == CHIP_RAVEN) |
1472 | if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) | ||
1473 | adev->family = AMDGPU_FAMILY_RV; | 1470 | adev->family = AMDGPU_FAMILY_RV; |
1474 | else | 1471 | else |
1475 | adev->family = AMDGPU_FAMILY_AI; | 1472 | adev->family = AMDGPU_FAMILY_AI; |
@@ -2183,7 +2180,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) | |||
2183 | case CHIP_VEGA20: | 2180 | case CHIP_VEGA20: |
2184 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 2181 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
2185 | case CHIP_RAVEN: | 2182 | case CHIP_RAVEN: |
2186 | case CHIP_PICASSO: | ||
2187 | #endif | 2183 | #endif |
2188 | return amdgpu_dc != 0; | 2184 | return amdgpu_dc != 0; |
2189 | #endif | 2185 | #endif |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 33e1856fb8cc..ff10df4f50d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | |||
@@ -874,8 +874,7 @@ static const struct pci_device_id pciidlist[] = { | |||
874 | {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | 874 | {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
875 | /* Raven */ | 875 | /* Raven */ |
876 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, | 876 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
877 | /* Picasso */ | 877 | {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
878 | {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PICASSO|AMD_IS_APU}, | ||
879 | 878 | ||
880 | {0, 0, 0} | 879 | {0, 0, 0} |
881 | }; | 880 | }; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 611c06d3600a..bd397d2916fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | |||
@@ -56,7 +56,6 @@ static int psp_sw_init(void *handle) | |||
56 | psp_v3_1_set_psp_funcs(psp); | 56 | psp_v3_1_set_psp_funcs(psp); |
57 | break; | 57 | break; |
58 | case CHIP_RAVEN: | 58 | case CHIP_RAVEN: |
59 | case CHIP_PICASSO: | ||
60 | psp_v10_0_set_psp_funcs(psp); | 59 | psp_v10_0_set_psp_funcs(psp); |
61 | break; | 60 | break; |
62 | case CHIP_VEGA20: | 61 | case CHIP_VEGA20: |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index acb4c66fe89b..1fa8bc337859 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |||
@@ -303,7 +303,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) | |||
303 | return AMDGPU_FW_LOAD_SMU; | 303 | return AMDGPU_FW_LOAD_SMU; |
304 | case CHIP_VEGA10: | 304 | case CHIP_VEGA10: |
305 | case CHIP_RAVEN: | 305 | case CHIP_RAVEN: |
306 | case CHIP_PICASSO: | ||
307 | case CHIP_VEGA12: | 306 | case CHIP_VEGA12: |
308 | case CHIP_VEGA20: | 307 | case CHIP_VEGA20: |
309 | if (!load_type) | 308 | if (!load_type) |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index a74498ce87ff..a73674f9a0f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | |||
@@ -63,14 +63,13 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) | |||
63 | 63 | ||
64 | switch (adev->asic_type) { | 64 | switch (adev->asic_type) { |
65 | case CHIP_RAVEN: | 65 | case CHIP_RAVEN: |
66 | if (adev->rev_id >= 8) | 66 | if (adev->rev_id >= 8) |
67 | fw_name = FIRMWARE_RAVEN2; | 67 | fw_name = FIRMWARE_RAVEN2; |
68 | else if (adev->pdev->device == 0x15d8) | ||
69 | fw_name = FIRMWARE_PICASSO; | ||
68 | else | 70 | else |
69 | fw_name = FIRMWARE_RAVEN; | 71 | fw_name = FIRMWARE_RAVEN; |
70 | break; | 72 | break; |
71 | case CHIP_PICASSO: | ||
72 | fw_name = FIRMWARE_PICASSO; | ||
73 | break; | ||
74 | default: | 73 | default: |
75 | return -EINVAL; | 74 | return -EINVAL; |
76 | } | 75 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 7a9ffe9eb8bb..a7f9aaa47c49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |||
@@ -2981,7 +2981,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |||
2981 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | 2981 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2982 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | 2982 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); |
2983 | 2983 | ||
2984 | if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) | 2984 | if (adev->asic_type == CHIP_RAVEN) |
2985 | vm->pte_support_ats = true; | 2985 | vm->pte_support_ats = true; |
2986 | } else { | 2986 | } else { |
2987 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | 2987 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
@@ -3073,7 +3073,7 @@ error_free_sched_entity: | |||
3073 | */ | 3073 | */ |
3074 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) | 3074 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) |
3075 | { | 3075 | { |
3076 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO); | 3076 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
3077 | int r; | 3077 | int r; |
3078 | 3078 | ||
3079 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | 3079 | r = amdgpu_bo_reserve(vm->root.base.bo, true); |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 4991ae00a4ca..75a91663019f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |||
@@ -277,7 +277,6 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = | |||
277 | #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 | 277 | #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 |
278 | #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 | 278 | #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 |
279 | #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 | 279 | #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 |
280 | #define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042 | ||
281 | #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 | 280 | #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 |
282 | 281 | ||
283 | static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); | 282 | static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); |
@@ -329,14 +328,6 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) | |||
329 | golden_settings_gc_9_1_rv1, | 328 | golden_settings_gc_9_1_rv1, |
330 | ARRAY_SIZE(golden_settings_gc_9_1_rv1)); | 329 | ARRAY_SIZE(golden_settings_gc_9_1_rv1)); |
331 | break; | 330 | break; |
332 | case CHIP_PICASSO: | ||
333 | soc15_program_register_sequence(adev, | ||
334 | golden_settings_gc_9_1, | ||
335 | ARRAY_SIZE(golden_settings_gc_9_1)); | ||
336 | soc15_program_register_sequence(adev, | ||
337 | golden_settings_gc_9_1_rv1, | ||
338 | ARRAY_SIZE(golden_settings_gc_9_1_rv1)); | ||
339 | break; | ||
340 | default: | 331 | default: |
341 | break; | 332 | break; |
342 | } | 333 | } |
@@ -617,12 +608,11 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) | |||
617 | case CHIP_RAVEN: | 608 | case CHIP_RAVEN: |
618 | if (adev->rev_id >= 8) | 609 | if (adev->rev_id >= 8) |
619 | chip_name = "raven2"; | 610 | chip_name = "raven2"; |
611 | else if (adev->pdev->device == 0x15d8) | ||
612 | chip_name = "picasso"; | ||
620 | else | 613 | else |
621 | chip_name = "raven"; | 614 | chip_name = "raven"; |
622 | break; | 615 | break; |
623 | case CHIP_PICASSO: | ||
624 | chip_name = "picasso"; | ||
625 | break; | ||
626 | default: | 616 | default: |
627 | BUG(); | 617 | BUG(); |
628 | } | 618 | } |
@@ -1076,7 +1066,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) | |||
1076 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | 1066 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); |
1077 | } | 1067 | } |
1078 | 1068 | ||
1079 | if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { | 1069 | if (adev->asic_type == CHIP_RAVEN) { |
1080 | /* TODO: double check the cp_table_size for RV */ | 1070 | /* TODO: double check the cp_table_size for RV */ |
1081 | adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ | 1071 | adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ |
1082 | r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, | 1072 | r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, |
@@ -1328,14 +1318,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) | |||
1328 | else | 1318 | else |
1329 | gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; | 1319 | gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; |
1330 | break; | 1320 | break; |
1331 | case CHIP_PICASSO: | ||
1332 | adev->gfx.config.max_hw_contexts = 8; | ||
1333 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | ||
1334 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | ||
1335 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | ||
1336 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | ||
1337 | gb_addr_config = PICASSO_GB_ADDR_CONFIG_GOLDEN; | ||
1338 | break; | ||
1339 | default: | 1321 | default: |
1340 | BUG(); | 1322 | BUG(); |
1341 | break; | 1323 | break; |
@@ -1614,7 +1596,6 @@ static int gfx_v9_0_sw_init(void *handle) | |||
1614 | case CHIP_VEGA12: | 1596 | case CHIP_VEGA12: |
1615 | case CHIP_VEGA20: | 1597 | case CHIP_VEGA20: |
1616 | case CHIP_RAVEN: | 1598 | case CHIP_RAVEN: |
1617 | case CHIP_PICASSO: | ||
1618 | adev->gfx.mec.num_mec = 2; | 1599 | adev->gfx.mec.num_mec = 2; |
1619 | break; | 1600 | break; |
1620 | default: | 1601 | default: |
@@ -1776,7 +1757,7 @@ static int gfx_v9_0_sw_fini(void *handle) | |||
1776 | amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, | 1757 | amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, |
1777 | &adev->gfx.rlc.clear_state_gpu_addr, | 1758 | &adev->gfx.rlc.clear_state_gpu_addr, |
1778 | (void **)&adev->gfx.rlc.cs_ptr); | 1759 | (void **)&adev->gfx.rlc.cs_ptr); |
1779 | if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) { | 1760 | if (adev->asic_type == CHIP_RAVEN) { |
1780 | amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, | 1761 | amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, |
1781 | &adev->gfx.rlc.cp_table_gpu_addr, | 1762 | &adev->gfx.rlc.cp_table_gpu_addr, |
1782 | (void **)&adev->gfx.rlc.cp_table_ptr); | 1763 | (void **)&adev->gfx.rlc.cp_table_ptr); |
@@ -2442,7 +2423,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) | |||
2442 | return r; | 2423 | return r; |
2443 | } | 2424 | } |
2444 | 2425 | ||
2445 | if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { | 2426 | if (adev->asic_type == CHIP_RAVEN) { |
2446 | if (amdgpu_lbpw != 0) | 2427 | if (amdgpu_lbpw != 0) |
2447 | gfx_v9_0_enable_lbpw(adev, true); | 2428 | gfx_v9_0_enable_lbpw(adev, true); |
2448 | else | 2429 | else |
@@ -3846,7 +3827,6 @@ static int gfx_v9_0_set_powergating_state(void *handle, | |||
3846 | 3827 | ||
3847 | switch (adev->asic_type) { | 3828 | switch (adev->asic_type) { |
3848 | case CHIP_RAVEN: | 3829 | case CHIP_RAVEN: |
3849 | case CHIP_PICASSO: | ||
3850 | if (!enable) { | 3830 | if (!enable) { |
3851 | amdgpu_gfx_off_ctrl(adev, false); | 3831 | amdgpu_gfx_off_ctrl(adev, false); |
3852 | cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); | 3832 | cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); |
@@ -3901,7 +3881,6 @@ static int gfx_v9_0_set_clockgating_state(void *handle, | |||
3901 | case CHIP_VEGA12: | 3881 | case CHIP_VEGA12: |
3902 | case CHIP_VEGA20: | 3882 | case CHIP_VEGA20: |
3903 | case CHIP_RAVEN: | 3883 | case CHIP_RAVEN: |
3904 | case CHIP_PICASSO: | ||
3905 | gfx_v9_0_update_gfx_clock_gating(adev, | 3884 | gfx_v9_0_update_gfx_clock_gating(adev, |
3906 | state == AMD_CG_STATE_GATE ? true : false); | 3885 | state == AMD_CG_STATE_GATE ? true : false); |
3907 | break; | 3886 | break; |
@@ -4911,7 +4890,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) | |||
4911 | case CHIP_VEGA12: | 4890 | case CHIP_VEGA12: |
4912 | case CHIP_VEGA20: | 4891 | case CHIP_VEGA20: |
4913 | case CHIP_RAVEN: | 4892 | case CHIP_RAVEN: |
4914 | case CHIP_PICASSO: | ||
4915 | adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; | 4893 | adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; |
4916 | break; | 4894 | break; |
4917 | default: | 4895 | default: |
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0ad1586c293f..aad3c7c5fb3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | |||
@@ -846,7 +846,6 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) | |||
846 | adev->gmc.gart_size = 512ULL << 20; | 846 | adev->gmc.gart_size = 512ULL << 20; |
847 | break; | 847 | break; |
848 | case CHIP_RAVEN: /* DCE SG support */ | 848 | case CHIP_RAVEN: /* DCE SG support */ |
849 | case CHIP_PICASSO: /* DCE SG support */ | ||
850 | adev->gmc.gart_size = 1024ULL << 20; | 849 | adev->gmc.gart_size = 1024ULL << 20; |
851 | break; | 850 | break; |
852 | } | 851 | } |
@@ -935,7 +934,6 @@ static int gmc_v9_0_sw_init(void *handle) | |||
935 | adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); | 934 | adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); |
936 | switch (adev->asic_type) { | 935 | switch (adev->asic_type) { |
937 | case CHIP_RAVEN: | 936 | case CHIP_RAVEN: |
938 | case CHIP_PICASSO: | ||
939 | if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { | 937 | if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { |
940 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); | 938 | amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); |
941 | } else { | 939 | } else { |
@@ -1062,7 +1060,6 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) | |||
1062 | case CHIP_VEGA12: | 1060 | case CHIP_VEGA12: |
1063 | break; | 1061 | break; |
1064 | case CHIP_RAVEN: | 1062 | case CHIP_RAVEN: |
1065 | case CHIP_PICASSO: | ||
1066 | soc15_program_register_sequence(adev, | 1063 | soc15_program_register_sequence(adev, |
1067 | golden_settings_athub_1_0_0, | 1064 | golden_settings_athub_1_0_0, |
1068 | ARRAY_SIZE(golden_settings_athub_1_0_0)); | 1065 | ARRAY_SIZE(golden_settings_athub_1_0_0)); |
@@ -1097,7 +1094,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) | |||
1097 | 1094 | ||
1098 | switch (adev->asic_type) { | 1095 | switch (adev->asic_type) { |
1099 | case CHIP_RAVEN: | 1096 | case CHIP_RAVEN: |
1100 | case CHIP_PICASSO: | ||
1101 | mmhub_v1_0_update_power_gating(adev, true); | 1097 | mmhub_v1_0_update_power_gating(adev, true); |
1102 | break; | 1098 | break; |
1103 | default: | 1099 | default: |
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 2a126c6950c7..80698b5ffa4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | |||
@@ -412,7 +412,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad | |||
412 | 412 | ||
413 | def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); | 413 | def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); |
414 | 414 | ||
415 | if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) { | 415 | if (adev->asic_type != CHIP_RAVEN) { |
416 | def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); | 416 | def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); |
417 | def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); | 417 | def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); |
418 | } else | 418 | } else |
@@ -428,7 +428,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad | |||
428 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | 428 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
429 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | 429 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
430 | 430 | ||
431 | if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) | 431 | if (adev->asic_type != CHIP_RAVEN) |
432 | data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | 432 | data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
433 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | 433 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
434 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | 434 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
@@ -445,7 +445,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad | |||
445 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | 445 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
446 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | 446 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
447 | 447 | ||
448 | if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) | 448 | if (adev->asic_type != CHIP_RAVEN) |
449 | data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | 449 | data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
450 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | 450 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
451 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | 451 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
@@ -458,13 +458,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad | |||
458 | WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); | 458 | WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); |
459 | 459 | ||
460 | if (def1 != data1) { | 460 | if (def1 != data1) { |
461 | if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) | 461 | if (adev->asic_type != CHIP_RAVEN) |
462 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); | 462 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); |
463 | else | 463 | else |
464 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); | 464 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); |
465 | } | 465 | } |
466 | 466 | ||
467 | if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO && def2 != data2) | 467 | if (adev->asic_type != CHIP_RAVEN && def2 != data2) |
468 | WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); | 468 | WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); |
469 | } | 469 | } |
470 | 470 | ||
@@ -528,7 +528,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, | |||
528 | case CHIP_VEGA12: | 528 | case CHIP_VEGA12: |
529 | case CHIP_VEGA20: | 529 | case CHIP_VEGA20: |
530 | case CHIP_RAVEN: | 530 | case CHIP_RAVEN: |
531 | case CHIP_PICASSO: | ||
532 | mmhub_v1_0_update_medium_grain_clock_gating(adev, | 531 | mmhub_v1_0_update_medium_grain_clock_gating(adev, |
533 | state == AMD_CG_STATE_GATE ? true : false); | 532 | state == AMD_CG_STATE_GATE ? true : false); |
534 | athub_update_medium_grain_clock_gating(adev, | 533 | athub_update_medium_grain_clock_gating(adev, |
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 2cfd1bb559dd..295c2205485a 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | |||
@@ -121,12 +121,11 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) | |||
121 | case CHIP_RAVEN: | 121 | case CHIP_RAVEN: |
122 | if (adev->rev_id >= 0x8) | 122 | if (adev->rev_id >= 0x8) |
123 | chip_name = "raven2"; | 123 | chip_name = "raven2"; |
124 | else if (adev->pdev->device == 0x15d8) | ||
125 | chip_name = "picasso"; | ||
124 | else | 126 | else |
125 | chip_name = "raven"; | 127 | chip_name = "raven"; |
126 | break; | 128 | break; |
127 | case CHIP_PICASSO: | ||
128 | chip_name = "picasso"; | ||
129 | break; | ||
130 | default: BUG(); | 129 | default: BUG(); |
131 | } | 130 | } |
132 | 131 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 75be0b9ed2c0..2ea1f0d8f5be 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | |||
@@ -229,7 +229,6 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) | |||
229 | ARRAY_SIZE(golden_settings_sdma1_4_2)); | 229 | ARRAY_SIZE(golden_settings_sdma1_4_2)); |
230 | break; | 230 | break; |
231 | case CHIP_RAVEN: | 231 | case CHIP_RAVEN: |
232 | case CHIP_PICASSO: | ||
233 | soc15_program_register_sequence(adev, | 232 | soc15_program_register_sequence(adev, |
234 | golden_settings_sdma_4_1, | 233 | golden_settings_sdma_4_1, |
235 | ARRAY_SIZE(golden_settings_sdma_4_1)); | 234 | ARRAY_SIZE(golden_settings_sdma_4_1)); |
@@ -283,12 +282,11 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) | |||
283 | case CHIP_RAVEN: | 282 | case CHIP_RAVEN: |
284 | if (adev->rev_id >= 8) | 283 | if (adev->rev_id >= 8) |
285 | chip_name = "raven2"; | 284 | chip_name = "raven2"; |
285 | else if (adev->pdev->device == 0x15d8) | ||
286 | chip_name = "picasso"; | ||
286 | else | 287 | else |
287 | chip_name = "raven"; | 288 | chip_name = "raven"; |
288 | break; | 289 | break; |
289 | case CHIP_PICASSO: | ||
290 | chip_name = "picasso"; | ||
291 | break; | ||
292 | default: | 290 | default: |
293 | BUG(); | 291 | BUG(); |
294 | } | 292 | } |
@@ -869,7 +867,6 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev) | |||
869 | 867 | ||
870 | switch (adev->asic_type) { | 868 | switch (adev->asic_type) { |
871 | case CHIP_RAVEN: | 869 | case CHIP_RAVEN: |
872 | case CHIP_PICASSO: | ||
873 | sdma_v4_1_init_power_gating(adev); | 870 | sdma_v4_1_init_power_gating(adev); |
874 | sdma_v4_1_update_power_gating(adev, true); | 871 | sdma_v4_1_update_power_gating(adev, true); |
875 | break; | 872 | break; |
@@ -1277,7 +1274,7 @@ static int sdma_v4_0_early_init(void *handle) | |||
1277 | { | 1274 | { |
1278 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 1275 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1279 | 1276 | ||
1280 | if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) | 1277 | if (adev->asic_type == CHIP_RAVEN) |
1281 | adev->sdma.num_instances = 1; | 1278 | adev->sdma.num_instances = 1; |
1282 | else | 1279 | else |
1283 | adev->sdma.num_instances = 2; | 1280 | adev->sdma.num_instances = 2; |
@@ -1620,7 +1617,6 @@ static int sdma_v4_0_set_clockgating_state(void *handle, | |||
1620 | case CHIP_VEGA12: | 1617 | case CHIP_VEGA12: |
1621 | case CHIP_VEGA20: | 1618 | case CHIP_VEGA20: |
1622 | case CHIP_RAVEN: | 1619 | case CHIP_RAVEN: |
1623 | case CHIP_PICASSO: | ||
1624 | sdma_v4_0_update_medium_grain_clock_gating(adev, | 1620 | sdma_v4_0_update_medium_grain_clock_gating(adev, |
1625 | state == AMD_CG_STATE_GATE ? true : false); | 1621 | state == AMD_CG_STATE_GATE ? true : false); |
1626 | sdma_v4_0_update_medium_grain_light_sleep(adev, | 1622 | sdma_v4_0_update_medium_grain_light_sleep(adev, |
@@ -1639,7 +1635,6 @@ static int sdma_v4_0_set_powergating_state(void *handle, | |||
1639 | 1635 | ||
1640 | switch (adev->asic_type) { | 1636 | switch (adev->asic_type) { |
1641 | case CHIP_RAVEN: | 1637 | case CHIP_RAVEN: |
1642 | case CHIP_PICASSO: | ||
1643 | sdma_v4_1_update_power_gating(adev, | 1638 | sdma_v4_1_update_power_gating(adev, |
1644 | state == AMD_PG_STATE_GATE ? true : false); | 1639 | state == AMD_PG_STATE_GATE ? true : false); |
1645 | break; | 1640 | break; |
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f930e09071d4..c4daf1f93486 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c | |||
@@ -491,7 +491,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) | |||
491 | case CHIP_VEGA10: | 491 | case CHIP_VEGA10: |
492 | case CHIP_VEGA12: | 492 | case CHIP_VEGA12: |
493 | case CHIP_RAVEN: | 493 | case CHIP_RAVEN: |
494 | case CHIP_PICASSO: | ||
495 | vega10_reg_base_init(adev); | 494 | vega10_reg_base_init(adev); |
496 | break; | 495 | break; |
497 | case CHIP_VEGA20: | 496 | case CHIP_VEGA20: |
@@ -546,7 +545,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) | |||
546 | amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); | 545 | amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); |
547 | break; | 546 | break; |
548 | case CHIP_RAVEN: | 547 | case CHIP_RAVEN: |
549 | case CHIP_PICASSO: | ||
550 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | 548 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
551 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | 549 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); |
552 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | 550 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
@@ -698,6 +696,13 @@ static int soc15_common_early_init(void *handle) | |||
698 | break; | 696 | break; |
699 | case CHIP_RAVEN: | 697 | case CHIP_RAVEN: |
700 | if (adev->rev_id >= 0x8) | 698 | if (adev->rev_id >= 0x8) |
699 | adev->external_rev_id = adev->rev_id + 0x81; | ||
700 | else if (adev->pdev->device == 0x15d8) | ||
701 | adev->external_rev_id = adev->rev_id + 0x41; | ||
702 | else | ||
703 | adev->external_rev_id = 0x1; | ||
704 | |||
705 | if (adev->rev_id >= 0x8) { | ||
701 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | | 706 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
702 | AMD_CG_SUPPORT_GFX_MGLS | | 707 | AMD_CG_SUPPORT_GFX_MGLS | |
703 | AMD_CG_SUPPORT_GFX_CP_LS | | 708 | AMD_CG_SUPPORT_GFX_CP_LS | |
@@ -713,7 +718,27 @@ static int soc15_common_early_init(void *handle) | |||
713 | AMD_CG_SUPPORT_SDMA_MGCG | | 718 | AMD_CG_SUPPORT_SDMA_MGCG | |
714 | AMD_CG_SUPPORT_SDMA_LS | | 719 | AMD_CG_SUPPORT_SDMA_LS | |
715 | AMD_CG_SUPPORT_VCN_MGCG; | 720 | AMD_CG_SUPPORT_VCN_MGCG; |
716 | else | 721 | |
722 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; | ||
723 | } else if (adev->pdev->device == 0x15d8) { | ||
724 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | | ||
725 | AMD_CG_SUPPORT_GFX_CP_LS | | ||
726 | AMD_CG_SUPPORT_GFX_3D_CGCG | | ||
727 | AMD_CG_SUPPORT_GFX_3D_CGLS | | ||
728 | AMD_CG_SUPPORT_GFX_CGCG | | ||
729 | AMD_CG_SUPPORT_GFX_CGLS | | ||
730 | AMD_CG_SUPPORT_BIF_LS | | ||
731 | AMD_CG_SUPPORT_HDP_LS | | ||
732 | AMD_CG_SUPPORT_ROM_MGCG | | ||
733 | AMD_CG_SUPPORT_MC_MGCG | | ||
734 | AMD_CG_SUPPORT_MC_LS | | ||
735 | AMD_CG_SUPPORT_SDMA_MGCG | | ||
736 | AMD_CG_SUPPORT_SDMA_LS; | ||
737 | |||
738 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | | ||
739 | AMD_PG_SUPPORT_MMHUB | | ||
740 | AMD_PG_SUPPORT_VCN; | ||
741 | } else { | ||
717 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | | 742 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
718 | AMD_CG_SUPPORT_GFX_MGLS | | 743 | AMD_CG_SUPPORT_GFX_MGLS | |
719 | AMD_CG_SUPPORT_GFX_RLC_LS | | 744 | AMD_CG_SUPPORT_GFX_RLC_LS | |
@@ -735,43 +760,13 @@ static int soc15_common_early_init(void *handle) | |||
735 | AMD_CG_SUPPORT_SDMA_LS | | 760 | AMD_CG_SUPPORT_SDMA_LS | |
736 | AMD_CG_SUPPORT_VCN_MGCG; | 761 | AMD_CG_SUPPORT_VCN_MGCG; |
737 | 762 | ||
738 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; | 763 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
739 | 764 | } | |
740 | if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) | ||
741 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | | ||
742 | AMD_PG_SUPPORT_CP | | ||
743 | AMD_PG_SUPPORT_RLC_SMU_HS; | ||
744 | |||
745 | if (adev->rev_id >= 0x8) | ||
746 | adev->external_rev_id = adev->rev_id + 0x81; | ||
747 | else | ||
748 | adev->external_rev_id = 0x1; | ||
749 | break; | ||
750 | case CHIP_PICASSO: | ||
751 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | | ||
752 | AMD_CG_SUPPORT_GFX_CP_LS | | ||
753 | AMD_CG_SUPPORT_GFX_3D_CGCG | | ||
754 | AMD_CG_SUPPORT_GFX_3D_CGLS | | ||
755 | AMD_CG_SUPPORT_GFX_CGCG | | ||
756 | AMD_CG_SUPPORT_GFX_CGLS | | ||
757 | AMD_CG_SUPPORT_BIF_LS | | ||
758 | AMD_CG_SUPPORT_HDP_LS | | ||
759 | AMD_CG_SUPPORT_ROM_MGCG | | ||
760 | AMD_CG_SUPPORT_MC_MGCG | | ||
761 | AMD_CG_SUPPORT_MC_LS | | ||
762 | AMD_CG_SUPPORT_SDMA_MGCG | | ||
763 | AMD_CG_SUPPORT_SDMA_LS; | ||
764 | |||
765 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | | ||
766 | AMD_PG_SUPPORT_MMHUB | | ||
767 | AMD_PG_SUPPORT_VCN; | ||
768 | 765 | ||
769 | if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) | 766 | if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) |
770 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | | 767 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | |
771 | AMD_PG_SUPPORT_CP | | 768 | AMD_PG_SUPPORT_CP | |
772 | AMD_PG_SUPPORT_RLC_SMU_HS; | 769 | AMD_PG_SUPPORT_RLC_SMU_HS; |
773 | |||
774 | adev->external_rev_id = adev->rev_id + 0x41; | ||
775 | break; | 770 | break; |
776 | default: | 771 | default: |
777 | /* FIXME: not supported yet */ | 772 | /* FIXME: not supported yet */ |
@@ -973,7 +968,6 @@ static int soc15_common_set_clockgating_state(void *handle, | |||
973 | state == AMD_CG_STATE_GATE ? true : false); | 968 | state == AMD_CG_STATE_GATE ? true : false); |
974 | break; | 969 | break; |
975 | case CHIP_RAVEN: | 970 | case CHIP_RAVEN: |
976 | case CHIP_PICASSO: | ||
977 | adev->nbio_funcs->update_medium_grain_clock_gating(adev, | 971 | adev->nbio_funcs->update_medium_grain_clock_gating(adev, |
978 | state == AMD_CG_STATE_GATE ? true : false); | 972 | state == AMD_CG_STATE_GATE ? true : false); |
979 | adev->nbio_funcs->update_medium_grain_light_sleep(adev, | 973 | adev->nbio_funcs->update_medium_grain_light_sleep(adev, |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 985c6291dbfd..47c3453c688a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |||
@@ -1215,8 +1215,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |||
1215 | if (adev->asic_type == CHIP_VEGA10 || | 1215 | if (adev->asic_type == CHIP_VEGA10 || |
1216 | adev->asic_type == CHIP_VEGA12 || | 1216 | adev->asic_type == CHIP_VEGA12 || |
1217 | adev->asic_type == CHIP_VEGA20 || | 1217 | adev->asic_type == CHIP_VEGA20 || |
1218 | adev->asic_type == CHIP_RAVEN || | 1218 | adev->asic_type == CHIP_RAVEN) |
1219 | adev->asic_type == CHIP_PICASSO) | ||
1220 | client_id = SOC15_IH_CLIENTID_DCE; | 1219 | client_id = SOC15_IH_CLIENTID_DCE; |
1221 | 1220 | ||
1222 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | 1221 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
@@ -1635,7 +1634,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) | |||
1635 | break; | 1634 | break; |
1636 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 1635 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1637 | case CHIP_RAVEN: | 1636 | case CHIP_RAVEN: |
1638 | case CHIP_PICASSO: | ||
1639 | if (dcn10_register_irq_handlers(dm->adev)) { | 1637 | if (dcn10_register_irq_handlers(dm->adev)) { |
1640 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | 1638 | DRM_ERROR("DM: Failed to initialize IRQ\n"); |
1641 | goto fail; | 1639 | goto fail; |
@@ -1862,7 +1860,6 @@ static int dm_early_init(void *handle) | |||
1862 | break; | 1860 | break; |
1863 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 1861 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1864 | case CHIP_RAVEN: | 1862 | case CHIP_RAVEN: |
1865 | case CHIP_PICASSO: | ||
1866 | adev->mode_info.num_crtc = 4; | 1863 | adev->mode_info.num_crtc = 4; |
1867 | adev->mode_info.num_hpd = 4; | 1864 | adev->mode_info.num_hpd = 4; |
1868 | adev->mode_info.num_dig = 4; | 1865 | adev->mode_info.num_dig = 4; |
@@ -2111,8 +2108,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, | |||
2111 | if (adev->asic_type == CHIP_VEGA10 || | 2108 | if (adev->asic_type == CHIP_VEGA10 || |
2112 | adev->asic_type == CHIP_VEGA12 || | 2109 | adev->asic_type == CHIP_VEGA12 || |
2113 | adev->asic_type == CHIP_VEGA20 || | 2110 | adev->asic_type == CHIP_VEGA20 || |
2114 | adev->asic_type == CHIP_RAVEN || | 2111 | adev->asic_type == CHIP_RAVEN) { |
2115 | adev->asic_type == CHIP_PICASSO) { | ||
2116 | /* Fill GFX9 params */ | 2112 | /* Fill GFX9 params */ |
2117 | plane_state->tiling_info.gfx9.num_pipes = | 2113 | plane_state->tiling_info.gfx9.num_pipes = |
2118 | adev->gfx.config.gb_addr_config_fields.num_pipes; | 2114 | adev->gfx.config.gb_addr_config_fields.num_pipes; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index a45578e6504a..7500a3e61dba 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -171,7 +171,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) | |||
171 | case AMDGPU_FAMILY_RV: | 171 | case AMDGPU_FAMILY_RV: |
172 | switch (hwmgr->chip_id) { | 172 | switch (hwmgr->chip_id) { |
173 | case CHIP_RAVEN: | 173 | case CHIP_RAVEN: |
174 | case CHIP_PICASSO: | ||
175 | hwmgr->od_enabled = false; | 174 | hwmgr->od_enabled = false; |
176 | hwmgr->smumgr_funcs = &smu10_smu_funcs; | 175 | hwmgr->smumgr_funcs = &smu10_smu_funcs; |
177 | smu10_init_function_pointers(hwmgr); | 176 | smu10_init_function_pointers(hwmgr); |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index f6fe9ce793ad..77c14671866c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | |||
@@ -832,7 +832,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( | |||
832 | uint16_t size; | 832 | uint16_t size; |
833 | 833 | ||
834 | if (!table_addr) { | 834 | if (!table_addr) { |
835 | if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) { | 835 | if (hwmgr->chip_id == CHIP_RAVEN) { |
836 | table_addr = &soft_dummy_pp_table[0]; | 836 | table_addr = &soft_dummy_pp_table[0]; |
837 | hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; | 837 | hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; |
838 | hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); | 838 | hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); |
@@ -1055,7 +1055,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, | |||
1055 | hwmgr->platform_descriptor.maxOverdriveVDDC = 0; | 1055 | hwmgr->platform_descriptor.maxOverdriveVDDC = 0; |
1056 | hwmgr->platform_descriptor.overdriveVDDCStep = 0; | 1056 | hwmgr->platform_descriptor.overdriveVDDCStep = 0; |
1057 | 1057 | ||
1058 | if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) | 1058 | if (hwmgr->chip_id == CHIP_RAVEN) |
1059 | return 0; | 1059 | return 0; |
1060 | 1060 | ||
1061 | /* We assume here that fw_info is unchanged if this call fails.*/ | 1061 | /* We assume here that fw_info is unchanged if this call fails.*/ |
@@ -1595,7 +1595,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) | |||
1595 | int result; | 1595 | int result; |
1596 | const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; | 1596 | const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; |
1597 | 1597 | ||
1598 | if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) | 1598 | if (hwmgr->chip_id == CHIP_RAVEN) |
1599 | return 0; | 1599 | return 0; |
1600 | 1600 | ||
1601 | hwmgr->need_pp_table_upload = true; | 1601 | hwmgr->need_pp_table_upload = true; |
@@ -1644,7 +1644,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) | |||
1644 | 1644 | ||
1645 | static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) | 1645 | static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) |
1646 | { | 1646 | { |
1647 | if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) | 1647 | if (hwmgr->chip_id == CHIP_RAVEN) |
1648 | return 0; | 1648 | return 0; |
1649 | 1649 | ||
1650 | kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); | 1650 | kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); |