diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2016-09-15 15:28:46 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-09-16 15:52:52 -0400 |
commit | 668f52c3039049cd293851599581c5eca745ec4e (patch) | |
tree | a9e9a112c50c43ead003093f24f774ece955ed78 /drivers/gpu/drm/amd | |
parent | 2255e8c1092fedbd3db9940e37ef44524f86a3d9 (diff) |
drm/amdgpu/gfx6: drop duplicate code
The compute functions just called the gfx functions, drop
the wrapper.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 33 |
1 files changed, 9 insertions, 24 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 9697994d3fff..3cf4e9eeea1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | |||
@@ -1324,8 +1324,8 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) | |||
1324 | amdgpu_ring_write(ring, 0x1); | 1324 | amdgpu_ring_write(ring, 0x1); |
1325 | } | 1325 | } |
1326 | 1326 | ||
1327 | static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, | 1327 | static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, |
1328 | u64 seq, unsigned flags) | 1328 | u64 seq, unsigned flags) |
1329 | { | 1329 | { |
1330 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; | 1330 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
1331 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; | 1331 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; |
@@ -1351,17 +1351,9 @@ static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, | |||
1351 | amdgpu_ring_write(ring, upper_32_bits(seq)); | 1351 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
1352 | } | 1352 | } |
1353 | 1353 | ||
1354 | static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring, | 1354 | static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, |
1355 | u64 addr, u64 seq, | 1355 | struct amdgpu_ib *ib, |
1356 | unsigned flags) | 1356 | unsigned vm_id, bool ctx_switch) |
1357 | { | ||
1358 | gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags); | ||
1359 | } | ||
1360 | |||
1361 | |||
1362 | static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | ||
1363 | struct amdgpu_ib *ib, | ||
1364 | unsigned vm_id, bool ctx_switch) | ||
1365 | { | 1357 | { |
1366 | u32 header, control = 0; | 1358 | u32 header, control = 0; |
1367 | 1359 | ||
@@ -1388,13 +1380,6 @@ static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, | |||
1388 | amdgpu_ring_write(ring, control); | 1380 | amdgpu_ring_write(ring, control); |
1389 | } | 1381 | } |
1390 | 1382 | ||
1391 | static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring, | ||
1392 | struct amdgpu_ib *ib, | ||
1393 | unsigned vm_id, bool ctx_switch) | ||
1394 | { | ||
1395 | gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch); | ||
1396 | } | ||
1397 | |||
1398 | /** | 1383 | /** |
1399 | * gfx_v6_0_ring_test_ib - basic ring IB test | 1384 | * gfx_v6_0_ring_test_ib - basic ring IB test |
1400 | * | 1385 | * |
@@ -3119,8 +3104,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { | |||
3119 | .get_wptr = gfx_v6_0_ring_get_wptr, | 3104 | .get_wptr = gfx_v6_0_ring_get_wptr, |
3120 | .set_wptr = gfx_v6_0_ring_set_wptr_gfx, | 3105 | .set_wptr = gfx_v6_0_ring_set_wptr_gfx, |
3121 | .parse_cs = NULL, | 3106 | .parse_cs = NULL, |
3122 | .emit_ib = gfx_v6_0_ring_emit_ib_gfx, | 3107 | .emit_ib = gfx_v6_0_ring_emit_ib, |
3123 | .emit_fence = gfx_v6_0_ring_emit_fence_gfx, | 3108 | .emit_fence = gfx_v6_0_ring_emit_fence, |
3124 | .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, | 3109 | .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, |
3125 | .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, | 3110 | .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, |
3126 | .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch, | 3111 | .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch, |
@@ -3136,8 +3121,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { | |||
3136 | .get_wptr = gfx_v6_0_ring_get_wptr, | 3121 | .get_wptr = gfx_v6_0_ring_get_wptr, |
3137 | .set_wptr = gfx_v6_0_ring_set_wptr_compute, | 3122 | .set_wptr = gfx_v6_0_ring_set_wptr_compute, |
3138 | .parse_cs = NULL, | 3123 | .parse_cs = NULL, |
3139 | .emit_ib = gfx_v6_0_ring_emit_ib_compute, | 3124 | .emit_ib = gfx_v6_0_ring_emit_ib, |
3140 | .emit_fence = gfx_v6_0_ring_emit_fence_compute, | 3125 | .emit_fence = gfx_v6_0_ring_emit_fence, |
3141 | .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, | 3126 | .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, |
3142 | .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, | 3127 | .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, |
3143 | .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch, | 3128 | .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch, |