diff options
author | Edward O'Callaghan <funfunctor@folklore1984.net> | 2016-07-11 20:17:57 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-07-29 14:36:51 -0400 |
commit | 538f1ef34c71aa5c6a7bd1b65d5e603080ff7b74 (patch) | |
tree | b87cd5bde2d249c47d58120a83dc99b0f17979f6 /drivers/gpu/drm/amd | |
parent | 4ba27f9ba993cdcb3637d9fedc61a121a5eb2387 (diff) |
drivers/amdgpu: Remove redundant itermediate return val
Found-by: Coccinelle
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
5 files changed, 7 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index c0c9cc32409a..120a9e2c3152 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | |||
@@ -1662,7 +1662,6 @@ static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr, | |||
1662 | { | 1662 | { |
1663 | uint32_t count; | 1663 | uint32_t count; |
1664 | uint8_t index; | 1664 | uint8_t index; |
1665 | int result = 0; | ||
1666 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); | 1665 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
1667 | struct phm_ppt_v1_information *table_info = | 1666 | struct phm_ppt_v1_information *table_info = |
1668 | (struct phm_ppt_v1_information *)(hwmgr->pptable); | 1667 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
@@ -1684,7 +1683,7 @@ static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr, | |||
1684 | VOLTAGE_SCALE)) / 25); | 1683 | VOLTAGE_SCALE)) / 25); |
1685 | } | 1684 | } |
1686 | 1685 | ||
1687 | return result; | 1686 | return 0; |
1688 | } | 1687 | } |
1689 | 1688 | ||
1690 | /** | 1689 | /** |
@@ -4573,7 +4572,6 @@ static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr, | |||
4573 | static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr, | 4572 | static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr, |
4574 | const struct fiji_power_state *fiji_ps) | 4573 | const struct fiji_power_state *fiji_ps) |
4575 | { | 4574 | { |
4576 | int result = 0; | ||
4577 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); | 4575 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
4578 | uint32_t high_limit_count; | 4576 | uint32_t high_limit_count; |
4579 | 4577 | ||
@@ -4593,7 +4591,7 @@ static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr, | |||
4593 | fiji_ps->performance_levels[0].memory_clock, | 4591 | fiji_ps->performance_levels[0].memory_clock, |
4594 | fiji_ps->performance_levels[high_limit_count].memory_clock); | 4592 | fiji_ps->performance_levels[high_limit_count].memory_clock); |
4595 | 4593 | ||
4596 | return result; | 4594 | return 0; |
4597 | } | 4595 | } |
4598 | 4596 | ||
4599 | static int fiji_generate_dpm_level_enable_mask( | 4597 | static int fiji_generate_dpm_level_enable_mask( |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index 417e525dc374..82d01d7bce60 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | |||
@@ -4322,7 +4322,6 @@ static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, | |||
4322 | static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, | 4322 | static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, |
4323 | const struct polaris10_power_state *polaris10_ps) | 4323 | const struct polaris10_power_state *polaris10_ps) |
4324 | { | 4324 | { |
4325 | int result = 0; | ||
4326 | struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); | 4325 | struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); |
4327 | uint32_t high_limit_count; | 4326 | uint32_t high_limit_count; |
4328 | 4327 | ||
@@ -4342,7 +4341,7 @@ static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, | |||
4342 | polaris10_ps->performance_levels[0].memory_clock, | 4341 | polaris10_ps->performance_levels[0].memory_clock, |
4343 | polaris10_ps->performance_levels[high_limit_count].memory_clock); | 4342 | polaris10_ps->performance_levels[high_limit_count].memory_clock); |
4344 | 4343 | ||
4345 | return result; | 4344 | return 0; |
4346 | } | 4345 | } |
4347 | 4346 | ||
4348 | static int polaris10_generate_dpm_level_enable_mask( | 4347 | static int polaris10_generate_dpm_level_enable_mask( |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 306483d8036a..c7dc111221c2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | |||
@@ -1334,7 +1334,6 @@ static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, | |||
1334 | { | 1334 | { |
1335 | uint32_t count; | 1335 | uint32_t count; |
1336 | uint8_t index; | 1336 | uint8_t index; |
1337 | int result = 0; | ||
1338 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); | 1337 | tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); |
1339 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); | 1338 | struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); |
1340 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table; | 1339 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table; |
@@ -1381,7 +1380,7 @@ static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, | |||
1381 | } | 1380 | } |
1382 | } | 1381 | } |
1383 | 1382 | ||
1384 | return result; | 1383 | return 0; |
1385 | } | 1384 | } |
1386 | 1385 | ||
1387 | 1386 | ||
@@ -5460,7 +5459,6 @@ static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr, | |||
5460 | 5459 | ||
5461 | static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state) | 5460 | static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state) |
5462 | { | 5461 | { |
5463 | int result = 0; | ||
5464 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); | 5462 | struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); |
5465 | uint32_t high_limit_count; | 5463 | uint32_t high_limit_count; |
5466 | 5464 | ||
@@ -5480,7 +5478,7 @@ static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_powe | |||
5480 | hw_state->performance_levels[0].memory_clock, | 5478 | hw_state->performance_levels[0].memory_clock, |
5481 | hw_state->performance_levels[high_limit_count].memory_clock); | 5479 | hw_state->performance_levels[high_limit_count].memory_clock); |
5482 | 5480 | ||
5483 | return result; | 5481 | return 0; |
5484 | } | 5482 | } |
5485 | 5483 | ||
5486 | static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) | 5484 | static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input) |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index 53f02c7bdec2..cfb647f76cbe 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | |||
@@ -1068,7 +1068,6 @@ int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr) | |||
1068 | 1068 | ||
1069 | int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) | 1069 | int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) |
1070 | { | 1070 | { |
1071 | int result = 0; | ||
1072 | struct phm_ppt_v1_information *pp_table_information = | 1071 | struct phm_ppt_v1_information *pp_table_information = |
1073 | (struct phm_ppt_v1_information *)(hwmgr->pptable); | 1072 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
1074 | 1073 | ||
@@ -1108,7 +1107,7 @@ int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) | |||
1108 | kfree(hwmgr->pptable); | 1107 | kfree(hwmgr->pptable); |
1109 | hwmgr->pptable = NULL; | 1108 | hwmgr->pptable = NULL; |
1110 | 1109 | ||
1111 | return result; | 1110 | return 0; |
1112 | } | 1111 | } |
1113 | 1112 | ||
1114 | const struct pp_table_func tonga_pptable_funcs = { | 1113 | const struct pp_table_func tonga_pptable_funcs = { |
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index b22722eabafc..f42c536b3af1 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | |||
@@ -479,7 +479,6 @@ static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr) | |||
479 | struct tonga_smumgr *tonga_smu = | 479 | struct tonga_smumgr *tonga_smu = |
480 | (struct tonga_smumgr *)(smumgr->backend); | 480 | (struct tonga_smumgr *)(smumgr->backend); |
481 | uint16_t fw_to_load; | 481 | uint16_t fw_to_load; |
482 | int result = 0; | ||
483 | struct SMU_DRAMData_TOC *toc; | 482 | struct SMU_DRAMData_TOC *toc; |
484 | /** | 483 | /** |
485 | * First time this gets called during SmuMgr init, | 484 | * First time this gets called during SmuMgr init, |
@@ -563,7 +562,7 @@ static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr) | |||
563 | smumgr, PPSMC_MSG_LoadUcodes, fw_to_load), | 562 | smumgr, PPSMC_MSG_LoadUcodes, fw_to_load), |
564 | "Fail to Request SMU Load uCode", return 0); | 563 | "Fail to Request SMU Load uCode", return 0); |
565 | 564 | ||
566 | return result; | 565 | return 0; |
567 | } | 566 | } |
568 | 567 | ||
569 | static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr, | 568 | static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr, |