diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-09-07 03:06:58 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-09-14 15:10:28 -0400 |
commit | 519df8a6f21d4f7a86f137dd65f75ebf66663f7d (patch) | |
tree | 20b204c26aac2eac934dfe98d5384d5703313df6 /drivers/gpu/drm/amd | |
parent | e7b54945f5eb3394ec630e350b5faa686c6a0eb6 (diff) |
drm/amd/powerplay: calculate flexible array member's address.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | 218 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/pp_debug.h | 3 |
3 files changed, 140 insertions, 83 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h index f127198aafc4..1e870f58dd12 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h | |||
@@ -164,7 +164,7 @@ typedef struct _ATOM_Tonga_State { | |||
164 | typedef struct _ATOM_Tonga_State_Array { | 164 | typedef struct _ATOM_Tonga_State_Array { |
165 | UCHAR ucRevId; | 165 | UCHAR ucRevId; |
166 | UCHAR ucNumEntries; /* Number of entries. */ | 166 | UCHAR ucNumEntries; /* Number of entries. */ |
167 | ATOM_Tonga_State states[1]; /* Dynamically allocate entries. */ | 167 | ATOM_Tonga_State entries[1]; /* Dynamically allocate entries. */ |
168 | } ATOM_Tonga_State_Array; | 168 | } ATOM_Tonga_State_Array; |
169 | 169 | ||
170 | typedef struct _ATOM_Tonga_MCLK_Dependency_Record { | 170 | typedef struct _ATOM_Tonga_MCLK_Dependency_Record { |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index 622ac0288898..0f3dad3c2296 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | |||
@@ -154,12 +154,14 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr) | |||
154 | static int get_vddc_lookup_table( | 154 | static int get_vddc_lookup_table( |
155 | struct pp_hwmgr *hwmgr, | 155 | struct pp_hwmgr *hwmgr, |
156 | phm_ppt_v1_voltage_lookup_table **lookup_table, | 156 | phm_ppt_v1_voltage_lookup_table **lookup_table, |
157 | const ATOM_Tonga_Voltage_Lookup_Table *vddc_lookup_pp_tables, | 157 | const ATOM_Tonga_Voltage_Lookup_Table *vddc_lookup_pp_tables, |
158 | uint32_t max_levels | 158 | uint32_t max_levels |
159 | ) | 159 | ) |
160 | { | 160 | { |
161 | uint32_t table_size, i; | 161 | uint32_t table_size, i; |
162 | phm_ppt_v1_voltage_lookup_table *table; | 162 | phm_ppt_v1_voltage_lookup_table *table; |
163 | phm_ppt_v1_voltage_lookup_record *record; | ||
164 | ATOM_Tonga_Voltage_Lookup_Record *atom_record; | ||
163 | 165 | ||
164 | PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries), | 166 | PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries), |
165 | "Invalid CAC Leakage PowerPlay Table!", return 1); | 167 | "Invalid CAC Leakage PowerPlay Table!", return 1); |
@@ -177,15 +179,17 @@ static int get_vddc_lookup_table( | |||
177 | table->count = vddc_lookup_pp_tables->ucNumEntries; | 179 | table->count = vddc_lookup_pp_tables->ucNumEntries; |
178 | 180 | ||
179 | for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) { | 181 | for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) { |
180 | table->entries[i].us_calculated = 0; | 182 | record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
181 | table->entries[i].us_vdd = | 183 | phm_ppt_v1_voltage_lookup_record, |
182 | vddc_lookup_pp_tables->entries[i].usVdd; | 184 | entries, table, i); |
183 | table->entries[i].us_cac_low = | 185 | atom_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
184 | vddc_lookup_pp_tables->entries[i].usCACLow; | 186 | ATOM_Tonga_Voltage_Lookup_Record, |
185 | table->entries[i].us_cac_mid = | 187 | entries, vddc_lookup_pp_tables, i); |
186 | vddc_lookup_pp_tables->entries[i].usCACMid; | 188 | record->us_calculated = 0; |
187 | table->entries[i].us_cac_high = | 189 | record->us_vdd = atom_record->usVdd; |
188 | vddc_lookup_pp_tables->entries[i].usCACHigh; | 190 | record->us_cac_low = atom_record->usCACLow; |
191 | record->us_cac_mid = atom_record->usCACMid; | ||
192 | record->us_cac_high = atom_record->usCACHigh; | ||
189 | } | 193 | } |
190 | 194 | ||
191 | *lookup_table = table; | 195 | *lookup_table = table; |
@@ -314,11 +318,12 @@ static int init_dpm_2_parameters( | |||
314 | static int get_valid_clk( | 318 | static int get_valid_clk( |
315 | struct pp_hwmgr *hwmgr, | 319 | struct pp_hwmgr *hwmgr, |
316 | struct phm_clock_array **clk_table, | 320 | struct phm_clock_array **clk_table, |
317 | const phm_ppt_v1_clock_voltage_dependency_table * clk_volt_pp_table | 321 | phm_ppt_v1_clock_voltage_dependency_table const *clk_volt_pp_table |
318 | ) | 322 | ) |
319 | { | 323 | { |
320 | uint32_t table_size, i; | 324 | uint32_t table_size, i; |
321 | struct phm_clock_array *table; | 325 | struct phm_clock_array *table; |
326 | phm_ppt_v1_clock_voltage_dependency_record *dep_record; | ||
322 | 327 | ||
323 | PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count), | 328 | PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count), |
324 | "Invalid PowerPlay Table!", return -1); | 329 | "Invalid PowerPlay Table!", return -1); |
@@ -335,9 +340,12 @@ static int get_valid_clk( | |||
335 | 340 | ||
336 | table->count = (uint32_t)clk_volt_pp_table->count; | 341 | table->count = (uint32_t)clk_volt_pp_table->count; |
337 | 342 | ||
338 | for (i = 0; i < table->count; i++) | 343 | for (i = 0; i < table->count; i++) { |
339 | table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk; | 344 | dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
340 | 345 | phm_ppt_v1_clock_voltage_dependency_record, | |
346 | entries, clk_volt_pp_table, i); | ||
347 | table->values[i] = (uint32_t)dep_record->clk; | ||
348 | } | ||
341 | *clk_table = table; | 349 | *clk_table = table; |
342 | 350 | ||
343 | return 0; | 351 | return 0; |
@@ -346,7 +354,7 @@ static int get_valid_clk( | |||
346 | static int get_hard_limits( | 354 | static int get_hard_limits( |
347 | struct pp_hwmgr *hwmgr, | 355 | struct pp_hwmgr *hwmgr, |
348 | struct phm_clock_and_voltage_limits *limits, | 356 | struct phm_clock_and_voltage_limits *limits, |
349 | const ATOM_Tonga_Hard_Limit_Table * limitable | 357 | ATOM_Tonga_Hard_Limit_Table const *limitable |
350 | ) | 358 | ) |
351 | { | 359 | { |
352 | PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1); | 360 | PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1); |
@@ -364,11 +372,13 @@ static int get_hard_limits( | |||
364 | static int get_mclk_voltage_dependency_table( | 372 | static int get_mclk_voltage_dependency_table( |
365 | struct pp_hwmgr *hwmgr, | 373 | struct pp_hwmgr *hwmgr, |
366 | phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table, | 374 | phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table, |
367 | const ATOM_Tonga_MCLK_Dependency_Table * mclk_dep_table | 375 | ATOM_Tonga_MCLK_Dependency_Table const *mclk_dep_table |
368 | ) | 376 | ) |
369 | { | 377 | { |
370 | uint32_t table_size, i; | 378 | uint32_t table_size, i; |
371 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table; | 379 | phm_ppt_v1_clock_voltage_dependency_table *mclk_table; |
380 | phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record; | ||
381 | ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record; | ||
372 | 382 | ||
373 | PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries), | 383 | PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries), |
374 | "Invalid PowerPlay Table!", return -1); | 384 | "Invalid PowerPlay Table!", return -1); |
@@ -386,16 +396,17 @@ static int get_mclk_voltage_dependency_table( | |||
386 | mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; | 396 | mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; |
387 | 397 | ||
388 | for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { | 398 | for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { |
389 | mclk_table->entries[i].vddInd = | 399 | mclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
390 | mclk_dep_table->entries[i].ucVddcInd; | 400 | phm_ppt_v1_clock_voltage_dependency_record, |
391 | mclk_table->entries[i].vdd_offset = | 401 | entries, mclk_table, i); |
392 | mclk_dep_table->entries[i].usVddgfxOffset; | 402 | mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
393 | mclk_table->entries[i].vddci = | 403 | ATOM_Tonga_MCLK_Dependency_Record, |
394 | mclk_dep_table->entries[i].usVddci; | 404 | entries, mclk_dep_table, i); |
395 | mclk_table->entries[i].mvdd = | 405 | mclk_table_record->vddInd = mclk_dep_record->ucVddcInd; |
396 | mclk_dep_table->entries[i].usMvdd; | 406 | mclk_table_record->vdd_offset = mclk_dep_record->usVddgfxOffset; |
397 | mclk_table->entries[i].clk = | 407 | mclk_table_record->vddci = mclk_dep_record->usVddci; |
398 | mclk_dep_table->entries[i].ulMclk; | 408 | mclk_table_record->mvdd = mclk_dep_record->usMvdd; |
409 | mclk_table_record->clk = mclk_dep_record->ulMclk; | ||
399 | } | 410 | } |
400 | 411 | ||
401 | *pp_tonga_mclk_dep_table = mclk_table; | 412 | *pp_tonga_mclk_dep_table = mclk_table; |
@@ -411,10 +422,12 @@ static int get_sclk_voltage_dependency_table( | |||
411 | { | 422 | { |
412 | uint32_t table_size, i; | 423 | uint32_t table_size, i; |
413 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table; | 424 | phm_ppt_v1_clock_voltage_dependency_table *sclk_table; |
425 | phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record; | ||
414 | 426 | ||
415 | if (sclk_dep_table->ucRevId < 1) { | 427 | if (sclk_dep_table->ucRevId < 1) { |
416 | const ATOM_Tonga_SCLK_Dependency_Table *tonga_table = | 428 | const ATOM_Tonga_SCLK_Dependency_Table *tonga_table = |
417 | (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table; | 429 | (ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table; |
430 | ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record; | ||
418 | 431 | ||
419 | PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries), | 432 | PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries), |
420 | "Invalid PowerPlay Table!", return -1); | 433 | "Invalid PowerPlay Table!", return -1); |
@@ -432,20 +445,23 @@ static int get_sclk_voltage_dependency_table( | |||
432 | sclk_table->count = (uint32_t)tonga_table->ucNumEntries; | 445 | sclk_table->count = (uint32_t)tonga_table->ucNumEntries; |
433 | 446 | ||
434 | for (i = 0; i < tonga_table->ucNumEntries; i++) { | 447 | for (i = 0; i < tonga_table->ucNumEntries; i++) { |
435 | sclk_table->entries[i].vddInd = | 448 | sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
436 | tonga_table->entries[i].ucVddInd; | 449 | ATOM_Tonga_SCLK_Dependency_Record, |
437 | sclk_table->entries[i].vdd_offset = | 450 | entries, tonga_table, i); |
438 | tonga_table->entries[i].usVddcOffset; | 451 | sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
439 | sclk_table->entries[i].clk = | 452 | phm_ppt_v1_clock_voltage_dependency_record, |
440 | tonga_table->entries[i].ulSclk; | 453 | entries, sclk_table, i); |
441 | sclk_table->entries[i].cks_enable = | 454 | sclk_table_record->vddInd = sclk_dep_record->ucVddInd; |
442 | (((tonga_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; | 455 | sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset; |
443 | sclk_table->entries[i].cks_voffset = | 456 | sclk_table_record->clk = sclk_dep_record->ulSclk; |
444 | (tonga_table->entries[i].ucCKSVOffsetandDisable & 0x7F); | 457 | sclk_table_record->cks_enable = |
458 | (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; | ||
459 | sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F); | ||
445 | } | 460 | } |
446 | } else { | 461 | } else { |
447 | const ATOM_Polaris_SCLK_Dependency_Table *polaris_table = | 462 | const ATOM_Polaris_SCLK_Dependency_Table *polaris_table = |
448 | (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table; | 463 | (ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table; |
464 | ATOM_Polaris_SCLK_Dependency_Record *sclk_dep_record; | ||
449 | 465 | ||
450 | PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries), | 466 | PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries), |
451 | "Invalid PowerPlay Table!", return -1); | 467 | "Invalid PowerPlay Table!", return -1); |
@@ -463,17 +479,19 @@ static int get_sclk_voltage_dependency_table( | |||
463 | sclk_table->count = (uint32_t)polaris_table->ucNumEntries; | 479 | sclk_table->count = (uint32_t)polaris_table->ucNumEntries; |
464 | 480 | ||
465 | for (i = 0; i < polaris_table->ucNumEntries; i++) { | 481 | for (i = 0; i < polaris_table->ucNumEntries; i++) { |
466 | sclk_table->entries[i].vddInd = | 482 | sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
467 | polaris_table->entries[i].ucVddInd; | 483 | ATOM_Polaris_SCLK_Dependency_Record, |
468 | sclk_table->entries[i].vdd_offset = | 484 | entries, polaris_table, i); |
469 | polaris_table->entries[i].usVddcOffset; | 485 | sclk_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
470 | sclk_table->entries[i].clk = | 486 | phm_ppt_v1_clock_voltage_dependency_record, |
471 | polaris_table->entries[i].ulSclk; | 487 | entries, sclk_table, i); |
472 | sclk_table->entries[i].cks_enable = | 488 | sclk_table_record->vddInd = sclk_dep_record->ucVddInd; |
473 | (((polaris_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; | 489 | sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset; |
474 | sclk_table->entries[i].cks_voffset = | 490 | sclk_table_record->clk = sclk_dep_record->ulSclk; |
475 | (polaris_table->entries[i].ucCKSVOffsetandDisable & 0x7F); | 491 | sclk_table_record->cks_enable = |
476 | sclk_table->entries[i].sclk_offset = polaris_table->entries[i].ulSclkOffset; | 492 | (((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0; |
493 | sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F); | ||
494 | sclk_table_record->sclk_offset = sclk_dep_record->ulSclkOffset; | ||
477 | } | 495 | } |
478 | } | 496 | } |
479 | *pp_tonga_sclk_dep_table = sclk_table; | 497 | *pp_tonga_sclk_dep_table = sclk_table; |
@@ -484,16 +502,19 @@ static int get_sclk_voltage_dependency_table( | |||
484 | static int get_pcie_table( | 502 | static int get_pcie_table( |
485 | struct pp_hwmgr *hwmgr, | 503 | struct pp_hwmgr *hwmgr, |
486 | phm_ppt_v1_pcie_table **pp_tonga_pcie_table, | 504 | phm_ppt_v1_pcie_table **pp_tonga_pcie_table, |
487 | const PPTable_Generic_SubTable_Header * pTable | 505 | PPTable_Generic_SubTable_Header const *ptable |
488 | ) | 506 | ) |
489 | { | 507 | { |
490 | uint32_t table_size, i, pcie_count; | 508 | uint32_t table_size, i, pcie_count; |
491 | phm_ppt_v1_pcie_table *pcie_table; | 509 | phm_ppt_v1_pcie_table *pcie_table; |
492 | struct phm_ppt_v1_information *pp_table_information = | 510 | struct phm_ppt_v1_information *pp_table_information = |
493 | (struct phm_ppt_v1_information *)(hwmgr->pptable); | 511 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
512 | phm_ppt_v1_pcie_record *pcie_record; | ||
513 | |||
514 | if (ptable->ucRevId < 1) { | ||
515 | const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)ptable; | ||
516 | ATOM_Tonga_PCIE_Record *atom_pcie_record; | ||
494 | 517 | ||
495 | if (pTable->ucRevId < 1) { | ||
496 | const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)pTable; | ||
497 | PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), | 518 | PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), |
498 | "Invalid PowerPlay Table!", return -1); | 519 | "Invalid PowerPlay Table!", return -1); |
499 | 520 | ||
@@ -519,18 +540,23 @@ static int get_pcie_table( | |||
519 | Disregarding the excess entries... \n"); | 540 | Disregarding the excess entries... \n"); |
520 | 541 | ||
521 | pcie_table->count = pcie_count; | 542 | pcie_table->count = pcie_count; |
522 | |||
523 | for (i = 0; i < pcie_count; i++) { | 543 | for (i = 0; i < pcie_count; i++) { |
524 | pcie_table->entries[i].gen_speed = | 544 | pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
525 | atom_pcie_table->entries[i].ucPCIEGenSpeed; | 545 | phm_ppt_v1_pcie_record, |
526 | pcie_table->entries[i].lane_width = | 546 | entries, pcie_table, i); |
527 | atom_pcie_table->entries[i].usPCIELaneWidth; | 547 | atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
548 | ATOM_Tonga_PCIE_Record, | ||
549 | entries, atom_pcie_table, i); | ||
550 | pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; | ||
551 | pcie_record->lane_width = atom_pcie_record->usPCIELaneWidth; | ||
528 | } | 552 | } |
529 | 553 | ||
530 | *pp_tonga_pcie_table = pcie_table; | 554 | *pp_tonga_pcie_table = pcie_table; |
531 | } else { | 555 | } else { |
532 | /* Polaris10/Polaris11 and newer. */ | 556 | /* Polaris10/Polaris11 and newer. */ |
533 | const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable; | 557 | const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)ptable; |
558 | ATOM_Polaris10_PCIE_Record *atom_pcie_record; | ||
559 | |||
534 | PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), | 560 | PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), |
535 | "Invalid PowerPlay Table!", return -1); | 561 | "Invalid PowerPlay Table!", return -1); |
536 | 562 | ||
@@ -558,12 +584,15 @@ static int get_pcie_table( | |||
558 | pcie_table->count = pcie_count; | 584 | pcie_table->count = pcie_count; |
559 | 585 | ||
560 | for (i = 0; i < pcie_count; i++) { | 586 | for (i = 0; i < pcie_count; i++) { |
561 | pcie_table->entries[i].gen_speed = | 587 | pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
562 | atom_pcie_table->entries[i].ucPCIEGenSpeed; | 588 | phm_ppt_v1_pcie_record, |
563 | pcie_table->entries[i].lane_width = | 589 | entries, pcie_table, i); |
564 | atom_pcie_table->entries[i].usPCIELaneWidth; | 590 | atom_pcie_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
565 | pcie_table->entries[i].pcie_sclk = | 591 | ATOM_Polaris10_PCIE_Record, |
566 | atom_pcie_table->entries[i].ulPCIE_Sclk; | 592 | entries, atom_pcie_table, i); |
593 | pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; | ||
594 | pcie_record->lane_width = atom_pcie_record->usPCIELaneWidth; | ||
595 | pcie_record->pcie_sclk = atom_pcie_record->ulPCIE_Sclk; | ||
567 | } | 596 | } |
568 | 597 | ||
569 | *pp_tonga_pcie_table = pcie_table; | 598 | *pp_tonga_pcie_table = pcie_table; |
@@ -685,6 +714,7 @@ static int get_mm_clock_voltage_table( | |||
685 | uint32_t table_size, i; | 714 | uint32_t table_size, i; |
686 | const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record; | 715 | const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record; |
687 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table; | 716 | phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table; |
717 | phm_ppt_v1_mm_clock_voltage_dependency_record *mm_table_record; | ||
688 | 718 | ||
689 | PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries), | 719 | PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries), |
690 | "Invalid PowerPlay Table!", return -1); | 720 | "Invalid PowerPlay Table!", return -1); |
@@ -701,14 +731,19 @@ static int get_mm_clock_voltage_table( | |||
701 | mm_table->count = mm_dependency_table->ucNumEntries; | 731 | mm_table->count = mm_dependency_table->ucNumEntries; |
702 | 732 | ||
703 | for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { | 733 | for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { |
704 | mm_dependency_record = &mm_dependency_table->entries[i]; | 734 | mm_dependency_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
705 | mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd; | 735 | ATOM_Tonga_MM_Dependency_Record, |
706 | mm_table->entries[i].vddgfx_offset = mm_dependency_record->usVddgfxOffset; | 736 | entries, mm_dependency_table, i); |
707 | mm_table->entries[i].aclk = mm_dependency_record->ulAClk; | 737 | mm_table_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
708 | mm_table->entries[i].samclock = mm_dependency_record->ulSAMUClk; | 738 | phm_ppt_v1_mm_clock_voltage_dependency_record, |
709 | mm_table->entries[i].eclk = mm_dependency_record->ulEClk; | 739 | entries, mm_table, i); |
710 | mm_table->entries[i].vclk = mm_dependency_record->ulVClk; | 740 | mm_table_record->vddcInd = mm_dependency_record->ucVddcInd; |
711 | mm_table->entries[i].dclk = mm_dependency_record->ulDClk; | 741 | mm_table_record->vddgfx_offset = mm_dependency_record->usVddgfxOffset; |
742 | mm_table_record->aclk = mm_dependency_record->ulAClk; | ||
743 | mm_table_record->samclock = mm_dependency_record->ulSAMUClk; | ||
744 | mm_table_record->eclk = mm_dependency_record->ulEClk; | ||
745 | mm_table_record->vclk = mm_dependency_record->ulVClk; | ||
746 | mm_table_record->dclk = mm_dependency_record->ulDClk; | ||
712 | } | 747 | } |
713 | 748 | ||
714 | *tonga_mm_table = mm_table; | 749 | *tonga_mm_table = mm_table; |
@@ -1176,11 +1211,13 @@ static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr) | |||
1176 | return vce_state_table->ucNumEntries; | 1211 | return vce_state_table->ucNumEntries; |
1177 | } | 1212 | } |
1178 | 1213 | ||
1179 | |||
1180 | static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i, | 1214 | static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i, |
1181 | struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag) | 1215 | struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag) |
1182 | { | 1216 | { |
1183 | const ATOM_Tonga_VCE_State_Record *vce_state_record; | 1217 | const ATOM_Tonga_VCE_State_Record *vce_state_record; |
1218 | ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record; | ||
1219 | ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record; | ||
1220 | ATOM_Tonga_MM_Dependency_Record *mm_dep_record; | ||
1184 | const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr); | 1221 | const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr); |
1185 | const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable) | 1222 | const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable) |
1186 | + le16_to_cpu(pptable->usVCEStateTableOffset)); | 1223 | + le16_to_cpu(pptable->usVCEStateTableOffset)); |
@@ -1195,20 +1232,35 @@ static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i | |||
1195 | "Requested state entry ID is out of range!", | 1232 | "Requested state entry ID is out of range!", |
1196 | return -EINVAL); | 1233 | return -EINVAL); |
1197 | 1234 | ||
1198 | vce_state_record = (ATOM_Tonga_VCE_State_Record *)((char *)&vce_state_table->entries[1] | 1235 | vce_state_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
1199 | + (sizeof(ATOM_Tonga_VCE_State_Record) * i)); | 1236 | ATOM_Tonga_VCE_State_Record, |
1200 | 1237 | entries, vce_state_table, i); | |
1238 | sclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( | ||
1239 | ATOM_Tonga_SCLK_Dependency_Record, | ||
1240 | entries, sclk_dep_table, | ||
1241 | vce_state_record->ucSCLKIndex); | ||
1242 | mm_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( | ||
1243 | ATOM_Tonga_MM_Dependency_Record, | ||
1244 | entries, mm_dep_table, | ||
1245 | vce_state_record->ucVCEClockIndex); | ||
1201 | *flag = vce_state_record->ucFlag; | 1246 | *flag = vce_state_record->ucFlag; |
1202 | 1247 | ||
1203 | vce_state->evclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk; | 1248 | vce_state->evclk = mm_dep_record->ulEClk; |
1204 | vce_state->ecclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk; | 1249 | vce_state->ecclk = mm_dep_record->ulEClk; |
1205 | vce_state->sclk = sclk_dep_table->entries[vce_state_record->ucSCLKIndex].ulSclk; | 1250 | vce_state->sclk = sclk_dep_record->ulSclk; |
1206 | 1251 | ||
1207 | if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries) | 1252 | if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries) |
1208 | vce_state->mclk = mclk_dep_table->entries[mclk_dep_table->ucNumEntries - 1].ulMclk; | 1253 | mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
1254 | ATOM_Tonga_MCLK_Dependency_Record, | ||
1255 | entries, mclk_dep_table, | ||
1256 | mclk_dep_table->ucNumEntries - 1); | ||
1209 | else | 1257 | else |
1210 | vce_state->mclk = mclk_dep_table->entries[vce_state_record->ucMCLKIndex].ulMclk; | 1258 | mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
1259 | ATOM_Tonga_MCLK_Dependency_Record, | ||
1260 | entries, mclk_dep_table, | ||
1261 | vce_state_record->ucMCLKIndex); | ||
1211 | 1262 | ||
1263 | vce_state->mclk = mclk_dep_record->ulMclk; | ||
1212 | return 0; | 1264 | return 0; |
1213 | } | 1265 | } |
1214 | 1266 | ||
@@ -1226,7 +1278,7 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, | |||
1226 | struct pp_power_state *, void *, uint32_t)) | 1278 | struct pp_power_state *, void *, uint32_t)) |
1227 | { | 1279 | { |
1228 | int result = 0; | 1280 | int result = 0; |
1229 | const ATOM_Tonga_State_Array * state_arrays; | 1281 | const ATOM_Tonga_State_Array *state_arrays; |
1230 | const ATOM_Tonga_State *state_entry; | 1282 | const ATOM_Tonga_State *state_entry; |
1231 | const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); | 1283 | const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); |
1232 | int i, j; | 1284 | int i, j; |
@@ -1247,7 +1299,9 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, | |||
1247 | PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), | 1299 | PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), |
1248 | "Invalid PowerPlay Table State Array Entry.", return -1); | 1300 | "Invalid PowerPlay Table State Array Entry.", return -1); |
1249 | 1301 | ||
1250 | state_entry = &(state_arrays->states[entry_index]); | 1302 | state_entry = GET_FLEXIBLE_ARRAY_MEMBER_ADDR( |
1303 | ATOM_Tonga_State, entries, | ||
1304 | state_arrays, entry_index); | ||
1251 | 1305 | ||
1252 | result = call_back_func(hwmgr, (void *)state_entry, power_state, | 1306 | result = call_back_func(hwmgr, (void *)state_entry, power_state, |
1253 | (void *)pp_table, | 1307 | (void *)pp_table, |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h index d7d83b7c7f95..bfdbec10cdd5 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h | |||
@@ -43,5 +43,8 @@ | |||
43 | } while (0) | 43 | } while (0) |
44 | 44 | ||
45 | 45 | ||
46 | #define GET_FLEXIBLE_ARRAY_MEMBER_ADDR(type, member, ptr, n) \ | ||
47 | (type *)((char *)&(ptr)->member + (sizeof(type) * (n))) | ||
48 | |||
46 | #endif /* PP_DEBUG_H */ | 49 | #endif /* PP_DEBUG_H */ |
47 | 50 | ||