diff options
| author | Boyuan Zhang <boyuan.zhang@amd.com> | 2018-04-30 16:55:39 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-06-15 13:20:35 -0400 |
| commit | 50613395abc00f150f051d6bc440877741b6fae9 (patch) | |
| tree | 24c4611f591ef545fc01ad5d1ca853c4a88d6a16 /drivers/gpu/drm/amd | |
| parent | d521093a5f84cacf9935e8c9834ad3054b423ee1 (diff) | |
drm/amdgpu: add more jpeg register offset headers
Add more jpeg registers defines that are needed for jpeg ring functions
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 18a32477ed1d..fe0cbaade3c3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | |||
| @@ -89,6 +89,8 @@ | |||
| 89 | #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 | 89 | #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 |
| 90 | #define mmUVD_JPEG_ADDR_CONFIG 0x021f | 90 | #define mmUVD_JPEG_ADDR_CONFIG 0x021f |
| 91 | #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 | 91 | #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 |
| 92 | #define mmUVD_JPEG_PITCH 0x0222 | ||
| 93 | #define mmUVD_JPEG_PITCH_BASE_IDX 1 | ||
| 92 | #define mmUVD_JPEG_GPCOM_CMD 0x022c | 94 | #define mmUVD_JPEG_GPCOM_CMD 0x022c |
| 93 | #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 1 | 95 | #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 1 |
| 94 | #define mmUVD_JPEG_GPCOM_DATA0 0x022d | 96 | #define mmUVD_JPEG_GPCOM_DATA0 0x022d |
| @@ -203,6 +205,8 @@ | |||
| 203 | #define mmUVD_RB_WPTR4_BASE_IDX 1 | 205 | #define mmUVD_RB_WPTR4_BASE_IDX 1 |
| 204 | #define mmUVD_JRBC_RB_RPTR 0x0457 | 206 | #define mmUVD_JRBC_RB_RPTR 0x0457 |
| 205 | #define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 | 207 | #define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 |
| 208 | #define mmUVD_LMI_JPEG_VMID 0x045d | ||
| 209 | #define mmUVD_LMI_JPEG_VMID_BASE_IDX 1 | ||
| 206 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e | 210 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e |
| 207 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 | 211 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
| 208 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f | 212 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f |
| @@ -231,6 +235,8 @@ | |||
| 231 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 | 235 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
| 232 | #define mmUVD_LMI_JRBC_IB_VMID 0x0507 | 236 | #define mmUVD_LMI_JRBC_IB_VMID 0x0507 |
| 233 | #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 | 237 | #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 |
| 238 | #define mmUVD_LMI_JRBC_RB_VMID 0x0508 | ||
| 239 | #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 | ||
| 234 | #define mmUVD_JRBC_RB_WPTR 0x0509 | 240 | #define mmUVD_JRBC_RB_WPTR 0x0509 |
| 235 | #define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 | 241 | #define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 |
| 236 | #define mmUVD_JRBC_RB_CNTL 0x050a | 242 | #define mmUVD_JRBC_RB_CNTL 0x050a |
| @@ -239,6 +245,20 @@ | |||
| 239 | #define mmUVD_JRBC_IB_SIZE_BASE_IDX 1 | 245 | #define mmUVD_JRBC_IB_SIZE_BASE_IDX 1 |
| 240 | #define mmUVD_JRBC_LMI_SWAP_CNTL 0x050d | 246 | #define mmUVD_JRBC_LMI_SWAP_CNTL 0x050d |
| 241 | #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX 1 | 247 | #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX 1 |
| 248 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x050e | ||
| 249 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 | ||
| 250 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x050f | ||
| 251 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 | ||
| 252 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0510 | ||
| 253 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 | ||
| 254 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0511 | ||
| 255 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 | ||
| 256 | #define mmUVD_JRBC_RB_REF_DATA 0x0512 | ||
| 257 | #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 1 | ||
| 258 | #define mmUVD_JRBC_RB_COND_RD_TIMER 0x0513 | ||
| 259 | #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 | ||
| 260 | #define mmUVD_JRBC_EXTERNAL_REG_BASE 0x0517 | ||
| 261 | #define mmUVD_JRBC_EXTERNAL_REG_BASE_BASE_IDX 1 | ||
| 242 | #define mmUVD_JRBC_SOFT_RESET 0x0519 | 262 | #define mmUVD_JRBC_SOFT_RESET 0x0519 |
| 243 | #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 1 | 263 | #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 1 |
| 244 | #define mmUVD_JRBC_STATUS 0x051a | 264 | #define mmUVD_JRBC_STATUS 0x051a |