diff options
author | Chunming Zhou <david1.zhou@amd.com> | 2015-08-19 04:41:19 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2015-08-25 10:38:41 -0400 |
commit | 4ce9891ee17c6e064cc334e3297f7e992d47f3a6 (patch) | |
tree | 402cc36ef6e4db0fc0158ae9cdcee6e9e7ff2445 /drivers/gpu/drm/amd | |
parent | 1aa4051b7f5474cca6009c13868c59d78d06f983 (diff) |
drm/amdgpu: improve sa_bo->fence by kernel fence
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 22 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 50 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 |
8 files changed, 58 insertions, 34 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4addac5f6763..80f2ceaf6af6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -441,7 +441,7 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | |||
441 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | 441 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); |
442 | 442 | ||
443 | signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, | 443 | signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, |
444 | struct amdgpu_fence **array, | 444 | struct fence **array, |
445 | uint32_t count, | 445 | uint32_t count, |
446 | bool wait_all, | 446 | bool wait_all, |
447 | bool intr, | 447 | bool intr, |
@@ -654,7 +654,7 @@ struct amdgpu_sa_bo { | |||
654 | struct amdgpu_sa_manager *manager; | 654 | struct amdgpu_sa_manager *manager; |
655 | unsigned soffset; | 655 | unsigned soffset; |
656 | unsigned eoffset; | 656 | unsigned eoffset; |
657 | struct amdgpu_fence *fence; | 657 | struct fence *fence; |
658 | }; | 658 | }; |
659 | 659 | ||
660 | /* | 660 | /* |
@@ -696,7 +696,7 @@ bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | |||
696 | struct amdgpu_semaphore *semaphore); | 696 | struct amdgpu_semaphore *semaphore); |
697 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | 697 | void amdgpu_semaphore_free(struct amdgpu_device *adev, |
698 | struct amdgpu_semaphore **semaphore, | 698 | struct amdgpu_semaphore **semaphore, |
699 | struct amdgpu_fence *fence); | 699 | struct fence *fence); |
700 | 700 | ||
701 | /* | 701 | /* |
702 | * Synchronization | 702 | * Synchronization |
@@ -717,7 +717,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, | |||
717 | int amdgpu_sync_rings(struct amdgpu_sync *sync, | 717 | int amdgpu_sync_rings(struct amdgpu_sync *sync, |
718 | struct amdgpu_ring *ring); | 718 | struct amdgpu_ring *ring); |
719 | void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, | 719 | void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
720 | struct amdgpu_fence *fence); | 720 | struct fence *fence); |
721 | 721 | ||
722 | /* | 722 | /* |
723 | * GART structures, functions & helpers | 723 | * GART structures, functions & helpers |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index ae014fcf524e..9a87372c3c79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | |||
@@ -836,30 +836,30 @@ static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence) | |||
836 | return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); | 836 | return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); |
837 | } | 837 | } |
838 | 838 | ||
839 | static bool amdgpu_test_signaled_any(struct amdgpu_fence **fences, uint32_t count) | 839 | static bool amdgpu_test_signaled_any(struct fence **fences, uint32_t count) |
840 | { | 840 | { |
841 | int idx; | 841 | int idx; |
842 | struct amdgpu_fence *fence; | 842 | struct fence *fence; |
843 | 843 | ||
844 | for (idx = 0; idx < count; ++idx) { | 844 | for (idx = 0; idx < count; ++idx) { |
845 | fence = fences[idx]; | 845 | fence = fences[idx]; |
846 | if (fence) { | 846 | if (fence) { |
847 | if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags)) | 847 | if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
848 | return true; | 848 | return true; |
849 | } | 849 | } |
850 | } | 850 | } |
851 | return false; | 851 | return false; |
852 | } | 852 | } |
853 | 853 | ||
854 | static bool amdgpu_test_signaled_all(struct amdgpu_fence **fences, uint32_t count) | 854 | static bool amdgpu_test_signaled_all(struct fence **fences, uint32_t count) |
855 | { | 855 | { |
856 | int idx; | 856 | int idx; |
857 | struct amdgpu_fence *fence; | 857 | struct fence *fence; |
858 | 858 | ||
859 | for (idx = 0; idx < count; ++idx) { | 859 | for (idx = 0; idx < count; ++idx) { |
860 | fence = fences[idx]; | 860 | fence = fences[idx]; |
861 | if (fence) { | 861 | if (fence) { |
862 | if (!test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags)) | 862 | if (!test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
863 | return false; | 863 | return false; |
864 | } | 864 | } |
865 | } | 865 | } |
@@ -885,7 +885,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, | |||
885 | struct amdgpu_fence *fence = to_amdgpu_fence(f); | 885 | struct amdgpu_fence *fence = to_amdgpu_fence(f); |
886 | struct amdgpu_device *adev = fence->ring->adev; | 886 | struct amdgpu_device *adev = fence->ring->adev; |
887 | 887 | ||
888 | return amdgpu_fence_wait_multiple(adev, &fence, 1, false, intr, t); | 888 | return amdgpu_fence_wait_multiple(adev, &f, 1, false, intr, t); |
889 | } | 889 | } |
890 | 890 | ||
891 | /** | 891 | /** |
@@ -902,7 +902,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, | |||
902 | * If wait_all is false, it will return when any fence is signaled or timeout. | 902 | * If wait_all is false, it will return when any fence is signaled or timeout. |
903 | */ | 903 | */ |
904 | signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, | 904 | signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, |
905 | struct amdgpu_fence **array, | 905 | struct fence **array, |
906 | uint32_t count, | 906 | uint32_t count, |
907 | bool wait_all, | 907 | bool wait_all, |
908 | bool intr, | 908 | bool intr, |
@@ -910,7 +910,7 @@ signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, | |||
910 | { | 910 | { |
911 | long idx = 0; | 911 | long idx = 0; |
912 | struct amdgpu_wait_cb *cb; | 912 | struct amdgpu_wait_cb *cb; |
913 | struct amdgpu_fence *fence; | 913 | struct fence *fence; |
914 | 914 | ||
915 | BUG_ON(!array); | 915 | BUG_ON(!array); |
916 | 916 | ||
@@ -924,7 +924,7 @@ signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, | |||
924 | fence = array[idx]; | 924 | fence = array[idx]; |
925 | if (fence) { | 925 | if (fence) { |
926 | cb[idx].task = current; | 926 | cb[idx].task = current; |
927 | if (fence_add_callback(&fence->base, | 927 | if (fence_add_callback(fence, |
928 | &cb[idx].base, amdgpu_fence_wait_cb)) { | 928 | &cb[idx].base, amdgpu_fence_wait_cb)) { |
929 | /* The fence is already signaled */ | 929 | /* The fence is already signaled */ |
930 | if (wait_all) | 930 | if (wait_all) |
@@ -967,7 +967,7 @@ fence_rm_cb: | |||
967 | for (idx = 0; idx < count; ++idx) { | 967 | for (idx = 0; idx < count; ++idx) { |
968 | fence = array[idx]; | 968 | fence = array[idx]; |
969 | if (fence) | 969 | if (fence) |
970 | fence_remove_callback(&fence->base, &cb[idx].base); | 970 | fence_remove_callback(fence, &cb[idx].base); |
971 | } | 971 | } |
972 | 972 | ||
973 | err_free_cb: | 973 | err_free_cb: |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 1c237f5e3365..13c5978ac69b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | |||
@@ -93,8 +93,8 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, | |||
93 | */ | 93 | */ |
94 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) | 94 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) |
95 | { | 95 | { |
96 | amdgpu_sync_free(adev, &ib->sync, ib->fence); | 96 | amdgpu_sync_free(adev, &ib->sync, &ib->fence->base); |
97 | amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence); | 97 | amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); |
98 | amdgpu_fence_unref(&ib->fence); | 98 | amdgpu_fence_unref(&ib->fence); |
99 | } | 99 | } |
100 | 100 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 238465a9ac55..6ea18dcec561 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | |||
@@ -193,7 +193,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, | |||
193 | unsigned size, unsigned align); | 193 | unsigned size, unsigned align); |
194 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, | 194 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, |
195 | struct amdgpu_sa_bo **sa_bo, | 195 | struct amdgpu_sa_bo **sa_bo, |
196 | struct amdgpu_fence *fence); | 196 | struct fence *fence); |
197 | #if defined(CONFIG_DEBUG_FS) | 197 | #if defined(CONFIG_DEBUG_FS) |
198 | void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, | 198 | void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, |
199 | struct seq_file *m); | 199 | struct seq_file *m); |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index 4597899e9758..b7cbaa9d532e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | |||
@@ -139,6 +139,20 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, | |||
139 | return r; | 139 | return r; |
140 | } | 140 | } |
141 | 141 | ||
142 | static uint32_t amdgpu_sa_get_ring_from_fence(struct fence *f) | ||
143 | { | ||
144 | struct amdgpu_fence *a_fence; | ||
145 | struct amd_sched_fence *s_fence; | ||
146 | |||
147 | s_fence = to_amd_sched_fence(f); | ||
148 | if (s_fence) | ||
149 | return s_fence->entity->scheduler->ring_id; | ||
150 | a_fence = to_amdgpu_fence(f); | ||
151 | if (a_fence) | ||
152 | return a_fence->ring->idx; | ||
153 | return 0; | ||
154 | } | ||
155 | |||
142 | static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) | 156 | static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) |
143 | { | 157 | { |
144 | struct amdgpu_sa_manager *sa_manager = sa_bo->manager; | 158 | struct amdgpu_sa_manager *sa_manager = sa_bo->manager; |
@@ -147,7 +161,7 @@ static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) | |||
147 | } | 161 | } |
148 | list_del_init(&sa_bo->olist); | 162 | list_del_init(&sa_bo->olist); |
149 | list_del_init(&sa_bo->flist); | 163 | list_del_init(&sa_bo->flist); |
150 | amdgpu_fence_unref(&sa_bo->fence); | 164 | fence_put(sa_bo->fence); |
151 | kfree(sa_bo); | 165 | kfree(sa_bo); |
152 | } | 166 | } |
153 | 167 | ||
@@ -161,7 +175,7 @@ static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager) | |||
161 | sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist); | 175 | sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist); |
162 | list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) { | 176 | list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) { |
163 | if (sa_bo->fence == NULL || | 177 | if (sa_bo->fence == NULL || |
164 | !fence_is_signaled(&sa_bo->fence->base)) { | 178 | !fence_is_signaled(sa_bo->fence)) { |
165 | return; | 179 | return; |
166 | } | 180 | } |
167 | amdgpu_sa_bo_remove_locked(sa_bo); | 181 | amdgpu_sa_bo_remove_locked(sa_bo); |
@@ -246,7 +260,7 @@ static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager, | |||
246 | } | 260 | } |
247 | 261 | ||
248 | static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, | 262 | static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, |
249 | struct amdgpu_fence **fences, | 263 | struct fence **fences, |
250 | unsigned *tries) | 264 | unsigned *tries) |
251 | { | 265 | { |
252 | struct amdgpu_sa_bo *best_bo = NULL; | 266 | struct amdgpu_sa_bo *best_bo = NULL; |
@@ -275,7 +289,7 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, | |||
275 | sa_bo = list_first_entry(&sa_manager->flist[i], | 289 | sa_bo = list_first_entry(&sa_manager->flist[i], |
276 | struct amdgpu_sa_bo, flist); | 290 | struct amdgpu_sa_bo, flist); |
277 | 291 | ||
278 | if (!fence_is_signaled(&sa_bo->fence->base)) { | 292 | if (!fence_is_signaled(sa_bo->fence)) { |
279 | fences[i] = sa_bo->fence; | 293 | fences[i] = sa_bo->fence; |
280 | continue; | 294 | continue; |
281 | } | 295 | } |
@@ -299,7 +313,8 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, | |||
299 | } | 313 | } |
300 | 314 | ||
301 | if (best_bo) { | 315 | if (best_bo) { |
302 | ++tries[best_bo->fence->ring->idx]; | 316 | uint32_t idx = amdgpu_sa_get_ring_from_fence(best_bo->fence); |
317 | ++tries[idx]; | ||
303 | sa_manager->hole = best_bo->olist.prev; | 318 | sa_manager->hole = best_bo->olist.prev; |
304 | 319 | ||
305 | /* we knew that this one is signaled, | 320 | /* we knew that this one is signaled, |
@@ -315,7 +330,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, | |||
315 | struct amdgpu_sa_bo **sa_bo, | 330 | struct amdgpu_sa_bo **sa_bo, |
316 | unsigned size, unsigned align) | 331 | unsigned size, unsigned align) |
317 | { | 332 | { |
318 | struct amdgpu_fence *fences[AMDGPU_MAX_RINGS]; | 333 | struct fence *fences[AMDGPU_MAX_RINGS]; |
319 | unsigned tries[AMDGPU_MAX_RINGS]; | 334 | unsigned tries[AMDGPU_MAX_RINGS]; |
320 | int i, r; | 335 | int i, r; |
321 | signed long t; | 336 | signed long t; |
@@ -373,7 +388,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, | |||
373 | } | 388 | } |
374 | 389 | ||
375 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, | 390 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, |
376 | struct amdgpu_fence *fence) | 391 | struct fence *fence) |
377 | { | 392 | { |
378 | struct amdgpu_sa_manager *sa_manager; | 393 | struct amdgpu_sa_manager *sa_manager; |
379 | 394 | ||
@@ -383,10 +398,11 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, | |||
383 | 398 | ||
384 | sa_manager = (*sa_bo)->manager; | 399 | sa_manager = (*sa_bo)->manager; |
385 | spin_lock(&sa_manager->wq.lock); | 400 | spin_lock(&sa_manager->wq.lock); |
386 | if (fence && !fence_is_signaled(&fence->base)) { | 401 | if (fence && !fence_is_signaled(fence)) { |
387 | (*sa_bo)->fence = amdgpu_fence_ref(fence); | 402 | uint32_t idx; |
388 | list_add_tail(&(*sa_bo)->flist, | 403 | (*sa_bo)->fence = fence_get(fence); |
389 | &sa_manager->flist[fence->ring->idx]); | 404 | idx = amdgpu_sa_get_ring_from_fence(fence); |
405 | list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]); | ||
390 | } else { | 406 | } else { |
391 | amdgpu_sa_bo_remove_locked(*sa_bo); | 407 | amdgpu_sa_bo_remove_locked(*sa_bo); |
392 | } | 408 | } |
@@ -413,8 +429,16 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, | |||
413 | seq_printf(m, "[0x%010llx 0x%010llx] size %8lld", | 429 | seq_printf(m, "[0x%010llx 0x%010llx] size %8lld", |
414 | soffset, eoffset, eoffset - soffset); | 430 | soffset, eoffset, eoffset - soffset); |
415 | if (i->fence) { | 431 | if (i->fence) { |
416 | seq_printf(m, " protected by 0x%016llx on ring %d", | 432 | struct amdgpu_fence *a_fence = to_amdgpu_fence(i->fence); |
417 | i->fence->seq, i->fence->ring->idx); | 433 | struct amd_sched_fence *s_fence = to_amd_sched_fence(i->fence); |
434 | if (a_fence) | ||
435 | seq_printf(m, " protected by 0x%016llx on ring %d", | ||
436 | a_fence->seq, a_fence->ring->idx); | ||
437 | if (s_fence) | ||
438 | seq_printf(m, " protected by 0x%016llx on ring %d", | ||
439 | s_fence->v_seq, | ||
440 | s_fence->entity->scheduler->ring_id); | ||
441 | |||
418 | } | 442 | } |
419 | seq_printf(m, "\n"); | 443 | seq_printf(m, "\n"); |
420 | } | 444 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c index d6d41a42ab65..ff3ca52ec6fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c | |||
@@ -87,7 +87,7 @@ bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | |||
87 | 87 | ||
88 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | 88 | void amdgpu_semaphore_free(struct amdgpu_device *adev, |
89 | struct amdgpu_semaphore **semaphore, | 89 | struct amdgpu_semaphore **semaphore, |
90 | struct amdgpu_fence *fence) | 90 | struct fence *fence) |
91 | { | 91 | { |
92 | if (semaphore == NULL || *semaphore == NULL) { | 92 | if (semaphore == NULL || *semaphore == NULL) { |
93 | return; | 93 | return; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 7cb711fc1ee2..ee68eebfded1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | |||
@@ -234,7 +234,7 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, | |||
234 | */ | 234 | */ |
235 | void amdgpu_sync_free(struct amdgpu_device *adev, | 235 | void amdgpu_sync_free(struct amdgpu_device *adev, |
236 | struct amdgpu_sync *sync, | 236 | struct amdgpu_sync *sync, |
237 | struct amdgpu_fence *fence) | 237 | struct fence *fence) |
238 | { | 238 | { |
239 | unsigned i; | 239 | unsigned i; |
240 | 240 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dd3415d2e45d..d7c02e1a309e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | |||
@@ -1042,7 +1042,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, | |||
1042 | } | 1042 | } |
1043 | 1043 | ||
1044 | amdgpu_ring_unlock_commit(ring); | 1044 | amdgpu_ring_unlock_commit(ring); |
1045 | amdgpu_sync_free(adev, &sync, *fence); | 1045 | amdgpu_sync_free(adev, &sync, &(*fence)->base); |
1046 | 1046 | ||
1047 | return 0; | 1047 | return 0; |
1048 | } | 1048 | } |