BackMerge v4.18-rc7 into drm-next

rmk requested this for armada and I think we've had a few
conflicts build up.

Signed-off-by: Dave Airlie <airlied@redhat.com>

8 files changed, 49 insertions, 16 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index f4c474a95875..71efcf38f11b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -57,6 +57,10 @@
 #define ACP_I2S_COMP2_CAP_REG_OFFSET            0xa8
 #define ACP_I2S_COMP1_PLAY_REG_OFFSET           0x6c
 #define ACP_I2S_COMP2_PLAY_REG_OFFSET           0x68
+#define ACP_BT_PLAY_REGS_START                  0x14970
+#define ACP_BT_PLAY_REGS_END                    0x14a24
+#define ACP_BT_COMP1_REG_OFFSET                 0xac
+#define ACP_BT_COMP2_REG_OFFSET                 0xa8
 
 #define mmACP_PGFSM_RETAIN_REG                  0x51c9
 #define mmACP_PGFSM_CONFIG_REG                  0x51ca
@@ -77,7 +81,7 @@
 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE      0x000000FF
 
 #define ACP_TIMEOUT_LOOP                        0x000000FF
-#define ACP_DEVS                                3
+#define ACP_DEVS                                4
 #define ACP_SRC_ID                              162
 
 enum {
@@ -316,14 +320,13 @@ static int acp_hw_init(void *handle)
         if (adev->acp.acp_cell == NULL)
                 return -ENOMEM;
 
-        adev->acp.acp_res = kcalloc(4, sizeof(struct resource), GFP_KERNEL);
-
+        adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
         if (adev->acp.acp_res == NULL) {
                 kfree(adev->acp.acp_cell);
                 return -ENOMEM;
         }
 
-        i2s_pdata = kcalloc(2, sizeof(struct i2s_platform_data), GFP_KERNEL);
+        i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
         if (i2s_pdata == NULL) {
                 kfree(adev->acp.acp_res);
                 kfree(adev->acp.acp_cell);
@@ -358,6 +361,20 @@ static int acp_hw_init(void *handle)
         i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
         i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
 
+        i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+        switch (adev->asic_type) {
+        case CHIP_STONEY:
+                i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+                break;
+        default:
+                break;
+        }
+
+        i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
+        i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
+        i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
+        i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
+
         adev->acp.acp_res[0].name = "acp2x_dma";
         adev->acp.acp_res[0].flags = IORESOURCE_MEM;
         adev->acp.acp_res[0].start = acp_base;
@@ -373,13 +390,18 @@ static int acp_hw_init(void *handle)
         adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
         adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
 
-        adev->acp.acp_res[3].name = "acp2x_dma_irq";
-        adev->acp.acp_res[3].flags = IORESOURCE_IRQ;
-        adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);
-        adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;
+        adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
+        adev->acp.acp_res[3].flags = IORESOURCE_MEM;
+        adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
+        adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
+
+        adev->acp.acp_res[4].name = "acp2x_dma_irq";
+        adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
+        adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
+        adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
 
         adev->acp.acp_cell[0].name = "acp_audio_dma";
-        adev->acp.acp_cell[0].num_resources = 4;
+        adev->acp.acp_cell[0].num_resources = 5;
         adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
         adev->acp.acp_cell[0].platform_data = &adev->asic_type;
         adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
@@ -396,6 +418,12 @@ static int acp_hw_init(void *handle)
         adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
         adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
 
+        adev->acp.acp_cell[3].name = "designware-i2s";
+        adev->acp.acp_cell[3].num_resources = 1;
+        adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
+        adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
+        adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
+
         r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
                                                                 ACP_DEVS);
         if (r)
@@ -451,7 +479,6 @@ static int acp_hw_init(void *handle)
         val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
         val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
         cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index b33f1680c9a3..a028661d9e20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -575,6 +575,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
         { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 13acef526c5b..e839470880d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2843,6 +2843,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
         if (r)
                 return r;
 
+        /* Make sure IB tests flushed */
+        flush_delayed_work(&adev->late_init_work);
+
         /* blat the mode back in */
         if (fbcon) {
                 if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 9f0a217603ad..516795342dd2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -74,4 +74,3 @@ bool dm_read_persistent_data(struct dc_context *ctx,
 
 /**** power component interfaces ****/
 
-
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9d901ca70588..af9386ee5a93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1781,12 +1781,10 @@ static void dp_test_send_link_training(struct dc_link *link)
         dp_retrain_link_dp_test(link, &link_settings, false);
 }
 
-/* TODO hbr2 compliance eye output is unstable
+/* TODO Raven hbr2 compliance eye output is unstable
  * (toggling on and off) with debugger break
  * This caueses intermittent PHY automation failure
  * Need to look into the root cause */
-static uint8_t force_tps4_for_cp2520 = 1;
-
 static void dp_test_send_phy_test_pattern(struct dc_link *link)
 {
         union phy_test_pattern dpcd_test_pattern;
@@ -1846,13 +1844,13 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
                 break;
         case PHY_TEST_PATTERN_CP2520_1:
                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
-                test_pattern = (force_tps4_for_cp2520 == 1) ?
+                test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
                 break;
         case PHY_TEST_PATTERN_CP2520_2:
                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
-                test_pattern = (force_tps4_for_cp2520 == 1) ?
+                test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
                 break;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7515c0dcbdd2..b91f14989aef 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -77,6 +77,7 @@ struct dc_caps {
         bool is_apu;
         bool dual_link_dvi;
         bool post_blend_color_processing;
+        bool force_dp_tps4_for_cp2520;
 };
 
 struct dc_dcc_surface_param {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index cd8c22839227..c39934f8677f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1127,6 +1127,8 @@ static bool construct(
         dc->caps.max_slave_planes = 1;
         dc->caps.is_apu = true;
         dc->caps.post_blend_color_processing = false;
+        /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
+        dc->caps.force_dp_tps4_for_cp2520 = true;
 
         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
                 dc->debug = debug_defaults_drv;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index f4f366b26fd1..cb3a5b1737c8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@ -226,6 +226,8 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
 
         ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
 
+        ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
+
         return 0;
 }