Merge drm/drm-next into drm-misc-next

Backmerging 5.2-rc1 to -misc-next for robher

Signed-off-by: Sean Paul <seanpaul@chromium.org>

19 files changed, 166 insertions, 52 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 4376b17ca594..56f8ca2a3bb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -464,8 +464,7 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
                         }
                 }
                 if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
-                        if ((adev->flags & AMD_IS_PX) &&
-                            amdgpu_atpx_dgpu_req_power_for_displays()) {
+                        if (adev->flags & AMD_IS_PX) {
                                 pm_runtime_get_sync(adev->ddev->dev);
                                 /* Just fire off a uevent and let userspace tell us what to do */
                                 drm_helper_hpd_irq_event(adev->ddev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9371ec5e04f..9f282e971197 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3184,6 +3184,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
 
                 /* No need to recover an evicted BO */
                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
+                    shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
                         continue;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 3e6823fdd939..58ed401c5996 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -256,14 +256,14 @@ static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn,
         /* TODO we should be able to split locking for interval tree and
          * amdgpu_mn_invalidate_node
          */
-        if (amdgpu_mn_read_lock(amn, range->blockable))
+        if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range)))
                 return -EAGAIN;
 
         it = interval_tree_iter_first(&amn->objects, range->start, end);
         while (it) {
                 struct amdgpu_mn_node *node;
 
-                if (!range->blockable) {
+                if (!mmu_notifier_range_blockable(range)) {
                         amdgpu_mn_read_unlock(amn);
                         return -EAGAIN;
                 }
@@ -299,7 +299,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn,
         /* notification is exclusive, but interval is inclusive */
         end = range->end - 1;
 
-        if (amdgpu_mn_read_lock(amn, range->blockable))
+        if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range)))
                 return -EAGAIN;
 
         it = interval_tree_iter_first(&amn->objects, range->start, end);
@@ -307,7 +307,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn,
                 struct amdgpu_mn_node *node;
                 struct amdgpu_bo *bo;
 
-                if (!range->blockable) {
+                if (!mmu_notifier_range_blockable(range)) {
                         amdgpu_mn_read_unlock(amn);
                         return -EAGAIN;
                 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 95144e49c7f9..34471dbaa872 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -342,6 +342,16 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
         if (current_level == level)
                 return count;
 
+        /* profile_exit setting is valid only when current mode is in profile mode */
+        if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
+            AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
+            AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
+            AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
+            (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
+                pr_err("Currently not in any profile mode!\n");
+                return -EINVAL;
+        }
+
         if (is_support_sw_smu(adev)) {
                 mutex_lock(&adev->pm.mutex);
                 if (adev->pm.dpm.thermal_active) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 905cce1814f3..05897b05766b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -38,18 +38,10 @@ static void psp_set_funcs(struct amdgpu_device *adev);
 static int psp_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        struct psp_context *psp = &adev->psp;
 
         psp_set_funcs(adev);
 
-        return 0;
-}
-
-static int psp_sw_init(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct psp_context *psp = &adev->psp;
-        int ret;
-
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
@@ -67,6 +59,15 @@ static int psp_sw_init(void *handle)
 
         psp->adev = adev;
 
+        return 0;
+}
+
+static int psp_sw_init(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        struct psp_context *psp = &adev->psp;
+        int ret;
+
         ret = psp_init_microcode(psp);
         if (ret) {
                 DRM_ERROR("Failed to load psp firmware!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index 0767a93e4d91..639297250c21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -53,26 +53,25 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
                                                   int fd,
                                                   enum drm_sched_priority priority)
 {
-        struct file *filp = fget(fd);
+        struct fd f = fdget(fd);
         struct amdgpu_fpriv *fpriv;
         struct amdgpu_ctx *ctx;
         uint32_t id;
         int r;
 
-        if (!filp)
+        if (!f.file)
                 return -EINVAL;
 
-        r = amdgpu_file_to_fpriv(filp, &fpriv);
+        r = amdgpu_file_to_fpriv(f.file, &fpriv);
         if (r) {
-                fput(filp);
+                fdput(f);
                 return r;
         }
 
         idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
                 amdgpu_ctx_priority_override(ctx, priority);
 
-        fput(filp);
-
+        fdput(f);
         return 0;
 }
 
@@ -81,30 +80,30 @@ static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev,
                                                   unsigned ctx_id,
                                                   enum drm_sched_priority priority)
 {
-        struct file *filp = fget(fd);
+        struct fd f = fdget(fd);
         struct amdgpu_fpriv *fpriv;
         struct amdgpu_ctx *ctx;
         int r;
 
-        if (!filp)
+        if (!f.file)
                 return -EINVAL;
 
-        r = amdgpu_file_to_fpriv(filp, &fpriv);
+        r = amdgpu_file_to_fpriv(f.file, &fpriv);
         if (r) {
-                fput(filp);
+                fdput(f);
                 return r;
         }
 
         ctx = amdgpu_ctx_get(fpriv, ctx_id);
 
         if (!ctx) {
-                fput(filp);
+                fdput(f);
                 return -EINVAL;
         }
 
         amdgpu_ctx_priority_override(ctx, priority);
         amdgpu_ctx_put(ctx);
-        fput(filp);
+        fdput(f);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a07c85815b7a..4f10f5aba00b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2757,6 +2757,37 @@ error_free_sched_entity:
 }
 
 /**
+ * amdgpu_vm_check_clean_reserved - check if a VM is clean
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: the VM to check
+ *
+ * check all entries of the root PD, if any subsequent PDs are allocated,
+ * it means there are page table creating and filling, and is no a clean
+ * VM
+ *
+ * Returns:
+ *      0 if this VM is clean
+ */
+static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
+        struct amdgpu_vm *vm)
+{
+        enum amdgpu_vm_level root = adev->vm_manager.root_level;
+        unsigned int entries = amdgpu_vm_num_entries(adev, root);
+        unsigned int i = 0;
+
+        if (!(vm->root.entries))
+                return 0;
+
+        for (i = 0; i < entries; i++) {
+                if (vm->root.entries[i].base.bo)
+                        return -EINVAL;
+        }
+
+        return 0;
+}
+
+/**
  * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
  *
  * @adev: amdgpu_device pointer
@@ -2786,10 +2817,9 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, uns
                 return r;
 
         /* Sanity checks */
-        if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
-                r = -EINVAL;
+        r = amdgpu_vm_check_clean_reserved(adev, vm);
+        if (r)
                 goto unreserve_bo;
-        }
 
         if (pasid) {
                 unsigned long flags;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 1741056e6af6..41a9a5779623 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -182,6 +182,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
         }
+        WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 
         tmp = mmVM_L2_CNTL4_DEFAULT;
         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 8dbad496b29f..2471e7cf75ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -372,6 +372,9 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
                 if (amdgpu_sriov_runtime(adev))
                         schedule_work(&adev->virt.flr_work);
                 break;
+                case IDH_QUERY_ALIVE:
+                        xgpu_ai_mailbox_send_ack(adev);
+                        break;
                 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
                  * it byfar since that polling thread will handle it,
                  * other msg like flr complete is not handled here.
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
index 39d151b79153..077e91a33d62 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
@@ -49,6 +49,7 @@ enum idh_event {
         IDH_FLR_NOTIFICATION_CMPL,
         IDH_SUCCESS,
         IDH_FAIL,
+        IDH_QUERY_ALIVE,
         IDH_EVENT_MAX
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index dc461df48da0..2191d3d0a219 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -787,10 +787,13 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
                                                            0xFFFFFFFF, 0x00000004);
                         /* mc resume*/
                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-                                                            lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
-                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-                                                            upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
+                                                        mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+                                                        adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo);
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
+                                                        mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+                                                        adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi);
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
                                 offset = 0;
                         } else {
                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
@@ -798,10 +801,11 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
                                 offset = size;
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
+                                                        AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+
                         }
 
-                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
-                                                    AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index f3f5938430d4..c0ec27991c22 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -244,13 +244,18 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
 
+                offset = AMDGPU_VCE_FIRMWARE_OFFSET;
                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+                        uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;
+                        uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi;
+                        uint64_t tmr_mc_addr = (uint64_t)(hi) << 32 | low;
+
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
-                                                mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
-                                                adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+                                                mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), tmr_mc_addr >> 8);
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
                                                 mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
-                                                (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
+                                                (tmr_mc_addr >> 40) & 0xff);
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
                 } else {
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
                                                 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
@@ -258,6 +263,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
                                                 mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
                                                 (adev->vce.gpu_addr >> 40) & 0xff);
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
+                                                offset & ~0x0f000000);
+
                 }
                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
                                                 mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
@@ -272,10 +280,7 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
                                                 mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
                                                 (adev->vce.gpu_addr >> 40) & 0xff);
 
-                offset = AMDGPU_VCE_FIRMWARE_OFFSET;
                 size = VCE_V4_0_FW_SIZE;
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
-                                        offset & ~0x0f000000);
                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
 
                 offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 1b2f69a9a24e..8d89ab7f0ae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -31,7 +31,7 @@
 #include "soc15_common.h"
 #include "vega10_ih.h"
 
-
+#define MAX_REARM_RETRY 10
 
 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
 
@@ -382,6 +382,38 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
 }
 
 /**
+ * vega10_ih_irq_rearm - rearm IRQ if lost
+ *
+ * @adev: amdgpu_device pointer
+ *
+ */
+static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
+                               struct amdgpu_ih_ring *ih)
+{
+        uint32_t reg_rptr = 0;
+        uint32_t v = 0;
+        uint32_t i = 0;
+
+        if (ih == &adev->irq.ih)
+                reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
+        else if (ih == &adev->irq.ih1)
+                reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
+        else if (ih == &adev->irq.ih2)
+                reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
+        else
+                return;
+
+        /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
+        for (i = 0; i < MAX_REARM_RETRY; i++) {
+                v = RREG32_NO_KIQ(reg_rptr);
+                if ((v < ih->ring_size) && (v != ih->rptr))
+                        WDOORBELL32(ih->doorbell_index, ih->rptr);
+                else
+                        break;
+        }
+}
+
+/**
  * vega10_ih_set_rptr - set the IH ring buffer rptr
  *
  * @adev: amdgpu_device pointer
@@ -395,6 +427,9 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
                 /* XXX check if swapping is necessary on BE */
                 *ih->rptr_cpu = ih->rptr;
                 WDOORBELL32(ih->doorbell_index, ih->rptr);
+
+                if (amdgpu_sriov_vf(adev))
+                        vega10_ih_irq_rearm(adev, ih);
         } else if (ih == &adev->irq.ih) {
                 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
         } else if (ih == &adev->irq.ih1) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 2cb09e088dce..769dbc7be8cb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1272,8 +1272,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 
         dev->node_props.vendor_id = gpu->pdev->vendor;
         dev->node_props.device_id = gpu->pdev->device;
-        dev->node_props.location_id = PCI_DEVID(gpu->pdev->bus->number,
-                gpu->pdev->devfn);
+        dev->node_props.location_id = pci_dev_id(gpu->pdev);
         dev->node_props.max_engine_clk_fcompute =
                 amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
         dev->node_props.max_engine_clk_ccompute =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1854506e3e8f..995f9df66142 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5242,7 +5242,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                     struct drm_crtc *pcrtc,
                                     bool wait_for_vblank)
 {
-        uint32_t i, r;
+        uint32_t i;
         uint64_t timestamp_ns;
         struct drm_plane *plane;
         struct drm_plane_state *old_plane_state, *new_plane_state;
@@ -5253,6 +5253,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
         struct dm_crtc_state *dm_old_crtc_state =
                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
         int planes_count = 0, vpos, hpos;
+        long r;
         unsigned long flags;
         struct amdgpu_bo *abo;
         uint64_t tiling_flags;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dda10b1f8574..18c775a950cc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1464,6 +1464,11 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
                 return UPDATE_TYPE_FULL;
         }
 
+        if (u->surface->force_full_update) {
+                update_flags->bits.full_update = 1;
+                return UPDATE_TYPE_FULL;
+        }
+
         type = get_plane_info_update_type(u);
         elevate_update_type(&overall_type, type);
 
@@ -1900,6 +1905,14 @@ void dc_commit_updates_for_stream(struct dc *dc,
                 }
 
                 dc_resource_state_copy_construct(state, context);
+
+                for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                        struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
+                        struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+                        if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
+                                new_pipe->plane_state->force_full_update = true;
+                }
         }
 
 
@@ -1936,6 +1949,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
                 dc->current_state = context;
                 dc_release_state(old);
 
+                for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+                        if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
+                                pipe_ctx->plane_state->force_full_update = false;
+                }
         }
         /*let's use current_state to update watermark etc*/
         if (update_type >= UPDATE_TYPE_FULL)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 70edd9ea5afe..44e4b0465587 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -612,6 +612,9 @@ struct dc_plane_state {
         struct dc_plane_status status;
         struct dc_context *ctx;
 
+        /* HACK: Workaround for forcing full reprogramming under some conditions */
+        bool force_full_update;
+
         /* private to dc_surface.c */
         enum dc_irq_source irq_source;
         struct kref refcount;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 937b5cffd7ef..bd33c47183fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -190,6 +190,12 @@ static void submit_channel_request(
                                 AUXP_IMPCAL_OVERRIDE_ENABLE, 1,
                                 AUXP_IMPCAL_OVERRIDE_ENABLE, 0);
         }
+
+        REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
+
+        REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
+                                10, aux110->timeout_period/10);
+
         /* set the delay and the number of bytes to write */
 
         /* The length include
@@ -242,9 +248,6 @@ static void submit_channel_request(
                 }
         }
 
-        REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
-        REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
-                                10, aux110->timeout_period/10);
         REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index aab5f0c34584..ce6a26d189b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -71,11 +71,11 @@ enum {	/* This is the timeout as defined in DP 1.2a,
          * at most within ~240usec. That means,
          * increasing this timeout will not affect normal operation,
          * and we'll timeout after
-         * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
+         * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec.
          * This timeout is especially important for
-         * resume from S3 and CTS.
+         * converters, resume from S3, and CTS.
          */
-        SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
+        SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6
 };
 
 struct dce_aux {