diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2019-04-11 15:54:40 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-04-12 12:24:16 -0400 |
| commit | 1925e7d3d4677e681cc2e878c2bdbeaee988c8e2 (patch) | |
| tree | b7c9a2ac4a2f4eacd5e215e2424e82e3c6c5be31 /drivers/gpu/drm/amd | |
| parent | b575f10dbd6f84c2c8744ff1f486bfae1e4f6f38 (diff) | |
drm/amdgpu/gmc9: fix VM_L2_CNTL3 programming
Got accidently dropped when 2+1 level support was added.
Fixes: 6a42fd6fbf534096 ("drm/amdgpu: implement 2+1 PD support for Raven v3")
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index d0d966d6080a..1696644ec022 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | |||
| @@ -182,6 +182,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) | |||
| 182 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, | 182 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, |
| 183 | L2_CACHE_BIGK_FRAGMENT_SIZE, 6); | 183 | L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
| 184 | } | 184 | } |
| 185 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); | ||
| 185 | 186 | ||
| 186 | tmp = mmVM_L2_CNTL4_DEFAULT; | 187 | tmp = mmVM_L2_CNTL4_DEFAULT; |
| 187 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); | 188 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); |