diff options
author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2017-08-23 15:44:42 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:17:07 -0400 |
commit | 156590454259a19d1709fab2ff7d59870574e822 (patch) | |
tree | 0e2a6dfa0667c2d1a4914a6f4048f85c59f0bae8 /drivers/gpu/drm/amd | |
parent | 9635b75436e5f536831c810c715f3ae24a5bbbae (diff) |
drm/amd/display: Clean up flattening core_dc to dc
Clean up some code related to flattening core_dc commit
(Remove redundent dc = dc, which was the result of removing
DC_TO_CORE() macro)
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 335 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 19 |
3 files changed, 164 insertions, 202 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index afd403ceb2a7..5e5766a63a47 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | |||
@@ -983,15 +983,14 @@ bool dcn_validate_bandwidth( | |||
983 | if (v->voltage_level == 0 && | 983 | if (v->voltage_level == 0 && |
984 | (dc->debug.sr_exit_time_dpm0_ns | 984 | (dc->debug.sr_exit_time_dpm0_ns |
985 | || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { | 985 | || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { |
986 | struct dc *dc_core = dc; | ||
987 | 986 | ||
988 | if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) | 987 | if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) |
989 | v->sr_enter_plus_exit_time = | 988 | v->sr_enter_plus_exit_time = |
990 | dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; | 989 | dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; |
991 | if (dc->debug.sr_exit_time_dpm0_ns) | 990 | if (dc->debug.sr_exit_time_dpm0_ns) |
992 | v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; | 991 | v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; |
993 | dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; | 992 | dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; |
994 | dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; | 993 | dc->dml.soc.sr_exit_time_us = v->sr_exit_time; |
995 | mode_support_and_system_configuration(v); | 994 | mode_support_and_system_configuration(v); |
996 | } | 995 | } |
997 | 996 | ||
@@ -1114,11 +1113,10 @@ bool dcn_validate_bandwidth( | |||
1114 | } | 1113 | } |
1115 | 1114 | ||
1116 | if (v->voltage_level == 0) { | 1115 | if (v->voltage_level == 0) { |
1117 | struct dc *dc_core = dc; | ||
1118 | 1116 | ||
1119 | dc_core->dml.soc.sr_enter_plus_exit_time_us = | 1117 | dc->dml.soc.sr_enter_plus_exit_time_us = |
1120 | dc_core->dcn_soc->sr_enter_plus_exit_time; | 1118 | dc->dcn_soc->sr_enter_plus_exit_time; |
1121 | dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc->sr_exit_time; | 1119 | dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; |
1122 | } | 1120 | } |
1123 | 1121 | ||
1124 | /* | 1122 | /* |
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 79980cb0900c..dc1b7d061be2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c | |||
@@ -155,20 +155,19 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, | |||
155 | int vmin, int vmax) | 155 | int vmin, int vmax) |
156 | { | 156 | { |
157 | /* TODO: Support multiple streams */ | 157 | /* TODO: Support multiple streams */ |
158 | struct dc *core_dc = dc; | ||
159 | struct dc_stream_state *stream = streams[0]; | 158 | struct dc_stream_state *stream = streams[0]; |
160 | int i = 0; | 159 | int i = 0; |
161 | bool ret = false; | 160 | bool ret = false; |
162 | 161 | ||
163 | for (i = 0; i < MAX_PIPES; i++) { | 162 | for (i = 0; i < MAX_PIPES; i++) { |
164 | struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; | 163 | struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; |
165 | 164 | ||
166 | if (pipe->stream == stream && pipe->stream_res.stream_enc) { | 165 | if (pipe->stream == stream && pipe->stream_res.stream_enc) { |
167 | core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); | 166 | dc->hwss.set_drr(&pipe, 1, vmin, vmax); |
168 | 167 | ||
169 | /* build and update the info frame */ | 168 | /* build and update the info frame */ |
170 | resource_build_info_frame(pipe); | 169 | resource_build_info_frame(pipe); |
171 | core_dc->hwss.update_info_frame(pipe); | 170 | dc->hwss.update_info_frame(pipe); |
172 | 171 | ||
173 | ret = true; | 172 | ret = true; |
174 | } | 173 | } |
@@ -181,7 +180,6 @@ static bool stream_get_crtc_position(struct dc *dc, | |||
181 | unsigned int *v_pos, unsigned int *nom_v_pos) | 180 | unsigned int *v_pos, unsigned int *nom_v_pos) |
182 | { | 181 | { |
183 | /* TODO: Support multiple streams */ | 182 | /* TODO: Support multiple streams */ |
184 | struct dc *core_dc = dc; | ||
185 | struct dc_stream_state *stream = streams[0]; | 183 | struct dc_stream_state *stream = streams[0]; |
186 | int i = 0; | 184 | int i = 0; |
187 | bool ret = false; | 185 | bool ret = false; |
@@ -189,10 +187,10 @@ static bool stream_get_crtc_position(struct dc *dc, | |||
189 | 187 | ||
190 | for (i = 0; i < MAX_PIPES; i++) { | 188 | for (i = 0; i < MAX_PIPES; i++) { |
191 | struct pipe_ctx *pipe = | 189 | struct pipe_ctx *pipe = |
192 | &core_dc->current_context->res_ctx.pipe_ctx[i]; | 190 | &dc->current_context->res_ctx.pipe_ctx[i]; |
193 | 191 | ||
194 | if (pipe->stream == stream && pipe->stream_res.stream_enc) { | 192 | if (pipe->stream == stream && pipe->stream_res.stream_enc) { |
195 | core_dc->hwss.get_position(&pipe, 1, &position); | 193 | dc->hwss.get_position(&pipe, 1, &position); |
196 | 194 | ||
197 | *v_pos = position.vertical_count; | 195 | *v_pos = position.vertical_count; |
198 | *nom_v_pos = position.nominal_vcount; | 196 | *nom_v_pos = position.nominal_vcount; |
@@ -204,15 +202,14 @@ static bool stream_get_crtc_position(struct dc *dc, | |||
204 | 202 | ||
205 | static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) | 203 | static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) |
206 | { | 204 | { |
207 | struct dc *core_dc = dc; | ||
208 | int i = 0; | 205 | int i = 0; |
209 | bool ret = false; | 206 | bool ret = false; |
210 | struct pipe_ctx *pipes; | 207 | struct pipe_ctx *pipes; |
211 | 208 | ||
212 | for (i = 0; i < MAX_PIPES; i++) { | 209 | for (i = 0; i < MAX_PIPES; i++) { |
213 | if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { | 210 | if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { |
214 | pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; | 211 | pipes = &dc->current_context->res_ctx.pipe_ctx[i]; |
215 | core_dc->hwss.program_gamut_remap(pipes); | 212 | dc->hwss.program_gamut_remap(pipes); |
216 | ret = true; | 213 | ret = true; |
217 | } | 214 | } |
218 | } | 215 | } |
@@ -222,17 +219,16 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) | |||
222 | 219 | ||
223 | static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) | 220 | static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) |
224 | { | 221 | { |
225 | struct dc *core_dc = dc; | ||
226 | int i = 0; | 222 | int i = 0; |
227 | bool ret = false; | 223 | bool ret = false; |
228 | struct pipe_ctx *pipes; | 224 | struct pipe_ctx *pipes; |
229 | 225 | ||
230 | for (i = 0; i < MAX_PIPES; i++) { | 226 | for (i = 0; i < MAX_PIPES; i++) { |
231 | if (core_dc->current_context->res_ctx.pipe_ctx[i].stream | 227 | if (dc->current_context->res_ctx.pipe_ctx[i].stream |
232 | == stream) { | 228 | == stream) { |
233 | 229 | ||
234 | pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; | 230 | pipes = &dc->current_context->res_ctx.pipe_ctx[i]; |
235 | core_dc->hwss.program_csc_matrix(pipes, | 231 | dc->hwss.program_csc_matrix(pipes, |
236 | stream->output_color_space, | 232 | stream->output_color_space, |
237 | stream->csc_color_matrix.matrix); | 233 | stream->csc_color_matrix.matrix); |
238 | ret = true; | 234 | ret = true; |
@@ -247,7 +243,6 @@ static void set_static_screen_events(struct dc *dc, | |||
247 | int num_streams, | 243 | int num_streams, |
248 | const struct dc_static_screen_events *events) | 244 | const struct dc_static_screen_events *events) |
249 | { | 245 | { |
250 | struct dc *core_dc = dc; | ||
251 | int i = 0; | 246 | int i = 0; |
252 | int j = 0; | 247 | int j = 0; |
253 | struct pipe_ctx *pipes_affected[MAX_PIPES]; | 248 | struct pipe_ctx *pipes_affected[MAX_PIPES]; |
@@ -257,45 +252,44 @@ static void set_static_screen_events(struct dc *dc, | |||
257 | struct dc_stream_state *stream = streams[i]; | 252 | struct dc_stream_state *stream = streams[i]; |
258 | 253 | ||
259 | for (j = 0; j < MAX_PIPES; j++) { | 254 | for (j = 0; j < MAX_PIPES; j++) { |
260 | if (core_dc->current_context->res_ctx.pipe_ctx[j].stream | 255 | if (dc->current_context->res_ctx.pipe_ctx[j].stream |
261 | == stream) { | 256 | == stream) { |
262 | pipes_affected[num_pipes_affected++] = | 257 | pipes_affected[num_pipes_affected++] = |
263 | &core_dc->current_context->res_ctx.pipe_ctx[j]; | 258 | &dc->current_context->res_ctx.pipe_ctx[j]; |
264 | } | 259 | } |
265 | } | 260 | } |
266 | } | 261 | } |
267 | 262 | ||
268 | core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); | 263 | dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); |
269 | } | 264 | } |
270 | 265 | ||
271 | static void set_drive_settings(struct dc *dc, | 266 | static void set_drive_settings(struct dc *dc, |
272 | struct link_training_settings *lt_settings, | 267 | struct link_training_settings *lt_settings, |
273 | const struct dc_link *link) | 268 | const struct dc_link *link) |
274 | { | 269 | { |
275 | struct dc *core_dc = dc; | 270 | |
276 | int i; | 271 | int i; |
277 | 272 | ||
278 | for (i = 0; i < core_dc->link_count; i++) { | 273 | for (i = 0; i < dc->link_count; i++) { |
279 | if (core_dc->links[i] == link) | 274 | if (dc->links[i] == link) |
280 | break; | 275 | break; |
281 | } | 276 | } |
282 | 277 | ||
283 | if (i >= core_dc->link_count) | 278 | if (i >= dc->link_count) |
284 | ASSERT_CRITICAL(false); | 279 | ASSERT_CRITICAL(false); |
285 | 280 | ||
286 | dc_link_dp_set_drive_settings(core_dc->links[i], lt_settings); | 281 | dc_link_dp_set_drive_settings(dc->links[i], lt_settings); |
287 | } | 282 | } |
288 | 283 | ||
289 | static void perform_link_training(struct dc *dc, | 284 | static void perform_link_training(struct dc *dc, |
290 | struct dc_link_settings *link_setting, | 285 | struct dc_link_settings *link_setting, |
291 | bool skip_video_pattern) | 286 | bool skip_video_pattern) |
292 | { | 287 | { |
293 | struct dc *core_dc = dc; | ||
294 | int i; | 288 | int i; |
295 | 289 | ||
296 | for (i = 0; i < core_dc->link_count; i++) | 290 | for (i = 0; i < dc->link_count; i++) |
297 | dc_link_dp_perform_link_training( | 291 | dc_link_dp_perform_link_training( |
298 | core_dc->links[i], | 292 | dc->links[i], |
299 | link_setting, | 293 | link_setting, |
300 | skip_video_pattern); | 294 | skip_video_pattern); |
301 | } | 295 | } |
@@ -371,44 +365,44 @@ void set_dither_option(struct dc_stream_state *stream, | |||
371 | opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); | 365 | opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); |
372 | } | 366 | } |
373 | 367 | ||
374 | static void allocate_dc_stream_funcs(struct dc *core_dc) | 368 | static void allocate_dc_stream_funcs(struct dc *dc) |
375 | { | 369 | { |
376 | if (core_dc->hwss.set_drr != NULL) { | 370 | if (dc->hwss.set_drr != NULL) { |
377 | core_dc->stream_funcs.adjust_vmin_vmax = | 371 | dc->stream_funcs.adjust_vmin_vmax = |
378 | stream_adjust_vmin_vmax; | 372 | stream_adjust_vmin_vmax; |
379 | } | 373 | } |
380 | 374 | ||
381 | core_dc->stream_funcs.set_static_screen_events = | 375 | dc->stream_funcs.set_static_screen_events = |
382 | set_static_screen_events; | 376 | set_static_screen_events; |
383 | 377 | ||
384 | core_dc->stream_funcs.get_crtc_position = | 378 | dc->stream_funcs.get_crtc_position = |
385 | stream_get_crtc_position; | 379 | stream_get_crtc_position; |
386 | 380 | ||
387 | core_dc->stream_funcs.set_gamut_remap = | 381 | dc->stream_funcs.set_gamut_remap = |
388 | set_gamut_remap; | 382 | set_gamut_remap; |
389 | 383 | ||
390 | core_dc->stream_funcs.program_csc_matrix = | 384 | dc->stream_funcs.program_csc_matrix = |
391 | program_csc_matrix; | 385 | program_csc_matrix; |
392 | 386 | ||
393 | core_dc->stream_funcs.set_dither_option = | 387 | dc->stream_funcs.set_dither_option = |
394 | set_dither_option; | 388 | set_dither_option; |
395 | 389 | ||
396 | core_dc->link_funcs.set_drive_settings = | 390 | dc->link_funcs.set_drive_settings = |
397 | set_drive_settings; | 391 | set_drive_settings; |
398 | 392 | ||
399 | core_dc->link_funcs.perform_link_training = | 393 | dc->link_funcs.perform_link_training = |
400 | perform_link_training; | 394 | perform_link_training; |
401 | 395 | ||
402 | core_dc->link_funcs.set_preferred_link_settings = | 396 | dc->link_funcs.set_preferred_link_settings = |
403 | set_preferred_link_settings; | 397 | set_preferred_link_settings; |
404 | 398 | ||
405 | core_dc->link_funcs.enable_hpd = | 399 | dc->link_funcs.enable_hpd = |
406 | enable_hpd; | 400 | enable_hpd; |
407 | 401 | ||
408 | core_dc->link_funcs.disable_hpd = | 402 | dc->link_funcs.disable_hpd = |
409 | disable_hpd; | 403 | disable_hpd; |
410 | 404 | ||
411 | core_dc->link_funcs.set_test_pattern = | 405 | dc->link_funcs.set_test_pattern = |
412 | set_test_pattern; | 406 | set_test_pattern; |
413 | } | 407 | } |
414 | 408 | ||
@@ -622,41 +616,41 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) | |||
622 | 616 | ||
623 | struct dc *dc_create(const struct dc_init_data *init_params) | 617 | struct dc *dc_create(const struct dc_init_data *init_params) |
624 | { | 618 | { |
625 | struct dc *core_dc = dm_alloc(sizeof(*core_dc)); | 619 | struct dc *dc = dm_alloc(sizeof(*dc)); |
626 | unsigned int full_pipe_count; | 620 | unsigned int full_pipe_count; |
627 | 621 | ||
628 | if (NULL == core_dc) | 622 | if (NULL == dc) |
629 | goto alloc_fail; | 623 | goto alloc_fail; |
630 | 624 | ||
631 | if (false == construct(core_dc, init_params)) | 625 | if (false == construct(dc, init_params)) |
632 | goto construct_fail; | 626 | goto construct_fail; |
633 | 627 | ||
634 | /*TODO: separate HW and SW initialization*/ | 628 | /*TODO: separate HW and SW initialization*/ |
635 | core_dc->hwss.init_hw(core_dc); | 629 | dc->hwss.init_hw(dc); |
636 | 630 | ||
637 | full_pipe_count = core_dc->res_pool->pipe_count; | 631 | full_pipe_count = dc->res_pool->pipe_count; |
638 | if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) | 632 | if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) |
639 | full_pipe_count--; | 633 | full_pipe_count--; |
640 | core_dc->caps.max_streams = min( | 634 | dc->caps.max_streams = min( |
641 | full_pipe_count, | 635 | full_pipe_count, |
642 | core_dc->res_pool->stream_enc_count); | 636 | dc->res_pool->stream_enc_count); |
643 | 637 | ||
644 | core_dc->caps.max_links = core_dc->link_count; | 638 | dc->caps.max_links = dc->link_count; |
645 | core_dc->caps.max_audios = core_dc->res_pool->audio_count; | 639 | dc->caps.max_audios = dc->res_pool->audio_count; |
646 | 640 | ||
647 | core_dc->config = init_params->flags; | 641 | dc->config = init_params->flags; |
648 | 642 | ||
649 | dm_logger_write(core_dc->ctx->logger, LOG_DC, | 643 | dm_logger_write(dc->ctx->logger, LOG_DC, |
650 | "Display Core initialized\n"); | 644 | "Display Core initialized\n"); |
651 | 645 | ||
652 | 646 | ||
653 | /* TODO: missing feature to be enabled */ | 647 | /* TODO: missing feature to be enabled */ |
654 | core_dc->debug.disable_dfs_bypass = true; | 648 | dc->debug.disable_dfs_bypass = true; |
655 | 649 | ||
656 | return core_dc; | 650 | return dc; |
657 | 651 | ||
658 | construct_fail: | 652 | construct_fail: |
659 | dm_free(core_dc); | 653 | dm_free(dc); |
660 | 654 | ||
661 | alloc_fail: | 655 | alloc_fail: |
662 | return NULL; | 656 | return NULL; |
@@ -664,9 +658,8 @@ alloc_fail: | |||
664 | 658 | ||
665 | void dc_destroy(struct dc **dc) | 659 | void dc_destroy(struct dc **dc) |
666 | { | 660 | { |
667 | struct dc *core_dc = *dc; | 661 | destruct(*dc); |
668 | destruct(core_dc); | 662 | dm_free(*dc); |
669 | dm_free(core_dc); | ||
670 | *dc = NULL; | 663 | *dc = NULL; |
671 | } | 664 | } |
672 | 665 | ||
@@ -674,7 +667,6 @@ bool dc_validate_guaranteed( | |||
674 | struct dc *dc, | 667 | struct dc *dc, |
675 | struct dc_stream_state *stream) | 668 | struct dc_stream_state *stream) |
676 | { | 669 | { |
677 | struct dc *core_dc = dc; | ||
678 | enum dc_status result = DC_ERROR_UNEXPECTED; | 670 | enum dc_status result = DC_ERROR_UNEXPECTED; |
679 | struct validate_context *context; | 671 | struct validate_context *context; |
680 | 672 | ||
@@ -687,14 +679,14 @@ bool dc_validate_guaranteed( | |||
687 | 679 | ||
688 | atomic_inc(&context->ref_count); | 680 | atomic_inc(&context->ref_count); |
689 | 681 | ||
690 | result = core_dc->res_pool->funcs->validate_guaranteed( | 682 | result = dc->res_pool->funcs->validate_guaranteed( |
691 | core_dc, stream, context); | 683 | dc, stream, context); |
692 | 684 | ||
693 | dc_release_validate_context(context); | 685 | dc_release_validate_context(context); |
694 | 686 | ||
695 | context_alloc_fail: | 687 | context_alloc_fail: |
696 | if (result != DC_OK) { | 688 | if (result != DC_OK) { |
697 | dm_logger_write(core_dc->ctx->logger, LOG_WARNING, | 689 | dm_logger_write(dc->ctx->logger, LOG_WARNING, |
698 | "%s:guaranteed validation failed, dc_status:%d\n", | 690 | "%s:guaranteed validation failed, dc_status:%d\n", |
699 | __func__, | 691 | __func__, |
700 | result); | 692 | result); |
@@ -704,12 +696,12 @@ context_alloc_fail: | |||
704 | } | 696 | } |
705 | 697 | ||
706 | static void program_timing_sync( | 698 | static void program_timing_sync( |
707 | struct dc *core_dc, | 699 | struct dc *dc, |
708 | struct validate_context *ctx) | 700 | struct validate_context *ctx) |
709 | { | 701 | { |
710 | int i, j; | 702 | int i, j; |
711 | int group_index = 0; | 703 | int group_index = 0; |
712 | int pipe_count = core_dc->res_pool->pipe_count; | 704 | int pipe_count = dc->res_pool->pipe_count; |
713 | struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; | 705 | struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL }; |
714 | 706 | ||
715 | for (i = 0; i < pipe_count; i++) { | 707 | for (i = 0; i < pipe_count; i++) { |
@@ -770,8 +762,8 @@ static void program_timing_sync( | |||
770 | } | 762 | } |
771 | 763 | ||
772 | if (group_size > 1) { | 764 | if (group_size > 1) { |
773 | core_dc->hwss.enable_timing_synchronization( | 765 | dc->hwss.enable_timing_synchronization( |
774 | core_dc, group_index, group_size, pipe_set); | 766 | dc, group_index, group_size, pipe_set); |
775 | group_index++; | 767 | group_index++; |
776 | } | 768 | } |
777 | } | 769 | } |
@@ -803,17 +795,16 @@ bool dc_enable_stereo( | |||
803 | bool ret = true; | 795 | bool ret = true; |
804 | int i, j; | 796 | int i, j; |
805 | struct pipe_ctx *pipe; | 797 | struct pipe_ctx *pipe; |
806 | struct dc *core_dc = dc; | ||
807 | 798 | ||
808 | for (i = 0; i < MAX_PIPES; i++) { | 799 | for (i = 0; i < MAX_PIPES; i++) { |
809 | if (context != NULL) | 800 | if (context != NULL) |
810 | pipe = &context->res_ctx.pipe_ctx[i]; | 801 | pipe = &context->res_ctx.pipe_ctx[i]; |
811 | else | 802 | else |
812 | pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; | 803 | pipe = &dc->current_context->res_ctx.pipe_ctx[i]; |
813 | for (j = 0 ; pipe && j < stream_count; j++) { | 804 | for (j = 0 ; pipe && j < stream_count; j++) { |
814 | if (streams[j] && streams[j] == pipe->stream && | 805 | if (streams[j] && streams[j] == pipe->stream && |
815 | core_dc->hwss.setup_stereo) | 806 | dc->hwss.setup_stereo) |
816 | core_dc->hwss.setup_stereo(pipe, core_dc); | 807 | dc->hwss.setup_stereo(pipe, dc); |
817 | } | 808 | } |
818 | } | 809 | } |
819 | 810 | ||
@@ -827,8 +818,7 @@ bool dc_enable_stereo( | |||
827 | */ | 818 | */ |
828 | static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) | 819 | static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) |
829 | { | 820 | { |
830 | struct dc *core_dc = dc; | 821 | struct dc_bios *dcb = dc->ctx->dc_bios; |
831 | struct dc_bios *dcb = core_dc->ctx->dc_bios; | ||
832 | enum dc_status result = DC_ERROR_UNEXPECTED; | 822 | enum dc_status result = DC_ERROR_UNEXPECTED; |
833 | struct pipe_ctx *pipe; | 823 | struct pipe_ctx *pipe; |
834 | int i, j, k, l; | 824 | int i, j, k, l; |
@@ -838,22 +828,22 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c | |||
838 | dc_streams[i] = context->streams[i]; | 828 | dc_streams[i] = context->streams[i]; |
839 | 829 | ||
840 | if (!dcb->funcs->is_accelerated_mode(dcb)) | 830 | if (!dcb->funcs->is_accelerated_mode(dcb)) |
841 | core_dc->hwss.enable_accelerated_mode(core_dc); | 831 | dc->hwss.enable_accelerated_mode(dc); |
842 | 832 | ||
843 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) { | 833 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
844 | pipe = &context->res_ctx.pipe_ctx[i]; | 834 | pipe = &context->res_ctx.pipe_ctx[i]; |
845 | core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe); | 835 | dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); |
846 | } | 836 | } |
847 | result = core_dc->hwss.apply_ctx_to_hw(core_dc, context); | 837 | result = dc->hwss.apply_ctx_to_hw(dc, context); |
848 | 838 | ||
849 | program_timing_sync(core_dc, context); | 839 | program_timing_sync(dc, context); |
850 | 840 | ||
851 | for (i = 0; i < context->stream_count; i++) { | 841 | for (i = 0; i < context->stream_count; i++) { |
852 | const struct dc_sink *sink = context->streams[i]->sink; | 842 | const struct dc_sink *sink = context->streams[i]->sink; |
853 | 843 | ||
854 | for (j = 0; j < context->stream_status[i].plane_count; j++) { | 844 | for (j = 0; j < context->stream_status[i].plane_count; j++) { |
855 | core_dc->hwss.apply_ctx_for_surface( | 845 | dc->hwss.apply_ctx_for_surface( |
856 | core_dc, context->streams[i], | 846 | dc, context->streams[i], |
857 | context->stream_status[i].plane_count, | 847 | context->stream_status[i].plane_count, |
858 | context); | 848 | context); |
859 | 849 | ||
@@ -867,8 +857,8 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c | |||
867 | for (l = 0 ; pipe && l < context->stream_count; l++) { | 857 | for (l = 0 ; pipe && l < context->stream_count; l++) { |
868 | if (context->streams[l] && | 858 | if (context->streams[l] && |
869 | context->streams[l] == pipe->stream && | 859 | context->streams[l] == pipe->stream && |
870 | core_dc->hwss.setup_stereo) | 860 | dc->hwss.setup_stereo) |
871 | core_dc->hwss.setup_stereo(pipe, core_dc); | 861 | dc->hwss.setup_stereo(pipe, dc); |
872 | } | 862 | } |
873 | } | 863 | } |
874 | } | 864 | } |
@@ -883,11 +873,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c | |||
883 | 873 | ||
884 | dc_enable_stereo(dc, context, dc_streams, context->stream_count); | 874 | dc_enable_stereo(dc, context, dc_streams, context->stream_count); |
885 | 875 | ||
886 | dc_release_validate_context(core_dc->current_context); | 876 | dc_release_validate_context(dc->current_context); |
887 | 877 | ||
888 | core_dc->current_context = context; | 878 | dc->current_context = context; |
889 | 879 | ||
890 | dc_retain_validate_context(core_dc->current_context); | 880 | dc_retain_validate_context(dc->current_context); |
891 | 881 | ||
892 | return (result == DC_OK); | 882 | return (result == DC_OK); |
893 | } | 883 | } |
@@ -895,20 +885,19 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c | |||
895 | bool dc_commit_context(struct dc *dc, struct validate_context *context) | 885 | bool dc_commit_context(struct dc *dc, struct validate_context *context) |
896 | { | 886 | { |
897 | enum dc_status result = DC_ERROR_UNEXPECTED; | 887 | enum dc_status result = DC_ERROR_UNEXPECTED; |
898 | struct dc *core_dc = dc; | ||
899 | int i; | 888 | int i; |
900 | 889 | ||
901 | if (false == context_changed(core_dc, context)) | 890 | if (false == context_changed(dc, context)) |
902 | return DC_OK; | 891 | return DC_OK; |
903 | 892 | ||
904 | dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", | 893 | dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n", |
905 | __func__, context->stream_count); | 894 | __func__, context->stream_count); |
906 | 895 | ||
907 | for (i = 0; i < context->stream_count; i++) { | 896 | for (i = 0; i < context->stream_count; i++) { |
908 | struct dc_stream_state *stream = context->streams[i]; | 897 | struct dc_stream_state *stream = context->streams[i]; |
909 | 898 | ||
910 | dc_stream_log(stream, | 899 | dc_stream_log(stream, |
911 | core_dc->ctx->logger, | 900 | dc->ctx->logger, |
912 | LOG_DC); | 901 | LOG_DC); |
913 | } | 902 | } |
914 | 903 | ||
@@ -921,21 +910,20 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) | |||
921 | bool dc_post_update_surfaces_to_stream(struct dc *dc) | 910 | bool dc_post_update_surfaces_to_stream(struct dc *dc) |
922 | { | 911 | { |
923 | int i; | 912 | int i; |
924 | struct dc *core_dc = dc; | 913 | struct validate_context *context = dc->current_context; |
925 | struct validate_context *context = core_dc->current_context; | ||
926 | 914 | ||
927 | post_surface_trace(dc); | 915 | post_surface_trace(dc); |
928 | 916 | ||
929 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) | 917 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
930 | if (context->res_ctx.pipe_ctx[i].stream == NULL | 918 | if (context->res_ctx.pipe_ctx[i].stream == NULL |
931 | || context->res_ctx.pipe_ctx[i].plane_state == NULL) | 919 | || context->res_ctx.pipe_ctx[i].plane_state == NULL) |
932 | core_dc->hwss.power_down_front_end(core_dc, i); | 920 | dc->hwss.power_down_front_end(dc, i); |
933 | 921 | ||
934 | /* 3rd param should be true, temp w/a for RV*/ | 922 | /* 3rd param should be true, temp w/a for RV*/ |
935 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 923 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
936 | core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version < DCN_VERSION_1_0); | 924 | dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0); |
937 | #else | 925 | #else |
938 | core_dc->hwss.set_bandwidth(core_dc, context, true); | 926 | dc->hwss.set_bandwidth(dc, context, true); |
939 | #endif | 927 | #endif |
940 | return true; | 928 | return true; |
941 | } | 929 | } |
@@ -1184,7 +1172,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( | |||
1184 | struct dc_stream_update *stream_update, | 1172 | struct dc_stream_update *stream_update, |
1185 | const struct dc_stream_status *stream_status) | 1173 | const struct dc_stream_status *stream_status) |
1186 | { | 1174 | { |
1187 | struct dc *core_dc = dc; | ||
1188 | int i; | 1175 | int i; |
1189 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | 1176 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; |
1190 | 1177 | ||
@@ -1196,7 +1183,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( | |||
1196 | 1183 | ||
1197 | for (i = 0 ; i < surface_count; i++) { | 1184 | for (i = 0 ; i < surface_count; i++) { |
1198 | enum surface_update_type type = | 1185 | enum surface_update_type type = |
1199 | det_surface_update(core_dc, &updates[i], i); | 1186 | det_surface_update(dc, &updates[i], i); |
1200 | 1187 | ||
1201 | if (type == UPDATE_TYPE_FULL) | 1188 | if (type == UPDATE_TYPE_FULL) |
1202 | return type; | 1189 | return type; |
@@ -1230,12 +1217,11 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1230 | struct dc_stream_state *stream, | 1217 | struct dc_stream_state *stream, |
1231 | struct dc_stream_update *stream_update) | 1218 | struct dc_stream_update *stream_update) |
1232 | { | 1219 | { |
1233 | struct dc *core_dc = dc; | ||
1234 | struct validate_context *context; | 1220 | struct validate_context *context; |
1235 | int i, j; | 1221 | int i, j; |
1236 | enum surface_update_type update_type; | 1222 | enum surface_update_type update_type; |
1237 | const struct dc_stream_status *stream_status; | 1223 | const struct dc_stream_status *stream_status; |
1238 | struct dc_context *dc_ctx = core_dc->ctx; | 1224 | struct dc_context *dc_ctx = dc->ctx; |
1239 | 1225 | ||
1240 | stream_status = dc_stream_get_status(stream); | 1226 | stream_status = dc_stream_get_status(stream); |
1241 | 1227 | ||
@@ -1249,7 +1235,7 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1249 | ASSERT(0); | 1235 | ASSERT(0); |
1250 | } | 1236 | } |
1251 | #endif | 1237 | #endif |
1252 | context = core_dc->current_context; | 1238 | context = dc->current_context; |
1253 | 1239 | ||
1254 | /* update current stream with the new updates */ | 1240 | /* update current stream with the new updates */ |
1255 | if (stream_update) { | 1241 | if (stream_update) { |
@@ -1303,7 +1289,7 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1303 | goto context_alloc_fail; | 1289 | goto context_alloc_fail; |
1304 | 1290 | ||
1305 | dc_resource_validate_ctx_copy_construct( | 1291 | dc_resource_validate_ctx_copy_construct( |
1306 | core_dc->current_context, context); | 1292 | dc->current_context, context); |
1307 | 1293 | ||
1308 | /*remove old surfaces from context */ | 1294 | /*remove old surfaces from context */ |
1309 | if (!dc_rem_all_planes_for_stream(dc, stream, context)) { | 1295 | if (!dc_rem_all_planes_for_stream(dc, stream, context)) { |
@@ -1365,7 +1351,7 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1365 | } | 1351 | } |
1366 | 1352 | ||
1367 | if (update_type >= UPDATE_TYPE_MED) { | 1353 | if (update_type >= UPDATE_TYPE_MED) { |
1368 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | 1354 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
1369 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | 1355 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1370 | 1356 | ||
1371 | if (pipe_ctx->plane_state != surface) | 1357 | if (pipe_ctx->plane_state != surface) |
@@ -1403,31 +1389,31 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1403 | } | 1389 | } |
1404 | 1390 | ||
1405 | if (update_type == UPDATE_TYPE_FULL) { | 1391 | if (update_type == UPDATE_TYPE_FULL) { |
1406 | if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { | 1392 | if (!dc->res_pool->funcs->validate_bandwidth(dc, context)) { |
1407 | BREAK_TO_DEBUGGER(); | 1393 | BREAK_TO_DEBUGGER(); |
1408 | goto fail; | 1394 | goto fail; |
1409 | } else { | 1395 | } else { |
1410 | core_dc->hwss.set_bandwidth(core_dc, context, false); | 1396 | dc->hwss.set_bandwidth(dc, context, false); |
1411 | context_clock_trace(dc, context); | 1397 | context_clock_trace(dc, context); |
1412 | } | 1398 | } |
1413 | } | 1399 | } |
1414 | 1400 | ||
1415 | if (update_type > UPDATE_TYPE_FAST) { | 1401 | if (update_type > UPDATE_TYPE_FAST) { |
1416 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | 1402 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
1417 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | 1403 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1418 | 1404 | ||
1419 | core_dc->hwss.wait_for_mpcc_disconnect(core_dc, core_dc->res_pool, pipe_ctx); | 1405 | dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); |
1420 | } | 1406 | } |
1421 | } | 1407 | } |
1422 | 1408 | ||
1423 | if (surface_count == 0) | 1409 | if (surface_count == 0) |
1424 | core_dc->hwss.apply_ctx_for_surface(core_dc, stream, surface_count, context); | 1410 | dc->hwss.apply_ctx_for_surface(dc, stream, surface_count, context); |
1425 | 1411 | ||
1426 | /* Lock pipes for provided surfaces, or all active if full update*/ | 1412 | /* Lock pipes for provided surfaces, or all active if full update*/ |
1427 | for (i = 0; i < surface_count; i++) { | 1413 | for (i = 0; i < surface_count; i++) { |
1428 | struct dc_plane_state *plane_state = srf_updates[i].surface; | 1414 | struct dc_plane_state *plane_state = srf_updates[i].surface; |
1429 | 1415 | ||
1430 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | 1416 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
1431 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | 1417 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1432 | 1418 | ||
1433 | if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) | 1419 | if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) |
@@ -1435,8 +1421,8 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1435 | if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) | 1421 | if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) |
1436 | continue; | 1422 | continue; |
1437 | 1423 | ||
1438 | core_dc->hwss.pipe_control_lock( | 1424 | dc->hwss.pipe_control_lock( |
1439 | core_dc, | 1425 | dc, |
1440 | pipe_ctx, | 1426 | pipe_ctx, |
1441 | true); | 1427 | true); |
1442 | } | 1428 | } |
@@ -1445,9 +1431,9 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1445 | } | 1431 | } |
1446 | 1432 | ||
1447 | /* Full fe update*/ | 1433 | /* Full fe update*/ |
1448 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | 1434 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
1449 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | 1435 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1450 | struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; | 1436 | struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; |
1451 | bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; | 1437 | bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; |
1452 | struct dc_cursor_position position = { 0 }; | 1438 | struct dc_cursor_position position = { 0 }; |
1453 | 1439 | ||
@@ -1458,18 +1444,18 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1458 | if (!pipe_ctx->top_pipe && pipe_ctx->stream) { | 1444 | if (!pipe_ctx->top_pipe && pipe_ctx->stream) { |
1459 | struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); | 1445 | struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); |
1460 | 1446 | ||
1461 | core_dc->hwss.apply_ctx_for_surface( | 1447 | dc->hwss.apply_ctx_for_surface( |
1462 | core_dc, pipe_ctx->stream, stream_status->plane_count, context); | 1448 | dc, pipe_ctx->stream, stream_status->plane_count, context); |
1463 | } | 1449 | } |
1464 | 1450 | ||
1465 | /* TODO: this is a hack w/a for switching from mpo to pipe split */ | 1451 | /* TODO: this is a hack w/a for switching from mpo to pipe split */ |
1466 | dc_stream_set_cursor_position(pipe_ctx->stream, &position); | 1452 | dc_stream_set_cursor_position(pipe_ctx->stream, &position); |
1467 | 1453 | ||
1468 | if (is_new_pipe_surface) { | 1454 | if (is_new_pipe_surface) { |
1469 | core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); | 1455 | dc->hwss.update_plane_addr(dc, pipe_ctx); |
1470 | core_dc->hwss.set_input_transfer_func( | 1456 | dc->hwss.set_input_transfer_func( |
1471 | pipe_ctx, pipe_ctx->plane_state); | 1457 | pipe_ctx, pipe_ctx->plane_state); |
1472 | core_dc->hwss.set_output_transfer_func( | 1458 | dc->hwss.set_output_transfer_func( |
1473 | pipe_ctx, pipe_ctx->stream); | 1459 | pipe_ctx, pipe_ctx->stream); |
1474 | } | 1460 | } |
1475 | } | 1461 | } |
@@ -1482,40 +1468,40 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1482 | struct dc_plane_state *plane_state = srf_updates[i].surface; | 1468 | struct dc_plane_state *plane_state = srf_updates[i].surface; |
1483 | 1469 | ||
1484 | if (update_type == UPDATE_TYPE_MED) | 1470 | if (update_type == UPDATE_TYPE_MED) |
1485 | core_dc->hwss.apply_ctx_for_surface( | 1471 | dc->hwss.apply_ctx_for_surface( |
1486 | core_dc, stream, surface_count, context); | 1472 | dc, stream, surface_count, context); |
1487 | 1473 | ||
1488 | for (j = 0; j < core_dc->res_pool->pipe_count; j++) { | 1474 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
1489 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | 1475 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; |
1490 | 1476 | ||
1491 | if (pipe_ctx->plane_state != plane_state) | 1477 | if (pipe_ctx->plane_state != plane_state) |
1492 | continue; | 1478 | continue; |
1493 | 1479 | ||
1494 | if (srf_updates[i].flip_addr) | 1480 | if (srf_updates[i].flip_addr) |
1495 | core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); | 1481 | dc->hwss.update_plane_addr(dc, pipe_ctx); |
1496 | 1482 | ||
1497 | if (update_type == UPDATE_TYPE_FAST) | 1483 | if (update_type == UPDATE_TYPE_FAST) |
1498 | continue; | 1484 | continue; |
1499 | 1485 | ||
1500 | if (srf_updates[i].in_transfer_func) | 1486 | if (srf_updates[i].in_transfer_func) |
1501 | core_dc->hwss.set_input_transfer_func( | 1487 | dc->hwss.set_input_transfer_func( |
1502 | pipe_ctx, pipe_ctx->plane_state); | 1488 | pipe_ctx, pipe_ctx->plane_state); |
1503 | 1489 | ||
1504 | if (stream_update != NULL && | 1490 | if (stream_update != NULL && |
1505 | stream_update->out_transfer_func != NULL) { | 1491 | stream_update->out_transfer_func != NULL) { |
1506 | core_dc->hwss.set_output_transfer_func( | 1492 | dc->hwss.set_output_transfer_func( |
1507 | pipe_ctx, pipe_ctx->stream); | 1493 | pipe_ctx, pipe_ctx->stream); |
1508 | } | 1494 | } |
1509 | 1495 | ||
1510 | if (srf_updates[i].hdr_static_metadata) { | 1496 | if (srf_updates[i].hdr_static_metadata) { |
1511 | resource_build_info_frame(pipe_ctx); | 1497 | resource_build_info_frame(pipe_ctx); |
1512 | core_dc->hwss.update_info_frame(pipe_ctx); | 1498 | dc->hwss.update_info_frame(pipe_ctx); |
1513 | } | 1499 | } |
1514 | } | 1500 | } |
1515 | } | 1501 | } |
1516 | 1502 | ||
1517 | /* Unlock pipes */ | 1503 | /* Unlock pipes */ |
1518 | for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) { | 1504 | for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { |
1519 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | 1505 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
1520 | 1506 | ||
1521 | for (j = 0; j < surface_count; j++) { | 1507 | for (j = 0; j < surface_count; j++) { |
@@ -1525,8 +1511,8 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1525 | if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) | 1511 | if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) |
1526 | continue; | 1512 | continue; |
1527 | 1513 | ||
1528 | core_dc->hwss.pipe_control_lock( | 1514 | dc->hwss.pipe_control_lock( |
1529 | core_dc, | 1515 | dc, |
1530 | pipe_ctx, | 1516 | pipe_ctx, |
1531 | false); | 1517 | false); |
1532 | 1518 | ||
@@ -1534,7 +1520,7 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1534 | } | 1520 | } |
1535 | } | 1521 | } |
1536 | 1522 | ||
1537 | if (core_dc->current_context != context) { | 1523 | if (dc->current_context != context) { |
1538 | 1524 | ||
1539 | /* Since memory free requires elevated IRQL, an interrupt | 1525 | /* Since memory free requires elevated IRQL, an interrupt |
1540 | * request is generated by mem free. If this happens | 1526 | * request is generated by mem free. If this happens |
@@ -1544,9 +1530,9 @@ void dc_update_planes_and_stream(struct dc *dc, | |||
1544 | * then free the old context. | 1530 | * then free the old context. |
1545 | */ | 1531 | */ |
1546 | 1532 | ||
1547 | struct validate_context *old = core_dc->current_context; | 1533 | struct validate_context *old = dc->current_context; |
1548 | 1534 | ||
1549 | core_dc->current_context = context; | 1535 | dc->current_context = context; |
1550 | dc_release_validate_context(old); | 1536 | dc_release_validate_context(old); |
1551 | 1537 | ||
1552 | } | 1538 | } |
@@ -1561,29 +1547,25 @@ context_alloc_fail: | |||
1561 | 1547 | ||
1562 | uint8_t dc_get_current_stream_count(struct dc *dc) | 1548 | uint8_t dc_get_current_stream_count(struct dc *dc) |
1563 | { | 1549 | { |
1564 | struct dc *core_dc = dc; | 1550 | return dc->current_context->stream_count; |
1565 | return core_dc->current_context->stream_count; | ||
1566 | } | 1551 | } |
1567 | 1552 | ||
1568 | struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) | 1553 | struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) |
1569 | { | 1554 | { |
1570 | struct dc *core_dc = dc; | 1555 | if (i < dc->current_context->stream_count) |
1571 | if (i < core_dc->current_context->stream_count) | 1556 | return dc->current_context->streams[i]; |
1572 | return core_dc->current_context->streams[i]; | ||
1573 | return NULL; | 1557 | return NULL; |
1574 | } | 1558 | } |
1575 | 1559 | ||
1576 | struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) | 1560 | struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) |
1577 | { | 1561 | { |
1578 | struct dc *core_dc = dc; | 1562 | return dc->links[link_index]; |
1579 | return core_dc->links[link_index]; | ||
1580 | } | 1563 | } |
1581 | 1564 | ||
1582 | struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) | 1565 | struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) |
1583 | { | 1566 | { |
1584 | struct dc *core_dc = dc; | ||
1585 | if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { | 1567 | if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { |
1586 | return core_dc->res_pool->dwbc[(int)pipe]; | 1568 | return dc->res_pool->dwbc[(int)pipe]; |
1587 | } else { | 1569 | } else { |
1588 | return NULL; | 1570 | return NULL; |
1589 | } | 1571 | } |
@@ -1592,21 +1574,18 @@ struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) | |||
1592 | const struct graphics_object_id dc_get_link_id_at_index( | 1574 | const struct graphics_object_id dc_get_link_id_at_index( |
1593 | struct dc *dc, uint32_t link_index) | 1575 | struct dc *dc, uint32_t link_index) |
1594 | { | 1576 | { |
1595 | struct dc *core_dc = dc; | 1577 | return dc->links[link_index]->link_id; |
1596 | return core_dc->links[link_index]->link_id; | ||
1597 | } | 1578 | } |
1598 | 1579 | ||
1599 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | 1580 | enum dc_irq_source dc_get_hpd_irq_source_at_index( |
1600 | struct dc *dc, uint32_t link_index) | 1581 | struct dc *dc, uint32_t link_index) |
1601 | { | 1582 | { |
1602 | struct dc *core_dc = dc; | 1583 | return dc->links[link_index]->irq_source_hpd; |
1603 | return core_dc->links[link_index]->irq_source_hpd; | ||
1604 | } | 1584 | } |
1605 | 1585 | ||
1606 | const struct audio **dc_get_audios(struct dc *dc) | 1586 | const struct audio **dc_get_audios(struct dc *dc) |
1607 | { | 1587 | { |
1608 | struct dc *core_dc = dc; | 1588 | return (const struct audio **)dc->res_pool->audios; |
1609 | return (const struct audio **)core_dc->res_pool->audios; | ||
1610 | } | 1589 | } |
1611 | 1590 | ||
1612 | enum dc_irq_source dc_interrupt_to_irq_source( | 1591 | enum dc_irq_source dc_interrupt_to_irq_source( |
@@ -1614,41 +1593,36 @@ enum dc_irq_source dc_interrupt_to_irq_source( | |||
1614 | uint32_t src_id, | 1593 | uint32_t src_id, |
1615 | uint32_t ext_id) | 1594 | uint32_t ext_id) |
1616 | { | 1595 | { |
1617 | struct dc *core_dc = dc; | 1596 | return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id); |
1618 | return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); | ||
1619 | } | 1597 | } |
1620 | 1598 | ||
1621 | void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) | 1599 | void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) |
1622 | { | 1600 | { |
1623 | struct dc *core_dc; | ||
1624 | 1601 | ||
1625 | if (dc == NULL) | 1602 | if (dc == NULL) |
1626 | return; | 1603 | return; |
1627 | core_dc = dc; | ||
1628 | 1604 | ||
1629 | dal_irq_service_set(core_dc->res_pool->irqs, src, enable); | 1605 | dal_irq_service_set(dc->res_pool->irqs, src, enable); |
1630 | } | 1606 | } |
1631 | 1607 | ||
1632 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) | 1608 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) |
1633 | { | 1609 | { |
1634 | struct dc *core_dc = dc; | 1610 | dal_irq_service_ack(dc->res_pool->irqs, src); |
1635 | dal_irq_service_ack(core_dc->res_pool->irqs, src); | ||
1636 | } | 1611 | } |
1637 | 1612 | ||
1638 | void dc_set_power_state( | 1613 | void dc_set_power_state( |
1639 | struct dc *dc, | 1614 | struct dc *dc, |
1640 | enum dc_acpi_cm_power_state power_state) | 1615 | enum dc_acpi_cm_power_state power_state) |
1641 | { | 1616 | { |
1642 | struct dc *core_dc = dc; | ||
1643 | atomic_t ref_count; | 1617 | atomic_t ref_count; |
1644 | 1618 | ||
1645 | switch (power_state) { | 1619 | switch (power_state) { |
1646 | case DC_ACPI_CM_POWER_STATE_D0: | 1620 | case DC_ACPI_CM_POWER_STATE_D0: |
1647 | core_dc->hwss.init_hw(core_dc); | 1621 | dc->hwss.init_hw(dc); |
1648 | break; | 1622 | break; |
1649 | default: | 1623 | default: |
1650 | 1624 | ||
1651 | core_dc->hwss.power_down(core_dc); | 1625 | dc->hwss.power_down(dc); |
1652 | 1626 | ||
1653 | /* Zero out the current context so that on resume we start with | 1627 | /* Zero out the current context so that on resume we start with |
1654 | * clean state, and dc hw programming optimizations will not | 1628 | * clean state, and dc hw programming optimizations will not |
@@ -1656,11 +1630,11 @@ void dc_set_power_state( | |||
1656 | */ | 1630 | */ |
1657 | 1631 | ||
1658 | /* Preserve refcount */ | 1632 | /* Preserve refcount */ |
1659 | ref_count = core_dc->current_context->ref_count; | 1633 | ref_count = dc->current_context->ref_count; |
1660 | dc_resource_validate_ctx_destruct(core_dc->current_context); | 1634 | dc_resource_validate_ctx_destruct(dc->current_context); |
1661 | memset(core_dc->current_context, 0, | 1635 | memset(dc->current_context, 0, |
1662 | sizeof(*core_dc->current_context)); | 1636 | sizeof(*dc->current_context)); |
1663 | core_dc->current_context->ref_count = ref_count; | 1637 | dc->current_context->ref_count = ref_count; |
1664 | 1638 | ||
1665 | break; | 1639 | break; |
1666 | } | 1640 | } |
@@ -1669,12 +1643,11 @@ void dc_set_power_state( | |||
1669 | 1643 | ||
1670 | void dc_resume(struct dc *dc) | 1644 | void dc_resume(struct dc *dc) |
1671 | { | 1645 | { |
1672 | struct dc *core_dc = dc; | ||
1673 | 1646 | ||
1674 | uint32_t i; | 1647 | uint32_t i; |
1675 | 1648 | ||
1676 | for (i = 0; i < core_dc->link_count; i++) | 1649 | for (i = 0; i < dc->link_count; i++) |
1677 | core_link_resume(core_dc->links[i]); | 1650 | core_link_resume(dc->links[i]); |
1678 | } | 1651 | } |
1679 | 1652 | ||
1680 | bool dc_read_aux_dpcd( | 1653 | bool dc_read_aux_dpcd( |
@@ -1684,9 +1657,8 @@ bool dc_read_aux_dpcd( | |||
1684 | uint8_t *data, | 1657 | uint8_t *data, |
1685 | uint32_t size) | 1658 | uint32_t size) |
1686 | { | 1659 | { |
1687 | struct dc *core_dc = dc; | ||
1688 | 1660 | ||
1689 | struct dc_link *link = core_dc->links[link_index]; | 1661 | struct dc_link *link = dc->links[link_index]; |
1690 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | 1662 | enum ddc_result r = dal_ddc_service_read_dpcd_data( |
1691 | link->ddc, | 1663 | link->ddc, |
1692 | false, | 1664 | false, |
@@ -1704,8 +1676,7 @@ bool dc_write_aux_dpcd( | |||
1704 | const uint8_t *data, | 1676 | const uint8_t *data, |
1705 | uint32_t size) | 1677 | uint32_t size) |
1706 | { | 1678 | { |
1707 | struct dc *core_dc = dc; | 1679 | struct dc_link *link = dc->links[link_index]; |
1708 | struct dc_link *link = core_dc->links[link_index]; | ||
1709 | 1680 | ||
1710 | enum ddc_result r = dal_ddc_service_write_dpcd_data( | 1681 | enum ddc_result r = dal_ddc_service_write_dpcd_data( |
1711 | link->ddc, | 1682 | link->ddc, |
@@ -1725,9 +1696,8 @@ bool dc_read_aux_i2c( | |||
1725 | uint8_t *data, | 1696 | uint8_t *data, |
1726 | uint32_t size) | 1697 | uint32_t size) |
1727 | { | 1698 | { |
1728 | struct dc *core_dc = dc; | ||
1729 | 1699 | ||
1730 | struct dc_link *link = core_dc->links[link_index]; | 1700 | struct dc_link *link = dc->links[link_index]; |
1731 | enum ddc_result r = dal_ddc_service_read_dpcd_data( | 1701 | enum ddc_result r = dal_ddc_service_read_dpcd_data( |
1732 | link->ddc, | 1702 | link->ddc, |
1733 | true, | 1703 | true, |
@@ -1746,8 +1716,7 @@ bool dc_write_aux_i2c( | |||
1746 | const uint8_t *data, | 1716 | const uint8_t *data, |
1747 | uint32_t size) | 1717 | uint32_t size) |
1748 | { | 1718 | { |
1749 | struct dc *core_dc = dc; | 1719 | struct dc_link *link = dc->links[link_index]; |
1750 | struct dc_link *link = core_dc->links[link_index]; | ||
1751 | 1720 | ||
1752 | enum ddc_result r = dal_ddc_service_write_dpcd_data( | 1721 | enum ddc_result r = dal_ddc_service_write_dpcd_data( |
1753 | link->ddc, | 1722 | link->ddc, |
@@ -1768,9 +1737,8 @@ bool dc_query_ddc_data( | |||
1768 | uint8_t *read_buf, | 1737 | uint8_t *read_buf, |
1769 | uint32_t read_size) { | 1738 | uint32_t read_size) { |
1770 | 1739 | ||
1771 | struct dc *core_dc = dc; | ||
1772 | 1740 | ||
1773 | struct dc_link *link = core_dc->links[link_index]; | 1741 | struct dc_link *link = dc->links[link_index]; |
1774 | 1742 | ||
1775 | bool result = dal_ddc_service_query_ddc_data( | 1743 | bool result = dal_ddc_service_query_ddc_data( |
1776 | link->ddc, | 1744 | link->ddc, |
@@ -1788,9 +1756,8 @@ bool dc_submit_i2c( | |||
1788 | uint32_t link_index, | 1756 | uint32_t link_index, |
1789 | struct i2c_command *cmd) | 1757 | struct i2c_command *cmd) |
1790 | { | 1758 | { |
1791 | struct dc *core_dc = dc; | ||
1792 | 1759 | ||
1793 | struct dc_link *link = core_dc->links[link_index]; | 1760 | struct dc_link *link = dc->links[link_index]; |
1794 | struct ddc_service *ddc = link->ddc; | 1761 | struct ddc_service *ddc = link->ddc; |
1795 | 1762 | ||
1796 | return dal_i2caux_submit_i2c_command( | 1763 | return dal_i2caux_submit_i2c_command( |
@@ -1907,12 +1874,11 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) | |||
1907 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) | 1874 | bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) |
1908 | { | 1875 | { |
1909 | int i; | 1876 | int i; |
1910 | struct dc *core_dc = dc; | ||
1911 | struct mem_input *mi = NULL; | 1877 | struct mem_input *mi = NULL; |
1912 | 1878 | ||
1913 | for (i = 0; i < core_dc->res_pool->pipe_count; i++) { | 1879 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1914 | if (core_dc->res_pool->mis[i] != NULL) { | 1880 | if (dc->res_pool->mis[i] != NULL) { |
1915 | mi = core_dc->res_pool->mis[i]; | 1881 | mi = dc->res_pool->mis[i]; |
1916 | break; | 1882 | break; |
1917 | } | 1883 | } |
1918 | } | 1884 | } |
@@ -1921,10 +1887,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) | |||
1921 | return false; | 1887 | return false; |
1922 | } | 1888 | } |
1923 | 1889 | ||
1924 | if (core_dc->hwss.update_dchub) | 1890 | if (dc->hwss.update_dchub) |
1925 | core_dc->hwss.update_dchub(core_dc->hwseq, dh_data); | 1891 | dc->hwss.update_dchub(dc->hwseq, dh_data); |
1926 | else | 1892 | else |
1927 | ASSERT(core_dc->hwss.update_dchub); | 1893 | ASSERT(dc->hwss.update_dchub); |
1928 | 1894 | ||
1929 | 1895 | ||
1930 | return true; | 1896 | return true; |
@@ -1933,9 +1899,8 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) | |||
1933 | 1899 | ||
1934 | void dc_log_hw_state(struct dc *dc) | 1900 | void dc_log_hw_state(struct dc *dc) |
1935 | { | 1901 | { |
1936 | struct dc *core_dc = dc; | ||
1937 | 1902 | ||
1938 | if (core_dc->hwss.log_hw_state) | 1903 | if (dc->hwss.log_hw_state) |
1939 | core_dc->hwss.log_hw_state(core_dc); | 1904 | dc->hwss.log_hw_state(dc); |
1940 | } | 1905 | } |
1941 | 1906 | ||
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f49203b3eb94..52350d0e68d0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |||
@@ -145,7 +145,6 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) | |||
145 | struct core_freesync *core_freesync = | 145 | struct core_freesync *core_freesync = |
146 | dm_alloc(sizeof(struct core_freesync)); | 146 | dm_alloc(sizeof(struct core_freesync)); |
147 | 147 | ||
148 | struct dc *core_dc = dc; | ||
149 | 148 | ||
150 | struct persistent_data_flag flag; | 149 | struct persistent_data_flag flag; |
151 | 150 | ||
@@ -176,19 +175,19 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) | |||
176 | /* Create initial module folder in registry for freesync enable data */ | 175 | /* Create initial module folder in registry for freesync enable data */ |
177 | flag.save_per_edid = true; | 176 | flag.save_per_edid = true; |
178 | flag.save_per_link = false; | 177 | flag.save_per_link = false; |
179 | dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, | 178 | dm_write_persistent_data(dc->ctx, NULL, FREESYNC_REGISTRY_NAME, |
180 | NULL, NULL, 0, &flag); | 179 | NULL, NULL, 0, &flag); |
181 | flag.save_per_edid = false; | 180 | flag.save_per_edid = false; |
182 | flag.save_per_link = false; | 181 | flag.save_per_link = false; |
183 | 182 | ||
184 | if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, | 183 | if (dm_read_persistent_data(dc->ctx, NULL, NULL, |
185 | FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY, | 184 | FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY, |
186 | &data, sizeof(data), &flag)) { | 185 | &data, sizeof(data), &flag)) { |
187 | core_freesync->opts.drr_internal_supported = | 186 | core_freesync->opts.drr_internal_supported = |
188 | (data & 1) ? false : true; | 187 | (data & 1) ? false : true; |
189 | } | 188 | } |
190 | 189 | ||
191 | if (dm_read_persistent_data(core_dc->ctx, NULL, NULL, | 190 | if (dm_read_persistent_data(dc->ctx, NULL, NULL, |
192 | FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY, | 191 | FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY, |
193 | &data, sizeof(data), &flag)) { | 192 | &data, sizeof(data), &flag)) { |
194 | core_freesync->opts.drr_external_supported = | 193 | core_freesync->opts.drr_external_supported = |
@@ -245,7 +244,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, | |||
245 | bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, | 244 | bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, |
246 | struct dc_stream_state *stream, struct mod_freesync_caps *caps) | 245 | struct dc_stream_state *stream, struct mod_freesync_caps *caps) |
247 | { | 246 | { |
248 | struct dc *core_dc = NULL; | 247 | struct dc *dc = NULL; |
249 | struct core_freesync *core_freesync = NULL; | 248 | struct core_freesync *core_freesync = NULL; |
250 | int persistent_freesync_enable = 0; | 249 | int persistent_freesync_enable = 0; |
251 | struct persistent_data_flag flag; | 250 | struct persistent_data_flag flag; |
@@ -256,7 +255,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, | |||
256 | return false; | 255 | return false; |
257 | 256 | ||
258 | core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); | 257 | core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); |
259 | core_dc = core_freesync->dc; | 258 | dc = core_freesync->dc; |
260 | 259 | ||
261 | flag.save_per_edid = true; | 260 | flag.save_per_edid = true; |
262 | flag.save_per_link = false; | 261 | flag.save_per_link = false; |
@@ -287,7 +286,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, | |||
287 | static_ramp.ramp_is_active = false; | 286 | static_ramp.ramp_is_active = false; |
288 | 287 | ||
289 | /* get persistent data from registry */ | 288 | /* get persistent data from registry */ |
290 | if (dm_read_persistent_data(core_dc->ctx, stream->sink, | 289 | if (dm_read_persistent_data(dc->ctx, stream->sink, |
291 | FREESYNC_REGISTRY_NAME, | 290 | FREESYNC_REGISTRY_NAME, |
292 | "userenable", &persistent_freesync_enable, | 291 | "userenable", &persistent_freesync_enable, |
293 | sizeof(int), &flag)) { | 292 | sizeof(int), &flag)) { |
@@ -970,14 +969,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, | |||
970 | unsigned int stream_index, map_index; | 969 | unsigned int stream_index, map_index; |
971 | int persistent_data = 0; | 970 | int persistent_data = 0; |
972 | struct persistent_data_flag flag; | 971 | struct persistent_data_flag flag; |
973 | struct dc *core_dc = NULL; | 972 | struct dc *dc = NULL; |
974 | struct core_freesync *core_freesync = NULL; | 973 | struct core_freesync *core_freesync = NULL; |
975 | 974 | ||
976 | if (mod_freesync == NULL) | 975 | if (mod_freesync == NULL) |
977 | return false; | 976 | return false; |
978 | 977 | ||
979 | core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); | 978 | core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); |
980 | core_dc = core_freesync->dc; | 979 | dc = core_freesync->dc; |
981 | 980 | ||
982 | flag.save_per_edid = true; | 981 | flag.save_per_edid = true; |
983 | flag.save_per_link = false; | 982 | flag.save_per_link = false; |
@@ -1001,7 +1000,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, | |||
1001 | enable_for_video) | 1000 | enable_for_video) |
1002 | persistent_data = persistent_data | 4; | 1001 | persistent_data = persistent_data | 4; |
1003 | 1002 | ||
1004 | dm_write_persistent_data(core_dc->ctx, | 1003 | dm_write_persistent_data(dc->ctx, |
1005 | streams[stream_index]->sink, | 1004 | streams[stream_index]->sink, |
1006 | FREESYNC_REGISTRY_NAME, | 1005 | FREESYNC_REGISTRY_NAME, |
1007 | "userenable", | 1006 | "userenable", |