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authorRex Zhu <Rex.Zhu@amd.com>2018-08-14 04:54:15 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 12:11:01 -0400
commit05df1f01b2924d2e1737deeb63ad115c1df19021 (patch)
tree130662a1e11852761a597089a7c7415fff8ca603 /drivers/gpu/drm/amd
parent1112a46b48b74766bd957742c853c8a582a81991 (diff)
drm/amdgpu: Set power ungate state when suspend/fini
Unify to set power ungate state at the begin of suspend/fini. Remove the workaround code for gfx off feature in amdgpu_device.c. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c19
3 files changed, 17 insertions, 17 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 04fbc63a83b7..13ea4da9f23a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1817,6 +1817,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1817 int i, r; 1817 int i, r;
1818 1818
1819 amdgpu_amdkfd_device_fini(adev); 1819 amdgpu_amdkfd_device_fini(adev);
1820
1821 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1820 /* need to disable SMC first */ 1822 /* need to disable SMC first */
1821 for (i = 0; i < adev->num_ip_blocks; i++) { 1823 for (i = 0; i < adev->num_ip_blocks; i++) {
1822 if (!adev->ip_blocks[i].status.hw) 1824 if (!adev->ip_blocks[i].status.hw)
@@ -1831,8 +1833,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1831 adev->ip_blocks[i].version->funcs->name, r); 1833 adev->ip_blocks[i].version->funcs->name, r);
1832 return r; 1834 return r;
1833 } 1835 }
1834 amdgpu_gfx_off_ctrl(adev, false); 1836
1835 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
1836 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); 1837 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1837 /* XXX handle errors */ 1838 /* XXX handle errors */
1838 if (r) { 1839 if (r) {
@@ -1955,6 +1956,8 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
1955 if (amdgpu_sriov_vf(adev)) 1956 if (amdgpu_sriov_vf(adev))
1956 amdgpu_virt_request_full_gpu(adev, false); 1957 amdgpu_virt_request_full_gpu(adev, false);
1957 1958
1959 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1960
1958 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1961 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1959 if (!adev->ip_blocks[i].status.valid) 1962 if (!adev->ip_blocks[i].status.valid)
1960 continue; 1963 continue;
@@ -2010,10 +2013,6 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2010 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); 2013 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
2011 } 2014 }
2012 2015
2013 /* call smu to disable gfx off feature first when suspend */
2014 amdgpu_gfx_off_ctrl(adev, false);
2015 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
2016
2017 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 2016 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2018 if (!adev->ip_blocks[i].status.valid) 2017 if (!adev->ip_blocks[i].status.valid)
2019 continue; 2018 continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5cd45210113f..282dba6cce86 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5164,10 +5164,6 @@ static int gfx_v8_0_hw_fini(void *handle)
5164 gfx_v8_0_cp_enable(adev, false); 5164 gfx_v8_0_cp_enable(adev, false);
5165 gfx_v8_0_rlc_stop(adev); 5165 gfx_v8_0_rlc_stop(adev);
5166 5166
5167 amdgpu_device_ip_set_powergating_state(adev,
5168 AMD_IP_BLOCK_TYPE_GFX,
5169 AMD_PG_STATE_UNGATE);
5170
5171 return 0; 5167 return 0;
5172} 5168}
5173 5169
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76d979e276a0..4e1e1a0dd681 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3242,9 +3242,6 @@ static int gfx_v9_0_hw_fini(void *handle)
3242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3242 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3243 int i; 3243 int i;
3244 3244
3245 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3246 AMD_PG_STATE_UNGATE);
3247
3248 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3245 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3249 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3246 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3250 3247
@@ -3763,6 +3760,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
3763 3760
3764 switch (adev->asic_type) { 3761 switch (adev->asic_type) {
3765 case CHIP_RAVEN: 3762 case CHIP_RAVEN:
3763 if (!enable) {
3764 amdgpu_gfx_off_ctrl(adev, false);
3765 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3766 }
3766 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3767 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3767 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3768 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3768 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3769 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
@@ -3782,12 +3783,16 @@ static int gfx_v9_0_set_powergating_state(void *handle,
3782 /* update mgcg state */ 3783 /* update mgcg state */
3783 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3784 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3784 3785
3785 /* set gfx off through smu */ 3786 if (enable)
3786 amdgpu_gfx_off_ctrl(adev, true); 3787 amdgpu_gfx_off_ctrl(adev, true);
3787 break; 3788 break;
3788 case CHIP_VEGA12: 3789 case CHIP_VEGA12:
3789 /* set gfx off through smu */ 3790 if (!enable) {
3790 amdgpu_gfx_off_ctrl(adev, true); 3791 amdgpu_gfx_off_ctrl(adev, false);
3792 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3793 } else {
3794 amdgpu_gfx_off_ctrl(adev, true);
3795 }
3791 break; 3796 break;
3792 default: 3797 default:
3793 break; 3798 break;