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authorEric Huang <JinHuiEric.Huang@amd.com>2015-08-26 16:52:28 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-12-21 16:42:17 -0500
commitaabcb7c11e3d9d8a5c28fb5b3aa60ec1cec58e64 (patch)
tree0fc48b194bb650e9939a6d1318f74231141ce9a3 /drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
parent74785623db6889e6fffb5d2565a27fbeb9ddb390 (diff)
drm/amd/powerplay: add Fiji DPM support.
This enabled DPM support for Fiji. DPM is dynamic clock and voltage scaling. v2: rename fiji_hwmgr_early_init to fiji_hwmgr_init v3: (agd) fold in endian fix, additional function addition Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h356
1 files changed, 356 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
new file mode 100644
index 000000000000..38dbe498394b
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
@@ -0,0 +1,356 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _FIJI_HWMGR_H_
25#define _FIJI_HWMGR_H_
26
27#include "hwmgr.h"
28#include "smu73.h"
29#include "smu73_discrete.h"
30#include "ppatomctrl.h"
31#include "fiji_ppsmc.h"
32
33#define FIJI_MAX_HARDWARE_POWERLEVELS 2
34#define FIJI_AT_DFLT 30
35
36#define FIJI_VOLTAGE_CONTROL_NONE 0x0
37#define FIJI_VOLTAGE_CONTROL_BY_GPIO 0x1
38#define FIJI_VOLTAGE_CONTROL_BY_SVID2 0x2
39#define FIJI_VOLTAGE_CONTROL_MERGED 0x3
40
41#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
42#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
43#define DPMTABLE_UPDATE_SCLK 0x00000004
44#define DPMTABLE_UPDATE_MCLK 0x00000008
45
46struct fiji_performance_level {
47 uint32_t memory_clock;
48 uint32_t engine_clock;
49 uint16_t pcie_gen;
50 uint16_t pcie_lane;
51};
52
53struct fiji_uvd_clocks {
54 uint32_t vclk;
55 uint32_t dclk;
56};
57
58struct fiji_vce_clocks {
59 uint32_t evclk;
60 uint32_t ecclk;
61};
62
63struct fiji_power_state {
64 uint32_t magic;
65 struct fiji_uvd_clocks uvd_clks;
66 struct fiji_vce_clocks vce_clks;
67 uint32_t sam_clk;
68 uint32_t acp_clk;
69 uint16_t performance_level_count;
70 bool dc_compatible;
71 uint32_t sclk_threshold;
72 struct fiji_performance_level performance_levels[FIJI_MAX_HARDWARE_POWERLEVELS];
73};
74
75struct fiji_dpm_level {
76 bool enabled;
77 uint32_t value;
78 uint32_t param1;
79};
80
81#define FIJI_MAX_DEEPSLEEP_DIVIDER_ID 5
82#define MAX_REGULAR_DPM_NUMBER 8
83#define FIJI_MINIMUM_ENGINE_CLOCK 2500
84
85struct fiji_single_dpm_table {
86 uint32_t count;
87 struct fiji_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
88};
89
90struct fiji_dpm_table {
91 struct fiji_single_dpm_table sclk_table;
92 struct fiji_single_dpm_table mclk_table;
93 struct fiji_single_dpm_table pcie_speed_table;
94 struct fiji_single_dpm_table vddc_table;
95 struct fiji_single_dpm_table vddci_table;
96 struct fiji_single_dpm_table mvdd_table;
97};
98
99struct fiji_clock_registers {
100 uint32_t vCG_SPLL_FUNC_CNTL;
101 uint32_t vCG_SPLL_FUNC_CNTL_2;
102 uint32_t vCG_SPLL_FUNC_CNTL_3;
103 uint32_t vCG_SPLL_FUNC_CNTL_4;
104 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
105 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
106 uint32_t vDLL_CNTL;
107 uint32_t vMCLK_PWRMGT_CNTL;
108 uint32_t vMPLL_AD_FUNC_CNTL;
109 uint32_t vMPLL_DQ_FUNC_CNTL;
110 uint32_t vMPLL_FUNC_CNTL;
111 uint32_t vMPLL_FUNC_CNTL_1;
112 uint32_t vMPLL_FUNC_CNTL_2;
113 uint32_t vMPLL_SS1;
114 uint32_t vMPLL_SS2;
115};
116
117struct fiji_voltage_smio_registers {
118 uint32_t vS0_VID_LOWER_SMIO_CNTL;
119};
120
121#define FIJI_MAX_LEAKAGE_COUNT 8
122struct fiji_leakage_voltage {
123 uint16_t count;
124 uint16_t leakage_id[FIJI_MAX_LEAKAGE_COUNT];
125 uint16_t actual_voltage[FIJI_MAX_LEAKAGE_COUNT];
126};
127
128struct fiji_vbios_boot_state {
129 uint16_t mvdd_bootup_value;
130 uint16_t vddc_bootup_value;
131 uint16_t vddci_bootup_value;
132 uint32_t sclk_bootup_value;
133 uint32_t mclk_bootup_value;
134 uint16_t pcie_gen_bootup_value;
135 uint16_t pcie_lane_bootup_value;
136};
137
138struct fiji_bacos {
139 uint32_t best_match;
140 uint32_t baco_flags;
141 struct fiji_performance_level performance_level;
142};
143
144/* Ultra Low Voltage parameter structure */
145struct fiji_ulv_parm {
146 bool ulv_supported;
147 uint32_t cg_ulv_parameter;
148 uint32_t ulv_volt_change_delay;
149 struct fiji_performance_level ulv_power_level;
150};
151
152struct fiji_display_timing {
153 uint32_t min_clock_in_sr;
154 uint32_t num_existing_displays;
155};
156
157struct fiji_dpmlevel_enable_mask {
158 uint32_t uvd_dpm_enable_mask;
159 uint32_t vce_dpm_enable_mask;
160 uint32_t acp_dpm_enable_mask;
161 uint32_t samu_dpm_enable_mask;
162 uint32_t sclk_dpm_enable_mask;
163 uint32_t mclk_dpm_enable_mask;
164 uint32_t pcie_dpm_enable_mask;
165};
166
167struct fiji_pcie_perf_range {
168 uint16_t max;
169 uint16_t min;
170};
171
172struct fiji_hwmgr {
173 struct fiji_dpm_table dpm_table;
174 struct fiji_dpm_table golden_dpm_table;
175
176 uint32_t voting_rights_clients0;
177 uint32_t voting_rights_clients1;
178 uint32_t voting_rights_clients2;
179 uint32_t voting_rights_clients3;
180 uint32_t voting_rights_clients4;
181 uint32_t voting_rights_clients5;
182 uint32_t voting_rights_clients6;
183 uint32_t voting_rights_clients7;
184 uint32_t static_screen_threshold_unit;
185 uint32_t static_screen_threshold;
186 uint32_t voltage_control;
187 uint32_t vddc_vddci_delta;
188
189 uint32_t active_auto_throttle_sources;
190
191 struct fiji_clock_registers clock_registers;
192 struct fiji_voltage_smio_registers voltage_smio_registers;
193
194 bool is_memory_gddr5;
195 uint16_t acpi_vddc;
196 bool pspp_notify_required;
197 uint16_t force_pcie_gen;
198 uint16_t acpi_pcie_gen;
199 uint32_t pcie_gen_cap;
200 uint32_t pcie_lane_cap;
201 uint32_t pcie_spc_cap;
202 struct fiji_leakage_voltage vddc_leakage;
203 struct fiji_leakage_voltage Vddci_leakage;
204
205 uint32_t mvdd_control;
206 uint32_t vddc_mask_low;
207 uint32_t mvdd_mask_low;
208 uint16_t max_vddc_in_pptable;
209 uint16_t min_vddc_in_pptable;
210 uint16_t max_vddci_in_pptable;
211 uint16_t min_vddci_in_pptable;
212 uint32_t mclk_strobe_mode_threshold;
213 uint32_t mclk_stutter_mode_threshold;
214 uint32_t mclk_edc_enable_threshold;
215 uint32_t mclk_edcwr_enable_threshold;
216 bool is_uvd_enabled;
217 struct fiji_vbios_boot_state vbios_boot_state;
218
219 bool battery_state;
220 bool is_tlu_enabled;
221
222 /* ---- SMC SRAM Address of firmware header tables ---- */
223 uint32_t sram_end;
224 uint32_t dpm_table_start;
225 uint32_t soft_regs_start;
226 uint32_t mc_reg_table_start;
227 uint32_t fan_table_start;
228 uint32_t arb_table_start;
229 struct SMU73_Discrete_DpmTable smc_state_table;
230 struct SMU73_Discrete_Ulv ulv_setting;
231
232 /* ---- Stuff originally coming from Evergreen ---- */
233 uint32_t vddci_control;
234 struct pp_atomctrl_voltage_table vddc_voltage_table;
235 struct pp_atomctrl_voltage_table vddci_voltage_table;
236 struct pp_atomctrl_voltage_table mvdd_voltage_table;
237
238 uint32_t mgcg_cgtt_local2;
239 uint32_t mgcg_cgtt_local3;
240 uint32_t gpio_debug;
241 uint32_t mc_micro_code_feature;
242 uint32_t highest_mclk;
243 uint16_t acpi_vddci;
244 uint8_t mvdd_high_index;
245 uint8_t mvdd_low_index;
246 bool dll_default_on;
247 bool performance_request_registered;
248
249 /* ---- Low Power Features ---- */
250 struct fiji_bacos bacos;
251 struct fiji_ulv_parm ulv;
252
253 /* ---- CAC Stuff ---- */
254 uint32_t cac_table_start;
255 bool cac_configuration_required;
256 bool driver_calculate_cac_leakage;
257 bool cac_enabled;
258
259 /* ---- DPM2 Parameters ---- */
260 uint32_t power_containment_features;
261 bool enable_dte_feature;
262 bool enable_tdc_limit_feature;
263 bool enable_pkg_pwr_tracking_feature;
264 bool disable_uvd_power_tune_feature;
265 struct fiji_pt_defaults *power_tune_defaults;
266 struct SMU73_Discrete_PmFuses power_tune_table;
267 uint32_t dte_tj_offset;
268 uint32_t fast_watermark_threshold;
269
270 /* ---- Phase Shedding ---- */
271 bool vddc_phase_shed_control;
272
273 /* ---- DI/DT ---- */
274 struct fiji_display_timing display_timing;
275
276 /* ---- Thermal Temperature Setting ---- */
277 struct fiji_dpmlevel_enable_mask dpm_level_enable_mask;
278 uint32_t need_update_smu7_dpm_table;
279 uint32_t sclk_dpm_key_disabled;
280 uint32_t mclk_dpm_key_disabled;
281 uint32_t pcie_dpm_key_disabled;
282 uint32_t min_engine_clocks;
283 struct fiji_pcie_perf_range pcie_gen_performance;
284 struct fiji_pcie_perf_range pcie_lane_performance;
285 struct fiji_pcie_perf_range pcie_gen_power_saving;
286 struct fiji_pcie_perf_range pcie_lane_power_saving;
287 bool use_pcie_performance_levels;
288 bool use_pcie_power_saving_levels;
289 uint32_t activity_target[SMU73_MAX_LEVELS_GRAPHICS];
290 uint32_t mclk_activity_target;
291 uint32_t mclk_dpm0_activity_target;
292 uint32_t low_sclk_interrupt_threshold;
293 uint32_t last_mclk_dpm_enable_mask;
294 bool uvd_enabled;
295
296 /* ---- Power Gating States ---- */
297 bool uvd_power_gated;
298 bool vce_power_gated;
299 bool samu_power_gated;
300 bool acp_power_gated;
301 bool pg_acp_init;
302 bool frtc_enabled;
303 bool frtc_status_changed;
304};
305
306/* To convert to Q8.8 format for firmware */
307#define FIJI_Q88_FORMAT_CONVERSION_UNIT 256
308
309enum Fiji_I2CLineID {
310 Fiji_I2CLineID_DDC1 = 0x90,
311 Fiji_I2CLineID_DDC2 = 0x91,
312 Fiji_I2CLineID_DDC3 = 0x92,
313 Fiji_I2CLineID_DDC4 = 0x93,
314 Fiji_I2CLineID_DDC5 = 0x94,
315 Fiji_I2CLineID_DDC6 = 0x95,
316 Fiji_I2CLineID_SCLSDA = 0x96,
317 Fiji_I2CLineID_DDCVGA = 0x97
318};
319
320#define Fiji_I2C_DDC1DATA 0
321#define Fiji_I2C_DDC1CLK 1
322#define Fiji_I2C_DDC2DATA 2
323#define Fiji_I2C_DDC2CLK 3
324#define Fiji_I2C_DDC3DATA 4
325#define Fiji_I2C_DDC3CLK 5
326#define Fiji_I2C_SDA 40
327#define Fiji_I2C_SCL 41
328#define Fiji_I2C_DDC4DATA 65
329#define Fiji_I2C_DDC4CLK 66
330#define Fiji_I2C_DDC5DATA 0x48
331#define Fiji_I2C_DDC5CLK 0x49
332#define Fiji_I2C_DDC6DATA 0x4a
333#define Fiji_I2C_DDC6CLK 0x4b
334#define Fiji_I2C_DDCVGADATA 0x4c
335#define Fiji_I2C_DDCVGACLK 0x4d
336
337#define FIJI_UNUSED_GPIO_PIN 0x7F
338
339extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
340extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
341extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
342extern uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen);
343extern uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes);
344
345#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
346#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
347
348#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
349#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
350
351#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
352#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
353
354#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
355
356#endif /* _FIJI_HWMGR_H_ */
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