diff options
| author | Dave Airlie <airlied@redhat.com> | 2015-11-04 19:57:25 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2015-11-04 19:57:25 -0500 |
| commit | 793423ffcb229ae5654b382a1356906f81da2018 (patch) | |
| tree | c95dcf05246a9c44d9ce15f4d9fb1c4012598fe5 /drivers/gpu/drm/amd/include | |
| parent | bf248ca1f5c7ba1e535ba4bd517a15a1ae965c69 (diff) | |
| parent | a95e264254dca5b6bfb331d5902930d0787bd7e1 (diff) | |
Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Updated register headers for GFX 8.1 for Stoney
- Add some new CZ revisions
- minor pageflip optimizations
- Fencing clean up
- Warning fix
- More fence cleanup
- oops fix
- Fiji fixes
* 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux: (29 commits)
drm/amdgpu: group together common fence implementation
drm/amdgpu: remove AMDGPU_FENCE_OWNER_MOVE
drm/amdgpu: remove now unused fence functions
drm/amdgpu: fix fence fallback check
drm/amdgpu: fix stoping the scheduler timeout
drm/amdgpu: cleanup on error in amdgpu_cs_ioctl()
drm/amdgpu: update Fiji's Golden setting
drm/amdgpu: update Fiji's rev id
drm/amdgpu: extract common code in vi_common_early_init
drm/amd/scheduler: don't oops on failure to load
drm/amdgpu: don't oops on failure to load (v2)
drm/amdgpu: don't VT switch on suspend
drm/amdgpu: Make amdgpu_mn functions inline
drm/amdgpu: remove amdgpu_fence_ref/unref
drm/amdgpu: use common fence for sync
drm/amdgpu: use the new fence_is_later
drm/amdgpu: use common fences for VMID management v2
drm/amdgpu: move ring_from_fence to common code
drm/amdgpu: switch to common fence_wait_any_timeout v2
drm/amdgpu: remove unneeded fence functions
...
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h | 2791 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h | 6808 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h | 21368 |
3 files changed, 30967 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h new file mode 100644 index 000000000000..2d672b3d2fed --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h | |||
| @@ -0,0 +1,2791 @@ | |||
| 1 | /* | ||
| 2 | * GFX_8_1 Register documentation | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included | ||
| 14 | * in all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN | ||
| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef GFX_8_1_D_H | ||
| 25 | #define GFX_8_1_D_H | ||
| 26 | |||
| 27 | #define mmCB_BLEND_RED 0xa105 | ||
| 28 | #define mmCB_BLEND_GREEN 0xa106 | ||
| 29 | #define mmCB_BLEND_BLUE 0xa107 | ||
| 30 | #define mmCB_BLEND_ALPHA 0xa108 | ||
| 31 | #define mmCB_DCC_CONTROL 0xa109 | ||
| 32 | #define mmCB_COLOR_CONTROL 0xa202 | ||
| 33 | #define mmCB_BLEND0_CONTROL 0xa1e0 | ||
| 34 | #define mmCB_BLEND1_CONTROL 0xa1e1 | ||
| 35 | #define mmCB_BLEND2_CONTROL 0xa1e2 | ||
| 36 | #define mmCB_BLEND3_CONTROL 0xa1e3 | ||
| 37 | #define mmCB_BLEND4_CONTROL 0xa1e4 | ||
| 38 | #define mmCB_BLEND5_CONTROL 0xa1e5 | ||
| 39 | #define mmCB_BLEND6_CONTROL 0xa1e6 | ||
| 40 | #define mmCB_BLEND7_CONTROL 0xa1e7 | ||
| 41 | #define mmCB_COLOR0_BASE 0xa318 | ||
| 42 | #define mmCB_COLOR1_BASE 0xa327 | ||
| 43 | #define mmCB_COLOR2_BASE 0xa336 | ||
| 44 | #define mmCB_COLOR3_BASE 0xa345 | ||
| 45 | #define mmCB_COLOR4_BASE 0xa354 | ||
| 46 | #define mmCB_COLOR5_BASE 0xa363 | ||
| 47 | #define mmCB_COLOR6_BASE 0xa372 | ||
| 48 | #define mmCB_COLOR7_BASE 0xa381 | ||
| 49 | #define mmCB_COLOR0_PITCH 0xa319 | ||
| 50 | #define mmCB_COLOR1_PITCH 0xa328 | ||
| 51 | #define mmCB_COLOR2_PITCH 0xa337 | ||
| 52 | #define mmCB_COLOR3_PITCH 0xa346 | ||
| 53 | #define mmCB_COLOR4_PITCH 0xa355 | ||
| 54 | #define mmCB_COLOR5_PITCH 0xa364 | ||
| 55 | #define mmCB_COLOR6_PITCH 0xa373 | ||
| 56 | #define mmCB_COLOR7_PITCH 0xa382 | ||
| 57 | #define mmCB_COLOR0_SLICE 0xa31a | ||
| 58 | #define mmCB_COLOR1_SLICE 0xa329 | ||
| 59 | #define mmCB_COLOR2_SLICE 0xa338 | ||
| 60 | #define mmCB_COLOR3_SLICE 0xa347 | ||
| 61 | #define mmCB_COLOR4_SLICE 0xa356 | ||
| 62 | #define mmCB_COLOR5_SLICE 0xa365 | ||
| 63 | #define mmCB_COLOR6_SLICE 0xa374 | ||
| 64 | #define mmCB_COLOR7_SLICE 0xa383 | ||
| 65 | #define mmCB_COLOR0_VIEW 0xa31b | ||
| 66 | #define mmCB_COLOR1_VIEW 0xa32a | ||
| 67 | #define mmCB_COLOR2_VIEW 0xa339 | ||
| 68 | #define mmCB_COLOR3_VIEW 0xa348 | ||
| 69 | #define mmCB_COLOR4_VIEW 0xa357 | ||
| 70 | #define mmCB_COLOR5_VIEW 0xa366 | ||
| 71 | #define mmCB_COLOR6_VIEW 0xa375 | ||
| 72 | #define mmCB_COLOR7_VIEW 0xa384 | ||
| 73 | #define mmCB_COLOR0_INFO 0xa31c | ||
| 74 | #define mmCB_COLOR1_INFO 0xa32b | ||
| 75 | #define mmCB_COLOR2_INFO 0xa33a | ||
| 76 | #define mmCB_COLOR3_INFO 0xa349 | ||
| 77 | #define mmCB_COLOR4_INFO 0xa358 | ||
| 78 | #define mmCB_COLOR5_INFO 0xa367 | ||
| 79 | #define mmCB_COLOR6_INFO 0xa376 | ||
| 80 | #define mmCB_COLOR7_INFO 0xa385 | ||
| 81 | #define mmCB_COLOR0_ATTRIB 0xa31d | ||
| 82 | #define mmCB_COLOR1_ATTRIB 0xa32c | ||
| 83 | #define mmCB_COLOR2_ATTRIB 0xa33b | ||
| 84 | #define mmCB_COLOR3_ATTRIB 0xa34a | ||
| 85 | #define mmCB_COLOR4_ATTRIB 0xa359 | ||
| 86 | #define mmCB_COLOR5_ATTRIB 0xa368 | ||
| 87 | #define mmCB_COLOR6_ATTRIB 0xa377 | ||
| 88 | #define mmCB_COLOR7_ATTRIB 0xa386 | ||
| 89 | #define mmCB_COLOR0_DCC_CONTROL 0xa31e | ||
| 90 | #define mmCB_COLOR1_DCC_CONTROL 0xa32d | ||
| 91 | #define mmCB_COLOR2_DCC_CONTROL 0xa33c | ||
| 92 | #define mmCB_COLOR3_DCC_CONTROL 0xa34b | ||
| 93 | #define mmCB_COLOR4_DCC_CONTROL 0xa35a | ||
| 94 | #define mmCB_COLOR5_DCC_CONTROL 0xa369 | ||
| 95 | #define mmCB_COLOR6_DCC_CONTROL 0xa378 | ||
| 96 | #define mmCB_COLOR7_DCC_CONTROL 0xa387 | ||
| 97 | #define mmCB_COLOR0_CMASK 0xa31f | ||
| 98 | #define mmCB_COLOR1_CMASK 0xa32e | ||
| 99 | #define mmCB_COLOR2_CMASK 0xa33d | ||
| 100 | #define mmCB_COLOR3_CMASK 0xa34c | ||
| 101 | #define mmCB_COLOR4_CMASK 0xa35b | ||
| 102 | #define mmCB_COLOR5_CMASK 0xa36a | ||
| 103 | #define mmCB_COLOR6_CMASK 0xa379 | ||
| 104 | #define mmCB_COLOR7_CMASK 0xa388 | ||
| 105 | #define mmCB_COLOR0_CMASK_SLICE 0xa320 | ||
| 106 | #define mmCB_COLOR1_CMASK_SLICE 0xa32f | ||
| 107 | #define mmCB_COLOR2_CMASK_SLICE 0xa33e | ||
| 108 | #define mmCB_COLOR3_CMASK_SLICE 0xa34d | ||
| 109 | #define mmCB_COLOR4_CMASK_SLICE 0xa35c | ||
| 110 | #define mmCB_COLOR5_CMASK_SLICE 0xa36b | ||
| 111 | #define mmCB_COLOR6_CMASK_SLICE 0xa37a | ||
| 112 | #define mmCB_COLOR7_CMASK_SLICE 0xa389 | ||
| 113 | #define mmCB_COLOR0_FMASK 0xa321 | ||
| 114 | #define mmCB_COLOR1_FMASK 0xa330 | ||
| 115 | #define mmCB_COLOR2_FMASK 0xa33f | ||
| 116 | #define mmCB_COLOR3_FMASK 0xa34e | ||
| 117 | #define mmCB_COLOR4_FMASK 0xa35d | ||
| 118 | #define mmCB_COLOR5_FMASK 0xa36c | ||
| 119 | #define mmCB_COLOR6_FMASK 0xa37b | ||
| 120 | #define mmCB_COLOR7_FMASK 0xa38a | ||
| 121 | #define mmCB_COLOR0_FMASK_SLICE 0xa322 | ||
| 122 | #define mmCB_COLOR1_FMASK_SLICE 0xa331 | ||
| 123 | #define mmCB_COLOR2_FMASK_SLICE 0xa340 | ||
| 124 | #define mmCB_COLOR3_FMASK_SLICE 0xa34f | ||
| 125 | #define mmCB_COLOR4_FMASK_SLICE 0xa35e | ||
| 126 | #define mmCB_COLOR5_FMASK_SLICE 0xa36d | ||
| 127 | #define mmCB_COLOR6_FMASK_SLICE 0xa37c | ||
| 128 | #define mmCB_COLOR7_FMASK_SLICE 0xa38b | ||
| 129 | #define mmCB_COLOR0_CLEAR_WORD0 0xa323 | ||
| 130 | #define mmCB_COLOR1_CLEAR_WORD0 0xa332 | ||
| 131 | #define mmCB_COLOR2_CLEAR_WORD0 0xa341 | ||
| 132 | #define mmCB_COLOR3_CLEAR_WORD0 0xa350 | ||
| 133 | #define mmCB_COLOR4_CLEAR_WORD0 0xa35f | ||
| 134 | #define mmCB_COLOR5_CLEAR_WORD0 0xa36e | ||
| 135 | #define mmCB_COLOR6_CLEAR_WORD0 0xa37d | ||
| 136 | #define mmCB_COLOR7_CLEAR_WORD0 0xa38c | ||
| 137 | #define mmCB_COLOR0_CLEAR_WORD1 0xa324 | ||
| 138 | #define mmCB_COLOR1_CLEAR_WORD1 0xa333 | ||
| 139 | #define mmCB_COLOR2_CLEAR_WORD1 0xa342 | ||
| 140 | #define mmCB_COLOR3_CLEAR_WORD1 0xa351 | ||
| 141 | #define mmCB_COLOR4_CLEAR_WORD1 0xa360 | ||
| 142 | #define mmCB_COLOR5_CLEAR_WORD1 0xa36f | ||
| 143 | #define mmCB_COLOR6_CLEAR_WORD1 0xa37e | ||
| 144 | #define mmCB_COLOR7_CLEAR_WORD1 0xa38d | ||
| 145 | #define mmCB_COLOR0_DCC_BASE 0xa325 | ||
| 146 | #define mmCB_COLOR1_DCC_BASE 0xa334 | ||
| 147 | #define mmCB_COLOR2_DCC_BASE 0xa343 | ||
| 148 | #define mmCB_COLOR3_DCC_BASE 0xa352 | ||
| 149 | #define mmCB_COLOR4_DCC_BASE 0xa361 | ||
| 150 | #define mmCB_COLOR5_DCC_BASE 0xa370 | ||
| 151 | #define mmCB_COLOR6_DCC_BASE 0xa37f | ||
| 152 | #define mmCB_COLOR7_DCC_BASE 0xa38e | ||
| 153 | #define mmCB_TARGET_MASK 0xa08e | ||
| 154 | #define mmCB_SHADER_MASK 0xa08f | ||
| 155 | #define mmCB_HW_CONTROL 0x2684 | ||
| 156 | #define mmCB_HW_CONTROL_1 0x2685 | ||
| 157 | #define mmCB_HW_CONTROL_2 0x2686 | ||
| 158 | #define mmCB_HW_CONTROL_3 0x2683 | ||
| 159 | #define mmCB_DCC_CONFIG 0x2687 | ||
| 160 | #define mmCB_PERFCOUNTER_FILTER 0xdc00 | ||
| 161 | #define mmCB_PERFCOUNTER0_SELECT 0xdc01 | ||
| 162 | #define mmCB_PERFCOUNTER0_SELECT1 0xdc02 | ||
| 163 | #define mmCB_PERFCOUNTER1_SELECT 0xdc03 | ||
| 164 | #define mmCB_PERFCOUNTER2_SELECT 0xdc04 | ||
| 165 | #define mmCB_PERFCOUNTER3_SELECT 0xdc05 | ||
| 166 | #define mmCB_PERFCOUNTER0_LO 0xd406 | ||
| 167 | #define mmCB_PERFCOUNTER1_LO 0xd408 | ||
| 168 | #define mmCB_PERFCOUNTER2_LO 0xd40a | ||
| 169 | #define mmCB_PERFCOUNTER3_LO 0xd40c | ||
| 170 | #define mmCB_PERFCOUNTER0_HI 0xd407 | ||
| 171 | #define mmCB_PERFCOUNTER1_HI 0xd409 | ||
| 172 | #define mmCB_PERFCOUNTER2_HI 0xd40b | ||
| 173 | #define mmCB_PERFCOUNTER3_HI 0xd40d | ||
| 174 | #define mmCB_CGTT_SCLK_CTRL 0xf0a8 | ||
| 175 | #define mmCB_DEBUG_BUS_1 0x2699 | ||
| 176 | #define mmCB_DEBUG_BUS_2 0x269a | ||
| 177 | #define mmCB_DEBUG_BUS_3 0x269b | ||
| 178 | #define mmCB_DEBUG_BUS_4 0x269c | ||
| 179 | #define mmCB_DEBUG_BUS_5 0x269d | ||
| 180 | #define mmCB_DEBUG_BUS_6 0x269e | ||
| 181 | #define mmCB_DEBUG_BUS_7 0x269f | ||
| 182 | #define mmCB_DEBUG_BUS_8 0x26a0 | ||
| 183 | #define mmCB_DEBUG_BUS_9 0x26a1 | ||
| 184 | #define mmCB_DEBUG_BUS_10 0x26a2 | ||
| 185 | #define mmCB_DEBUG_BUS_11 0x26a3 | ||
| 186 | #define mmCB_DEBUG_BUS_12 0x26a4 | ||
| 187 | #define mmCB_DEBUG_BUS_13 0x26a5 | ||
| 188 | #define mmCB_DEBUG_BUS_14 0x26a6 | ||
| 189 | #define mmCB_DEBUG_BUS_15 0x26a7 | ||
| 190 | #define mmCB_DEBUG_BUS_16 0x26a8 | ||
| 191 | #define mmCB_DEBUG_BUS_17 0x26a9 | ||
| 192 | #define mmCB_DEBUG_BUS_18 0x26aa | ||
| 193 | #define mmCB_DEBUG_BUS_19 0x26ab | ||
| 194 | #define mmCB_DEBUG_BUS_20 0x26ac | ||
| 195 | #define mmCB_DEBUG_BUS_21 0x26ad | ||
| 196 | #define mmCB_DEBUG_BUS_22 0x26ae | ||
| 197 | #define mmCP_DFY_CNTL 0x3020 | ||
| 198 | #define mmCP_DFY_STAT 0x3021 | ||
| 199 | #define mmCP_DFY_ADDR_HI 0x3022 | ||
| 200 | #define mmCP_DFY_ADDR_LO 0x3023 | ||
| 201 | #define mmCP_DFY_DATA_0 0x3024 | ||
| 202 | #define mmCP_DFY_DATA_1 0x3025 | ||
| 203 | #define mmCP_DFY_DATA_2 0x3026 | ||
| 204 | #define mmCP_DFY_DATA_3 0x3027 | ||
| 205 | #define mmCP_DFY_DATA_4 0x3028 | ||
| 206 | #define mmCP_DFY_DATA_5 0x3029 | ||
| 207 | #define mmCP_DFY_DATA_6 0x302a | ||
| 208 | #define mmCP_DFY_DATA_7 0x302b | ||
| 209 | #define mmCP_DFY_DATA_8 0x302c | ||
| 210 | #define mmCP_DFY_DATA_9 0x302d | ||
| 211 | #define mmCP_DFY_DATA_10 0x302e | ||
| 212 | #define mmCP_DFY_DATA_11 0x302f | ||
| 213 | #define mmCP_DFY_DATA_12 0x3030 | ||
| 214 | #define mmCP_DFY_DATA_13 0x3031 | ||
| 215 | #define mmCP_DFY_DATA_14 0x3032 | ||
| 216 | #define mmCP_DFY_DATA_15 0x3033 | ||
| 217 | #define mmCP_DFY_CMD 0x3034 | ||
| 218 | #define mmCP_CPC_MGCG_SYNC_CNTL 0x3036 | ||
| 219 | #define mmCP_ATCL1_CNTL 0x303c | ||
| 220 | #define mmCP_RB0_BASE 0x3040 | ||
| 221 | #define mmCP_RB0_BASE_HI 0x30b1 | ||
| 222 | #define mmCP_RB_BASE 0x3040 | ||
| 223 | #define mmCP_RB1_BASE 0x3060 | ||
| 224 | #define mmCP_RB1_BASE_HI 0x30b2 | ||
| 225 | #define mmCP_RB2_BASE 0x3065 | ||
| 226 | #define mmCP_RB0_CNTL 0x3041 | ||
| 227 | #define mmCP_RB_CNTL 0x3041 | ||
| 228 | #define mmCP_RB1_CNTL 0x3061 | ||
| 229 | #define mmCP_RB2_CNTL 0x3066 | ||
| 230 | #define mmCP_RB_RPTR_WR 0x3042 | ||
| 231 | #define mmCP_RB0_RPTR_ADDR 0x3043 | ||
| 232 | #define mmCP_RB_RPTR_ADDR 0x3043 | ||
| 233 | #define mmCP_RB1_RPTR_ADDR 0x3062 | ||
| 234 | #define mmCP_RB2_RPTR_ADDR 0x3067 | ||
| 235 | #define mmCP_RB0_RPTR_ADDR_HI 0x3044 | ||
| 236 | #define mmCP_RB_RPTR_ADDR_HI 0x3044 | ||
| 237 | #define mmCP_RB1_RPTR_ADDR_HI 0x3063 | ||
| 238 | #define mmCP_RB2_RPTR_ADDR_HI 0x3068 | ||
| 239 | #define mmCP_RB0_WPTR 0x3045 | ||
| 240 | #define mmCP_RB_WPTR 0x3045 | ||
| 241 | #define mmCP_RB1_WPTR 0x3064 | ||
| 242 | #define mmCP_RB2_WPTR 0x3069 | ||
| 243 | #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 | ||
| 244 | #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 | ||
| 245 | #define mmGC_PRIV_MODE 0x3048 | ||
| 246 | #define mmCP_INT_CNTL 0x3049 | ||
| 247 | #define mmCP_INT_CNTL_RING0 0x306a | ||
| 248 | #define mmCP_INT_CNTL_RING1 0x306b | ||
| 249 | #define mmCP_INT_CNTL_RING2 0x306c | ||
| 250 | #define mmCP_INT_STATUS 0x304a | ||
| 251 | #define mmCP_INT_STATUS_RING0 0x306d | ||
| 252 | #define mmCP_INT_STATUS_RING1 0x306e | ||
| 253 | #define mmCP_INT_STATUS_RING2 0x306f | ||
| 254 | #define mmCP_DEVICE_ID 0x304b | ||
| 255 | #define mmCP_RING_PRIORITY_CNTS 0x304c | ||
| 256 | #define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c | ||
| 257 | #define mmCP_RING0_PRIORITY 0x304d | ||
| 258 | #define mmCP_ME0_PIPE0_PRIORITY 0x304d | ||
| 259 | #define mmCP_RING1_PRIORITY 0x304e | ||
| 260 | #define mmCP_ME0_PIPE1_PRIORITY 0x304e | ||
| 261 | #define mmCP_RING2_PRIORITY 0x304f | ||
| 262 | #define mmCP_ME0_PIPE2_PRIORITY 0x304f | ||
| 263 | #define mmCP_ENDIAN_SWAP 0x3050 | ||
| 264 | #define mmCP_RB_VMID 0x3051 | ||
| 265 | #define mmCP_ME0_PIPE0_VMID 0x3052 | ||
| 266 | #define mmCP_ME0_PIPE1_VMID 0x3053 | ||
| 267 | #define mmCP_RB_DOORBELL_CONTROL 0x3059 | ||
| 268 | #define mmCP_RB_DOORBELL_RANGE_LOWER 0x305a | ||
| 269 | #define mmCP_RB_DOORBELL_RANGE_UPPER 0x305b | ||
| 270 | #define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305c | ||
| 271 | #define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305d | ||
| 272 | #define mmCP_PFP_UCODE_ADDR 0xf814 | ||
| 273 | #define mmCP_PFP_UCODE_DATA 0xf815 | ||
| 274 | #define mmCP_ME_RAM_RADDR 0xf816 | ||
| 275 | #define mmCP_ME_RAM_WADDR 0xf816 | ||
| 276 | #define mmCP_ME_RAM_DATA 0xf817 | ||
| 277 | #define mmCGTT_CPC_CLK_CTRL 0xf0b2 | ||
| 278 | #define mmCGTT_CPF_CLK_CTRL 0xf0b1 | ||
| 279 | #define mmCGTT_CP_CLK_CTRL 0xf0b0 | ||
| 280 | #define mmCP_CE_UCODE_ADDR 0xf818 | ||
| 281 | #define mmCP_CE_UCODE_DATA 0xf819 | ||
| 282 | #define mmCP_MEC_ME1_UCODE_ADDR 0xf81a | ||
| 283 | #define mmCP_MEC_ME1_UCODE_DATA 0xf81b | ||
| 284 | #define mmCP_MEC_ME2_UCODE_ADDR 0xf81c | ||
| 285 | #define mmCP_MEC_ME2_UCODE_DATA 0xf81d | ||
| 286 | #define mmCP_MEC1_F32_INT_DIS 0x30bd | ||
| 287 | #define mmCP_MEC2_F32_INT_DIS 0x30be | ||
| 288 | #define mmCP_PWR_CNTL 0x3078 | ||
| 289 | #define mmCP_MEM_SLP_CNTL 0x3079 | ||
| 290 | #define mmCP_ECC_FIRSTOCCURRENCE 0x307a | ||
| 291 | #define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b | ||
| 292 | #define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c | ||
| 293 | #define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d | ||
| 294 | #define mmCP_CPF_DEBUG 0x3080 | ||
| 295 | #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 | ||
| 296 | #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 | ||
| 297 | #define mmCPC_INT_CNTL 0x30b4 | ||
| 298 | #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 | ||
| 299 | #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 | ||
| 300 | #define mmCP_ME1_PIPE2_INT_CNTL 0x3087 | ||
| 301 | #define mmCP_ME1_PIPE3_INT_CNTL 0x3088 | ||
| 302 | #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 | ||
| 303 | #define mmCP_ME2_PIPE1_INT_CNTL 0x308a | ||
| 304 | #define mmCP_ME2_PIPE2_INT_CNTL 0x308b | ||
| 305 | #define mmCP_ME2_PIPE3_INT_CNTL 0x308c | ||
| 306 | #define mmCPC_INT_STATUS 0x30b5 | ||
| 307 | #define mmCP_ME1_PIPE0_INT_STATUS 0x308d | ||
| 308 | #define mmCP_ME1_PIPE1_INT_STATUS 0x308e | ||
| 309 | #define mmCP_ME1_PIPE2_INT_STATUS 0x308f | ||
| 310 | #define mmCP_ME1_PIPE3_INT_STATUS 0x3090 | ||
| 311 | #define mmCP_ME2_PIPE0_INT_STATUS 0x3091 | ||
| 312 | #define mmCP_ME2_PIPE1_INT_STATUS 0x3092 | ||
| 313 | #define mmCP_ME2_PIPE2_INT_STATUS 0x3093 | ||
| 314 | #define mmCP_ME2_PIPE3_INT_STATUS 0x3094 | ||
| 315 | #define mmCP_ME1_INT_STAT_DEBUG 0x3095 | ||
| 316 | #define mmCP_ME2_INT_STAT_DEBUG 0x3096 | ||
| 317 | #define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 | ||
| 318 | #define mmCP_ME1_PIPE0_PRIORITY 0x309a | ||
| 319 | #define mmCP_ME1_PIPE1_PRIORITY 0x309b | ||
| 320 | #define mmCP_ME1_PIPE2_PRIORITY 0x309c | ||
| 321 | #define mmCP_ME1_PIPE3_PRIORITY 0x309d | ||
| 322 | #define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e | ||
| 323 | #define mmCP_ME2_PIPE0_PRIORITY 0x309f | ||
| 324 | #define mmCP_ME2_PIPE1_PRIORITY 0x30a0 | ||
| 325 | #define mmCP_ME2_PIPE2_PRIORITY 0x30a1 | ||
| 326 | #define mmCP_ME2_PIPE3_PRIORITY 0x30a2 | ||
| 327 | #define mmCP_CE_PRGRM_CNTR_START 0x30a3 | ||
| 328 | #define mmCP_PFP_PRGRM_CNTR_START 0x30a4 | ||
| 329 | #define mmCP_ME_PRGRM_CNTR_START 0x30a5 | ||
| 330 | #define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 | ||
| 331 | #define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 | ||
| 332 | #define mmCP_CE_INTR_ROUTINE_START 0x30a8 | ||
| 333 | #define mmCP_PFP_INTR_ROUTINE_START 0x30a9 | ||
| 334 | #define mmCP_ME_INTR_ROUTINE_START 0x30aa | ||
| 335 | #define mmCP_MEC1_INTR_ROUTINE_START 0x30ab | ||
| 336 | #define mmCP_MEC2_INTR_ROUTINE_START 0x30ac | ||
| 337 | #define mmCP_CONTEXT_CNTL 0x30ad | ||
| 338 | #define mmCP_MAX_CONTEXT 0x30ae | ||
| 339 | #define mmCP_IQ_WAIT_TIME1 0x30af | ||
| 340 | #define mmCP_IQ_WAIT_TIME2 0x30b0 | ||
| 341 | #define mmCP_VMID_RESET 0x30b3 | ||
| 342 | #define mmCP_VMID_PREEMPT 0x30b6 | ||
| 343 | #define mmCP_VMID_STATUS 0x30bf | ||
| 344 | #define mmCPC_INT_CNTX_ID 0x30b7 | ||
| 345 | #define mmCP_PQ_STATUS 0x30b8 | ||
| 346 | #define mmCP_CPC_IC_BASE_LO 0x30b9 | ||
| 347 | #define mmCP_CPC_IC_BASE_HI 0x30ba | ||
| 348 | #define mmCP_CPC_IC_BASE_CNTL 0x30bb | ||
| 349 | #define mmCP_CPC_IC_OP_CNTL 0x30bc | ||
| 350 | #define mmCP_CPC_STATUS 0x2084 | ||
| 351 | #define mmCP_CPC_BUSY_STAT 0x2085 | ||
| 352 | #define mmCP_CPC_STALLED_STAT1 0x2086 | ||
| 353 | #define mmCP_CPF_STATUS 0x2087 | ||
| 354 | #define mmCP_CPF_BUSY_STAT 0x2088 | ||
| 355 | #define mmCP_CPF_STALLED_STAT1 0x2089 | ||
| 356 | #define mmCP_CPC_GRBM_FREE_COUNT 0x208b | ||
| 357 | #define mmCP_MEC_CNTL 0x208d | ||
| 358 | #define mmCP_MEC_ME1_HEADER_DUMP 0x208e | ||
| 359 | #define mmCP_MEC_ME2_HEADER_DUMP 0x208f | ||
| 360 | #define mmCP_CPC_SCRATCH_INDEX 0x2090 | ||
| 361 | #define mmCP_CPC_SCRATCH_DATA 0x2091 | ||
| 362 | #define mmCPG_PERFCOUNTER1_SELECT 0xd800 | ||
| 363 | #define mmCPG_PERFCOUNTER1_LO 0xd000 | ||
| 364 | #define mmCPG_PERFCOUNTER1_HI 0xd001 | ||
| 365 | #define mmCPG_PERFCOUNTER0_SELECT1 0xd801 | ||
| 366 | #define mmCPG_PERFCOUNTER0_SELECT 0xd802 | ||
| 367 | #define mmCPG_PERFCOUNTER0_LO 0xd002 | ||
| 368 | #define mmCPG_PERFCOUNTER0_HI 0xd003 | ||
| 369 | #define mmCPC_PERFCOUNTER1_SELECT 0xd803 | ||
| 370 | #define mmCPC_PERFCOUNTER1_LO 0xd004 | ||
| 371 | #define mmCPC_PERFCOUNTER1_HI 0xd005 | ||
| 372 | #define mmCPC_PERFCOUNTER0_SELECT1 0xd804 | ||
| 373 | #define mmCPC_PERFCOUNTER0_SELECT 0xd809 | ||
| 374 | #define mmCPC_PERFCOUNTER0_LO 0xd006 | ||
| 375 | #define mmCPC_PERFCOUNTER0_HI 0xd007 | ||
| 376 | #define mmCPF_PERFCOUNTER1_SELECT 0xd805 | ||
| 377 | #define mmCPF_PERFCOUNTER1_LO 0xd008 | ||
| 378 | #define mmCPF_PERFCOUNTER1_HI 0xd009 | ||
| 379 | #define mmCPF_PERFCOUNTER0_SELECT1 0xd806 | ||
| 380 | #define mmCPF_PERFCOUNTER0_SELECT 0xd807 | ||
| 381 | #define mmCPF_PERFCOUNTER0_LO 0xd00a | ||
| 382 | #define mmCPF_PERFCOUNTER0_HI 0xd00b | ||
| 383 | #define mmCP_CPC_HALT_HYST_COUNT 0x20a7 | ||
| 384 | #define mmCP_DRAW_OBJECT 0xd810 | ||
| 385 | #define mmCP_DRAW_OBJECT_COUNTER 0xd811 | ||
| 386 | #define mmCP_DRAW_WINDOW_MASK_HI 0xd812 | ||
| 387 | #define mmCP_DRAW_WINDOW_HI 0xd813 | ||
| 388 | #define mmCP_DRAW_WINDOW_LO 0xd814 | ||
| 389 | #define mmCP_DRAW_WINDOW_CNTL 0xd815 | ||
| 390 | #define mmCP_PRT_LOD_STATS_CNTL0 0x20ad | ||
| 391 | #define mmCP_PRT_LOD_STATS_CNTL1 0x20ae | ||
| 392 | #define mmCP_PRT_LOD_STATS_CNTL2 0x20af | ||
| 393 | #define mmCP_CE_COMPARE_COUNT 0x20c0 | ||
| 394 | #define mmCP_CE_DE_COUNT 0x20c1 | ||
| 395 | #define mmCP_DE_CE_COUNT 0x20c2 | ||
| 396 | #define mmCP_DE_LAST_INVAL_COUNT 0x20c3 | ||
| 397 | #define mmCP_DE_DE_COUNT 0x20c4 | ||
| 398 | #define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 | ||
| 399 | #define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 | ||
| 400 | #define mmCP_EOP_DONE_CNTX_ID 0xc0d7 | ||
| 401 | #define mmCP_EOP_DONE_ADDR_LO 0xc000 | ||
| 402 | #define mmCP_EOP_DONE_ADDR_HI 0xc001 | ||
| 403 | #define mmCP_EOP_DONE_DATA_LO 0xc002 | ||
| 404 | #define mmCP_EOP_DONE_DATA_HI 0xc003 | ||
| 405 | #define mmCP_EOP_LAST_FENCE_LO 0xc004 | ||
| 406 | #define mmCP_EOP_LAST_FENCE_HI 0xc005 | ||
| 407 | #define mmCP_STREAM_OUT_ADDR_LO 0xc006 | ||
| 408 | #define mmCP_STREAM_OUT_ADDR_HI 0xc007 | ||
| 409 | #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 | ||
| 410 | #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 | ||
| 411 | #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a | ||
| 412 | #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b | ||
| 413 | #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c | ||
| 414 | #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d | ||
| 415 | #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e | ||
| 416 | #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f | ||
| 417 | #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 | ||
| 418 | #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 | ||
| 419 | #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 | ||
| 420 | #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 | ||
| 421 | #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 | ||
| 422 | #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 | ||
| 423 | #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 | ||
| 424 | #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 | ||
| 425 | #define mmCP_PIPE_STATS_ADDR_LO 0xc018 | ||
| 426 | #define mmCP_PIPE_STATS_ADDR_HI 0xc019 | ||
| 427 | #define mmCP_VGT_IAVERT_COUNT_LO 0xc01a | ||
| 428 | #define mmCP_VGT_IAVERT_COUNT_HI 0xc01b | ||
| 429 | #define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c | ||
| 430 | #define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d | ||
| 431 | #define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e | ||
| 432 | #define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f | ||
| 433 | #define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 | ||
| 434 | #define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 | ||
| 435 | #define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 | ||
| 436 | #define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 | ||
| 437 | #define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 | ||
| 438 | #define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 | ||
| 439 | #define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 | ||
| 440 | #define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 | ||
| 441 | #define mmCP_PA_CINVOC_COUNT_LO 0xc028 | ||
| 442 | #define mmCP_PA_CINVOC_COUNT_HI 0xc029 | ||
| 443 | #define mmCP_PA_CPRIM_COUNT_LO 0xc02a | ||
| 444 | #define mmCP_PA_CPRIM_COUNT_HI 0xc02b | ||
| 445 | #define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c | ||
| 446 | #define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d | ||
| 447 | #define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e | ||
| 448 | #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f | ||
| 449 | #define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 | ||
| 450 | #define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 | ||
| 451 | #define mmCP_PIPE_STATS_CONTROL 0xc03d | ||
| 452 | #define mmCP_STREAM_OUT_CONTROL 0xc03e | ||
| 453 | #define mmCP_STRMOUT_CNTL 0xc03f | ||
| 454 | #define mmSCRATCH_REG0 0xc040 | ||
| 455 | #define mmSCRATCH_REG1 0xc041 | ||
| 456 | #define mmSCRATCH_REG2 0xc042 | ||
| 457 | #define mmSCRATCH_REG3 0xc043 | ||
| 458 | #define mmSCRATCH_REG4 0xc044 | ||
| 459 | #define mmSCRATCH_REG5 0xc045 | ||
| 460 | #define mmSCRATCH_REG6 0xc046 | ||
| 461 | #define mmSCRATCH_REG7 0xc047 | ||
| 462 | #define mmSCRATCH_UMSK 0xc050 | ||
| 463 | #define mmSCRATCH_ADDR 0xc051 | ||
| 464 | #define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 | ||
| 465 | #define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 | ||
| 466 | #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 | ||
| 467 | #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 | ||
| 468 | #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 | ||
| 469 | #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 | ||
| 470 | #define mmCP_APPEND_ADDR_LO 0xc058 | ||
| 471 | #define mmCP_APPEND_ADDR_HI 0xc059 | ||
| 472 | #define mmCP_APPEND_DATA 0xc05a | ||
| 473 | #define mmCP_APPEND_LAST_CS_FENCE 0xc05b | ||
| 474 | #define mmCP_APPEND_LAST_PS_FENCE 0xc05c | ||
| 475 | #define mmCP_ATOMIC_PREOP_LO 0xc05d | ||
| 476 | #define mmCP_ME_ATOMIC_PREOP_LO 0xc05d | ||
| 477 | #define mmCP_ATOMIC_PREOP_HI 0xc05e | ||
| 478 | #define mmCP_ME_ATOMIC_PREOP_HI 0xc05e | ||
| 479 | #define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f | ||
| 480 | #define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f | ||
| 481 | #define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 | ||
| 482 | #define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 | ||
| 483 | #define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 | ||
| 484 | #define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 | ||
| 485 | #define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 | ||
| 486 | #define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 | ||
| 487 | #define mmCP_ME_MC_WADDR_LO 0xc069 | ||
| 488 | #define mmCP_ME_MC_WADDR_HI 0xc06a | ||
| 489 | #define mmCP_ME_MC_WDATA_LO 0xc06b | ||
| 490 | #define mmCP_ME_MC_WDATA_HI 0xc06c | ||
| 491 | #define mmCP_ME_MC_RADDR_LO 0xc06d | ||
| 492 | #define mmCP_ME_MC_RADDR_HI 0xc06e | ||
| 493 | #define mmCP_SEM_WAIT_TIMER 0xc06f | ||
| 494 | #define mmCP_SIG_SEM_ADDR_LO 0xc070 | ||
| 495 | #define mmCP_SIG_SEM_ADDR_HI 0xc071 | ||
| 496 | #define mmCP_WAIT_SEM_ADDR_LO 0xc075 | ||
| 497 | #define mmCP_WAIT_SEM_ADDR_HI 0xc076 | ||
| 498 | #define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 | ||
| 499 | #define mmCP_COHER_START_DELAY 0xc07b | ||
| 500 | #define mmCP_COHER_CNTL 0xc07c | ||
| 501 | #define mmCP_COHER_SIZE 0xc07d | ||
| 502 | #define mmCP_COHER_SIZE_HI 0xc08c | ||
| 503 | #define mmCP_COHER_BASE 0xc07e | ||
| 504 | #define mmCP_COHER_BASE_HI 0xc079 | ||
| 505 | #define mmCP_COHER_STATUS 0xc07f | ||
| 506 | #define mmCOHER_DEST_BASE_0 0xa092 | ||
| 507 | #define mmCOHER_DEST_BASE_1 0xa093 | ||
| 508 | #define mmCOHER_DEST_BASE_2 0xa07e | ||
| 509 | #define mmCOHER_DEST_BASE_3 0xa07f | ||
| 510 | #define mmCOHER_DEST_BASE_HI_0 0xa07a | ||
| 511 | #define mmCOHER_DEST_BASE_HI_1 0xa07b | ||
| 512 | #define mmCOHER_DEST_BASE_HI_2 0xa07c | ||
| 513 | #define mmCOHER_DEST_BASE_HI_3 0xa07d | ||
| 514 | #define mmCP_DMA_ME_SRC_ADDR 0xc080 | ||
| 515 | #define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 | ||
| 516 | #define mmCP_DMA_ME_DST_ADDR 0xc082 | ||
| 517 | #define mmCP_DMA_ME_DST_ADDR_HI 0xc083 | ||
| 518 | #define mmCP_DMA_ME_CONTROL 0xc078 | ||
| 519 | #define mmCP_DMA_ME_COMMAND 0xc084 | ||
| 520 | #define mmCP_DMA_PFP_SRC_ADDR 0xc085 | ||
| 521 | #define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 | ||
| 522 | #define mmCP_DMA_PFP_DST_ADDR 0xc087 | ||
| 523 | #define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 | ||
| 524 | #define mmCP_DMA_PFP_CONTROL 0xc077 | ||
| 525 | #define mmCP_DMA_PFP_COMMAND 0xc089 | ||
| 526 | #define mmCP_DMA_CNTL 0xc08a | ||
| 527 | #define mmCP_DMA_READ_TAGS 0xc08b | ||
| 528 | #define mmCP_PFP_IB_CONTROL 0xc08d | ||
| 529 | #define mmCP_PFP_LOAD_CONTROL 0xc08e | ||
| 530 | #define mmCP_SCRATCH_INDEX 0xc08f | ||
| 531 | #define mmCP_SCRATCH_DATA 0xc090 | ||
| 532 | #define mmCP_RB_OFFSET 0xc091 | ||
| 533 | #define mmCP_IB1_OFFSET 0xc092 | ||
| 534 | #define mmCP_IB2_OFFSET 0xc093 | ||
| 535 | #define mmCP_IB1_PREAMBLE_BEGIN 0xc094 | ||
| 536 | #define mmCP_IB1_PREAMBLE_END 0xc095 | ||
| 537 | #define mmCP_IB2_PREAMBLE_BEGIN 0xc096 | ||
| 538 | #define mmCP_IB2_PREAMBLE_END 0xc097 | ||
| 539 | #define mmCP_CE_IB1_OFFSET 0xc098 | ||
| 540 | #define mmCP_CE_IB2_OFFSET 0xc099 | ||
| 541 | #define mmCP_CE_COUNTER 0xc09a | ||
| 542 | #define mmCP_CE_RB_OFFSET 0xc09b | ||
| 543 | #define mmCP_PFP_COMPLETION_STATUS 0xc0ec | ||
| 544 | #define mmCP_CE_COMPLETION_STATUS 0xc0ed | ||
| 545 | #define mmCP_PRED_NOT_VISIBLE 0xc0ee | ||
| 546 | #define mmCP_PFP_METADATA_BASE_ADDR 0xc0f0 | ||
| 547 | #define mmCP_PFP_METADATA_BASE_ADDR_HI 0xc0f1 | ||
| 548 | #define mmCP_CE_METADATA_BASE_ADDR 0xc0f2 | ||
| 549 | #define mmCP_CE_METADATA_BASE_ADDR_HI 0xc0f3 | ||
| 550 | #define mmCP_DRAW_INDX_INDR_ADDR 0xc0f4 | ||
| 551 | #define mmCP_DRAW_INDX_INDR_ADDR_HI 0xc0f5 | ||
| 552 | #define mmCP_DISPATCH_INDR_ADDR 0xc0f6 | ||
| 553 | #define mmCP_DISPATCH_INDR_ADDR_HI 0xc0f7 | ||
| 554 | #define mmCP_INDEX_BASE_ADDR 0xc0f8 | ||
| 555 | #define mmCP_INDEX_BASE_ADDR_HI 0xc0f9 | ||
| 556 | #define mmCP_INDEX_TYPE 0xc0fa | ||
| 557 | #define mmCP_GDS_BKUP_ADDR 0xc0fb | ||
| 558 | #define mmCP_GDS_BKUP_ADDR_HI 0xc0fc | ||
| 559 | #define mmCP_SAMPLE_STATUS 0xc0fd | ||
| 560 | #define mmCP_STALLED_STAT1 0x219d | ||
| 561 | #define mmCP_STALLED_STAT2 0x219e | ||
| 562 | #define mmCP_STALLED_STAT3 0x219c | ||
| 563 | #define mmCP_BUSY_STAT 0x219f | ||
| 564 | #define mmCP_STAT 0x21a0 | ||
| 565 | #define mmCP_ME_HEADER_DUMP 0x21a1 | ||
| 566 | #define mmCP_PFP_HEADER_DUMP 0x21a2 | ||
| 567 | #define mmCP_GRBM_FREE_COUNT 0x21a3 | ||
| 568 | #define mmCP_CE_HEADER_DUMP 0x21a4 | ||
| 569 | #define mmCP_CSF_STAT 0x21b4 | ||
| 570 | #define mmCP_CSF_CNTL 0x21b5 | ||
| 571 | #define mmCP_ME_CNTL 0x21b6 | ||
| 572 | #define mmCP_CNTX_STAT 0x21b8 | ||
| 573 | #define mmCP_ME_PREEMPTION 0x21b9 | ||
| 574 | #define mmCP_RB0_RPTR 0x21c0 | ||
| 575 | #define mmCP_RB_RPTR 0x21c0 | ||
| 576 | #define mmCP_RB1_RPTR 0x21bf | ||
| 577 | #define mmCP_RB2_RPTR 0x21be | ||
| 578 | #define mmCP_RB_WPTR_DELAY 0x21c1 | ||
| 579 | #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 | ||
| 580 | #define mmCP_CE_INIT_BASE_LO 0xc0c3 | ||
| 581 | #define mmCP_CE_INIT_BASE_HI 0xc0c4 | ||
| 582 | #define mmCP_CE_INIT_BUFSZ 0xc0c5 | ||
| 583 | #define mmCP_CE_IB1_BASE_LO 0xc0c6 | ||
| 584 | #define mmCP_CE_IB1_BASE_HI 0xc0c7 | ||
| 585 | #define mmCP_CE_IB1_BUFSZ 0xc0c8 | ||
| 586 | #define mmCP_CE_IB2_BASE_LO 0xc0c9 | ||
| 587 | #define mmCP_CE_IB2_BASE_HI 0xc0ca | ||
| 588 | #define mmCP_CE_IB2_BUFSZ 0xc0cb | ||
| 589 | #define mmCP_IB1_BASE_LO 0xc0cc | ||
| 590 | #define mmCP_IB1_BASE_HI 0xc0cd | ||
| 591 | #define mmCP_IB1_BUFSZ 0xc0ce | ||
| 592 | #define mmCP_IB2_BASE_LO 0xc0cf | ||
| 593 | #define mmCP_IB2_BASE_HI 0xc0d0 | ||
| 594 | #define mmCP_IB2_BUFSZ 0xc0d1 | ||
| 595 | #define mmCP_ST_BASE_LO 0xc0d2 | ||
| 596 | #define mmCP_ST_BASE_HI 0xc0d3 | ||
| 597 | #define mmCP_ST_BUFSZ 0xc0d4 | ||
| 598 | #define mmCP_ROQ_THRESHOLDS 0x21bc | ||
| 599 | #define mmCP_MEQ_STQ_THRESHOLD 0x21bd | ||
| 600 | #define mmCP_ROQ1_THRESHOLDS 0x21d5 | ||
| 601 | #define mmCP_ROQ2_THRESHOLDS 0x21d6 | ||
| 602 | #define mmCP_STQ_THRESHOLDS 0x21d7 | ||
| 603 | #define mmCP_QUEUE_THRESHOLDS 0x21d8 | ||
| 604 | #define mmCP_MEQ_THRESHOLDS 0x21d9 | ||
| 605 | #define mmCP_ROQ_AVAIL 0x21da | ||
| 606 | #define mmCP_STQ_AVAIL 0x21db | ||
| 607 | #define mmCP_ROQ2_AVAIL 0x21dc | ||
| 608 | #define mmCP_MEQ_AVAIL 0x21dd | ||
| 609 | #define mmCP_CMD_INDEX 0x21de | ||
| 610 | #define mmCP_CMD_DATA 0x21df | ||
| 611 | #define mmCP_ROQ_RB_STAT 0x21e0 | ||
| 612 | #define mmCP_ROQ_IB1_STAT 0x21e1 | ||
| 613 | #define mmCP_ROQ_IB2_STAT 0x21e2 | ||
| 614 | #define mmCP_STQ_STAT 0x21e3 | ||
| 615 | #define mmCP_STQ_WR_STAT 0x21e4 | ||
| 616 | #define mmCP_MEQ_STAT 0x21e5 | ||
| 617 | #define mmCP_CEQ1_AVAIL 0x21e6 | ||
| 618 | #define mmCP_CEQ2_AVAIL 0x21e7 | ||
| 619 | #define mmCP_CE_ROQ_RB_STAT 0x21e8 | ||
| 620 | #define mmCP_CE_ROQ_IB1_STAT 0x21e9 | ||
| 621 | #define mmCP_CE_ROQ_IB2_STAT 0x21ea | ||
| 622 | #define mmCP_INT_STAT_DEBUG 0x21f7 | ||
| 623 | #define mmCP_PERFMON_CNTL 0xd808 | ||
| 624 | #define mmCP_PERFMON_CNTX_CNTL 0xa0d8 | ||
| 625 | #define mmCP_RINGID 0xa0d9 | ||
| 626 | #define mmCP_PIPEID 0xa0d9 | ||
| 627 | #define mmCP_VMID 0xa0da | ||
| 628 | #define mmCP_HPD_ROQ_OFFSETS 0x3240 | ||
| 629 | #define mmCP_HPD_STATUS0 0x3241 | ||
| 630 | #define mmCP_MQD_BASE_ADDR 0x3245 | ||
| 631 | #define mmCP_MQD_BASE_ADDR_HI 0x3246 | ||
| 632 | #define mmCP_HQD_ACTIVE 0x3247 | ||
| 633 | #define mmCP_HQD_VMID 0x3248 | ||
| 634 | #define mmCP_HQD_PERSISTENT_STATE 0x3249 | ||
| 635 | #define mmCP_HQD_PIPE_PRIORITY 0x324a | ||
| 636 | #define mmCP_HQD_QUEUE_PRIORITY 0x324b | ||
| 637 | #define mmCP_HQD_QUANTUM 0x324c | ||
| 638 | #define mmCP_HQD_PQ_BASE 0x324d | ||
| 639 | #define mmCP_HQD_PQ_BASE_HI 0x324e | ||
| 640 | #define mmCP_HQD_PQ_RPTR 0x324f | ||
| 641 | #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 | ||
| 642 | #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 | ||
| 643 | #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 | ||
| 644 | #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 | ||
| 645 | #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 | ||
| 646 | #define mmCP_HQD_PQ_WPTR 0x3255 | ||
| 647 | #define mmCP_HQD_PQ_CONTROL 0x3256 | ||
| 648 | #define mmCP_HQD_IB_BASE_ADDR 0x3257 | ||
| 649 | #define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 | ||
| 650 | #define mmCP_HQD_IB_RPTR 0x3259 | ||
| 651 | #define mmCP_HQD_IB_CONTROL 0x325a | ||
| 652 | #define mmCP_HQD_IQ_TIMER 0x325b | ||
| 653 | #define mmCP_HQD_IQ_RPTR 0x325c | ||
| 654 | #define mmCP_HQD_DEQUEUE_REQUEST 0x325d | ||
| 655 | #define mmCP_HQD_DMA_OFFLOAD 0x325e | ||
| 656 | #define mmCP_HQD_OFFLOAD 0x325e | ||
| 657 | #define mmCP_HQD_SEMA_CMD 0x325f | ||
| 658 | #define mmCP_HQD_MSG_TYPE 0x3260 | ||
| 659 | #define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 | ||
| 660 | #define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 | ||
| 661 | #define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 | ||
| 662 | #define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 | ||
| 663 | #define mmCP_HQD_HQ_SCHEDULER0 0x3265 | ||
| 664 | #define mmCP_HQD_HQ_STATUS0 0x3265 | ||
| 665 | #define mmCP_HQD_HQ_SCHEDULER1 0x3266 | ||
| 666 | #define mmCP_HQD_HQ_CONTROL0 0x3266 | ||
| 667 | #define mmCP_MQD_CONTROL 0x3267 | ||
| 668 | #define mmCP_HQD_HQ_STATUS1 0x3268 | ||
| 669 | #define mmCP_HQD_HQ_CONTROL1 0x3269 | ||
| 670 | #define mmCP_HQD_EOP_BASE_ADDR 0x326a | ||
| 671 | #define mmCP_HQD_EOP_BASE_ADDR_HI 0x326b | ||
| 672 | #define mmCP_HQD_EOP_CONTROL 0x326c | ||
| 673 | #define mmCP_HQD_EOP_RPTR 0x326d | ||
| 674 | #define mmCP_HQD_EOP_WPTR 0x326e | ||
| 675 | #define mmCP_HQD_EOP_EVENTS 0x326f | ||
| 676 | #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270 | ||
| 677 | #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271 | ||
| 678 | #define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 | ||
| 679 | #define mmCP_HQD_CNTL_STACK_OFFSET 0x3273 | ||
| 680 | #define mmCP_HQD_CNTL_STACK_SIZE 0x3274 | ||
| 681 | #define mmCP_HQD_WG_STATE_OFFSET 0x3275 | ||
| 682 | #define mmCP_HQD_CTX_SAVE_SIZE 0x3276 | ||
| 683 | #define mmCP_HQD_GDS_RESOURCE_STATE 0x3277 | ||
| 684 | #define mmCP_HQD_ERROR 0x3278 | ||
| 685 | #define mmCP_HQD_EOP_WPTR_MEM 0x3279 | ||
| 686 | #define mmCP_HQD_EOP_DONES 0x327a | ||
| 687 | #define mmDB_Z_READ_BASE 0xa012 | ||
| 688 | #define mmDB_STENCIL_READ_BASE 0xa013 | ||
| 689 | #define mmDB_Z_WRITE_BASE 0xa014 | ||
| 690 | #define mmDB_STENCIL_WRITE_BASE 0xa015 | ||
| 691 | #define mmDB_DEPTH_INFO 0xa00f | ||
| 692 | #define mmDB_Z_INFO 0xa010 | ||
| 693 | #define mmDB_STENCIL_INFO 0xa011 | ||
| 694 | #define mmDB_DEPTH_SIZE 0xa016 | ||
| 695 | #define mmDB_DEPTH_SLICE 0xa017 | ||
| 696 | #define mmDB_DEPTH_VIEW 0xa002 | ||
| 697 | #define mmDB_RENDER_CONTROL 0xa000 | ||
| 698 | #define mmDB_COUNT_CONTROL 0xa001 | ||
| 699 | #define mmDB_RENDER_OVERRIDE 0xa003 | ||
| 700 | #define mmDB_RENDER_OVERRIDE2 0xa004 | ||
| 701 | #define mmDB_EQAA 0xa201 | ||
| 702 | #define mmDB_SHADER_CONTROL 0xa203 | ||
| 703 | #define mmDB_DEPTH_BOUNDS_MIN 0xa008 | ||
| 704 | #define mmDB_DEPTH_BOUNDS_MAX 0xa009 | ||
| 705 | #define mmDB_STENCIL_CLEAR 0xa00a | ||
| 706 | #define mmDB_DEPTH_CLEAR 0xa00b | ||
| 707 | #define mmDB_HTILE_DATA_BASE 0xa005 | ||
| 708 | #define mmDB_HTILE_SURFACE 0xa2af | ||
| 709 | #define mmDB_PRELOAD_CONTROL 0xa2b2 | ||
| 710 | #define mmDB_STENCILREFMASK 0xa10c | ||
| 711 | #define mmDB_STENCILREFMASK_BF 0xa10d | ||
| 712 | #define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 | ||
| 713 | #define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 | ||
| 714 | #define mmDB_DEPTH_CONTROL 0xa200 | ||
| 715 | #define mmDB_STENCIL_CONTROL 0xa10b | ||
| 716 | #define mmDB_ALPHA_TO_MASK 0xa2dc | ||
| 717 | #define mmDB_PERFCOUNTER0_SELECT 0xdc40 | ||
| 718 | #define mmDB_PERFCOUNTER1_SELECT 0xdc42 | ||
| 719 | #define mmDB_PERFCOUNTER2_SELECT 0xdc44 | ||
| 720 | #define mmDB_PERFCOUNTER3_SELECT 0xdc46 | ||
| 721 | #define mmDB_PERFCOUNTER0_SELECT1 0xdc41 | ||
| 722 | #define mmDB_PERFCOUNTER1_SELECT1 0xdc43 | ||
| 723 | #define mmDB_PERFCOUNTER0_LO 0xd440 | ||
| 724 | #define mmDB_PERFCOUNTER1_LO 0xd442 | ||
| 725 | #define mmDB_PERFCOUNTER2_LO 0xd444 | ||
| 726 | #define mmDB_PERFCOUNTER3_LO 0xd446 | ||
| 727 | #define mmDB_PERFCOUNTER0_HI 0xd441 | ||
| 728 | #define mmDB_PERFCOUNTER1_HI 0xd443 | ||
| 729 | #define mmDB_PERFCOUNTER2_HI 0xd445 | ||
| 730 | #define mmDB_PERFCOUNTER3_HI 0xd447 | ||
| 731 | #define mmDB_DEBUG 0x260c | ||
| 732 | #define mmDB_DEBUG2 0x260d | ||
| 733 | #define mmDB_DEBUG3 0x260e | ||
| 734 | #define mmDB_DEBUG4 0x260f | ||
| 735 | #define mmDB_CREDIT_LIMIT 0x2614 | ||
| 736 | #define mmDB_WATERMARKS 0x2615 | ||
| 737 | #define mmDB_SUBTILE_CONTROL 0x2616 | ||
| 738 | #define mmDB_FREE_CACHELINES 0x2617 | ||
| 739 | #define mmDB_FIFO_DEPTH1 0x2618 | ||
| 740 | #define mmDB_FIFO_DEPTH2 0x2619 | ||
| 741 | #define mmDB_CGTT_CLK_CTRL_0 0xf0a4 | ||
| 742 | #define mmDB_ZPASS_COUNT_LOW 0xc3fe | ||
| 743 | #define mmDB_ZPASS_COUNT_HI 0xc3ff | ||
| 744 | #define mmDB_RING_CONTROL 0x261b | ||
| 745 | #define mmDB_READ_DEBUG_0 0x2620 | ||
| 746 | #define mmDB_READ_DEBUG_1 0x2621 | ||
| 747 | #define mmDB_READ_DEBUG_2 0x2622 | ||
| 748 | #define mmDB_READ_DEBUG_3 0x2623 | ||
| 749 | #define mmDB_READ_DEBUG_4 0x2624 | ||
| 750 | #define mmDB_READ_DEBUG_5 0x2625 | ||
| 751 | #define mmDB_READ_DEBUG_6 0x2626 | ||
| 752 | #define mmDB_READ_DEBUG_7 0x2627 | ||
| 753 | #define mmDB_READ_DEBUG_8 0x2628 | ||
| 754 | #define mmDB_READ_DEBUG_9 0x2629 | ||
| 755 | #define mmDB_READ_DEBUG_A 0x262a | ||
| 756 | #define mmDB_READ_DEBUG_B 0x262b | ||
| 757 | #define mmDB_READ_DEBUG_C 0x262c | ||
| 758 | #define mmDB_READ_DEBUG_D 0x262d | ||
| 759 | #define mmDB_READ_DEBUG_E 0x262e | ||
| 760 | #define mmDB_READ_DEBUG_F 0x262f | ||
| 761 | #define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 | ||
| 762 | #define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 | ||
| 763 | #define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 | ||
| 764 | #define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 | ||
| 765 | #define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 | ||
| 766 | #define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 | ||
| 767 | #define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 | ||
| 768 | #define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 | ||
| 769 | #define mmCC_RB_REDUNDANCY 0x263c | ||
| 770 | #define mmCC_RB_BACKEND_DISABLE 0x263d | ||
| 771 | #define mmGC_USER_RB_REDUNDANCY 0x26de | ||
| 772 | #define mmGC_USER_RB_BACKEND_DISABLE 0x26df | ||
| 773 | #define mmGB_ADDR_CONFIG 0x263e | ||
| 774 | #define mmGB_BACKEND_MAP 0x263f | ||
| 775 | #define mmGB_GPU_ID 0x2640 | ||
| 776 | #define mmCC_RB_DAISY_CHAIN 0x2641 | ||
| 777 | #define mmGB_TILE_MODE0 0x2644 | ||
| 778 | #define mmGB_TILE_MODE1 0x2645 | ||
| 779 | #define mmGB_TILE_MODE2 0x2646 | ||
| 780 | #define mmGB_TILE_MODE3 0x2647 | ||
| 781 | #define mmGB_TILE_MODE4 0x2648 | ||
| 782 | #define mmGB_TILE_MODE5 0x2649 | ||
| 783 | #define mmGB_TILE_MODE6 0x264a | ||
| 784 | #define mmGB_TILE_MODE7 0x264b | ||
| 785 | #define mmGB_TILE_MODE8 0x264c | ||
| 786 | #define mmGB_TILE_MODE9 0x264d | ||
| 787 | #define mmGB_TILE_MODE10 0x264e | ||
| 788 | #define mmGB_TILE_MODE11 0x264f | ||
| 789 | #define mmGB_TILE_MODE12 0x2650 | ||
| 790 | #define mmGB_TILE_MODE13 0x2651 | ||
| 791 | #define mmGB_TILE_MODE14 0x2652 | ||
| 792 | #define mmGB_TILE_MODE15 0x2653 | ||
| 793 | #define mmGB_TILE_MODE16 0x2654 | ||
| 794 | #define mmGB_TILE_MODE17 0x2655 | ||
| 795 | #define mmGB_TILE_MODE18 0x2656 | ||
| 796 | #define mmGB_TILE_MODE19 0x2657 | ||
| 797 | #define mmGB_TILE_MODE20 0x2658 | ||
| 798 | #define mmGB_TILE_MODE21 0x2659 | ||
| 799 | #define mmGB_TILE_MODE22 0x265a | ||
| 800 | #define mmGB_TILE_MODE23 0x265b | ||
| 801 | #define mmGB_TILE_MODE24 0x265c | ||
| 802 | #define mmGB_TILE_MODE25 0x265d | ||
| 803 | #define mmGB_TILE_MODE26 0x265e | ||
| 804 | #define mmGB_TILE_MODE27 0x265f | ||
| 805 | #define mmGB_TILE_MODE28 0x2660 | ||
| 806 | #define mmGB_TILE_MODE29 0x2661 | ||
| 807 | #define mmGB_TILE_MODE30 0x2662 | ||
| 808 | #define mmGB_TILE_MODE31 0x2663 | ||
| 809 | #define mmGB_MACROTILE_MODE0 0x2664 | ||
| 810 | #define mmGB_MACROTILE_MODE1 0x2665 | ||
| 811 | #define mmGB_MACROTILE_MODE2 0x2666 | ||
| 812 | #define mmGB_MACROTILE_MODE3 0x2667 | ||
| 813 | #define mmGB_MACROTILE_MODE4 0x2668 | ||
| 814 | #define mmGB_MACROTILE_MODE5 0x2669 | ||
| 815 | #define mmGB_MACROTILE_MODE6 0x266a | ||
| 816 | #define mmGB_MACROTILE_MODE7 0x266b | ||
| 817 | #define mmGB_MACROTILE_MODE8 0x266c | ||
| 818 | #define mmGB_MACROTILE_MODE9 0x266d | ||
| 819 | #define mmGB_MACROTILE_MODE10 0x266e | ||
| 820 | #define mmGB_MACROTILE_MODE11 0x266f | ||
| 821 | #define mmGB_MACROTILE_MODE12 0x2670 | ||
| 822 | #define mmGB_MACROTILE_MODE13 0x2671 | ||
| 823 | #define mmGB_MACROTILE_MODE14 0x2672 | ||
| 824 | #define mmGB_MACROTILE_MODE15 0x2673 | ||
| 825 | #define mmGB_EDC_MODE 0x307e | ||
| 826 | #define mmCC_GC_EDC_CONFIG 0x3098 | ||
| 827 | #define mmRAS_SIGNATURE_CONTROL 0x3380 | ||
| 828 | #define mmRAS_SIGNATURE_MASK 0x3381 | ||
| 829 | #define mmRAS_SX_SIGNATURE0 0x3382 | ||
| 830 | #define mmRAS_SX_SIGNATURE1 0x3383 | ||
| 831 | #define mmRAS_SX_SIGNATURE2 0x3384 | ||
| 832 | #define mmRAS_SX_SIGNATURE3 0x3385 | ||
| 833 | #define mmRAS_DB_SIGNATURE0 0x338b | ||
| 834 | #define mmRAS_PA_SIGNATURE0 0x338c | ||
| 835 | #define mmRAS_VGT_SIGNATURE0 0x338d | ||
| 836 | #define mmRAS_SC_SIGNATURE0 0x338f | ||
| 837 | #define mmRAS_SC_SIGNATURE1 0x3390 | ||
| 838 | #define mmRAS_SC_SIGNATURE2 0x3391 | ||
| 839 | #define mmRAS_SC_SIGNATURE3 0x3392 | ||
| 840 | #define mmRAS_SC_SIGNATURE4 0x3393 | ||
| 841 | #define mmRAS_SC_SIGNATURE5 0x3394 | ||
| 842 | #define mmRAS_SC_SIGNATURE6 0x3395 | ||
| 843 | #define mmRAS_SC_SIGNATURE7 0x3396 | ||
| 844 | #define mmRAS_IA_SIGNATURE0 0x3397 | ||
| 845 | #define mmRAS_IA_SIGNATURE1 0x3398 | ||
| 846 | #define mmRAS_SPI_SIGNATURE0 0x3399 | ||
| 847 | #define mmRAS_SPI_SIGNATURE1 0x339a | ||
| 848 | #define mmRAS_TA_SIGNATURE0 0x339b | ||
| 849 | #define mmRAS_TD_SIGNATURE0 0x339c | ||
| 850 | #define mmRAS_CB_SIGNATURE0 0x339d | ||
| 851 | #define mmRAS_BCI_SIGNATURE0 0x339e | ||
| 852 | #define mmRAS_BCI_SIGNATURE1 0x339f | ||
| 853 | #define mmRAS_TA_SIGNATURE1 0x33a0 | ||
| 854 | #define mmGRBM_HYP_CAM_INDEX 0xf83e | ||
| 855 | #define mmGRBM_CAM_INDEX 0xf83e | ||
| 856 | #define mmGRBM_HYP_CAM_DATA 0xf83f | ||
| 857 | #define mmGRBM_CAM_DATA 0xf83f | ||
| 858 | #define mmGRBM_CNTL 0x2000 | ||
| 859 | #define mmGRBM_SKEW_CNTL 0x2001 | ||
| 860 | #define mmGRBM_PWR_CNTL 0x2003 | ||
| 861 | #define mmGRBM_STATUS 0x2004 | ||
| 862 | #define mmGRBM_STATUS2 0x2002 | ||
| 863 | #define mmGRBM_STATUS_SE0 0x2005 | ||
| 864 | #define mmGRBM_STATUS_SE1 0x2006 | ||
| 865 | #define mmGRBM_STATUS_SE2 0x200e | ||
| 866 | #define mmGRBM_STATUS_SE3 0x200f | ||
| 867 | #define mmGRBM_SOFT_RESET 0x2008 | ||
| 868 | #define mmGRBM_DEBUG_CNTL 0x2009 | ||
| 869 | #define mmGRBM_DEBUG_DATA 0x200a | ||
| 870 | #define mmGRBM_CGTT_CLK_CNTL 0x200b | ||
| 871 | #define mmGRBM_GFX_INDEX 0xc200 | ||
| 872 | #define mmGRBM_GFX_CLKEN_CNTL 0x200c | ||
| 873 | #define mmGRBM_WAIT_IDLE_CLOCKS 0x200d | ||
| 874 | #define mmGRBM_DEBUG 0x2014 | ||
| 875 | #define mmGRBM_DEBUG_SNAPSHOT 0x2015 | ||
| 876 | #define mmGRBM_READ_ERROR 0x2016 | ||
| 877 | #define mmGRBM_READ_ERROR2 0x2017 | ||
| 878 | #define mmGRBM_INT_CNTL 0x2018 | ||
| 879 | #define mmGRBM_TRAP_OP 0x2019 | ||
| 880 | #define mmGRBM_TRAP_ADDR 0x201a | ||
| 881 | #define mmGRBM_TRAP_ADDR_MSK 0x201b | ||
| 882 | #define mmGRBM_TRAP_WD 0x201c | ||
| 883 | #define mmGRBM_TRAP_WD_MSK 0x201d | ||
| 884 | #define mmGRBM_DSM_BYPASS 0x201e | ||
| 885 | #define mmGRBM_WRITE_ERROR 0x201f | ||
| 886 | #define mmGRBM_PERFCOUNTER0_SELECT 0xd840 | ||
| 887 | #define mmGRBM_PERFCOUNTER1_SELECT 0xd841 | ||
| 888 | #define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 | ||
| 889 | #define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 | ||
| 890 | #define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 | ||
| 891 | #define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 | ||
| 892 | #define mmGRBM_PERFCOUNTER0_LO 0xd040 | ||
| 893 | #define mmGRBM_PERFCOUNTER0_HI 0xd041 | ||
| 894 | #define mmGRBM_PERFCOUNTER1_LO 0xd043 | ||
| 895 | #define mmGRBM_PERFCOUNTER1_HI 0xd044 | ||
| 896 | #define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 | ||
| 897 | #define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 | ||
| 898 | #define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 | ||
| 899 | #define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 | ||
| 900 | #define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 | ||
| 901 | #define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a | ||
| 902 | #define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b | ||
| 903 | #define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c | ||
| 904 | #define mmGRBM_SCRATCH_REG0 0x2040 | ||
| 905 | #define mmGRBM_SCRATCH_REG1 0x2041 | ||
| 906 | #define mmGRBM_SCRATCH_REG2 0x2042 | ||
| 907 | #define mmGRBM_SCRATCH_REG3 0x2043 | ||
| 908 | #define mmGRBM_SCRATCH_REG4 0x2044 | ||
| 909 | #define mmGRBM_SCRATCH_REG5 0x2045 | ||
| 910 | #define mmGRBM_SCRATCH_REG6 0x2046 | ||
| 911 | #define mmGRBM_SCRATCH_REG7 0x2047 | ||
| 912 | #define mmDEBUG_INDEX 0x203c | ||
| 913 | #define mmDEBUG_DATA 0x203d | ||
| 914 | #define mmGRBM_NOWHERE 0x203f | ||
| 915 | #define mmPA_CL_VPORT_XSCALE 0xa10f | ||
| 916 | #define mmPA_CL_VPORT_XOFFSET 0xa110 | ||
| 917 | #define mmPA_CL_VPORT_YSCALE 0xa111 | ||
| 918 | #define mmPA_CL_VPORT_YOFFSET 0xa112 | ||
| 919 | #define mmPA_CL_VPORT_ZSCALE 0xa113 | ||
| 920 | #define mmPA_CL_VPORT_ZOFFSET 0xa114 | ||
| 921 | #define mmPA_CL_VPORT_XSCALE_1 0xa115 | ||
| 922 | #define mmPA_CL_VPORT_XSCALE_2 0xa11b | ||
| 923 | #define mmPA_CL_VPORT_XSCALE_3 0xa121 | ||
| 924 | #define mmPA_CL_VPORT_XSCALE_4 0xa127 | ||
| 925 | #define mmPA_CL_VPORT_XSCALE_5 0xa12d | ||
| 926 | #define mmPA_CL_VPORT_XSCALE_6 0xa133 | ||
| 927 | #define mmPA_CL_VPORT_XSCALE_7 0xa139 | ||
| 928 | #define mmPA_CL_VPORT_XSCALE_8 0xa13f | ||
| 929 | #define mmPA_CL_VPORT_XSCALE_9 0xa145 | ||
| 930 | #define mmPA_CL_VPORT_XSCALE_10 0xa14b | ||
| 931 | #define mmPA_CL_VPORT_XSCALE_11 0xa151 | ||
| 932 | #define mmPA_CL_VPORT_XSCALE_12 0xa157 | ||
| 933 | #define mmPA_CL_VPORT_XSCALE_13 0xa15d | ||
| 934 | #define mmPA_CL_VPORT_XSCALE_14 0xa163 | ||
| 935 | #define mmPA_CL_VPORT_XSCALE_15 0xa169 | ||
| 936 | #define mmPA_CL_VPORT_XOFFSET_1 0xa116 | ||
| 937 | #define mmPA_CL_VPORT_XOFFSET_2 0xa11c | ||
| 938 | #define mmPA_CL_VPORT_XOFFSET_3 0xa122 | ||
| 939 | #define mmPA_CL_VPORT_XOFFSET_4 0xa128 | ||
| 940 | #define mmPA_CL_VPORT_XOFFSET_5 0xa12e | ||
| 941 | #define mmPA_CL_VPORT_XOFFSET_6 0xa134 | ||
| 942 | #define mmPA_CL_VPORT_XOFFSET_7 0xa13a | ||
| 943 | #define mmPA_CL_VPORT_XOFFSET_8 0xa140 | ||
| 944 | #define mmPA_CL_VPORT_XOFFSET_9 0xa146 | ||
| 945 | #define mmPA_CL_VPORT_XOFFSET_10 0xa14c | ||
| 946 | #define mmPA_CL_VPORT_XOFFSET_11 0xa152 | ||
| 947 | #define mmPA_CL_VPORT_XOFFSET_12 0xa158 | ||
| 948 | #define mmPA_CL_VPORT_XOFFSET_13 0xa15e | ||
| 949 | #define mmPA_CL_VPORT_XOFFSET_14 0xa164 | ||
| 950 | #define mmPA_CL_VPORT_XOFFSET_15 0xa16a | ||
| 951 | #define mmPA_CL_VPORT_YSCALE_1 0xa117 | ||
| 952 | #define mmPA_CL_VPORT_YSCALE_2 0xa11d | ||
| 953 | #define mmPA_CL_VPORT_YSCALE_3 0xa123 | ||
| 954 | #define mmPA_CL_VPORT_YSCALE_4 0xa129 | ||
| 955 | #define mmPA_CL_VPORT_YSCALE_5 0xa12f | ||
| 956 | #define mmPA_CL_VPORT_YSCALE_6 0xa135 | ||
| 957 | #define mmPA_CL_VPORT_YSCALE_7 0xa13b | ||
| 958 | #define mmPA_CL_VPORT_YSCALE_8 0xa141 | ||
| 959 | #define mmPA_CL_VPORT_YSCALE_9 0xa147 | ||
| 960 | #define mmPA_CL_VPORT_YSCALE_10 0xa14d | ||
| 961 | #define mmPA_CL_VPORT_YSCALE_11 0xa153 | ||
| 962 | #define mmPA_CL_VPORT_YSCALE_12 0xa159 | ||
| 963 | #define mmPA_CL_VPORT_YSCALE_13 0xa15f | ||
| 964 | #define mmPA_CL_VPORT_YSCALE_14 0xa165 | ||
| 965 | #define mmPA_CL_VPORT_YSCALE_15 0xa16b | ||
| 966 | #define mmPA_CL_VPORT_YOFFSET_1 0xa118 | ||
| 967 | #define mmPA_CL_VPORT_YOFFSET_2 0xa11e | ||
| 968 | #define mmPA_CL_VPORT_YOFFSET_3 0xa124 | ||
| 969 | #define mmPA_CL_VPORT_YOFFSET_4 0xa12a | ||
| 970 | #define mmPA_CL_VPORT_YOFFSET_5 0xa130 | ||
| 971 | #define mmPA_CL_VPORT_YOFFSET_6 0xa136 | ||
| 972 | #define mmPA_CL_VPORT_YOFFSET_7 0xa13c | ||
| 973 | #define mmPA_CL_VPORT_YOFFSET_8 0xa142 | ||
| 974 | #define mmPA_CL_VPORT_YOFFSET_9 0xa148 | ||
| 975 | #define mmPA_CL_VPORT_YOFFSET_10 0xa14e | ||
| 976 | #define mmPA_CL_VPORT_YOFFSET_11 0xa154 | ||
| 977 | #define mmPA_CL_VPORT_YOFFSET_12 0xa15a | ||
| 978 | #define mmPA_CL_VPORT_YOFFSET_13 0xa160 | ||
| 979 | #define mmPA_CL_VPORT_YOFFSET_14 0xa166 | ||
| 980 | #define mmPA_CL_VPORT_YOFFSET_15 0xa16c | ||
| 981 | #define mmPA_CL_VPORT_ZSCALE_1 0xa119 | ||
| 982 | #define mmPA_CL_VPORT_ZSCALE_2 0xa11f | ||
| 983 | #define mmPA_CL_VPORT_ZSCALE_3 0xa125 | ||
| 984 | #define mmPA_CL_VPORT_ZSCALE_4 0xa12b | ||
| 985 | #define mmPA_CL_VPORT_ZSCALE_5 0xa131 | ||
| 986 | #define mmPA_CL_VPORT_ZSCALE_6 0xa137 | ||
| 987 | #define mmPA_CL_VPORT_ZSCALE_7 0xa13d | ||
| 988 | #define mmPA_CL_VPORT_ZSCALE_8 0xa143 | ||
| 989 | #define mmPA_CL_VPORT_ZSCALE_9 0xa149 | ||
| 990 | #define mmPA_CL_VPORT_ZSCALE_10 0xa14f | ||
| 991 | #define mmPA_CL_VPORT_ZSCALE_11 0xa155 | ||
| 992 | #define mmPA_CL_VPORT_ZSCALE_12 0xa15b | ||
| 993 | #define mmPA_CL_VPORT_ZSCALE_13 0xa161 | ||
| 994 | #define mmPA_CL_VPORT_ZSCALE_14 0xa167 | ||
| 995 | #define mmPA_CL_VPORT_ZSCALE_15 0xa16d | ||
| 996 | #define mmPA_CL_VPORT_ZOFFSET_1 0xa11a | ||
| 997 | #define mmPA_CL_VPORT_ZOFFSET_2 0xa120 | ||
| 998 | #define mmPA_CL_VPORT_ZOFFSET_3 0xa126 | ||
| 999 | #define mmPA_CL_VPORT_ZOFFSET_4 0xa12c | ||
| 1000 | #define mmPA_CL_VPORT_ZOFFSET_5 0xa132 | ||
| 1001 | #define mmPA_CL_VPORT_ZOFFSET_6 0xa138 | ||
| 1002 | #define mmPA_CL_VPORT_ZOFFSET_7 0xa13e | ||
| 1003 | #define mmPA_CL_VPORT_ZOFFSET_8 0xa144 | ||
| 1004 | #define mmPA_CL_VPORT_ZOFFSET_9 0xa14a | ||
| 1005 | #define mmPA_CL_VPORT_ZOFFSET_10 0xa150 | ||
| 1006 | #define mmPA_CL_VPORT_ZOFFSET_11 0xa156 | ||
| 1007 | #define mmPA_CL_VPORT_ZOFFSET_12 0xa15c | ||
| 1008 | #define mmPA_CL_VPORT_ZOFFSET_13 0xa162 | ||
| 1009 | #define mmPA_CL_VPORT_ZOFFSET_14 0xa168 | ||
| 1010 | #define mmPA_CL_VPORT_ZOFFSET_15 0xa16e | ||
| 1011 | #define mmPA_CL_VTE_CNTL 0xa206 | ||
| 1012 | #define mmPA_CL_VS_OUT_CNTL 0xa207 | ||
| 1013 | #define mmPA_CL_NANINF_CNTL 0xa208 | ||
| 1014 | #define mmPA_CL_CLIP_CNTL 0xa204 | ||
| 1015 | #define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa | ||
| 1016 | #define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb | ||
| 1017 | #define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc | ||
| 1018 | #define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd | ||
| 1019 | #define mmPA_CL_UCP_0_X 0xa16f | ||
| 1020 | #define mmPA_CL_UCP_0_Y 0xa170 | ||
| 1021 | #define mmPA_CL_UCP_0_Z 0xa171 | ||
| 1022 | #define mmPA_CL_UCP_0_W 0xa172 | ||
| 1023 | #define mmPA_CL_UCP_1_X 0xa173 | ||
| 1024 | #define mmPA_CL_UCP_1_Y 0xa174 | ||
| 1025 | #define mmPA_CL_UCP_1_Z 0xa175 | ||
| 1026 | #define mmPA_CL_UCP_1_W 0xa176 | ||
| 1027 | #define mmPA_CL_UCP_2_X 0xa177 | ||
| 1028 | #define mmPA_CL_UCP_2_Y 0xa178 | ||
| 1029 | #define mmPA_CL_UCP_2_Z 0xa179 | ||
| 1030 | #define mmPA_CL_UCP_2_W 0xa17a | ||
| 1031 | #define mmPA_CL_UCP_3_X 0xa17b | ||
| 1032 | #define mmPA_CL_UCP_3_Y 0xa17c | ||
| 1033 | #define mmPA_CL_UCP_3_Z 0xa17d | ||
| 1034 | #define mmPA_CL_UCP_3_W 0xa17e | ||
| 1035 | #define mmPA_CL_UCP_4_X 0xa17f | ||
| 1036 | #define mmPA_CL_UCP_4_Y 0xa180 | ||
| 1037 | #define mmPA_CL_UCP_4_Z 0xa181 | ||
| 1038 | #define mmPA_CL_UCP_4_W 0xa182 | ||
| 1039 | #define mmPA_CL_UCP_5_X 0xa183 | ||
| 1040 | #define mmPA_CL_UCP_5_Y 0xa184 | ||
| 1041 | #define mmPA_CL_UCP_5_Z 0xa185 | ||
| 1042 | #define mmPA_CL_UCP_5_W 0xa186 | ||
| 1043 | #define mmPA_CL_POINT_X_RAD 0xa1f5 | ||
| 1044 | #define mmPA_CL_POINT_Y_RAD 0xa1f6 | ||
| 1045 | #define mmPA_CL_POINT_SIZE 0xa1f7 | ||
| 1046 | #define mmPA_CL_POINT_CULL_RAD 0xa1f8 | ||
| 1047 | #define mmPA_CL_ENHANCE 0x2285 | ||
| 1048 | #define mmPA_CL_RESET_DEBUG 0x2286 | ||
| 1049 | #define mmPA_SU_VTX_CNTL 0xa2f9 | ||
| 1050 | #define mmPA_SU_POINT_SIZE 0xa280 | ||
| 1051 | #define mmPA_SU_POINT_MINMAX 0xa281 | ||
| 1052 | #define mmPA_SU_LINE_CNTL 0xa282 | ||
| 1053 | #define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 | ||
| 1054 | #define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a | ||
| 1055 | #define mmPA_SU_PRIM_FILTER_CNTL 0xa20b | ||
| 1056 | #define mmPA_SU_SC_MODE_CNTL 0xa205 | ||
| 1057 | #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de | ||
| 1058 | #define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df | ||
| 1059 | #define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 | ||
| 1060 | #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 | ||
| 1061 | #define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 | ||
| 1062 | #define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 | ||
| 1063 | #define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d | ||
| 1064 | #define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 | ||
| 1065 | #define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 | ||
| 1066 | #define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 | ||
| 1067 | #define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 | ||
| 1068 | #define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 | ||
| 1069 | #define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 | ||
| 1070 | #define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 | ||
| 1071 | #define mmPA_SU_PERFCOUNTER0_LO 0xd100 | ||
| 1072 | #define mmPA_SU_PERFCOUNTER0_HI 0xd101 | ||
| 1073 | #define mmPA_SU_PERFCOUNTER1_LO 0xd102 | ||
| 1074 | #define mmPA_SU_PERFCOUNTER1_HI 0xd103 | ||
| 1075 | #define mmPA_SU_PERFCOUNTER2_LO 0xd104 | ||
| 1076 | #define mmPA_SU_PERFCOUNTER2_HI 0xd105 | ||
| 1077 | #define mmPA_SU_PERFCOUNTER3_LO 0xd106 | ||
| 1078 | #define mmPA_SU_PERFCOUNTER3_HI 0xd107 | ||
| 1079 | #define mmPA_SC_AA_CONFIG 0xa2f8 | ||
| 1080 | #define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e | ||
| 1081 | #define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f | ||
| 1082 | #define mmPA_SC_SHADER_CONTROL 0xa310 | ||
| 1083 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe | ||
| 1084 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff | ||
| 1085 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 | ||
| 1086 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 | ||
| 1087 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 | ||
| 1088 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 | ||
| 1089 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 | ||
| 1090 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 | ||
| 1091 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 | ||
| 1092 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 | ||
| 1093 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 | ||
| 1094 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 | ||
| 1095 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a | ||
| 1096 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b | ||
| 1097 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c | ||
| 1098 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d | ||
| 1099 | #define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 | ||
| 1100 | #define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 | ||
| 1101 | #define mmPA_SC_CLIPRECT_0_TL 0xa084 | ||
| 1102 | #define mmPA_SC_CLIPRECT_0_BR 0xa085 | ||
| 1103 | #define mmPA_SC_CLIPRECT_1_TL 0xa086 | ||
| 1104 | #define mmPA_SC_CLIPRECT_1_BR 0xa087 | ||
| 1105 | #define mmPA_SC_CLIPRECT_2_TL 0xa088 | ||
| 1106 | #define mmPA_SC_CLIPRECT_2_BR 0xa089 | ||
| 1107 | #define mmPA_SC_CLIPRECT_3_TL 0xa08a | ||
| 1108 | #define mmPA_SC_CLIPRECT_3_BR 0xa08b | ||
| 1109 | #define mmPA_SC_CLIPRECT_RULE 0xa083 | ||
| 1110 | #define mmPA_SC_EDGERULE 0xa08c | ||
| 1111 | #define mmPA_SC_LINE_CNTL 0xa2f7 | ||
| 1112 | #define mmPA_SC_LINE_STIPPLE 0xa283 | ||
| 1113 | #define mmPA_SC_MODE_CNTL_0 0xa292 | ||
| 1114 | #define mmPA_SC_MODE_CNTL_1 0xa293 | ||
| 1115 | #define mmPA_SC_RASTER_CONFIG 0xa0d4 | ||
| 1116 | #define mmPA_SC_RASTER_CONFIG_1 0xa0d5 | ||
| 1117 | #define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 | ||
| 1118 | #define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 | ||
| 1119 | #define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 | ||
| 1120 | #define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c | ||
| 1121 | #define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d | ||
| 1122 | #define mmPA_SC_WINDOW_OFFSET 0xa080 | ||
| 1123 | #define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 | ||
| 1124 | #define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 | ||
| 1125 | #define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 | ||
| 1126 | #define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 | ||
| 1127 | #define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 | ||
| 1128 | #define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a | ||
| 1129 | #define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c | ||
| 1130 | #define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e | ||
| 1131 | #define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 | ||
| 1132 | #define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 | ||
| 1133 | #define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 | ||
| 1134 | #define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 | ||
| 1135 | #define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 | ||
| 1136 | #define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa | ||
| 1137 | #define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac | ||
| 1138 | #define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae | ||
| 1139 | #define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 | ||
| 1140 | #define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 | ||
| 1141 | #define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 | ||
| 1142 | #define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 | ||
| 1143 | #define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 | ||
| 1144 | #define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b | ||
| 1145 | #define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d | ||
| 1146 | #define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f | ||
| 1147 | #define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 | ||
| 1148 | #define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 | ||
| 1149 | #define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 | ||
| 1150 | #define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 | ||
| 1151 | #define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 | ||
| 1152 | #define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab | ||
| 1153 | #define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad | ||
| 1154 | #define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af | ||
| 1155 | #define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 | ||
| 1156 | #define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 | ||
| 1157 | #define mmPA_SC_VPORT_ZMIN_0 0xa0b4 | ||
| 1158 | #define mmPA_SC_VPORT_ZMIN_1 0xa0b6 | ||
| 1159 | #define mmPA_SC_VPORT_ZMIN_2 0xa0b8 | ||
| 1160 | #define mmPA_SC_VPORT_ZMIN_3 0xa0ba | ||
| 1161 | #define mmPA_SC_VPORT_ZMIN_4 0xa0bc | ||
| 1162 | #define mmPA_SC_VPORT_ZMIN_5 0xa0be | ||
| 1163 | #define mmPA_SC_VPORT_ZMIN_6 0xa0c0 | ||
| 1164 | #define mmPA_SC_VPORT_ZMIN_7 0xa0c2 | ||
| 1165 | #define mmPA_SC_VPORT_ZMIN_8 0xa0c4 | ||
| 1166 | #define mmPA_SC_VPORT_ZMIN_9 0xa0c6 | ||
| 1167 | #define mmPA_SC_VPORT_ZMIN_10 0xa0c8 | ||
| 1168 | #define mmPA_SC_VPORT_ZMIN_11 0xa0ca | ||
| 1169 | #define mmPA_SC_VPORT_ZMIN_12 0xa0cc | ||
| 1170 | #define mmPA_SC_VPORT_ZMIN_13 0xa0ce | ||
| 1171 | #define mmPA_SC_VPORT_ZMIN_14 0xa0d0 | ||
| 1172 | #define mmPA_SC_VPORT_ZMIN_15 0xa0d2 | ||
| 1173 | #define mmPA_SC_VPORT_ZMAX_0 0xa0b5 | ||
| 1174 | #define mmPA_SC_VPORT_ZMAX_1 0xa0b7 | ||
| 1175 | #define mmPA_SC_VPORT_ZMAX_2 0xa0b9 | ||
| 1176 | #define mmPA_SC_VPORT_ZMAX_3 0xa0bb | ||
| 1177 | #define mmPA_SC_VPORT_ZMAX_4 0xa0bd | ||
| 1178 | #define mmPA_SC_VPORT_ZMAX_5 0xa0bf | ||
| 1179 | #define mmPA_SC_VPORT_ZMAX_6 0xa0c1 | ||
| 1180 | #define mmPA_SC_VPORT_ZMAX_7 0xa0c3 | ||
| 1181 | #define mmPA_SC_VPORT_ZMAX_8 0xa0c5 | ||
| 1182 | #define mmPA_SC_VPORT_ZMAX_9 0xa0c7 | ||
| 1183 | #define mmPA_SC_VPORT_ZMAX_10 0xa0c9 | ||
| 1184 | #define mmPA_SC_VPORT_ZMAX_11 0xa0cb | ||
| 1185 | #define mmPA_SC_VPORT_ZMAX_12 0xa0cd | ||
| 1186 | #define mmPA_SC_VPORT_ZMAX_13 0xa0cf | ||
| 1187 | #define mmPA_SC_VPORT_ZMAX_14 0xa0d1 | ||
| 1188 | #define mmPA_SC_VPORT_ZMAX_15 0xa0d3 | ||
| 1189 | #define mmPA_SC_ENHANCE 0x22fc | ||
| 1190 | #define mmPA_SC_ENHANCE_1 0x22fd | ||
| 1191 | #define mmPA_SC_DSM_CNTL 0x22fe | ||
| 1192 | #define mmPA_SC_FIFO_SIZE 0x22f3 | ||
| 1193 | #define mmPA_SC_IF_FIFO_SIZE 0x22f5 | ||
| 1194 | #define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 | ||
| 1195 | #define mmPA_SC_LINE_STIPPLE_STATE 0xc281 | ||
| 1196 | #define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 | ||
| 1197 | #define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 | ||
| 1198 | #define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 | ||
| 1199 | #define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b | ||
| 1200 | #define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 | ||
| 1201 | #define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 | ||
| 1202 | #define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 | ||
| 1203 | #define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 | ||
| 1204 | #define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 | ||
| 1205 | #define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 | ||
| 1206 | #define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 | ||
| 1207 | #define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 | ||
| 1208 | #define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 | ||
| 1209 | #define mmPA_SC_PERFCOUNTER0_LO 0xd140 | ||
| 1210 | #define mmPA_SC_PERFCOUNTER0_HI 0xd141 | ||
| 1211 | #define mmPA_SC_PERFCOUNTER1_LO 0xd142 | ||
| 1212 | #define mmPA_SC_PERFCOUNTER1_HI 0xd143 | ||
| 1213 | #define mmPA_SC_PERFCOUNTER2_LO 0xd144 | ||
| 1214 | #define mmPA_SC_PERFCOUNTER2_HI 0xd145 | ||
| 1215 | #define mmPA_SC_PERFCOUNTER3_LO 0xd146 | ||
| 1216 | #define mmPA_SC_PERFCOUNTER3_HI 0xd147 | ||
| 1217 | #define mmPA_SC_PERFCOUNTER4_LO 0xd148 | ||
| 1218 | #define mmPA_SC_PERFCOUNTER4_HI 0xd149 | ||
| 1219 | #define mmPA_SC_PERFCOUNTER5_LO 0xd14a | ||
| 1220 | #define mmPA_SC_PERFCOUNTER5_HI 0xd14b | ||
| 1221 | #define mmPA_SC_PERFCOUNTER6_LO 0xd14c | ||
| 1222 | #define mmPA_SC_PERFCOUNTER6_HI 0xd14d | ||
| 1223 | #define mmPA_SC_PERFCOUNTER7_LO 0xd14e | ||
| 1224 | #define mmPA_SC_PERFCOUNTER7_HI 0xd14f | ||
| 1225 | #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 | ||
| 1226 | #define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 | ||
| 1227 | #define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 | ||
| 1228 | #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 | ||
| 1229 | #define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 | ||
| 1230 | #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 | ||
| 1231 | #define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 | ||
| 1232 | #define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa | ||
| 1233 | #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab | ||
| 1234 | #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac | ||
| 1235 | #define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 | ||
| 1236 | #define mmPA_SC_TRAP_SCREEN_H 0xc2b1 | ||
| 1237 | #define mmPA_SC_TRAP_SCREEN_V 0xc2b2 | ||
| 1238 | #define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 | ||
| 1239 | #define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 | ||
| 1240 | #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 | ||
| 1241 | #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 | ||
| 1242 | #define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 | ||
| 1243 | #define mmPA_CL_CNTL_STATUS 0x2284 | ||
| 1244 | #define mmPA_SU_CNTL_STATUS 0x2294 | ||
| 1245 | #define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 | ||
| 1246 | #define mmCGTT_PA_CLK_CTRL 0xf088 | ||
| 1247 | #define mmCGTT_SC_CLK_CTRL 0xf089 | ||
| 1248 | #define mmPA_SU_DEBUG_CNTL 0x2280 | ||
| 1249 | #define mmPA_SU_DEBUG_DATA 0x2281 | ||
| 1250 | #define mmPA_SC_DEBUG_CNTL 0x22f6 | ||
| 1251 | #define mmPA_SC_DEBUG_DATA 0x22f7 | ||
| 1252 | #define ixCLIPPER_DEBUG_REG00 0x0 | ||
| 1253 | #define ixCLIPPER_DEBUG_REG01 0x1 | ||
| 1254 | #define ixCLIPPER_DEBUG_REG02 0x2 | ||
| 1255 | #define ixCLIPPER_DEBUG_REG03 0x3 | ||
| 1256 | #define ixCLIPPER_DEBUG_REG04 0x4 | ||
| 1257 | #define ixCLIPPER_DEBUG_REG05 0x5 | ||
| 1258 | #define ixCLIPPER_DEBUG_REG06 0x6 | ||
| 1259 | #define ixCLIPPER_DEBUG_REG07 0x7 | ||
| 1260 | #define ixCLIPPER_DEBUG_REG08 0x8 | ||
| 1261 | #define ixCLIPPER_DEBUG_REG09 0x9 | ||
| 1262 | #define ixCLIPPER_DEBUG_REG10 0xa | ||
| 1263 | #define ixCLIPPER_DEBUG_REG11 0xb | ||
| 1264 | #define ixCLIPPER_DEBUG_REG12 0xc | ||
| 1265 | #define ixCLIPPER_DEBUG_REG13 0xd | ||
| 1266 | #define ixCLIPPER_DEBUG_REG14 0xe | ||
| 1267 | #define ixCLIPPER_DEBUG_REG15 0xf | ||
| 1268 | #define ixCLIPPER_DEBUG_REG16 0x10 | ||
| 1269 | #define ixCLIPPER_DEBUG_REG17 0x11 | ||
| 1270 | #define ixCLIPPER_DEBUG_REG18 0x12 | ||
| 1271 | #define ixCLIPPER_DEBUG_REG19 0x13 | ||
| 1272 | #define ixSXIFCCG_DEBUG_REG0 0x14 | ||
| 1273 | #define ixSXIFCCG_DEBUG_REG1 0x15 | ||
| 1274 | #define ixSXIFCCG_DEBUG_REG2 0x16 | ||
| 1275 | #define ixSXIFCCG_DEBUG_REG3 0x17 | ||
| 1276 | #define ixSETUP_DEBUG_REG0 0x18 | ||
| 1277 | #define ixSETUP_DEBUG_REG1 0x19 | ||
| 1278 | #define ixSETUP_DEBUG_REG2 0x1a | ||
| 1279 | #define ixSETUP_DEBUG_REG3 0x1b | ||
| 1280 | #define ixSETUP_DEBUG_REG4 0x1c | ||
| 1281 | #define ixSETUP_DEBUG_REG5 0x1d | ||
| 1282 | #define ixPA_SC_DEBUG_REG0 0x0 | ||
| 1283 | #define ixPA_SC_DEBUG_REG1 0x1 | ||
| 1284 | #define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 | ||
| 1285 | #define mmCOMPUTE_DIM_X 0x2e01 | ||
| 1286 | #define mmCOMPUTE_DIM_Y 0x2e02 | ||
| 1287 | #define mmCOMPUTE_DIM_Z 0x2e03 | ||
| 1288 | #define mmCOMPUTE_START_X 0x2e04 | ||
| 1289 | #define mmCOMPUTE_START_Y 0x2e05 | ||
| 1290 | #define mmCOMPUTE_START_Z 0x2e06 | ||
| 1291 | #define mmCOMPUTE_NUM_THREAD_X 0x2e07 | ||
| 1292 | #define mmCOMPUTE_NUM_THREAD_Y 0x2e08 | ||
| 1293 | #define mmCOMPUTE_NUM_THREAD_Z 0x2e09 | ||
| 1294 | #define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a | ||
| 1295 | #define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b | ||
| 1296 | #define mmCOMPUTE_PGM_LO 0x2e0c | ||
| 1297 | #define mmCOMPUTE_PGM_HI 0x2e0d | ||
| 1298 | #define mmCOMPUTE_TBA_LO 0x2e0e | ||
| 1299 | #define mmCOMPUTE_TBA_HI 0x2e0f | ||
| 1300 | #define mmCOMPUTE_TMA_LO 0x2e10 | ||
| 1301 | #define mmCOMPUTE_TMA_HI 0x2e11 | ||
| 1302 | #define mmCOMPUTE_PGM_RSRC1 0x2e12 | ||
| 1303 | #define mmCOMPUTE_PGM_RSRC2 0x2e13 | ||
| 1304 | #define mmCOMPUTE_VMID 0x2e14 | ||
| 1305 | #define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 | ||
| 1306 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 | ||
| 1307 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 | ||
| 1308 | #define mmCOMPUTE_TMPRING_SIZE 0x2e18 | ||
| 1309 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 | ||
| 1310 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a | ||
| 1311 | #define mmCOMPUTE_RESTART_X 0x2e1b | ||
| 1312 | #define mmCOMPUTE_RESTART_Y 0x2e1c | ||
| 1313 | #define mmCOMPUTE_RESTART_Z 0x2e1d | ||
| 1314 | #define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e | ||
| 1315 | #define mmCOMPUTE_MISC_RESERVED 0x2e1f | ||
| 1316 | #define mmCOMPUTE_DISPATCH_ID 0x2e20 | ||
| 1317 | #define mmCOMPUTE_THREADGROUP_ID 0x2e21 | ||
| 1318 | #define mmCOMPUTE_RELAUNCH 0x2e22 | ||
| 1319 | #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2e23 | ||
| 1320 | #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2e24 | ||
| 1321 | #define mmCOMPUTE_WAVE_RESTORE_CONTROL 0x2e25 | ||
| 1322 | #define mmCOMPUTE_USER_DATA_0 0x2e40 | ||
| 1323 | #define mmCOMPUTE_USER_DATA_1 0x2e41 | ||
| 1324 | #define mmCOMPUTE_USER_DATA_2 0x2e42 | ||
| 1325 | #define mmCOMPUTE_USER_DATA_3 0x2e43 | ||
| 1326 | #define mmCOMPUTE_USER_DATA_4 0x2e44 | ||
| 1327 | #define mmCOMPUTE_USER_DATA_5 0x2e45 | ||
| 1328 | #define mmCOMPUTE_USER_DATA_6 0x2e46 | ||
| 1329 | #define mmCOMPUTE_USER_DATA_7 0x2e47 | ||
| 1330 | #define mmCOMPUTE_USER_DATA_8 0x2e48 | ||
| 1331 | #define mmCOMPUTE_USER_DATA_9 0x2e49 | ||
| 1332 | #define mmCOMPUTE_USER_DATA_10 0x2e4a | ||
| 1333 | #define mmCOMPUTE_USER_DATA_11 0x2e4b | ||
| 1334 | #define mmCOMPUTE_USER_DATA_12 0x2e4c | ||
| 1335 | #define mmCOMPUTE_USER_DATA_13 0x2e4d | ||
| 1336 | #define mmCOMPUTE_USER_DATA_14 0x2e4e | ||
| 1337 | #define mmCOMPUTE_USER_DATA_15 0x2e4f | ||
| 1338 | #define mmCOMPUTE_NOWHERE 0x2e7f | ||
| 1339 | #define mmCSPRIV_CONNECT 0x0 | ||
| 1340 | #define mmCSPRIV_THREAD_TRACE_TG0 0x1e | ||
| 1341 | #define mmCSPRIV_THREAD_TRACE_TG1 0x1e | ||
| 1342 | #define mmCSPRIV_THREAD_TRACE_TG2 0x1e | ||
| 1343 | #define mmCSPRIV_THREAD_TRACE_TG3 0x1e | ||
| 1344 | #define mmCSPRIV_THREAD_TRACE_EVENT 0x1f | ||
| 1345 | #define mmRLC_CNTL 0xec00 | ||
| 1346 | #define mmRLC_DEBUG_SELECT 0xec01 | ||
| 1347 | #define mmRLC_DEBUG 0xec02 | ||
| 1348 | #define mmRLC_MC_CNTL 0xec03 | ||
| 1349 | #define mmRLC_STAT 0xec04 | ||
| 1350 | #define mmRLC_SAFE_MODE 0xec05 | ||
| 1351 | #define mmRLC_MEM_SLP_CNTL 0xec06 | ||
| 1352 | #define mmSMU_RLC_RESPONSE 0xec07 | ||
| 1353 | #define mmRLC_RLCV_SAFE_MODE 0xec08 | ||
| 1354 | #define mmRLC_SMU_SAFE_MODE 0xec09 | ||
| 1355 | #define mmRLC_RLCV_COMMAND 0xec0a | ||
| 1356 | #define mmRLC_CLK_CNTL 0xec0b | ||
| 1357 | #define mmRLC_PERFMON_CLK_CNTL 0xdcbf | ||
| 1358 | #define mmRLC_PERFMON_CNTL 0xdcc0 | ||
| 1359 | #define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 | ||
| 1360 | #define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 | ||
| 1361 | #define mmRLC_PERFCOUNTER0_LO 0xd480 | ||
| 1362 | #define mmRLC_PERFCOUNTER1_LO 0xd482 | ||
| 1363 | #define mmRLC_PERFCOUNTER0_HI 0xd481 | ||
| 1364 | #define mmRLC_PERFCOUNTER1_HI 0xd483 | ||
| 1365 | #define mmCGTT_RLC_CLK_CTRL 0xf0b8 | ||
| 1366 | #define mmRLC_LB_CNTL 0xec19 | ||
| 1367 | #define mmRLC_LB_CNTR_MAX 0xec12 | ||
| 1368 | #define mmRLC_LB_CNTR_INIT 0xec1b | ||
| 1369 | #define mmRLC_LOAD_BALANCE_CNTR 0xec1c | ||
| 1370 | #define mmRLC_JUMP_TABLE_RESTORE 0xec1e | ||
| 1371 | #define mmRLC_PG_DELAY_2 0xec1f | ||
| 1372 | #define mmRLC_GPM_DEBUG_SELECT 0xec20 | ||
| 1373 | #define mmRLC_GPM_DEBUG 0xec21 | ||
| 1374 | #define mmRLC_GPM_DEBUG_INST_A 0xec22 | ||
| 1375 | #define mmRLC_GPM_DEBUG_INST_B 0xec23 | ||
| 1376 | #define mmRLC_GPM_DEBUG_INST_ADDR 0xec1d | ||
| 1377 | #define mmRLC_GPM_UCODE_ADDR 0xf83c | ||
| 1378 | #define mmRLC_GPM_UCODE_DATA 0xf83d | ||
| 1379 | #define mmGPU_BIST_CONTROL 0xf835 | ||
| 1380 | #define mmRLC_ROM_CNTL 0xf836 | ||
| 1381 | #define mmRLC_GPU_CLOCK_COUNT_LSB 0xec24 | ||
| 1382 | #define mmRLC_GPU_CLOCK_COUNT_MSB 0xec25 | ||
| 1383 | #define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xec26 | ||
| 1384 | #define mmRLC_UCODE_CNTL 0xec27 | ||
| 1385 | #define mmRLC_GPM_STAT 0xec40 | ||
| 1386 | #define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41 | ||
| 1387 | #define mmRLC_GPU_CLOCK_32 0xec42 | ||
| 1388 | #define mmRLC_PG_CNTL 0xec43 | ||
| 1389 | #define mmRLC_GPM_THREAD_PRIORITY 0xec44 | ||
| 1390 | #define mmRLC_GPM_THREAD_ENABLE 0xec45 | ||
| 1391 | #define mmRLC_GPM_VMID_THREAD0 0xec46 | ||
| 1392 | #define mmRLC_GPM_VMID_THREAD1 0xec47 | ||
| 1393 | #define mmRLC_CGTT_MGCG_OVERRIDE 0xec48 | ||
| 1394 | #define mmRLC_CGCG_CGLS_CTRL 0xec49 | ||
| 1395 | #define mmRLC_CGCG_RAMP_CTRL 0xec4a | ||
| 1396 | #define mmRLC_DYN_PG_STATUS 0xec4b | ||
| 1397 | #define mmRLC_DYN_PG_REQUEST 0xec4c | ||
| 1398 | #define mmRLC_PG_DELAY 0xec4d | ||
| 1399 | #define mmRLC_CU_STATUS 0xec4e | ||
| 1400 | #define mmRLC_LB_INIT_CU_MASK 0xec4f | ||
| 1401 | #define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xec50 | ||
| 1402 | #define mmRLC_LB_PARAMS 0xec51 | ||
| 1403 | #define mmRLC_THREAD1_DELAY 0xec52 | ||
| 1404 | #define mmRLC_PG_ALWAYS_ON_CU_MASK 0xec53 | ||
| 1405 | #define mmRLC_MAX_PG_CU 0xec54 | ||
| 1406 | #define mmRLC_AUTO_PG_CTRL 0xec55 | ||
| 1407 | #define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xec56 | ||
| 1408 | #define mmRLC_SERDES_RD_MASTER_INDEX 0xec59 | ||
| 1409 | #define mmRLC_SERDES_RD_DATA_0 0xec5a | ||
| 1410 | #define mmRLC_SERDES_RD_DATA_1 0xec5b | ||
| 1411 | #define mmRLC_SERDES_RD_DATA_2 0xec5c | ||
| 1412 | #define mmRLC_SERDES_WR_CU_MASTER_MASK 0xec5d | ||
| 1413 | #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e | ||
| 1414 | #define mmRLC_SERDES_WR_CTRL 0xec5f | ||
| 1415 | #define mmRLC_SERDES_WR_DATA 0xec60 | ||
| 1416 | #define mmRLC_SERDES_CU_MASTER_BUSY 0xec61 | ||
| 1417 | #define mmRLC_SERDES_NONCU_MASTER_BUSY 0xec62 | ||
| 1418 | #define mmRLC_GPM_GENERAL_0 0xec63 | ||
| 1419 | #define mmRLC_GPM_GENERAL_1 0xec64 | ||
| 1420 | #define mmRLC_GPM_GENERAL_2 0xec65 | ||
| 1421 | #define mmRLC_GPM_GENERAL_3 0xec66 | ||
| 1422 | #define mmRLC_GPM_GENERAL_4 0xec67 | ||
| 1423 | #define mmRLC_GPM_GENERAL_5 0xec68 | ||
| 1424 | #define mmRLC_GPM_GENERAL_6 0xec69 | ||
| 1425 | #define mmRLC_GPM_GENERAL_7 0xec6a | ||
| 1426 | #define mmRLC_GPM_SCRATCH_ADDR 0xec6c | ||
| 1427 | #define mmRLC_GPM_SCRATCH_DATA 0xec6d | ||
| 1428 | #define mmRLC_STATIC_PG_STATUS 0xec6e | ||
| 1429 | #define mmRLC_GPM_PERF_COUNT_0 0xec6f | ||
| 1430 | #define mmRLC_GPM_PERF_COUNT_1 0xec70 | ||
| 1431 | #define mmRLC_GPR_REG1 0xec79 | ||
| 1432 | #define mmRLC_GPR_REG2 0xec7a | ||
| 1433 | #define mmRLC_MGCG_CTRL 0xec1a | ||
| 1434 | #define mmRLC_GPM_THREAD_RESET 0xec28 | ||
| 1435 | #define mmRLC_SPM_VMID 0xec71 | ||
| 1436 | #define mmRLC_SPM_INT_CNTL 0xec72 | ||
| 1437 | #define mmRLC_SPM_INT_STATUS 0xec73 | ||
| 1438 | #define mmRLC_SPM_DEBUG_SELECT 0xec74 | ||
| 1439 | #define mmRLC_SPM_DEBUG 0xec75 | ||
| 1440 | #define mmRLC_SMU_MESSAGE 0xec76 | ||
| 1441 | #define mmRLC_GPM_LOG_SIZE 0xec77 | ||
| 1442 | #define mmRLC_GPM_LOG_CONT 0xec7b | ||
| 1443 | #define mmRLC_PG_DELAY_3 0xec78 | ||
| 1444 | #define mmRLC_GPM_INT_DISABLE_TH0 0xec7c | ||
| 1445 | #define mmRLC_GPM_INT_DISABLE_TH1 0xec7d | ||
| 1446 | #define mmRLC_GPM_INT_FORCE_TH0 0xec7e | ||
| 1447 | #define mmRLC_GPM_INT_FORCE_TH1 0xec7f | ||
| 1448 | #define mmRLC_SRM_CNTL 0xec80 | ||
| 1449 | #define mmRLC_SRM_DEBUG_SELECT 0xec81 | ||
| 1450 | #define mmRLC_SRM_DEBUG 0xec82 | ||
| 1451 | #define mmRLC_SRM_ARAM_ADDR 0xec83 | ||
| 1452 | #define mmRLC_SRM_ARAM_DATA 0xec84 | ||
| 1453 | #define mmRLC_SRM_DRAM_ADDR 0xec85 | ||
| 1454 | #define mmRLC_SRM_DRAM_DATA 0xec86 | ||
| 1455 | #define mmRLC_SRM_GPM_COMMAND 0xec87 | ||
| 1456 | #define mmRLC_SRM_GPM_COMMAND_STATUS 0xec88 | ||
| 1457 | #define mmRLC_SRM_RLCV_COMMAND 0xec89 | ||
| 1458 | #define mmRLC_SRM_RLCV_COMMAND_STATUS 0xec8a | ||
| 1459 | #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b | ||
| 1460 | #define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xec8c | ||
| 1461 | #define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xec8d | ||
| 1462 | #define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xec8e | ||
| 1463 | #define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f | ||
| 1464 | #define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xec90 | ||
| 1465 | #define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xec91 | ||
| 1466 | #define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xec92 | ||
| 1467 | #define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93 | ||
| 1468 | #define mmRLC_SRM_INDEX_CNTL_DATA_1 0xec94 | ||
| 1469 | #define mmRLC_SRM_INDEX_CNTL_DATA_2 0xec95 | ||
| 1470 | #define mmRLC_SRM_INDEX_CNTL_DATA_3 0xec96 | ||
| 1471 | #define mmRLC_SRM_INDEX_CNTL_DATA_4 0xec97 | ||
| 1472 | #define mmRLC_SRM_INDEX_CNTL_DATA_5 0xec98 | ||
| 1473 | #define mmRLC_SRM_INDEX_CNTL_DATA_6 0xec99 | ||
| 1474 | #define mmRLC_SRM_INDEX_CNTL_DATA_7 0xec9a | ||
| 1475 | #define mmRLC_SRM_STAT 0xec9b | ||
| 1476 | #define mmRLC_SRM_GPM_ABORT 0xec9c | ||
| 1477 | #define mmRLC_CSIB_ADDR_LO 0xeca2 | ||
| 1478 | #define mmRLC_CSIB_ADDR_HI 0xeca3 | ||
| 1479 | #define mmRLC_CSIB_LENGTH 0xeca4 | ||
| 1480 | #define mmRLC_CP_RESPONSE0 0xeca5 | ||
| 1481 | #define mmRLC_CP_RESPONSE1 0xeca6 | ||
| 1482 | #define mmRLC_CP_RESPONSE2 0xeca7 | ||
| 1483 | #define mmRLC_CP_RESPONSE3 0xeca8 | ||
| 1484 | #define mmRLC_SMU_COMMAND 0xeca9 | ||
| 1485 | #define mmRLC_CP_SCHEDULERS 0xecaa | ||
| 1486 | #define mmRLC_SMU_ARGUMENT_1 0xecab | ||
| 1487 | #define mmRLC_SMU_ARGUMENT_2 0xecac | ||
| 1488 | #define mmRLC_GPM_GENERAL_8 0xecad | ||
| 1489 | #define mmRLC_GPM_GENERAL_9 0xecae | ||
| 1490 | #define mmRLC_GPM_GENERAL_10 0xecaf | ||
| 1491 | #define mmRLC_GPM_GENERAL_11 0xecb0 | ||
| 1492 | #define mmRLC_GPM_GENERAL_12 0xecb1 | ||
| 1493 | #define mmRLC_SPM_PERFMON_CNTL 0xdc80 | ||
| 1494 | #define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 | ||
| 1495 | #define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 | ||
| 1496 | #define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 | ||
| 1497 | #define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 | ||
| 1498 | #define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 | ||
| 1499 | #define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 | ||
| 1500 | #define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 | ||
| 1501 | #define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 | ||
| 1502 | #define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 | ||
| 1503 | #define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a | ||
| 1504 | #define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b | ||
| 1505 | #define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c | ||
| 1506 | #define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d | ||
| 1507 | #define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e | ||
| 1508 | #define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 | ||
| 1509 | #define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 | ||
| 1510 | #define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 | ||
| 1511 | #define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 | ||
| 1512 | #define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 | ||
| 1513 | #define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 | ||
| 1514 | #define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 | ||
| 1515 | #define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 | ||
| 1516 | #define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 | ||
| 1517 | #define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a | ||
| 1518 | #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b | ||
| 1519 | #define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c | ||
| 1520 | #define mmRLC_SPM_RING_RDPTR 0xdc9d | ||
| 1521 | #define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e | ||
| 1522 | #define mmRLC_GPU_IOV_VF_ENABLE 0xfb00 | ||
| 1523 | #define mmRLC_GPU_IOV_RLC_RESPONSE 0xfb4d | ||
| 1524 | #define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xfb40 | ||
| 1525 | #define mmSPI_PS_INPUT_CNTL_0 0xa191 | ||
| 1526 | #define mmSPI_PS_INPUT_CNTL_1 0xa192 | ||
| 1527 | #define mmSPI_PS_INPUT_CNTL_2 0xa193 | ||
| 1528 | #define mmSPI_PS_INPUT_CNTL_3 0xa194 | ||
| 1529 | #define mmSPI_PS_INPUT_CNTL_4 0xa195 | ||
| 1530 | #define mmSPI_PS_INPUT_CNTL_5 0xa196 | ||
| 1531 | #define mmSPI_PS_INPUT_CNTL_6 0xa197 | ||
| 1532 | #define mmSPI_PS_INPUT_CNTL_7 0xa198 | ||
| 1533 | #define mmSPI_PS_INPUT_CNTL_8 0xa199 | ||
| 1534 | #define mmSPI_PS_INPUT_CNTL_9 0xa19a | ||
| 1535 | #define mmSPI_PS_INPUT_CNTL_10 0xa19b | ||
| 1536 | #define mmSPI_PS_INPUT_CNTL_11 0xa19c | ||
| 1537 | #define mmSPI_PS_INPUT_CNTL_12 0xa19d | ||
| 1538 | #define mmSPI_PS_INPUT_CNTL_13 0xa19e | ||
| 1539 | #define mmSPI_PS_INPUT_CNTL_14 0xa19f | ||
| 1540 | #define mmSPI_PS_INPUT_CNTL_15 0xa1a0 | ||
| 1541 | #define mmSPI_PS_INPUT_CNTL_16 0xa1a1 | ||
| 1542 | #define mmSPI_PS_INPUT_CNTL_17 0xa1a2 | ||
| 1543 | #define mmSPI_PS_INPUT_CNTL_18 0xa1a3 | ||
| 1544 | #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 | ||
| 1545 | #define mmSPI_PS_INPUT_CNTL_20 0xa1a5 | ||
| 1546 | #define mmSPI_PS_INPUT_CNTL_21 0xa1a6 | ||
| 1547 | #define mmSPI_PS_INPUT_CNTL_22 0xa1a7 | ||
| 1548 | #define mmSPI_PS_INPUT_CNTL_23 0xa1a8 | ||
| 1549 | #define mmSPI_PS_INPUT_CNTL_24 0xa1a9 | ||
| 1550 | #define mmSPI_PS_INPUT_CNTL_25 0xa1aa | ||
| 1551 | #define mmSPI_PS_INPUT_CNTL_26 0xa1ab | ||
| 1552 | #define mmSPI_PS_INPUT_CNTL_27 0xa1ac | ||
| 1553 | #define mmSPI_PS_INPUT_CNTL_28 0xa1ad | ||
| 1554 | #define mmSPI_PS_INPUT_CNTL_29 0xa1ae | ||
| 1555 | #define mmSPI_PS_INPUT_CNTL_30 0xa1af | ||
| 1556 | #define mmSPI_PS_INPUT_CNTL_31 0xa1b0 | ||
| 1557 | #define mmSPI_VS_OUT_CONFIG 0xa1b1 | ||
| 1558 | #define mmSPI_PS_INPUT_ENA 0xa1b3 | ||
| 1559 | #define mmSPI_PS_INPUT_ADDR 0xa1b4 | ||
| 1560 | #define mmSPI_INTERP_CONTROL_0 0xa1b5 | ||
| 1561 | #define mmSPI_PS_IN_CONTROL 0xa1b6 | ||
| 1562 | #define mmSPI_BARYC_CNTL 0xa1b8 | ||
| 1563 | #define mmSPI_TMPRING_SIZE 0xa1ba | ||
| 1564 | #define mmSPI_SHADER_POS_FORMAT 0xa1c3 | ||
| 1565 | #define mmSPI_SHADER_Z_FORMAT 0xa1c4 | ||
| 1566 | #define mmSPI_SHADER_COL_FORMAT 0xa1c5 | ||
| 1567 | #define mmSPI_ARB_PRIORITY 0x31c0 | ||
| 1568 | #define mmSPI_ARB_CYCLES_0 0x31c1 | ||
| 1569 | #define mmSPI_ARB_CYCLES_1 0x31c2 | ||
| 1570 | #define mmSPI_CDBG_SYS_GFX 0x31c3 | ||
| 1571 | #define mmSPI_CDBG_SYS_HP3D 0x31c4 | ||
| 1572 | #define mmSPI_CDBG_SYS_CS0 0x31c5 | ||
| 1573 | #define mmSPI_CDBG_SYS_CS1 0x31c6 | ||
| 1574 | #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 | ||
| 1575 | #define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 | ||
| 1576 | #define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 | ||
| 1577 | #define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca | ||
| 1578 | #define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb | ||
| 1579 | #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc | ||
| 1580 | #define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd | ||
| 1581 | #define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce | ||
| 1582 | #define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf | ||
| 1583 | #define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 | ||
| 1584 | #define mmSPI_GDBG_WAVE_CNTL 0x31d1 | ||
| 1585 | #define mmSPI_GDBG_TRAP_CONFIG 0x31d2 | ||
| 1586 | #define mmSPI_GDBG_TRAP_MASK 0x31d3 | ||
| 1587 | #define mmSPI_GDBG_TBA_LO 0x31d4 | ||
| 1588 | #define mmSPI_GDBG_TBA_HI 0x31d5 | ||
| 1589 | #define mmSPI_GDBG_TMA_LO 0x31d6 | ||
| 1590 | #define mmSPI_GDBG_TMA_HI 0x31d7 | ||
| 1591 | #define mmSPI_GDBG_TRAP_DATA0 0x31d8 | ||
| 1592 | #define mmSPI_GDBG_TRAP_DATA1 0x31d9 | ||
| 1593 | #define mmSPI_RESET_DEBUG 0x31da | ||
| 1594 | #define mmSPI_COMPUTE_QUEUE_RESET 0x31db | ||
| 1595 | #define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc | ||
| 1596 | #define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd | ||
| 1597 | #define mmSPI_RESOURCE_RESERVE_CU_2 0x31de | ||
| 1598 | #define mmSPI_RESOURCE_RESERVE_CU_3 0x31df | ||
| 1599 | #define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 | ||
| 1600 | #define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 | ||
| 1601 | #define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 | ||
| 1602 | #define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 | ||
| 1603 | #define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 | ||
| 1604 | #define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 | ||
| 1605 | #define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 | ||
| 1606 | #define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 | ||
| 1607 | #define mmSPI_RESOURCE_RESERVE_CU_12 0x31f4 | ||
| 1608 | #define mmSPI_RESOURCE_RESERVE_CU_13 0x31f5 | ||
| 1609 | #define mmSPI_RESOURCE_RESERVE_CU_14 0x31f6 | ||
| 1610 | #define mmSPI_RESOURCE_RESERVE_CU_15 0x31f7 | ||
| 1611 | #define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 | ||
| 1612 | #define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 | ||
| 1613 | #define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 | ||
| 1614 | #define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 | ||
| 1615 | #define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea | ||
| 1616 | #define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb | ||
| 1617 | #define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec | ||
| 1618 | #define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed | ||
| 1619 | #define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee | ||
| 1620 | #define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef | ||
| 1621 | #define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 | ||
| 1622 | #define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 | ||
| 1623 | #define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31f8 | ||
| 1624 | #define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31f9 | ||
| 1625 | #define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31fa | ||
| 1626 | #define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31fb | ||
| 1627 | #define mmSPI_COMPUTE_WF_CTX_SAVE 0x31fc | ||
| 1628 | #define mmSPI_PS_MAX_WAVE_ID 0x243a | ||
| 1629 | #define mmSPI_START_PHASE 0x243b | ||
| 1630 | #define mmSPI_GFX_CNTL 0x243c | ||
| 1631 | #define mmSPI_CONFIG_CNTL 0x2440 | ||
| 1632 | #define mmSPI_DEBUG_CNTL 0x2441 | ||
| 1633 | #define mmSPI_DEBUG_READ 0x2442 | ||
| 1634 | #define mmSPI_DSM_CNTL 0x2443 | ||
| 1635 | #define mmSPI_EDC_CNT 0x2444 | ||
| 1636 | #define mmSPI_PERFCOUNTER0_SELECT 0xd980 | ||
| 1637 | #define mmSPI_PERFCOUNTER1_SELECT 0xd981 | ||
| 1638 | #define mmSPI_PERFCOUNTER2_SELECT 0xd982 | ||
| 1639 | #define mmSPI_PERFCOUNTER3_SELECT 0xd983 | ||
| 1640 | #define mmSPI_PERFCOUNTER0_SELECT1 0xd984 | ||
| 1641 | #define mmSPI_PERFCOUNTER1_SELECT1 0xd985 | ||
| 1642 | #define mmSPI_PERFCOUNTER2_SELECT1 0xd986 | ||
| 1643 | #define mmSPI_PERFCOUNTER3_SELECT1 0xd987 | ||
| 1644 | #define mmSPI_PERFCOUNTER4_SELECT 0xd988 | ||
| 1645 | #define mmSPI_PERFCOUNTER5_SELECT 0xd989 | ||
| 1646 | #define mmSPI_PERFCOUNTER_BINS 0xd98a | ||
| 1647 | #define mmSPI_PERFCOUNTER0_HI 0xd180 | ||
| 1648 | #define mmSPI_PERFCOUNTER0_LO 0xd181 | ||
| 1649 | #define mmSPI_PERFCOUNTER1_HI 0xd182 | ||
| 1650 | #define mmSPI_PERFCOUNTER1_LO 0xd183 | ||
| 1651 | #define mmSPI_PERFCOUNTER2_HI 0xd184 | ||
| 1652 | #define mmSPI_PERFCOUNTER2_LO 0xd185 | ||
| 1653 | #define mmSPI_PERFCOUNTER3_HI 0xd186 | ||
| 1654 | #define mmSPI_PERFCOUNTER3_LO 0xd187 | ||
| 1655 | #define mmSPI_PERFCOUNTER4_HI 0xd188 | ||
| 1656 | #define mmSPI_PERFCOUNTER4_LO 0xd189 | ||
| 1657 | #define mmSPI_PERFCOUNTER5_HI 0xd18a | ||
| 1658 | #define mmSPI_PERFCOUNTER5_LO 0xd18b | ||
| 1659 | #define mmSPI_CONFIG_CNTL_1 0x244f | ||
| 1660 | #define mmSPI_DEBUG_BUSY 0x2450 | ||
| 1661 | #define mmSPI_CONFIG_CNTL_2 0x2451 | ||
| 1662 | #define mmCGTS_SM_CTRL_REG 0xf000 | ||
| 1663 | #define mmCGTS_RD_CTRL_REG 0xf001 | ||
| 1664 | #define mmCGTS_RD_REG 0xf002 | ||
| 1665 | #define mmCGTS_TCC_DISABLE 0xf003 | ||
| 1666 | #define mmCGTS_USER_TCC_DISABLE 0xf004 | ||
| 1667 | #define mmCGTS_CU0_SP0_CTRL_REG 0xf008 | ||
| 1668 | #define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 | ||
| 1669 | #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a | ||
| 1670 | #define mmCGTS_CU0_SP1_CTRL_REG 0xf00b | ||
| 1671 | #define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c | ||
| 1672 | #define mmCGTS_CU1_SP0_CTRL_REG 0xf00d | ||
| 1673 | #define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e | ||
| 1674 | #define mmCGTS_CU1_TA_CTRL_REG 0xf00f | ||
| 1675 | #define mmCGTS_CU1_SP1_CTRL_REG 0xf010 | ||
| 1676 | #define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 | ||
| 1677 | #define mmCGTS_CU2_SP0_CTRL_REG 0xf012 | ||
| 1678 | #define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 | ||
| 1679 | #define mmCGTS_CU2_TA_CTRL_REG 0xf014 | ||
| 1680 | #define mmCGTS_CU2_SP1_CTRL_REG 0xf015 | ||
| 1681 | #define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 | ||
| 1682 | #define mmCGTS_CU3_SP0_CTRL_REG 0xf017 | ||
| 1683 | #define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 | ||
| 1684 | #define mmCGTS_CU3_TA_CTRL_REG 0xf019 | ||
| 1685 | #define mmCGTS_CU3_SP1_CTRL_REG 0xf01a | ||
| 1686 | #define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b | ||
| 1687 | #define mmCGTS_CU4_SP0_CTRL_REG 0xf01c | ||
| 1688 | #define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d | ||
| 1689 | #define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e | ||
| 1690 | #define mmCGTS_CU4_SP1_CTRL_REG 0xf01f | ||
| 1691 | #define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 | ||
| 1692 | #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 | ||
| 1693 | #define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 | ||
| 1694 | #define mmCGTS_CU5_TA_CTRL_REG 0xf023 | ||
| 1695 | #define mmCGTS_CU5_SP1_CTRL_REG 0xf024 | ||
| 1696 | #define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 | ||
| 1697 | #define mmCGTS_CU6_SP0_CTRL_REG 0xf026 | ||
| 1698 | #define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 | ||
| 1699 | #define mmCGTS_CU6_TA_CTRL_REG 0xf028 | ||
| 1700 | #define mmCGTS_CU6_SP1_CTRL_REG 0xf029 | ||
| 1701 | #define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a | ||
| 1702 | #define mmCGTS_CU7_SP0_CTRL_REG 0xf02b | ||
| 1703 | #define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c | ||
| 1704 | #define mmCGTS_CU7_TA_CTRL_REG 0xf02d | ||
| 1705 | #define mmCGTS_CU7_SP1_CTRL_REG 0xf02e | ||
| 1706 | #define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f | ||
| 1707 | #define mmCGTS_CU8_SP0_CTRL_REG 0xf030 | ||
| 1708 | #define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 | ||
| 1709 | #define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 | ||
| 1710 | #define mmCGTS_CU8_SP1_CTRL_REG 0xf033 | ||
| 1711 | #define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 | ||
| 1712 | #define mmCGTS_CU9_SP0_CTRL_REG 0xf035 | ||
| 1713 | #define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 | ||
| 1714 | #define mmCGTS_CU9_TA_CTRL_REG 0xf037 | ||
| 1715 | #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 | ||
| 1716 | #define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 | ||
| 1717 | #define mmCGTS_CU10_SP0_CTRL_REG 0xf03a | ||
| 1718 | #define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b | ||
| 1719 | #define mmCGTS_CU10_TA_CTRL_REG 0xf03c | ||
| 1720 | #define mmCGTS_CU10_SP1_CTRL_REG 0xf03d | ||
| 1721 | #define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e | ||
| 1722 | #define mmCGTS_CU11_SP0_CTRL_REG 0xf03f | ||
| 1723 | #define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 | ||
| 1724 | #define mmCGTS_CU11_TA_CTRL_REG 0xf041 | ||
| 1725 | #define mmCGTS_CU11_SP1_CTRL_REG 0xf042 | ||
| 1726 | #define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 | ||
| 1727 | #define mmCGTS_CU12_SP0_CTRL_REG 0xf044 | ||
| 1728 | #define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 | ||
| 1729 | #define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 | ||
| 1730 | #define mmCGTS_CU12_SP1_CTRL_REG 0xf047 | ||
| 1731 | #define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 | ||
| 1732 | #define mmCGTS_CU13_SP0_CTRL_REG 0xf049 | ||
| 1733 | #define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a | ||
| 1734 | #define mmCGTS_CU13_TA_CTRL_REG 0xf04b | ||
| 1735 | #define mmCGTS_CU13_SP1_CTRL_REG 0xf04c | ||
| 1736 | #define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d | ||
| 1737 | #define mmCGTS_CU14_SP0_CTRL_REG 0xf04e | ||
| 1738 | #define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f | ||
| 1739 | #define mmCGTS_CU14_TA_CTRL_REG 0xf050 | ||
| 1740 | #define mmCGTS_CU14_SP1_CTRL_REG 0xf051 | ||
| 1741 | #define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 | ||
| 1742 | #define mmCGTS_CU15_SP0_CTRL_REG 0xf053 | ||
| 1743 | #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 | ||
| 1744 | #define mmCGTS_CU15_TA_CTRL_REG 0xf055 | ||
| 1745 | #define mmCGTS_CU15_SP1_CTRL_REG 0xf056 | ||
| 1746 | #define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 | ||
| 1747 | #define mmCGTT_SPI_CLK_CTRL 0xf080 | ||
| 1748 | #define mmCGTT_PC_CLK_CTRL 0xf081 | ||
| 1749 | #define mmCGTT_BCI_CLK_CTRL 0xf082 | ||
| 1750 | #define mmSPI_WF_LIFETIME_CNTL 0x24aa | ||
| 1751 | #define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab | ||
| 1752 | #define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac | ||
| 1753 | #define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad | ||
| 1754 | #define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae | ||
| 1755 | #define mmSPI_WF_LIFETIME_LIMIT_4 0x24af | ||
| 1756 | #define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 | ||
| 1757 | #define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 | ||
| 1758 | #define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 | ||
| 1759 | #define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 | ||
| 1760 | #define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 | ||
| 1761 | #define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 | ||
| 1762 | #define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 | ||
| 1763 | #define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 | ||
| 1764 | #define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 | ||
| 1765 | #define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 | ||
| 1766 | #define mmSPI_WF_LIFETIME_STATUS_5 0x24ba | ||
| 1767 | #define mmSPI_WF_LIFETIME_STATUS_6 0x24bb | ||
| 1768 | #define mmSPI_WF_LIFETIME_STATUS_7 0x24bc | ||
| 1769 | #define mmSPI_WF_LIFETIME_STATUS_8 0x24bd | ||
| 1770 | #define mmSPI_WF_LIFETIME_STATUS_9 0x24be | ||
| 1771 | #define mmSPI_WF_LIFETIME_STATUS_10 0x24bf | ||
| 1772 | #define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 | ||
| 1773 | #define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 | ||
| 1774 | #define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 | ||
| 1775 | #define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 | ||
| 1776 | #define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 | ||
| 1777 | #define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 | ||
| 1778 | #define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 | ||
| 1779 | #define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 | ||
| 1780 | #define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 | ||
| 1781 | #define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 | ||
| 1782 | #define mmSPI_WF_LIFETIME_DEBUG 0x24ca | ||
| 1783 | #define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 | ||
| 1784 | #define mmSPI_LB_CTR_CTRL 0x24d4 | ||
| 1785 | #define mmSPI_LB_CU_MASK 0x24d5 | ||
| 1786 | #define mmSPI_LB_DATA_REG 0x24d6 | ||
| 1787 | #define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 | ||
| 1788 | #define mmSPI_GDS_CREDITS 0x24d8 | ||
| 1789 | #define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 | ||
| 1790 | #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da | ||
| 1791 | #define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db | ||
| 1792 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc | ||
| 1793 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd | ||
| 1794 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de | ||
| 1795 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df | ||
| 1796 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 | ||
| 1797 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 | ||
| 1798 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 | ||
| 1799 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 | ||
| 1800 | #define mmBCI_DEBUG_READ 0x24eb | ||
| 1801 | #define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec | ||
| 1802 | #define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed | ||
| 1803 | #define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee | ||
| 1804 | #define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef | ||
| 1805 | #define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 | ||
| 1806 | #define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 | ||
| 1807 | #define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 | ||
| 1808 | #define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 | ||
| 1809 | #define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 | ||
| 1810 | #define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 | ||
| 1811 | #define mmSPI_SHADER_TBA_LO_PS 0x2c00 | ||
| 1812 | #define mmSPI_SHADER_TBA_HI_PS 0x2c01 | ||
| 1813 | #define mmSPI_SHADER_TMA_LO_PS 0x2c02 | ||
| 1814 | #define mmSPI_SHADER_TMA_HI_PS 0x2c03 | ||
| 1815 | #define mmSPI_SHADER_PGM_LO_PS 0x2c08 | ||
| 1816 | #define mmSPI_SHADER_PGM_HI_PS 0x2c09 | ||
| 1817 | #define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a | ||
| 1818 | #define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b | ||
| 1819 | #define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 | ||
| 1820 | #define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c | ||
| 1821 | #define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d | ||
| 1822 | #define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e | ||
| 1823 | #define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f | ||
| 1824 | #define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 | ||
| 1825 | #define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 | ||
| 1826 | #define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 | ||
| 1827 | #define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 | ||
| 1828 | #define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 | ||
| 1829 | #define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 | ||
| 1830 | #define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 | ||
| 1831 | #define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 | ||
| 1832 | #define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 | ||
| 1833 | #define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 | ||
| 1834 | #define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a | ||
| 1835 | #define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b | ||
| 1836 | #define mmSPI_SHADER_TBA_LO_VS 0x2c40 | ||
| 1837 | #define mmSPI_SHADER_TBA_HI_VS 0x2c41 | ||
| 1838 | #define mmSPI_SHADER_TMA_LO_VS 0x2c42 | ||
| 1839 | #define mmSPI_SHADER_TMA_HI_VS 0x2c43 | ||
| 1840 | #define mmSPI_SHADER_PGM_LO_VS 0x2c48 | ||
| 1841 | #define mmSPI_SHADER_PGM_HI_VS 0x2c49 | ||
| 1842 | #define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a | ||
| 1843 | #define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b | ||
| 1844 | #define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 | ||
| 1845 | #define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 | ||
| 1846 | #define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c | ||
| 1847 | #define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d | ||
| 1848 | #define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e | ||
| 1849 | #define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f | ||
| 1850 | #define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 | ||
| 1851 | #define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 | ||
| 1852 | #define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 | ||
| 1853 | #define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 | ||
| 1854 | #define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 | ||
| 1855 | #define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 | ||
| 1856 | #define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 | ||
| 1857 | #define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 | ||
| 1858 | #define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 | ||
| 1859 | #define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 | ||
| 1860 | #define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a | ||
| 1861 | #define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b | ||
| 1862 | #define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c | ||
| 1863 | #define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d | ||
| 1864 | #define mmSPI_SHADER_TBA_LO_GS 0x2c80 | ||
| 1865 | #define mmSPI_SHADER_TBA_HI_GS 0x2c81 | ||
| 1866 | #define mmSPI_SHADER_TMA_LO_GS 0x2c82 | ||
| 1867 | #define mmSPI_SHADER_TMA_HI_GS 0x2c83 | ||
| 1868 | #define mmSPI_SHADER_PGM_LO_GS 0x2c88 | ||
| 1869 | #define mmSPI_SHADER_PGM_HI_GS 0x2c89 | ||
| 1870 | #define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a | ||
| 1871 | #define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b | ||
| 1872 | #define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 | ||
| 1873 | #define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c | ||
| 1874 | #define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d | ||
| 1875 | #define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e | ||
| 1876 | #define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f | ||
| 1877 | #define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 | ||
| 1878 | #define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 | ||
| 1879 | #define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 | ||
| 1880 | #define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 | ||
| 1881 | #define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 | ||
| 1882 | #define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 | ||
| 1883 | #define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 | ||
| 1884 | #define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 | ||
| 1885 | #define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 | ||
| 1886 | #define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 | ||
| 1887 | #define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a | ||
| 1888 | #define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b | ||
| 1889 | #define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc | ||
| 1890 | #define mmSPI_SHADER_TBA_LO_ES 0x2cc0 | ||
| 1891 | #define mmSPI_SHADER_TBA_HI_ES 0x2cc1 | ||
| 1892 | #define mmSPI_SHADER_TMA_LO_ES 0x2cc2 | ||
| 1893 | #define mmSPI_SHADER_TMA_HI_ES 0x2cc3 | ||
| 1894 | #define mmSPI_SHADER_PGM_LO_ES 0x2cc8 | ||
| 1895 | #define mmSPI_SHADER_PGM_HI_ES 0x2cc9 | ||
| 1896 | #define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca | ||
| 1897 | #define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb | ||
| 1898 | #define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 | ||
| 1899 | #define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc | ||
| 1900 | #define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd | ||
| 1901 | #define mmSPI_SHADER_USER_DATA_ES_2 0x2cce | ||
| 1902 | #define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf | ||
| 1903 | #define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 | ||
| 1904 | #define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 | ||
| 1905 | #define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 | ||
| 1906 | #define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 | ||
| 1907 | #define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 | ||
| 1908 | #define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 | ||
| 1909 | #define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 | ||
| 1910 | #define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 | ||
| 1911 | #define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 | ||
| 1912 | #define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 | ||
| 1913 | #define mmSPI_SHADER_USER_DATA_ES_14 0x2cda | ||
| 1914 | #define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb | ||
| 1915 | #define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd | ||
| 1916 | #define mmSPI_SHADER_TBA_LO_HS 0x2d00 | ||
| 1917 | #define mmSPI_SHADER_TBA_HI_HS 0x2d01 | ||
| 1918 | #define mmSPI_SHADER_TMA_LO_HS 0x2d02 | ||
| 1919 | #define mmSPI_SHADER_TMA_HI_HS 0x2d03 | ||
| 1920 | #define mmSPI_SHADER_PGM_LO_HS 0x2d08 | ||
| 1921 | #define mmSPI_SHADER_PGM_HI_HS 0x2d09 | ||
| 1922 | #define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a | ||
| 1923 | #define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b | ||
| 1924 | #define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 | ||
| 1925 | #define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c | ||
| 1926 | #define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d | ||
| 1927 | #define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e | ||
| 1928 | #define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f | ||
| 1929 | #define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 | ||
| 1930 | #define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 | ||
| 1931 | #define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 | ||
| 1932 | #define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 | ||
| 1933 | #define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 | ||
| 1934 | #define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 | ||
| 1935 | #define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 | ||
| 1936 | #define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 | ||
| 1937 | #define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 | ||
| 1938 | #define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 | ||
| 1939 | #define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a | ||
| 1940 | #define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b | ||
| 1941 | #define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d | ||
| 1942 | #define mmSPI_SHADER_TBA_LO_LS 0x2d40 | ||
| 1943 | #define mmSPI_SHADER_TBA_HI_LS 0x2d41 | ||
| 1944 | #define mmSPI_SHADER_TMA_LO_LS 0x2d42 | ||
| 1945 | #define mmSPI_SHADER_TMA_HI_LS 0x2d43 | ||
| 1946 | #define mmSPI_SHADER_PGM_LO_LS 0x2d48 | ||
| 1947 | #define mmSPI_SHADER_PGM_HI_LS 0x2d49 | ||
| 1948 | #define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a | ||
| 1949 | #define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b | ||
| 1950 | #define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 | ||
| 1951 | #define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c | ||
| 1952 | #define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d | ||
| 1953 | #define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e | ||
| 1954 | #define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f | ||
| 1955 | #define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 | ||
| 1956 | #define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 | ||
| 1957 | #define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 | ||
| 1958 | #define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 | ||
| 1959 | #define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 | ||
| 1960 | #define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 | ||
| 1961 | #define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 | ||
| 1962 | #define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 | ||
| 1963 | #define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 | ||
| 1964 | #define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 | ||
| 1965 | #define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a | ||
| 1966 | #define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b | ||
| 1967 | #define mmSQ_CONFIG 0x2300 | ||
| 1968 | #define mmSQC_CONFIG 0x2301 | ||
| 1969 | #define mmSQC_CACHES 0xc348 | ||
| 1970 | #define mmSQC_WRITEBACK 0xc349 | ||
| 1971 | #define mmSQC_DSM_CNTL 0x230f | ||
| 1972 | #define mmSQ_RANDOM_WAVE_PRI 0x2303 | ||
| 1973 | #define mmSQ_REG_CREDITS 0x2304 | ||
| 1974 | #define mmSQ_FIFO_SIZES 0x2305 | ||
| 1975 | #define mmSQ_DSM_CNTL 0x2306 | ||
| 1976 | #define mmCC_GC_SHADER_RATE_CONFIG 0x2312 | ||
| 1977 | #define mmGC_USER_SHADER_RATE_CONFIG 0x2313 | ||
| 1978 | #define mmSQ_INTERRUPT_AUTO_MASK 0x2314 | ||
| 1979 | #define mmSQ_INTERRUPT_MSG_CTRL 0x2315 | ||
| 1980 | #define mmSQ_PERFCOUNTER_CTRL 0xd9e0 | ||
| 1981 | #define mmSQ_PERFCOUNTER_MASK 0xd9e1 | ||
| 1982 | #define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 | ||
| 1983 | #define mmCC_SQC_BANK_DISABLE 0x2307 | ||
| 1984 | #define mmUSER_SQC_BANK_DISABLE 0x2308 | ||
| 1985 | #define mmSQ_PERFCOUNTER0_LO 0xd1c0 | ||
| 1986 | #define mmSQ_PERFCOUNTER1_LO 0xd1c2 | ||
| 1987 | #define mmSQ_PERFCOUNTER2_LO 0xd1c4 | ||
| 1988 | #define mmSQ_PERFCOUNTER3_LO 0xd1c6 | ||
| 1989 | #define mmSQ_PERFCOUNTER4_LO 0xd1c8 | ||
| 1990 | #define mmSQ_PERFCOUNTER5_LO 0xd1ca | ||
| 1991 | #define mmSQ_PERFCOUNTER6_LO 0xd1cc | ||
| 1992 | #define mmSQ_PERFCOUNTER7_LO 0xd1ce | ||
| 1993 | #define mmSQ_PERFCOUNTER8_LO 0xd1d0 | ||
| 1994 | #define mmSQ_PERFCOUNTER9_LO 0xd1d2 | ||
| 1995 | #define mmSQ_PERFCOUNTER10_LO 0xd1d4 | ||
| 1996 | #define mmSQ_PERFCOUNTER11_LO 0xd1d6 | ||
| 1997 | #define mmSQ_PERFCOUNTER12_LO 0xd1d8 | ||
| 1998 | #define mmSQ_PERFCOUNTER13_LO 0xd1da | ||
| 1999 | #define mmSQ_PERFCOUNTER14_LO 0xd1dc | ||
| 2000 | #define mmSQ_PERFCOUNTER15_LO 0xd1de | ||
| 2001 | #define mmSQ_PERFCOUNTER0_HI 0xd1c1 | ||
| 2002 | #define mmSQ_PERFCOUNTER1_HI 0xd1c3 | ||
| 2003 | #define mmSQ_PERFCOUNTER2_HI 0xd1c5 | ||
| 2004 | #define mmSQ_PERFCOUNTER3_HI 0xd1c7 | ||
| 2005 | #define mmSQ_PERFCOUNTER4_HI 0xd1c9 | ||
| 2006 | #define mmSQ_PERFCOUNTER5_HI 0xd1cb | ||
| 2007 | #define mmSQ_PERFCOUNTER6_HI 0xd1cd | ||
| 2008 | #define mmSQ_PERFCOUNTER7_HI 0xd1cf | ||
| 2009 | #define mmSQ_PERFCOUNTER8_HI 0xd1d1 | ||
| 2010 | #define mmSQ_PERFCOUNTER9_HI 0xd1d3 | ||
| 2011 | #define mmSQ_PERFCOUNTER10_HI 0xd1d5 | ||
| 2012 | #define mmSQ_PERFCOUNTER11_HI 0xd1d7 | ||
| 2013 | #define mmSQ_PERFCOUNTER12_HI 0xd1d9 | ||
| 2014 | #define mmSQ_PERFCOUNTER13_HI 0xd1db | ||
| 2015 | #define mmSQ_PERFCOUNTER14_HI 0xd1dd | ||
| 2016 | #define mmSQ_PERFCOUNTER15_HI 0xd1df | ||
| 2017 | #define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 | ||
| 2018 | #define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 | ||
| 2019 | #define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 | ||
| 2020 | #define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 | ||
| 2021 | #define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 | ||
| 2022 | #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 | ||
| 2023 | #define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 | ||
| 2024 | #define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 | ||
| 2025 | #define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 | ||
| 2026 | #define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 | ||
| 2027 | #define mmSQ_PERFCOUNTER10_SELECT 0xd9ca | ||
| 2028 | #define mmSQ_PERFCOUNTER11_SELECT 0xd9cb | ||
| 2029 | #define mmSQ_PERFCOUNTER12_SELECT 0xd9cc | ||
| 2030 | #define mmSQ_PERFCOUNTER13_SELECT 0xd9cd | ||
| 2031 | #define mmSQ_PERFCOUNTER14_SELECT 0xd9ce | ||
| 2032 | #define mmSQ_PERFCOUNTER15_SELECT 0xd9cf | ||
| 2033 | #define mmCGTT_SQ_CLK_CTRL 0xf08c | ||
| 2034 | #define mmCGTT_SQG_CLK_CTRL 0xf08d | ||
| 2035 | #define mmSQ_ALU_CLK_CTRL 0xf08e | ||
| 2036 | #define mmSQ_TEX_CLK_CTRL 0xf08f | ||
| 2037 | #define mmSQ_LDS_CLK_CTRL 0xf090 | ||
| 2038 | #define mmSQ_POWER_THROTTLE 0xf091 | ||
| 2039 | #define mmSQ_POWER_THROTTLE2 0xf092 | ||
| 2040 | #define mmSQ_TIME_HI 0x237c | ||
| 2041 | #define mmSQ_TIME_LO 0x237d | ||
| 2042 | #define mmSQ_THREAD_TRACE_BASE 0xc330 | ||
| 2043 | #define mmSQ_THREAD_TRACE_BASE2 0xc337 | ||
| 2044 | #define mmSQ_THREAD_TRACE_SIZE 0xc331 | ||
| 2045 | #define mmSQ_THREAD_TRACE_MASK 0xc332 | ||
| 2046 | #define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 | ||
| 2047 | #define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 | ||
| 2048 | #define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 | ||
| 2049 | #define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 | ||
| 2050 | #define mmSQ_THREAD_TRACE_MODE 0xc336 | ||
| 2051 | #define mmSQ_THREAD_TRACE_CTRL 0xc335 | ||
| 2052 | #define mmSQ_THREAD_TRACE_TOKEN_MASK 0xc333 | ||
| 2053 | #define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xc338 | ||
| 2054 | #define mmSQ_THREAD_TRACE_PERF_MASK 0xc334 | ||
| 2055 | #define mmSQ_THREAD_TRACE_WPTR 0xc339 | ||
| 2056 | #define mmSQ_THREAD_TRACE_STATUS 0xc33a | ||
| 2057 | #define mmSQ_THREAD_TRACE_CNTR 0x2390 | ||
| 2058 | #define mmSQ_THREAD_TRACE_HIWATER 0xc33b | ||
| 2059 | #define mmSQ_LB_CTR_CTRL 0x2398 | ||
| 2060 | #define mmSQ_LB_DATA_ALU_CYCLES 0x2399 | ||
| 2061 | #define mmSQ_LB_DATA_TEX_CYCLES 0x239a | ||
| 2062 | #define mmSQ_LB_DATA_ALU_STALLS 0x239b | ||
| 2063 | #define mmSQ_LB_DATA_TEX_STALLS 0x239c | ||
| 2064 | #define mmSQC_EDC_CNT 0x23a0 | ||
| 2065 | #define mmSQ_EDC_SEC_CNT 0x23a1 | ||
| 2066 | #define mmSQ_EDC_DED_CNT 0x23a2 | ||
| 2067 | #define mmSQ_EDC_INFO 0x23a3 | ||
| 2068 | #define mmSQ_BUF_RSRC_WORD0 0x23c0 | ||
| 2069 | #define mmSQ_BUF_RSRC_WORD1 0x23c1 | ||
| 2070 | #define mmSQ_BUF_RSRC_WORD2 0x23c2 | ||
| 2071 | #define mmSQ_BUF_RSRC_WORD3 0x23c3 | ||
| 2072 | #define mmSQ_IMG_RSRC_WORD0 0x23c4 | ||
| 2073 | #define mmSQ_IMG_RSRC_WORD1 0x23c5 | ||
| 2074 | #define mmSQ_IMG_RSRC_WORD2 0x23c6 | ||
| 2075 | #define mmSQ_IMG_RSRC_WORD3 0x23c7 | ||
| 2076 | #define mmSQ_IMG_RSRC_WORD4 0x23c8 | ||
| 2077 | #define mmSQ_IMG_RSRC_WORD5 0x23c9 | ||
| 2078 | #define mmSQ_IMG_RSRC_WORD6 0x23ca | ||
| 2079 | #define mmSQ_IMG_RSRC_WORD7 0x23cb | ||
| 2080 | #define mmSQ_IMG_SAMP_WORD0 0x23cc | ||
| 2081 | #define mmSQ_IMG_SAMP_WORD1 0x23cd | ||
| 2082 | #define mmSQ_IMG_SAMP_WORD2 0x23ce | ||
| 2083 | #define mmSQ_IMG_SAMP_WORD3 0x23cf | ||
| 2084 | #define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 | ||
| 2085 | #define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 | ||
| 2086 | #define mmSQ_M0_GPR_IDX_WORD 0x23d2 | ||
| 2087 | #define mmSQ_IND_INDEX 0x2378 | ||
| 2088 | #define mmSQ_CMD 0x237b | ||
| 2089 | #define mmSQ_IND_DATA 0x2379 | ||
| 2090 | #define mmSQ_REG_TIMESTAMP 0x2374 | ||
| 2091 | #define mmSQ_CMD_TIMESTAMP 0x2375 | ||
| 2092 | #define mmSQ_HV_VMID_CTRL 0xf840 | ||
| 2093 | #define ixSQ_WAVE_INST_DW0 0x1a | ||
| 2094 | #define ixSQ_WAVE_INST_DW1 0x1b | ||
| 2095 | #define ixSQ_WAVE_PC_LO 0x18 | ||
| 2096 | #define ixSQ_WAVE_PC_HI 0x19 | ||
| 2097 | #define ixSQ_WAVE_IB_DBG0 0x1c | ||
| 2098 | #define ixSQ_WAVE_IB_DBG1 0x1d | ||
| 2099 | #define ixSQ_WAVE_EXEC_LO 0x27e | ||
| 2100 | #define ixSQ_WAVE_EXEC_HI 0x27f | ||
| 2101 | #define ixSQ_WAVE_STATUS 0x12 | ||
| 2102 | #define ixSQ_WAVE_MODE 0x11 | ||
| 2103 | #define ixSQ_WAVE_TRAPSTS 0x13 | ||
| 2104 | #define ixSQ_WAVE_HW_ID 0x14 | ||
| 2105 | #define ixSQ_WAVE_GPR_ALLOC 0x15 | ||
| 2106 | #define ixSQ_WAVE_LDS_ALLOC 0x16 | ||
| 2107 | #define ixSQ_WAVE_IB_STS 0x17 | ||
| 2108 | #define ixSQ_WAVE_M0 0x27c | ||
| 2109 | #define ixSQ_WAVE_TBA_LO 0x26c | ||
| 2110 | #define ixSQ_WAVE_TBA_HI 0x26d | ||
| 2111 | #define ixSQ_WAVE_TMA_LO 0x26e | ||
| 2112 | #define ixSQ_WAVE_TMA_HI 0x26f | ||
| 2113 | #define ixSQ_WAVE_TTMP0 0x270 | ||
| 2114 | #define ixSQ_WAVE_TTMP1 0x271 | ||
| 2115 | #define ixSQ_WAVE_TTMP2 0x272 | ||
| 2116 | #define ixSQ_WAVE_TTMP3 0x273 | ||
| 2117 | #define ixSQ_WAVE_TTMP4 0x274 | ||
| 2118 | #define ixSQ_WAVE_TTMP5 0x275 | ||
| 2119 | #define ixSQ_WAVE_TTMP6 0x276 | ||
| 2120 | #define ixSQ_WAVE_TTMP7 0x277 | ||
| 2121 | #define ixSQ_WAVE_TTMP8 0x278 | ||
| 2122 | #define ixSQ_WAVE_TTMP9 0x279 | ||
| 2123 | #define ixSQ_WAVE_TTMP10 0x27a | ||
| 2124 | #define ixSQ_WAVE_TTMP11 0x27b | ||
| 2125 | #define mmSQ_DEBUG_STS_GLOBAL 0x2309 | ||
| 2126 | #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 | ||
| 2127 | #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 | ||
| 2128 | #define ixSQ_DEBUG_STS_LOCAL 0x8 | ||
| 2129 | #define ixSQ_DEBUG_CTRL_LOCAL 0x9 | ||
| 2130 | #define mmSH_MEM_BASES 0x230a | ||
| 2131 | #define mmSH_MEM_APE1_BASE 0x230b | ||
| 2132 | #define mmSH_MEM_APE1_LIMIT 0x230c | ||
| 2133 | #define mmSH_MEM_CONFIG 0x230d | ||
| 2134 | #define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 | ||
| 2135 | #define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 | ||
| 2136 | #define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 | ||
| 2137 | #define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 | ||
| 2138 | #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 | ||
| 2139 | #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 | ||
| 2140 | #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 | ||
| 2141 | #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 | ||
| 2142 | #define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 | ||
| 2143 | #define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 | ||
| 2144 | #define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 | ||
| 2145 | #define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 | ||
| 2146 | #define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 | ||
| 2147 | #define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 | ||
| 2148 | #define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 | ||
| 2149 | #define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 | ||
| 2150 | #define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 | ||
| 2151 | #define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 | ||
| 2152 | #define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 | ||
| 2153 | #define mmSQ_WREXEC_EXEC_LO 0x23b1 | ||
| 2154 | #define mmSQ_WREXEC_EXEC_HI 0x23b1 | ||
| 2155 | #define mmSQC_GATCL1_CNTL 0x23b2 | ||
| 2156 | #define mmSQC_ATC_EDC_GATCL1_CNT 0x23b3 | ||
| 2157 | #define ixSQ_INTERRUPT_WORD_CMN 0x20c0 | ||
| 2158 | #define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 | ||
| 2159 | #define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 | ||
| 2160 | #define mmSQ_SOP2 0x237f | ||
| 2161 | #define mmSQ_VOP1 0x237f | ||
| 2162 | #define mmSQ_MTBUF_1 0x237f | ||
| 2163 | #define mmSQ_EXP_1 0x237f | ||
| 2164 | #define mmSQ_MUBUF_1 0x237f | ||
| 2165 | #define mmSQ_SMEM_1 0x237f | ||
| 2166 | #define mmSQ_INST 0x237f | ||
| 2167 | #define mmSQ_EXP_0 0x237f | ||
| 2168 | #define mmSQ_MUBUF_0 0x237f | ||
| 2169 | #define mmSQ_VOP_SDWA 0x237f | ||
| 2170 | #define mmSQ_VOP3_0 0x237f | ||
| 2171 | #define mmSQ_VOP2 0x237f | ||
| 2172 | #define mmSQ_MTBUF_0 0x237f | ||
| 2173 | #define mmSQ_SOPP 0x237f | ||
| 2174 | #define mmSQ_FLAT_0 0x237f | ||
| 2175 | #define mmSQ_VOP3_0_SDST_ENC 0x237f | ||
| 2176 | #define mmSQ_MIMG_1 0x237f | ||
| 2177 | #define mmSQ_SOP1 0x237f | ||
| 2178 | #define mmSQ_SOPC 0x237f | ||
| 2179 | #define mmSQ_FLAT_1 0x237f | ||
| 2180 | #define mmSQ_DS_1 0x237f | ||
| 2181 | #define mmSQ_VOP3_1 0x237f | ||
| 2182 | #define mmSQ_SMEM_0 0x237f | ||
| 2183 | #define mmSQ_MIMG_0 0x237f | ||
| 2184 | #define mmSQ_SOPK 0x237f | ||
| 2185 | #define mmSQ_DS_0 0x237f | ||
| 2186 | #define mmSQ_VOP_DPP 0x237f | ||
| 2187 | #define mmSQ_VOPC 0x237f | ||
| 2188 | #define mmSQ_VINTRP 0x237f | ||
| 2189 | #define mmCGTT_SX_CLK_CTRL0 0xf094 | ||
| 2190 | #define mmCGTT_SX_CLK_CTRL1 0xf095 | ||
| 2191 | #define mmCGTT_SX_CLK_CTRL2 0xf096 | ||
| 2192 | #define mmCGTT_SX_CLK_CTRL3 0xf097 | ||
| 2193 | #define mmCGTT_SX_CLK_CTRL4 0xf098 | ||
| 2194 | #define mmSX_DEBUG_BUSY 0x2414 | ||
| 2195 | #define mmSX_DEBUG_BUSY_2 0x2415 | ||
| 2196 | #define mmSX_DEBUG_BUSY_3 0x2416 | ||
| 2197 | #define mmSX_DEBUG_BUSY_4 0x2417 | ||
| 2198 | #define mmSX_DEBUG_1 0x2418 | ||
| 2199 | #define mmSX_PERFCOUNTER0_SELECT 0xda40 | ||
| 2200 | #define mmSX_PERFCOUNTER1_SELECT 0xda41 | ||
| 2201 | #define mmSX_PERFCOUNTER2_SELECT 0xda42 | ||
| 2202 | #define mmSX_PERFCOUNTER3_SELECT 0xda43 | ||
| 2203 | #define mmSX_PERFCOUNTER0_SELECT1 0xda44 | ||
| 2204 | #define mmSX_PERFCOUNTER1_SELECT1 0xda45 | ||
| 2205 | #define mmSX_PERFCOUNTER0_LO 0xd240 | ||
| 2206 | #define mmSX_PERFCOUNTER0_HI 0xd241 | ||
| 2207 | #define mmSX_PERFCOUNTER1_LO 0xd242 | ||
| 2208 | #define mmSX_PERFCOUNTER1_HI 0xd243 | ||
| 2209 | #define mmSX_PERFCOUNTER2_LO 0xd244 | ||
| 2210 | #define mmSX_PERFCOUNTER2_HI 0xd245 | ||
| 2211 | #define mmSX_PERFCOUNTER3_LO 0xd246 | ||
| 2212 | #define mmSX_PERFCOUNTER3_HI 0xd247 | ||
| 2213 | #define mmSX_PS_DOWNCONVERT 0xa1d5 | ||
| 2214 | #define mmSX_BLEND_OPT_EPSILON 0xa1d6 | ||
| 2215 | #define mmSX_BLEND_OPT_CONTROL 0xa1d7 | ||
| 2216 | #define mmSX_MRT0_BLEND_OPT 0xa1d8 | ||
| 2217 | #define mmSX_MRT1_BLEND_OPT 0xa1d9 | ||
| 2218 | #define mmSX_MRT2_BLEND_OPT 0xa1da | ||
| 2219 | #define mmSX_MRT3_BLEND_OPT 0xa1db | ||
| 2220 | #define mmSX_MRT4_BLEND_OPT 0xa1dc | ||
| 2221 | #define mmSX_MRT5_BLEND_OPT 0xa1dd | ||
| 2222 | #define mmSX_MRT6_BLEND_OPT 0xa1de | ||
| 2223 | #define mmSX_MRT7_BLEND_OPT 0xa1df | ||
| 2224 | #define mmTCC_CTRL 0x2b80 | ||
| 2225 | #define mmTCC_EDC_CNT 0x2b82 | ||
| 2226 | #define mmTCC_REDUNDANCY 0x2b83 | ||
| 2227 | #define mmTCC_EXE_DISABLE 0x2b84 | ||
| 2228 | #define mmTCC_DSM_CNTL 0x2b85 | ||
| 2229 | #define mmTCC_CGTT_SCLK_CTRL 0xf0ac | ||
| 2230 | #define mmTCA_CGTT_SCLK_CTRL 0xf0ad | ||
| 2231 | #define mmTCC_PERFCOUNTER0_SELECT 0xdb80 | ||
| 2232 | #define mmTCC_PERFCOUNTER1_SELECT 0xdb82 | ||
| 2233 | #define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 | ||
| 2234 | #define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 | ||
| 2235 | #define mmTCC_PERFCOUNTER2_SELECT 0xdb84 | ||
| 2236 | #define mmTCC_PERFCOUNTER3_SELECT 0xdb85 | ||
| 2237 | #define mmTCC_PERFCOUNTER0_LO 0xd380 | ||
| 2238 | #define mmTCC_PERFCOUNTER1_LO 0xd382 | ||
| 2239 | #define mmTCC_PERFCOUNTER2_LO 0xd384 | ||
| 2240 | #define mmTCC_PERFCOUNTER3_LO 0xd386 | ||
| 2241 | #define mmTCC_PERFCOUNTER0_HI 0xd381 | ||
| 2242 | #define mmTCC_PERFCOUNTER1_HI 0xd383 | ||
| 2243 | #define mmTCC_PERFCOUNTER2_HI 0xd385 | ||
| 2244 | #define mmTCC_PERFCOUNTER3_HI 0xd387 | ||
| 2245 | #define mmTCA_CTRL 0x2bc0 | ||
| 2246 | #define mmTCA_PERFCOUNTER0_SELECT 0xdb90 | ||
| 2247 | #define mmTCA_PERFCOUNTER1_SELECT 0xdb92 | ||
| 2248 | #define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 | ||
| 2249 | #define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 | ||
| 2250 | #define mmTCA_PERFCOUNTER2_SELECT 0xdb94 | ||
| 2251 | #define mmTCA_PERFCOUNTER3_SELECT 0xdb95 | ||
| 2252 | #define mmTCA_PERFCOUNTER0_LO 0xd390 | ||
| 2253 | #define mmTCA_PERFCOUNTER1_LO 0xd392 | ||
| 2254 | #define mmTCA_PERFCOUNTER2_LO 0xd394 | ||
| 2255 | #define mmTCA_PERFCOUNTER3_LO 0xd396 | ||
| 2256 | #define mmTCA_PERFCOUNTER0_HI 0xd391 | ||
| 2257 | #define mmTCA_PERFCOUNTER1_HI 0xd393 | ||
| 2258 | #define mmTCA_PERFCOUNTER2_HI 0xd395 | ||
| 2259 | #define mmTCA_PERFCOUNTER3_HI 0xd397 | ||
| 2260 | #define mmTA_BC_BASE_ADDR 0xa020 | ||
| 2261 | #define mmTA_BC_BASE_ADDR_HI 0xa021 | ||
| 2262 | #define mmTD_CNTL 0x2525 | ||
| 2263 | #define mmTD_STATUS 0x2526 | ||
| 2264 | #define mmTD_DEBUG_INDEX 0x2528 | ||
| 2265 | #define mmTD_DEBUG_DATA 0x2529 | ||
| 2266 | #define mmTD_DSM_CNTL 0x252f | ||
| 2267 | #define mmTD_PERFCOUNTER0_SELECT 0xdb00 | ||
| 2268 | #define mmTD_PERFCOUNTER1_SELECT 0xdb02 | ||
| 2269 | #define mmTD_PERFCOUNTER0_SELECT1 0xdb01 | ||
| 2270 | #define mmTD_PERFCOUNTER0_LO 0xd300 | ||
| 2271 | #define mmTD_PERFCOUNTER1_LO 0xd302 | ||
| 2272 | #define mmTD_PERFCOUNTER0_HI 0xd301 | ||
| 2273 | #define mmTD_PERFCOUNTER1_HI 0xd303 | ||
| 2274 | #define mmTD_SCRATCH 0x2533 | ||
| 2275 | #define mmTA_CNTL 0x2541 | ||
| 2276 | #define mmTA_CNTL_AUX 0x2542 | ||
| 2277 | #define mmTA_RESERVED_010C 0x2543 | ||
| 2278 | #define mmTA_CS_BC_BASE_ADDR 0xc380 | ||
| 2279 | #define mmTA_CS_BC_BASE_ADDR_HI 0xc381 | ||
| 2280 | #define mmTA_STATUS 0x2548 | ||
| 2281 | #define mmTA_DEBUG_INDEX 0x254c | ||
| 2282 | #define mmTA_DEBUG_DATA 0x254d | ||
| 2283 | #define mmTA_PERFCOUNTER0_SELECT 0xdac0 | ||
| 2284 | #define mmTA_PERFCOUNTER1_SELECT 0xdac2 | ||
| 2285 | #define mmTA_PERFCOUNTER0_SELECT1 0xdac1 | ||
| 2286 | #define mmTA_PERFCOUNTER0_LO 0xd2c0 | ||
| 2287 | #define mmTA_PERFCOUNTER1_LO 0xd2c2 | ||
| 2288 | #define mmTA_PERFCOUNTER0_HI 0xd2c1 | ||
| 2289 | #define mmTA_PERFCOUNTER1_HI 0xd2c3 | ||
| 2290 | #define mmTA_SCRATCH 0x2564 | ||
| 2291 | #define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 | ||
| 2292 | #define mmSH_STATIC_MEM_CONFIG 0x2581 | ||
| 2293 | #define mmTCP_INVALIDATE 0x2b00 | ||
| 2294 | #define mmTCP_STATUS 0x2b01 | ||
| 2295 | #define mmTCP_CNTL 0x2b02 | ||
| 2296 | #define mmTCP_CHAN_STEER_LO 0x2b03 | ||
| 2297 | #define mmTCP_CHAN_STEER_HI 0x2b04 | ||
| 2298 | #define mmTCP_ADDR_CONFIG 0x2b05 | ||
| 2299 | #define mmTCP_CREDIT 0x2b06 | ||
| 2300 | #define mmTCP_PERFCOUNTER0_SELECT 0xdb40 | ||
| 2301 | #define mmTCP_PERFCOUNTER1_SELECT 0xdb42 | ||
| 2302 | #define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 | ||
| 2303 | #define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 | ||
| 2304 | #define mmTCP_PERFCOUNTER2_SELECT 0xdb44 | ||
| 2305 | #define mmTCP_PERFCOUNTER3_SELECT 0xdb45 | ||
| 2306 | #define mmTCP_PERFCOUNTER0_LO 0xd340 | ||
| 2307 | #define mmTCP_PERFCOUNTER1_LO 0xd342 | ||
| 2308 | #define mmTCP_PERFCOUNTER2_LO 0xd344 | ||
| 2309 | #define mmTCP_PERFCOUNTER3_LO 0xd346 | ||
| 2310 | #define mmTCP_PERFCOUNTER0_HI 0xd341 | ||
| 2311 | #define mmTCP_PERFCOUNTER1_HI 0xd343 | ||
| 2312 | #define mmTCP_PERFCOUNTER2_HI 0xd345 | ||
| 2313 | #define mmTCP_PERFCOUNTER3_HI 0xd347 | ||
| 2314 | #define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 | ||
| 2315 | #define mmTCP_EDC_CNT 0x2b17 | ||
| 2316 | #define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a | ||
| 2317 | #define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b | ||
| 2318 | #define mmTC_CFG_L1_STORE_POLICY 0x2b1c | ||
| 2319 | #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d | ||
| 2320 | #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e | ||
| 2321 | #define mmTC_CFG_L2_STORE_POLICY0 0x2b1f | ||
| 2322 | #define mmTC_CFG_L2_STORE_POLICY1 0x2b20 | ||
| 2323 | #define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 | ||
| 2324 | #define mmTC_CFG_L1_VOLATILE 0x2b22 | ||
| 2325 | #define mmTC_CFG_L2_VOLATILE 0x2b23 | ||
| 2326 | #define mmTCP_WATCH0_ADDR_H 0x32a0 | ||
| 2327 | #define mmTCP_WATCH1_ADDR_H 0x32a3 | ||
| 2328 | #define mmTCP_WATCH2_ADDR_H 0x32a6 | ||
| 2329 | #define mmTCP_WATCH3_ADDR_H 0x32a9 | ||
| 2330 | #define mmTCP_WATCH0_ADDR_L 0x32a1 | ||
| 2331 | #define mmTCP_WATCH1_ADDR_L 0x32a4 | ||
| 2332 | #define mmTCP_WATCH2_ADDR_L 0x32a7 | ||
| 2333 | #define mmTCP_WATCH3_ADDR_L 0x32aa | ||
| 2334 | #define mmTCP_WATCH0_CNTL 0x32a2 | ||
| 2335 | #define mmTCP_WATCH1_CNTL 0x32a5 | ||
| 2336 | #define mmTCP_WATCH2_CNTL 0x32a8 | ||
| 2337 | #define mmTCP_WATCH3_CNTL 0x32ab | ||
| 2338 | #define mmTCP_GATCL1_CNTL 0x32b0 | ||
| 2339 | #define mmTCP_ATC_EDC_GATCL1_CNT 0x32b1 | ||
| 2340 | #define mmTCP_GATCL1_DSM_CNTL 0x32b2 | ||
| 2341 | #define mmTCP_DSM_CNTL 0x32b3 | ||
| 2342 | #define mmTCP_CNTL2 0x32b4 | ||
| 2343 | #define mmTD_CGTT_CTRL 0xf09c | ||
| 2344 | #define mmTA_CGTT_CTRL 0xf09d | ||
| 2345 | #define mmCGTT_TCP_CLK_CTRL 0xf09e | ||
| 2346 | #define mmCGTT_TCI_CLK_CTRL 0xf09f | ||
| 2347 | #define mmTCI_STATUS 0x2b61 | ||
| 2348 | #define mmTCI_CNTL_1 0x2b62 | ||
| 2349 | #define mmTCI_CNTL_2 0x2b63 | ||
| 2350 | #define mmGDS_CONFIG 0x25c0 | ||
| 2351 | #define mmGDS_CNTL_STATUS 0x25c1 | ||
| 2352 | #define mmGDS_ENHANCE2 0x25c2 | ||
| 2353 | #define mmGDS_PROTECTION_FAULT 0x25c3 | ||
| 2354 | #define mmGDS_VM_PROTECTION_FAULT 0x25c4 | ||
| 2355 | #define mmGDS_EDC_CNT 0x25c5 | ||
| 2356 | #define mmGDS_EDC_GRBM_CNT 0x25c6 | ||
| 2357 | #define mmGDS_EDC_OA_DED 0x25c7 | ||
| 2358 | #define mmGDS_DEBUG_CNTL 0x25c8 | ||
| 2359 | #define mmGDS_DEBUG_DATA 0x25c9 | ||
| 2360 | #define mmGDS_DSM_CNTL 0x25ca | ||
| 2361 | #define mmCGTT_GDS_CLK_CTRL 0xf0a0 | ||
| 2362 | #define mmGDS_RD_ADDR 0xc400 | ||
| 2363 | #define mmGDS_RD_DATA 0xc401 | ||
| 2364 | #define mmGDS_RD_BURST_ADDR 0xc402 | ||
| 2365 | #define mmGDS_RD_BURST_COUNT 0xc403 | ||
| 2366 | #define mmGDS_RD_BURST_DATA 0xc404 | ||
| 2367 | #define mmGDS_WR_ADDR 0xc405 | ||
| 2368 | #define mmGDS_WR_DATA 0xc406 | ||
| 2369 | #define mmGDS_WR_BURST_ADDR 0xc407 | ||
| 2370 | #define mmGDS_WR_BURST_DATA 0xc408 | ||
| 2371 | #define mmGDS_WRITE_COMPLETE 0xc409 | ||
| 2372 | #define mmGDS_ATOM_CNTL 0xc40a | ||
| 2373 | #define mmGDS_ATOM_COMPLETE 0xc40b | ||
| 2374 | #define mmGDS_ATOM_BASE 0xc40c | ||
| 2375 | #define mmGDS_ATOM_SIZE 0xc40d | ||
| 2376 | #define mmGDS_ATOM_OFFSET0 0xc40e | ||
| 2377 | #define mmGDS_ATOM_OFFSET1 0xc40f | ||
| 2378 | #define mmGDS_ATOM_DST 0xc410 | ||
| 2379 | #define mmGDS_ATOM_OP 0xc411 | ||
| 2380 | #define mmGDS_ATOM_SRC0 0xc412 | ||
| 2381 | #define mmGDS_ATOM_SRC0_U 0xc413 | ||
| 2382 | #define mmGDS_ATOM_SRC1 0xc414 | ||
| 2383 | #define mmGDS_ATOM_SRC1_U 0xc415 | ||
| 2384 | #define mmGDS_ATOM_READ0 0xc416 | ||
| 2385 | #define mmGDS_ATOM_READ0_U 0xc417 | ||
| 2386 | #define mmGDS_ATOM_READ1 0xc418 | ||
| 2387 | #define mmGDS_ATOM_READ1_U 0xc419 | ||
| 2388 | #define mmGDS_GWS_RESOURCE_CNTL 0xc41a | ||
| 2389 | #define mmGDS_GWS_RESOURCE 0xc41b | ||
| 2390 | #define mmGDS_GWS_RESOURCE_CNT 0xc41c | ||
| 2391 | #define mmGDS_OA_CNTL 0xc41d | ||
| 2392 | #define mmGDS_OA_COUNTER 0xc41e | ||
| 2393 | #define mmGDS_OA_ADDRESS 0xc41f | ||
| 2394 | #define mmGDS_OA_INCDEC 0xc420 | ||
| 2395 | #define mmGDS_OA_RING_SIZE 0xc421 | ||
| 2396 | #define ixGDS_DEBUG_REG0 0x0 | ||
| 2397 | #define ixGDS_DEBUG_REG1 0x1 | ||
| 2398 | #define ixGDS_DEBUG_REG2 0x2 | ||
| 2399 | #define ixGDS_DEBUG_REG3 0x3 | ||
| 2400 | #define ixGDS_DEBUG_REG4 0x4 | ||
| 2401 | #define ixGDS_DEBUG_REG5 0x5 | ||
| 2402 | #define ixGDS_DEBUG_REG6 0x6 | ||
| 2403 | #define mmGDS_PERFCOUNTER0_SELECT 0xda80 | ||
| 2404 | #define mmGDS_PERFCOUNTER1_SELECT 0xda81 | ||
| 2405 | #define mmGDS_PERFCOUNTER2_SELECT 0xda82 | ||
| 2406 | #define mmGDS_PERFCOUNTER3_SELECT 0xda83 | ||
| 2407 | #define mmGDS_PERFCOUNTER0_LO 0xd280 | ||
| 2408 | #define mmGDS_PERFCOUNTER1_LO 0xd282 | ||
| 2409 | #define mmGDS_PERFCOUNTER2_LO 0xd284 | ||
| 2410 | #define mmGDS_PERFCOUNTER3_LO 0xd286 | ||
| 2411 | #define mmGDS_PERFCOUNTER0_HI 0xd281 | ||
| 2412 | #define mmGDS_PERFCOUNTER1_HI 0xd283 | ||
| 2413 | #define mmGDS_PERFCOUNTER2_HI 0xd285 | ||
| 2414 | #define mmGDS_PERFCOUNTER3_HI 0xd287 | ||
| 2415 | #define mmGDS_PERFCOUNTER0_SELECT1 0xda84 | ||
| 2416 | #define mmGDS_VMID0_BASE 0x3300 | ||
| 2417 | #define mmGDS_VMID1_BASE 0x3302 | ||
| 2418 | #define mmGDS_VMID2_BASE 0x3304 | ||
| 2419 | #define mmGDS_VMID3_BASE 0x3306 | ||
| 2420 | #define mmGDS_VMID4_BASE 0x3308 | ||
| 2421 | #define mmGDS_VMID5_BASE 0x330a | ||
| 2422 | #define mmGDS_VMID6_BASE 0x330c | ||
| 2423 | #define mmGDS_VMID7_BASE 0x330e | ||
| 2424 | #define mmGDS_VMID8_BASE 0x3310 | ||
| 2425 | #define mmGDS_VMID9_BASE 0x3312 | ||
| 2426 | #define mmGDS_VMID10_BASE 0x3314 | ||
| 2427 | #define mmGDS_VMID11_BASE 0x3316 | ||
| 2428 | #define mmGDS_VMID12_BASE 0x3318 | ||
| 2429 | #define mmGDS_VMID13_BASE 0x331a | ||
| 2430 | #define mmGDS_VMID14_BASE 0x331c | ||
| 2431 | #define mmGDS_VMID15_BASE 0x331e | ||
| 2432 | #define mmGDS_VMID0_SIZE 0x3301 | ||
| 2433 | #define mmGDS_VMID1_SIZE 0x3303 | ||
| 2434 | #define mmGDS_VMID2_SIZE 0x3305 | ||
| 2435 | #define mmGDS_VMID3_SIZE 0x3307 | ||
| 2436 | #define mmGDS_VMID4_SIZE 0x3309 | ||
| 2437 | #define mmGDS_VMID5_SIZE 0x330b | ||
| 2438 | #define mmGDS_VMID6_SIZE 0x330d | ||
| 2439 | #define mmGDS_VMID7_SIZE 0x330f | ||
| 2440 | #define mmGDS_VMID8_SIZE 0x3311 | ||
| 2441 | #define mmGDS_VMID9_SIZE 0x3313 | ||
| 2442 | #define mmGDS_VMID10_SIZE 0x3315 | ||
| 2443 | #define mmGDS_VMID11_SIZE 0x3317 | ||
| 2444 | #define mmGDS_VMID12_SIZE 0x3319 | ||
| 2445 | #define mmGDS_VMID13_SIZE 0x331b | ||
| 2446 | #define mmGDS_VMID14_SIZE 0x331d | ||
| 2447 | #define mmGDS_VMID15_SIZE 0x331f | ||
| 2448 | #define mmGDS_GWS_VMID0 0x3320 | ||
| 2449 | #define mmGDS_GWS_VMID1 0x3321 | ||
| 2450 | #define mmGDS_GWS_VMID2 0x3322 | ||
| 2451 | #define mmGDS_GWS_VMID3 0x3323 | ||
| 2452 | #define mmGDS_GWS_VMID4 0x3324 | ||
| 2453 | #define mmGDS_GWS_VMID5 0x3325 | ||
| 2454 | #define mmGDS_GWS_VMID6 0x3326 | ||
| 2455 | #define mmGDS_GWS_VMID7 0x3327 | ||
| 2456 | #define mmGDS_GWS_VMID8 0x3328 | ||
| 2457 | #define mmGDS_GWS_VMID9 0x3329 | ||
| 2458 | #define mmGDS_GWS_VMID10 0x332a | ||
| 2459 | #define mmGDS_GWS_VMID11 0x332b | ||
| 2460 | #define mmGDS_GWS_VMID12 0x332c | ||
| 2461 | #define mmGDS_GWS_VMID13 0x332d | ||
| 2462 | #define mmGDS_GWS_VMID14 0x332e | ||
| 2463 | #define mmGDS_GWS_VMID15 0x332f | ||
| 2464 | #define mmGDS_OA_VMID0 0x3330 | ||
| 2465 | #define mmGDS_OA_VMID1 0x3331 | ||
| 2466 | #define mmGDS_OA_VMID2 0x3332 | ||
| 2467 | #define mmGDS_OA_VMID3 0x3333 | ||
| 2468 | #define mmGDS_OA_VMID4 0x3334 | ||
| 2469 | #define mmGDS_OA_VMID5 0x3335 | ||
| 2470 | #define mmGDS_OA_VMID6 0x3336 | ||
| 2471 | #define mmGDS_OA_VMID7 0x3337 | ||
| 2472 | #define mmGDS_OA_VMID8 0x3338 | ||
| 2473 | #define mmGDS_OA_VMID9 0x3339 | ||
| 2474 | #define mmGDS_OA_VMID10 0x333a | ||
| 2475 | #define mmGDS_OA_VMID11 0x333b | ||
| 2476 | #define mmGDS_OA_VMID12 0x333c | ||
| 2477 | #define mmGDS_OA_VMID13 0x333d | ||
| 2478 | #define mmGDS_OA_VMID14 0x333e | ||
| 2479 | #define mmGDS_OA_VMID15 0x333f | ||
| 2480 | #define mmGDS_GWS_RESET0 0x3344 | ||
| 2481 | #define mmGDS_GWS_RESET1 0x3345 | ||
| 2482 | #define mmGDS_GWS_RESOURCE_RESET 0x3346 | ||
| 2483 | #define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 | ||
| 2484 | #define mmGDS_OA_RESET_MASK 0x3349 | ||
| 2485 | #define mmGDS_OA_RESET 0x334a | ||
| 2486 | #define mmGDS_ENHANCE 0x334b | ||
| 2487 | #define mmGDS_OA_CGPG_RESTORE 0x334c | ||
| 2488 | #define mmGDS_CS_CTXSW_STATUS 0x334d | ||
| 2489 | #define mmGDS_CS_CTXSW_CNT0 0x334e | ||
| 2490 | #define mmGDS_CS_CTXSW_CNT1 0x334f | ||
| 2491 | #define mmGDS_CS_CTXSW_CNT2 0x3350 | ||
| 2492 | #define mmGDS_CS_CTXSW_CNT3 0x3351 | ||
| 2493 | #define mmGDS_GFX_CTXSW_STATUS 0x3352 | ||
| 2494 | #define mmGDS_VS_CTXSW_CNT0 0x3353 | ||
| 2495 | #define mmGDS_VS_CTXSW_CNT1 0x3354 | ||
| 2496 | #define mmGDS_VS_CTXSW_CNT2 0x3355 | ||
| 2497 | #define mmGDS_VS_CTXSW_CNT3 0x3356 | ||
| 2498 | #define mmGDS_PS0_CTXSW_CNT0 0x3357 | ||
| 2499 | #define mmGDS_PS1_CTXSW_CNT0 0x335b | ||
| 2500 | #define mmGDS_PS2_CTXSW_CNT0 0x335f | ||
| 2501 | #define mmGDS_PS3_CTXSW_CNT0 0x3363 | ||
| 2502 | #define mmGDS_PS4_CTXSW_CNT0 0x3367 | ||
| 2503 | #define mmGDS_PS5_CTXSW_CNT0 0x336b | ||
| 2504 | #define mmGDS_PS6_CTXSW_CNT0 0x336f | ||
| 2505 | #define mmGDS_PS7_CTXSW_CNT0 0x3373 | ||
| 2506 | #define mmGDS_PS0_CTXSW_CNT1 0x3358 | ||
| 2507 | #define mmGDS_PS1_CTXSW_CNT1 0x335c | ||
| 2508 | #define mmGDS_PS2_CTXSW_CNT1 0x3360 | ||
| 2509 | #define mmGDS_PS3_CTXSW_CNT1 0x3364 | ||
| 2510 | #define mmGDS_PS4_CTXSW_CNT1 0x3368 | ||
| 2511 | #define mmGDS_PS5_CTXSW_CNT1 0x336c | ||
| 2512 | #define mmGDS_PS6_CTXSW_CNT1 0x3370 | ||
| 2513 | #define mmGDS_PS7_CTXSW_CNT1 0x3374 | ||
| 2514 | #define mmGDS_PS0_CTXSW_CNT2 0x3359 | ||
| 2515 | #define mmGDS_PS1_CTXSW_CNT2 0x335d | ||
| 2516 | #define mmGDS_PS2_CTXSW_CNT2 0x3361 | ||
| 2517 | #define mmGDS_PS3_CTXSW_CNT2 0x3365 | ||
| 2518 | #define mmGDS_PS4_CTXSW_CNT2 0x3369 | ||
| 2519 | #define mmGDS_PS5_CTXSW_CNT2 0x336d | ||
| 2520 | #define mmGDS_PS6_CTXSW_CNT2 0x3371 | ||
| 2521 | #define mmGDS_PS7_CTXSW_CNT2 0x3375 | ||
| 2522 | #define mmGDS_PS0_CTXSW_CNT3 0x335a | ||
| 2523 | #define mmGDS_PS1_CTXSW_CNT3 0x335e | ||
| 2524 | #define mmGDS_PS2_CTXSW_CNT3 0x3362 | ||
| 2525 | #define mmGDS_PS3_CTXSW_CNT3 0x3366 | ||
| 2526 | #define mmGDS_PS4_CTXSW_CNT3 0x336a | ||
| 2527 | #define mmGDS_PS5_CTXSW_CNT3 0x336e | ||
| 2528 | #define mmGDS_PS6_CTXSW_CNT3 0x3372 | ||
| 2529 | #define mmGDS_PS7_CTXSW_CNT3 0x3376 | ||
| 2530 | #define mmCS_COPY_STATE 0xa1f3 | ||
| 2531 | #define mmGFX_COPY_STATE 0xa1f4 | ||
| 2532 | #define mmVGT_DRAW_INITIATOR 0xa1fc | ||
| 2533 | #define mmVGT_EVENT_INITIATOR 0xa2a4 | ||
| 2534 | #define mmVGT_EVENT_ADDRESS_REG 0xa1fe | ||
| 2535 | #define mmVGT_DMA_BASE_HI 0xa1f9 | ||
| 2536 | #define mmVGT_DMA_BASE 0xa1fa | ||
| 2537 | #define mmVGT_DMA_INDEX_TYPE 0xa29f | ||
| 2538 | #define mmVGT_DMA_NUM_INSTANCES 0xa2a2 | ||
| 2539 | #define mmIA_ENHANCE 0xa29c | ||
| 2540 | #define mmVGT_DMA_SIZE 0xa29d | ||
| 2541 | #define mmVGT_DMA_MAX_SIZE 0xa29e | ||
| 2542 | #define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 | ||
| 2543 | #define mmVGT_DMA_CONTROL 0x2272 | ||
| 2544 | #define mmVGT_IMMED_DATA 0xa1fd | ||
| 2545 | #define mmVGT_INDEX_TYPE 0xc243 | ||
| 2546 | #define mmVGT_NUM_INDICES 0xc24c | ||
| 2547 | #define mmVGT_NUM_INSTANCES 0xc24d | ||
| 2548 | #define mmVGT_PRIMITIVE_TYPE 0xc242 | ||
| 2549 | #define mmVGT_PRIMITIVEID_EN 0xa2a1 | ||
| 2550 | #define mmVGT_PRIMITIVEID_RESET 0xa2a3 | ||
| 2551 | #define mmVGT_VTX_CNT_EN 0xa2ae | ||
| 2552 | #define mmVGT_REUSE_OFF 0xa2ad | ||
| 2553 | #define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 | ||
| 2554 | #define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 | ||
| 2555 | #define mmVGT_MAX_VTX_INDX 0xa100 | ||
| 2556 | #define mmVGT_MIN_VTX_INDX 0xa101 | ||
| 2557 | #define mmVGT_INDX_OFFSET 0xa102 | ||
| 2558 | #define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 | ||
| 2559 | #define mmVGT_OUT_DEALLOC_CNTL 0xa317 | ||
| 2560 | #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 | ||
| 2561 | #define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 | ||
| 2562 | #define mmVGT_ENHANCE 0xa294 | ||
| 2563 | #define mmVGT_OUTPUT_PATH_CNTL 0xa284 | ||
| 2564 | #define mmVGT_HOS_CNTL 0xa285 | ||
| 2565 | #define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 | ||
| 2566 | #define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 | ||
| 2567 | #define mmVGT_HOS_REUSE_DEPTH 0xa288 | ||
| 2568 | #define mmVGT_GROUP_PRIM_TYPE 0xa289 | ||
| 2569 | #define mmVGT_GROUP_FIRST_DECR 0xa28a | ||
| 2570 | #define mmVGT_GROUP_DECR 0xa28b | ||
| 2571 | #define mmVGT_GROUP_VECT_0_CNTL 0xa28c | ||
| 2572 | #define mmVGT_GROUP_VECT_1_CNTL 0xa28d | ||
| 2573 | #define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e | ||
| 2574 | #define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f | ||
| 2575 | #define mmVGT_VTX_VECT_EJECT_REG 0x222c | ||
| 2576 | #define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d | ||
| 2577 | #define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e | ||
| 2578 | #define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f | ||
| 2579 | #define mmVGT_LAST_COPY_STATE 0x2230 | ||
| 2580 | #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f | ||
| 2581 | #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 | ||
| 2582 | #define mmVGT_GS_MODE 0xa290 | ||
| 2583 | #define mmVGT_GS_ONCHIP_CNTL 0xa291 | ||
| 2584 | #define mmVGT_GS_OUT_PRIM_TYPE 0xa29b | ||
| 2585 | #define mmVGT_CACHE_INVALIDATION 0x2231 | ||
| 2586 | #define mmVGT_RESET_DEBUG 0x2232 | ||
| 2587 | #define mmVGT_STRMOUT_DELAY 0x2233 | ||
| 2588 | #define mmVGT_FIFO_DEPTHS 0x2234 | ||
| 2589 | #define mmVGT_GS_PER_ES 0xa295 | ||
| 2590 | #define mmVGT_ES_PER_GS 0xa296 | ||
| 2591 | #define mmVGT_GS_PER_VS 0xa297 | ||
| 2592 | #define mmVGT_GS_VERTEX_REUSE 0x2235 | ||
| 2593 | #define mmVGT_MC_LAT_CNTL 0x2236 | ||
| 2594 | #define mmIA_CNTL_STATUS 0x2237 | ||
| 2595 | #define mmVGT_STRMOUT_CONFIG 0xa2e5 | ||
| 2596 | #define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 | ||
| 2597 | #define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 | ||
| 2598 | #define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc | ||
| 2599 | #define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 | ||
| 2600 | #define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 | ||
| 2601 | #define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb | ||
| 2602 | #define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf | ||
| 2603 | #define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 | ||
| 2604 | #define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 | ||
| 2605 | #define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 | ||
| 2606 | #define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd | ||
| 2607 | #define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 | ||
| 2608 | #define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 | ||
| 2609 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 | ||
| 2610 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 | ||
| 2611 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 | ||
| 2612 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 | ||
| 2613 | #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca | ||
| 2614 | #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb | ||
| 2615 | #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc | ||
| 2616 | #define mmVGT_GS_MAX_VERT_OUT 0xa2ce | ||
| 2617 | #define mmVGT_SHADER_STAGES_EN 0xa2d5 | ||
| 2618 | #define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd | ||
| 2619 | #define mmVGT_LS_HS_CONFIG 0xa2d6 | ||
| 2620 | #define mmVGT_DMA_LS_HS_CONFIG 0x2273 | ||
| 2621 | #define mmVGT_TF_PARAM 0xa2db | ||
| 2622 | #define mmVGT_TESS_DISTRIBUTION 0xa2d4 | ||
| 2623 | #define mmVGT_TF_RING_SIZE 0xc24e | ||
| 2624 | #define mmVGT_SYS_CONFIG 0x2263 | ||
| 2625 | #define mmVGT_HS_OFFCHIP_PARAM 0xc24f | ||
| 2626 | #define mmVGT_TF_MEMORY_BASE 0xc250 | ||
| 2627 | #define mmVGT_GS_INSTANCE_CNT 0xa2e4 | ||
| 2628 | #define mmIA_MULTI_VGT_PARAM 0xa2aa | ||
| 2629 | #define mmVGT_VS_MAX_WAVE_ID 0x2268 | ||
| 2630 | #define mmVGT_ESGS_RING_SIZE 0xc240 | ||
| 2631 | #define mmVGT_GSVS_RING_SIZE 0xc241 | ||
| 2632 | #define mmVGT_GSVS_RING_OFFSET_1 0xa298 | ||
| 2633 | #define mmVGT_GSVS_RING_OFFSET_2 0xa299 | ||
| 2634 | #define mmVGT_GSVS_RING_OFFSET_3 0xa29a | ||
| 2635 | #define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab | ||
| 2636 | #define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac | ||
| 2637 | #define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 | ||
| 2638 | #define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 | ||
| 2639 | #define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 | ||
| 2640 | #define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da | ||
| 2641 | #define mmWD_CNTL_STATUS 0x223f | ||
| 2642 | #define mmWD_ENHANCE 0xa2a0 | ||
| 2643 | #define mmGFX_PIPE_CONTROL 0x226d | ||
| 2644 | #define mmCGTT_VGT_CLK_CTRL 0xf084 | ||
| 2645 | #define mmCGTT_IA_CLK_CTRL 0xf085 | ||
| 2646 | #define mmCGTT_WD_CLK_CTRL 0xf086 | ||
| 2647 | #define mmVGT_DEBUG_CNTL 0x2238 | ||
| 2648 | #define mmVGT_DEBUG_DATA 0x2239 | ||
| 2649 | #define mmIA_DEBUG_CNTL 0x223a | ||
| 2650 | #define mmIA_DEBUG_DATA 0x223b | ||
| 2651 | #define mmVGT_CNTL_STATUS 0x223c | ||
| 2652 | #define mmWD_DEBUG_CNTL 0x223d | ||
| 2653 | #define mmWD_DEBUG_DATA 0x223e | ||
| 2654 | #define mmWD_QOS 0x2242 | ||
| 2655 | #define mmCC_GC_PRIM_CONFIG 0x2240 | ||
| 2656 | #define mmGC_USER_PRIM_CONFIG 0x2241 | ||
| 2657 | #define ixWD_DEBUG_REG0 0x0 | ||
| 2658 | #define ixWD_DEBUG_REG1 0x1 | ||
| 2659 | #define ixWD_DEBUG_REG2 0x2 | ||
| 2660 | #define ixWD_DEBUG_REG3 0x3 | ||
| 2661 | #define ixWD_DEBUG_REG4 0x4 | ||
| 2662 | #define ixWD_DEBUG_REG5 0x5 | ||
| 2663 | #define ixWD_DEBUG_REG6 0x6 | ||
| 2664 | #define ixWD_DEBUG_REG7 0x7 | ||
| 2665 | #define ixWD_DEBUG_REG8 0x8 | ||
| 2666 | #define ixWD_DEBUG_REG9 0x9 | ||
| 2667 | #define ixWD_DEBUG_REG10 0xa | ||
| 2668 | #define ixIA_DEBUG_REG0 0x0 | ||
| 2669 | #define ixIA_DEBUG_REG1 0x1 | ||
| 2670 | #define ixIA_DEBUG_REG2 0x2 | ||
| 2671 | #define ixIA_DEBUG_REG3 0x3 | ||
| 2672 | #define ixIA_DEBUG_REG4 0x4 | ||
| 2673 | #define ixIA_DEBUG_REG5 0x5 | ||
| 2674 | #define ixIA_DEBUG_REG6 0x6 | ||
| 2675 | #define ixIA_DEBUG_REG7 0x7 | ||
| 2676 | #define ixIA_DEBUG_REG8 0x8 | ||
| 2677 | #define ixIA_DEBUG_REG9 0x9 | ||
| 2678 | #define ixVGT_DEBUG_REG0 0x0 | ||
| 2679 | #define ixVGT_DEBUG_REG1 0x1 | ||
| 2680 | #define ixVGT_DEBUG_REG2 0x1e | ||
| 2681 | #define ixVGT_DEBUG_REG3 0x1f | ||
| 2682 | #define ixVGT_DEBUG_REG4 0x20 | ||
| 2683 | #define ixVGT_DEBUG_REG5 0x21 | ||
| 2684 | #define ixVGT_DEBUG_REG6 0x22 | ||
| 2685 | #define ixVGT_DEBUG_REG7 0x23 | ||
| 2686 | #define ixVGT_DEBUG_REG8 0x8 | ||
| 2687 | #define ixVGT_DEBUG_REG9 0x9 | ||
| 2688 | #define ixVGT_DEBUG_REG10 0xa | ||
| 2689 | #define ixVGT_DEBUG_REG11 0xb | ||
| 2690 | #define ixVGT_DEBUG_REG12 0xc | ||
| 2691 | #define ixVGT_DEBUG_REG13 0xd | ||
| 2692 | #define ixVGT_DEBUG_REG14 0xe | ||
| 2693 | #define ixVGT_DEBUG_REG15 0xf | ||
| 2694 | #define ixVGT_DEBUG_REG16 0x10 | ||
| 2695 | #define ixVGT_DEBUG_REG17 0x11 | ||
| 2696 | #define ixVGT_DEBUG_REG18 0x7 | ||
| 2697 | #define ixVGT_DEBUG_REG19 0x13 | ||
| 2698 | #define ixVGT_DEBUG_REG20 0x14 | ||
| 2699 | #define ixVGT_DEBUG_REG21 0x15 | ||
| 2700 | #define ixVGT_DEBUG_REG22 0x16 | ||
| 2701 | #define ixVGT_DEBUG_REG23 0x17 | ||
| 2702 | #define ixVGT_DEBUG_REG24 0x18 | ||
| 2703 | #define ixVGT_DEBUG_REG25 0x19 | ||
| 2704 | #define ixVGT_DEBUG_REG26 0x24 | ||
| 2705 | #define ixVGT_DEBUG_REG27 0x1b | ||
| 2706 | #define ixVGT_DEBUG_REG28 0x1c | ||
| 2707 | #define ixVGT_DEBUG_REG29 0x1d | ||
| 2708 | #define ixVGT_DEBUG_REG31 0x26 | ||
| 2709 | #define ixVGT_DEBUG_REG32 0x27 | ||
| 2710 | #define ixVGT_DEBUG_REG33 0x28 | ||
| 2711 | #define ixVGT_DEBUG_REG34 0x29 | ||
| 2712 | #define ixVGT_DEBUG_REG36 0x2b | ||
| 2713 | #define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 | ||
| 2714 | #define mmVGT_PERFCOUNTER0_SELECT 0xd88c | ||
| 2715 | #define mmVGT_PERFCOUNTER1_SELECT 0xd88d | ||
| 2716 | #define mmVGT_PERFCOUNTER2_SELECT 0xd88e | ||
| 2717 | #define mmVGT_PERFCOUNTER3_SELECT 0xd88f | ||
| 2718 | #define mmVGT_PERFCOUNTER0_SELECT1 0xd890 | ||
| 2719 | #define mmVGT_PERFCOUNTER1_SELECT1 0xd891 | ||
| 2720 | #define mmVGT_PERFCOUNTER0_LO 0xd090 | ||
| 2721 | #define mmVGT_PERFCOUNTER1_LO 0xd092 | ||
| 2722 | #define mmVGT_PERFCOUNTER2_LO 0xd094 | ||
| 2723 | #define mmVGT_PERFCOUNTER3_LO 0xd096 | ||
| 2724 | #define mmVGT_PERFCOUNTER0_HI 0xd091 | ||
| 2725 | #define mmVGT_PERFCOUNTER1_HI 0xd093 | ||
| 2726 | #define mmVGT_PERFCOUNTER2_HI 0xd095 | ||
| 2727 | #define mmVGT_PERFCOUNTER3_HI 0xd097 | ||
| 2728 | #define mmIA_PERFCOUNTER0_SELECT 0xd884 | ||
| 2729 | #define mmIA_PERFCOUNTER1_SELECT 0xd885 | ||
| 2730 | #define mmIA_PERFCOUNTER2_SELECT 0xd886 | ||
| 2731 | #define mmIA_PERFCOUNTER3_SELECT 0xd887 | ||
| 2732 | #define mmIA_PERFCOUNTER0_SELECT1 0xd888 | ||
| 2733 | #define mmIA_PERFCOUNTER0_LO 0xd088 | ||
| 2734 | #define mmIA_PERFCOUNTER1_LO 0xd08a | ||
| 2735 | #define mmIA_PERFCOUNTER2_LO 0xd08c | ||
| 2736 | #define mmIA_PERFCOUNTER3_LO 0xd08e | ||
| 2737 | #define mmIA_PERFCOUNTER0_HI 0xd089 | ||
| 2738 | #define mmIA_PERFCOUNTER1_HI 0xd08b | ||
| 2739 | #define mmIA_PERFCOUNTER2_HI 0xd08d | ||
| 2740 | #define mmIA_PERFCOUNTER3_HI 0xd08f | ||
| 2741 | #define mmWD_PERFCOUNTER0_SELECT 0xd880 | ||
| 2742 | #define mmWD_PERFCOUNTER1_SELECT 0xd881 | ||
| 2743 | #define mmWD_PERFCOUNTER2_SELECT 0xd882 | ||
| 2744 | #define mmWD_PERFCOUNTER3_SELECT 0xd883 | ||
| 2745 | #define mmWD_PERFCOUNTER0_LO 0xd080 | ||
| 2746 | #define mmWD_PERFCOUNTER1_LO 0xd082 | ||
| 2747 | #define mmWD_PERFCOUNTER2_LO 0xd084 | ||
| 2748 | #define mmWD_PERFCOUNTER3_LO 0xd086 | ||
| 2749 | #define mmWD_PERFCOUNTER0_HI 0xd081 | ||
| 2750 | #define mmWD_PERFCOUNTER1_HI 0xd083 | ||
| 2751 | #define mmWD_PERFCOUNTER2_HI 0xd085 | ||
| 2752 | #define mmWD_PERFCOUNTER3_HI 0xd087 | ||
| 2753 | #define mmDIDT_IND_INDEX 0x3280 | ||
| 2754 | #define mmDIDT_IND_DATA 0x3281 | ||
| 2755 | #define ixDIDT_SQ_CTRL0 0x0 | ||
| 2756 | #define ixDIDT_SQ_CTRL1 0x1 | ||
| 2757 | #define ixDIDT_SQ_CTRL2 0x2 | ||
| 2758 | #define ixDIDT_SQ_CTRL_OCP 0x3 | ||
| 2759 | #define ixDIDT_SQ_WEIGHT0_3 0x10 | ||
| 2760 | #define ixDIDT_SQ_WEIGHT4_7 0x11 | ||
| 2761 | #define ixDIDT_SQ_WEIGHT8_11 0x12 | ||
| 2762 | #define ixDIDT_DB_CTRL0 0x20 | ||
| 2763 | #define ixDIDT_DB_CTRL1 0x21 | ||
| 2764 | #define ixDIDT_DB_CTRL2 0x22 | ||
| 2765 | #define ixDIDT_DB_CTRL_OCP 0x23 | ||
| 2766 | #define ixDIDT_DB_WEIGHT0_3 0x30 | ||
| 2767 | #define ixDIDT_DB_WEIGHT4_7 0x31 | ||
| 2768 | #define ixDIDT_DB_WEIGHT8_11 0x32 | ||
| 2769 | #define ixDIDT_TD_CTRL0 0x40 | ||
| 2770 | #define ixDIDT_TD_CTRL1 0x41 | ||
| 2771 | #define ixDIDT_TD_CTRL2 0x42 | ||
| 2772 | #define ixDIDT_TD_CTRL_OCP 0x43 | ||
| 2773 | #define ixDIDT_TD_WEIGHT0_3 0x50 | ||
| 2774 | #define ixDIDT_TD_WEIGHT4_7 0x51 | ||
| 2775 | #define ixDIDT_TD_WEIGHT8_11 0x52 | ||
| 2776 | #define ixDIDT_TCP_CTRL0 0x60 | ||
| 2777 | #define ixDIDT_TCP_CTRL1 0x61 | ||
| 2778 | #define ixDIDT_TCP_CTRL2 0x62 | ||
| 2779 | #define ixDIDT_TCP_CTRL_OCP 0x63 | ||
| 2780 | #define ixDIDT_TCP_WEIGHT0_3 0x70 | ||
| 2781 | #define ixDIDT_TCP_WEIGHT4_7 0x71 | ||
| 2782 | #define ixDIDT_TCP_WEIGHT8_11 0x72 | ||
| 2783 | #define ixDIDT_DBR_CTRL0 0x80 | ||
| 2784 | #define ixDIDT_DBR_CTRL1 0x81 | ||
| 2785 | #define ixDIDT_DBR_CTRL2 0x82 | ||
| 2786 | #define ixDIDT_DBR_CTRL_OCP 0x83 | ||
| 2787 | #define ixDIDT_DBR_WEIGHT0_3 0x90 | ||
| 2788 | #define ixDIDT_DBR_WEIGHT4_7 0x91 | ||
| 2789 | #define ixDIDT_DBR_WEIGHT8_11 0x92 | ||
| 2790 | |||
| 2791 | #endif /* GFX_8_1_D_H */ | ||
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h new file mode 100644 index 000000000000..f9022097fbe9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h | |||
| @@ -0,0 +1,6808 @@ | |||
| 1 | /* | ||
| 2 | * GFX_8_1 Register documentation | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included | ||
| 14 | * in all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN | ||
| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef GFX_8_1_ENUM_H | ||
| 25 | #define GFX_8_1_ENUM_H | ||
| 26 | |||
| 27 | typedef enum SurfaceNumber { | ||
| 28 | NUMBER_UNORM = 0x0, | ||
| 29 | NUMBER_SNORM = 0x1, | ||
| 30 | NUMBER_USCALED = 0x2, | ||
| 31 | NUMBER_SSCALED = 0x3, | ||
| 32 | NUMBER_UINT = 0x4, | ||
| 33 | NUMBER_SINT = 0x5, | ||
| 34 | NUMBER_SRGB = 0x6, | ||
| 35 | NUMBER_FLOAT = 0x7, | ||
| 36 | } SurfaceNumber; | ||
| 37 | typedef enum SurfaceSwap { | ||
| 38 | SWAP_STD = 0x0, | ||
| 39 | SWAP_ALT = 0x1, | ||
| 40 | SWAP_STD_REV = 0x2, | ||
| 41 | SWAP_ALT_REV = 0x3, | ||
| 42 | } SurfaceSwap; | ||
| 43 | typedef enum CBMode { | ||
| 44 | CB_DISABLE = 0x0, | ||
| 45 | CB_NORMAL = 0x1, | ||
| 46 | CB_ELIMINATE_FAST_CLEAR = 0x2, | ||
| 47 | CB_RESOLVE = 0x3, | ||
| 48 | CB_DECOMPRESS = 0x4, | ||
| 49 | CB_FMASK_DECOMPRESS = 0x5, | ||
| 50 | CB_DCC_DECOMPRESS = 0x6, | ||
| 51 | } CBMode; | ||
| 52 | typedef enum RoundMode { | ||
| 53 | ROUND_BY_HALF = 0x0, | ||
| 54 | ROUND_TRUNCATE = 0x1, | ||
| 55 | } RoundMode; | ||
| 56 | typedef enum SourceFormat { | ||
| 57 | EXPORT_4C_32BPC = 0x0, | ||
| 58 | EXPORT_4C_16BPC = 0x1, | ||
| 59 | EXPORT_2C_32BPC_GR = 0x2, | ||
| 60 | EXPORT_2C_32BPC_AR = 0x3, | ||
| 61 | } SourceFormat; | ||
| 62 | typedef enum BlendOp { | ||
| 63 | BLEND_ZERO = 0x0, | ||
| 64 | BLEND_ONE = 0x1, | ||
| 65 | BLEND_SRC_COLOR = 0x2, | ||
| 66 | BLEND_ONE_MINUS_SRC_COLOR = 0x3, | ||
| 67 | BLEND_SRC_ALPHA = 0x4, | ||
| 68 | BLEND_ONE_MINUS_SRC_ALPHA = 0x5, | ||
| 69 | BLEND_DST_ALPHA = 0x6, | ||
| 70 | BLEND_ONE_MINUS_DST_ALPHA = 0x7, | ||
| 71 | BLEND_DST_COLOR = 0x8, | ||
| 72 | BLEND_ONE_MINUS_DST_COLOR = 0x9, | ||
| 73 | BLEND_SRC_ALPHA_SATURATE = 0xa, | ||
| 74 | BLEND_BOTH_SRC_ALPHA = 0xb, | ||
| 75 | BLEND_BOTH_INV_SRC_ALPHA = 0xc, | ||
| 76 | BLEND_CONSTANT_COLOR = 0xd, | ||
| 77 | BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, | ||
| 78 | BLEND_SRC1_COLOR = 0xf, | ||
| 79 | BLEND_INV_SRC1_COLOR = 0x10, | ||
| 80 | BLEND_SRC1_ALPHA = 0x11, | ||
| 81 | BLEND_INV_SRC1_ALPHA = 0x12, | ||
| 82 | BLEND_CONSTANT_ALPHA = 0x13, | ||
| 83 | BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, | ||
| 84 | } BlendOp; | ||
| 85 | typedef enum CombFunc { | ||
| 86 | COMB_DST_PLUS_SRC = 0x0, | ||
| 87 | COMB_SRC_MINUS_DST = 0x1, | ||
| 88 | COMB_MIN_DST_SRC = 0x2, | ||
| 89 | COMB_MAX_DST_SRC = 0x3, | ||
| 90 | COMB_DST_MINUS_SRC = 0x4, | ||
| 91 | } CombFunc; | ||
| 92 | typedef enum BlendOpt { | ||
| 93 | FORCE_OPT_AUTO = 0x0, | ||
| 94 | FORCE_OPT_DISABLE = 0x1, | ||
| 95 | FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, | ||
| 96 | FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, | ||
| 97 | FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, | ||
| 98 | FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, | ||
| 99 | FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, | ||
| 100 | FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, | ||
| 101 | } BlendOpt; | ||
| 102 | typedef enum CmaskCode { | ||
| 103 | CMASK_CLR00_F0 = 0x0, | ||
| 104 | CMASK_CLR00_F1 = 0x1, | ||
| 105 | CMASK_CLR00_F2 = 0x2, | ||
| 106 | CMASK_CLR00_FX = 0x3, | ||
| 107 | CMASK_CLR01_F0 = 0x4, | ||
| 108 | CMASK_CLR01_F1 = 0x5, | ||
| 109 | CMASK_CLR01_F2 = 0x6, | ||
| 110 | CMASK_CLR01_FX = 0x7, | ||
| 111 | CMASK_CLR10_F0 = 0x8, | ||
| 112 | CMASK_CLR10_F1 = 0x9, | ||
| 113 | CMASK_CLR10_F2 = 0xa, | ||
| 114 | CMASK_CLR10_FX = 0xb, | ||
| 115 | CMASK_CLR11_F0 = 0xc, | ||
| 116 | CMASK_CLR11_F1 = 0xd, | ||
| 117 | CMASK_CLR11_F2 = 0xe, | ||
| 118 | CMASK_CLR11_FX = 0xf, | ||
| 119 | } CmaskCode; | ||
| 120 | typedef enum CmaskAddr { | ||
| 121 | CMASK_ADDR_TILED = 0x0, | ||
| 122 | CMASK_ADDR_LINEAR = 0x1, | ||
| 123 | CMASK_ADDR_COMPATIBLE = 0x2, | ||
| 124 | } CmaskAddr; | ||
| 125 | typedef enum CBPerfSel { | ||
| 126 | CB_PERF_SEL_NONE = 0x0, | ||
| 127 | CB_PERF_SEL_BUSY = 0x1, | ||
| 128 | CB_PERF_SEL_CORE_SCLK_VLD = 0x2, | ||
| 129 | CB_PERF_SEL_REG_SCLK0_VLD = 0x3, | ||
| 130 | CB_PERF_SEL_REG_SCLK1_VLD = 0x4, | ||
| 131 | CB_PERF_SEL_DRAWN_QUAD = 0x5, | ||
| 132 | CB_PERF_SEL_DRAWN_PIXEL = 0x6, | ||
| 133 | CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, | ||
| 134 | CB_PERF_SEL_DRAWN_TILE = 0x8, | ||
| 135 | CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, | ||
| 136 | CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, | ||
| 137 | CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, | ||
| 138 | CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, | ||
| 139 | CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, | ||
| 140 | CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, | ||
| 141 | CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, | ||
| 142 | CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, | ||
| 143 | CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, | ||
| 144 | CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, | ||
| 145 | CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, | ||
| 146 | CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, | ||
| 147 | CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, | ||
| 148 | CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, | ||
| 149 | CB_PERF_SEL_LQUAD_NO_TILE = 0x17, | ||
| 150 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, | ||
| 151 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, | ||
| 152 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, | ||
| 153 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, | ||
| 154 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, | ||
| 155 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, | ||
| 156 | CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, | ||
| 157 | CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, | ||
| 158 | CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, | ||
| 159 | CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, | ||
| 160 | CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, | ||
| 161 | CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, | ||
| 162 | CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, | ||
| 163 | CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, | ||
| 164 | CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, | ||
| 165 | CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, | ||
| 166 | CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, | ||
| 167 | CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, | ||
| 168 | CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, | ||
| 169 | CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, | ||
| 170 | CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, | ||
| 171 | CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, | ||
| 172 | CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, | ||
| 173 | CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, | ||
| 174 | CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, | ||
| 175 | CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, | ||
| 176 | CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, | ||
| 177 | CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, | ||
| 178 | CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, | ||
| 179 | CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, | ||
| 180 | CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, | ||
| 181 | CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, | ||
| 182 | CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, | ||
| 183 | CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, | ||
| 184 | CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, | ||
| 185 | CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, | ||
| 186 | CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, | ||
| 187 | CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, | ||
| 188 | CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, | ||
| 189 | CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, | ||
| 190 | CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, | ||
| 191 | CB_PERF_SEL_CM_CACHE_HIT = 0x41, | ||
| 192 | CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, | ||
| 193 | CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, | ||
| 194 | CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, | ||
| 195 | CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, | ||
| 196 | CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, | ||
| 197 | CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, | ||
| 198 | CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, | ||
| 199 | CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, | ||
| 200 | CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, | ||
| 201 | CB_PERF_SEL_CM_CACHE_STALL = 0x4b, | ||
| 202 | CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, | ||
| 203 | CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, | ||
| 204 | CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, | ||
| 205 | CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, | ||
| 206 | CB_PERF_SEL_FC_CACHE_HIT = 0x50, | ||
| 207 | CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, | ||
| 208 | CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, | ||
| 209 | CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, | ||
| 210 | CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, | ||
| 211 | CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, | ||
| 212 | CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, | ||
| 213 | CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, | ||
| 214 | CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, | ||
| 215 | CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, | ||
| 216 | CB_PERF_SEL_FC_CACHE_STALL = 0x5a, | ||
| 217 | CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, | ||
| 218 | CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, | ||
| 219 | CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, | ||
| 220 | CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, | ||
| 221 | CB_PERF_SEL_CC_CACHE_HIT = 0x5f, | ||
| 222 | CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, | ||
| 223 | CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, | ||
| 224 | CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, | ||
| 225 | CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, | ||
| 226 | CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, | ||
| 227 | CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, | ||
| 228 | CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, | ||
| 229 | CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, | ||
| 230 | CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, | ||
| 231 | CB_PERF_SEL_CC_CACHE_STALL = 0x69, | ||
| 232 | CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, | ||
| 233 | CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, | ||
| 234 | CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, | ||
| 235 | CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, | ||
| 236 | CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, | ||
| 237 | CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f, | ||
| 238 | CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70, | ||
| 239 | CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71, | ||
| 240 | CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72, | ||
| 241 | CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73, | ||
| 242 | CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74, | ||
| 243 | CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75, | ||
| 244 | CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76, | ||
| 245 | CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, | ||
| 246 | CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, | ||
| 247 | CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79, | ||
| 248 | CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a, | ||
| 249 | CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b, | ||
| 250 | CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c, | ||
| 251 | CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d, | ||
| 252 | CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e, | ||
| 253 | CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f, | ||
| 254 | CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80, | ||
| 255 | CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81, | ||
| 256 | CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, | ||
| 257 | CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83, | ||
| 258 | CB_PERF_SEL_CM_TQ_FULL = 0x84, | ||
| 259 | CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85, | ||
| 260 | CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86, | ||
| 261 | CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87, | ||
| 262 | CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88, | ||
| 263 | CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89, | ||
| 264 | CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a, | ||
| 265 | CB_PERF_SEL_CC_SF_FULL = 0x8b, | ||
| 266 | CB_PERF_SEL_CC_RB_FULL = 0x8c, | ||
| 267 | CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d, | ||
| 268 | CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e, | ||
| 269 | CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f, | ||
| 270 | CB_PERF_SEL_EVENT = 0x90, | ||
| 271 | CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91, | ||
| 272 | CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92, | ||
| 273 | CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93, | ||
| 274 | CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94, | ||
| 275 | CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95, | ||
| 276 | CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96, | ||
| 277 | CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97, | ||
| 278 | CB_PERF_SEL_CC_SURFACE_SYNC = 0x98, | ||
| 279 | CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99, | ||
| 280 | CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a, | ||
| 281 | CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b, | ||
| 282 | CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c, | ||
| 283 | CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d, | ||
| 284 | CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e, | ||
| 285 | CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f, | ||
| 286 | CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0, | ||
| 287 | CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1, | ||
| 288 | CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2, | ||
| 289 | CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3, | ||
| 290 | CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4, | ||
| 291 | CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5, | ||
| 292 | CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6, | ||
| 293 | CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7, | ||
| 294 | CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8, | ||
| 295 | CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9, | ||
| 296 | CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa, | ||
| 297 | CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab, | ||
| 298 | CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac, | ||
| 299 | CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad, | ||
| 300 | CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae, | ||
| 301 | CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf, | ||
| 302 | CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0, | ||
| 303 | CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1, | ||
| 304 | CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2, | ||
| 305 | CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3, | ||
| 306 | CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4, | ||
| 307 | CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5, | ||
| 308 | CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6, | ||
| 309 | CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7, | ||
| 310 | CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8, | ||
| 311 | CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9, | ||
| 312 | CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba, | ||
| 313 | CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb, | ||
| 314 | CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc, | ||
| 315 | CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd, | ||
| 316 | CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe, | ||
| 317 | CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf, | ||
| 318 | CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0, | ||
| 319 | CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1, | ||
| 320 | CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2, | ||
| 321 | CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3, | ||
| 322 | CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4, | ||
| 323 | CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5, | ||
| 324 | CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6, | ||
| 325 | CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7, | ||
| 326 | CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8, | ||
| 327 | CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9, | ||
| 328 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca, | ||
| 329 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb, | ||
| 330 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc, | ||
| 331 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd, | ||
| 332 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce, | ||
| 333 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf, | ||
| 334 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0, | ||
| 335 | CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1, | ||
| 336 | CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2, | ||
| 337 | CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3, | ||
| 338 | CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4, | ||
| 339 | CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5, | ||
| 340 | CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6, | ||
| 341 | CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7, | ||
| 342 | CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8, | ||
| 343 | CB_PERF_SEL_DRAWN_BUSY = 0xd9, | ||
| 344 | CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda, | ||
| 345 | CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb, | ||
| 346 | CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc, | ||
| 347 | CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd, | ||
| 348 | CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde, | ||
| 349 | CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf, | ||
| 350 | CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0, | ||
| 351 | CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1, | ||
| 352 | CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2, | ||
| 353 | CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3, | ||
| 354 | CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4, | ||
| 355 | CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5, | ||
| 356 | CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6, | ||
| 357 | CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7, | ||
| 358 | CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8, | ||
| 359 | CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9, | ||
| 360 | CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea, | ||
| 361 | CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb, | ||
| 362 | CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec, | ||
| 363 | CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed, | ||
| 364 | CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee, | ||
| 365 | CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef, | ||
| 366 | CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0, | ||
| 367 | CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1, | ||
| 368 | CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2, | ||
| 369 | CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3, | ||
| 370 | CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4, | ||
| 371 | CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5, | ||
| 372 | CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6, | ||
| 373 | CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7, | ||
| 374 | CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8, | ||
| 375 | CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9, | ||
| 376 | CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa, | ||
| 377 | CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb, | ||
| 378 | CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc, | ||
| 379 | CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd, | ||
| 380 | CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe, | ||
| 381 | CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff, | ||
| 382 | CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100, | ||
| 383 | CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101, | ||
| 384 | CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102, | ||
| 385 | CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103, | ||
| 386 | CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104, | ||
| 387 | CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105, | ||
| 388 | CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106, | ||
| 389 | CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107, | ||
| 390 | CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108, | ||
| 391 | CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109, | ||
| 392 | CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a, | ||
| 393 | CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b, | ||
| 394 | CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c, | ||
| 395 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d, | ||
| 396 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e, | ||
| 397 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f, | ||
| 398 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110, | ||
| 399 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111, | ||
| 400 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112, | ||
| 401 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113, | ||
| 402 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114, | ||
| 403 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115, | ||
| 404 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116, | ||
| 405 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117, | ||
| 406 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118, | ||
| 407 | CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119, | ||
| 408 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a, | ||
| 409 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b, | ||
| 410 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c, | ||
| 411 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d, | ||
| 412 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e, | ||
| 413 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f, | ||
| 414 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120, | ||
| 415 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121, | ||
| 416 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122, | ||
| 417 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123, | ||
| 418 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124, | ||
| 419 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125, | ||
| 420 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126, | ||
| 421 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127, | ||
| 422 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128, | ||
| 423 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129, | ||
| 424 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a, | ||
| 425 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b, | ||
| 426 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c, | ||
| 427 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d, | ||
| 428 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e, | ||
| 429 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f, | ||
| 430 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130, | ||
| 431 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131, | ||
| 432 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132, | ||
| 433 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133, | ||
| 434 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134, | ||
| 435 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135, | ||
| 436 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136, | ||
| 437 | CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137, | ||
| 438 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138, | ||
| 439 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139, | ||
| 440 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a, | ||
| 441 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b, | ||
| 442 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c, | ||
| 443 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d, | ||
| 444 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e, | ||
| 445 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f, | ||
| 446 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140, | ||
| 447 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141, | ||
| 448 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142, | ||
| 449 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143, | ||
| 450 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144, | ||
| 451 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145, | ||
| 452 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146, | ||
| 453 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147, | ||
| 454 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148, | ||
| 455 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149, | ||
| 456 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a, | ||
| 457 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b, | ||
| 458 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c, | ||
| 459 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d, | ||
| 460 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e, | ||
| 461 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f, | ||
| 462 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150, | ||
| 463 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151, | ||
| 464 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152, | ||
| 465 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153, | ||
| 466 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154, | ||
| 467 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155, | ||
| 468 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156, | ||
| 469 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157, | ||
| 470 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158, | ||
| 471 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159, | ||
| 472 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a, | ||
| 473 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b, | ||
| 474 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c, | ||
| 475 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d, | ||
| 476 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e, | ||
| 477 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f, | ||
| 478 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160, | ||
| 479 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161, | ||
| 480 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162, | ||
| 481 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163, | ||
| 482 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164, | ||
| 483 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165, | ||
| 484 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166, | ||
| 485 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167, | ||
| 486 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168, | ||
| 487 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169, | ||
| 488 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a, | ||
| 489 | CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b, | ||
| 490 | CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c, | ||
| 491 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d, | ||
| 492 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e, | ||
| 493 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f, | ||
| 494 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170, | ||
| 495 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171, | ||
| 496 | CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172, | ||
| 497 | CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173, | ||
| 498 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174, | ||
| 499 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175, | ||
| 500 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176, | ||
| 501 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177, | ||
| 502 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178, | ||
| 503 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179, | ||
| 504 | CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a, | ||
| 505 | CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b, | ||
| 506 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c, | ||
| 507 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d, | ||
| 508 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e, | ||
| 509 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f, | ||
| 510 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180, | ||
| 511 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181, | ||
| 512 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182, | ||
| 513 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183, | ||
| 514 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184, | ||
| 515 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185, | ||
| 516 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186, | ||
| 517 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187, | ||
| 518 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188, | ||
| 519 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189, | ||
| 520 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a, | ||
| 521 | CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b, | ||
| 522 | CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x18c, | ||
| 523 | CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x18d, | ||
| 524 | CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x18e, | ||
| 525 | CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x18f, | ||
| 526 | CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x190, | ||
| 527 | CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x191, | ||
| 528 | CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x192, | ||
| 529 | CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x193, | ||
| 530 | CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x194, | ||
| 531 | } CBPerfSel; | ||
| 532 | typedef enum CBPerfOpFilterSel { | ||
| 533 | CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, | ||
| 534 | CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, | ||
| 535 | CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, | ||
| 536 | CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, | ||
| 537 | CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, | ||
| 538 | CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, | ||
| 539 | } CBPerfOpFilterSel; | ||
| 540 | typedef enum CBPerfClearFilterSel { | ||
| 541 | CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, | ||
| 542 | CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, | ||
| 543 | } CBPerfClearFilterSel; | ||
| 544 | typedef enum CP_RING_ID { | ||
| 545 | RINGID0 = 0x0, | ||
| 546 | RINGID1 = 0x1, | ||
| 547 | RINGID2 = 0x2, | ||
| 548 | RINGID3 = 0x3, | ||
| 549 | } CP_RING_ID; | ||
| 550 | typedef enum CP_PIPE_ID { | ||
| 551 | PIPE_ID0 = 0x0, | ||
| 552 | PIPE_ID1 = 0x1, | ||
| 553 | PIPE_ID2 = 0x2, | ||
| 554 | PIPE_ID3 = 0x3, | ||
| 555 | } CP_PIPE_ID; | ||
| 556 | typedef enum CP_ME_ID { | ||
| 557 | ME_ID0 = 0x0, | ||
| 558 | ME_ID1 = 0x1, | ||
| 559 | ME_ID2 = 0x2, | ||
| 560 | ME_ID3 = 0x3, | ||
| 561 | } CP_ME_ID; | ||
| 562 | typedef enum SPM_PERFMON_STATE { | ||
| 563 | STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, | ||
| 564 | STRM_PERFMON_STATE_START_COUNTING = 0x1, | ||
| 565 | STRM_PERFMON_STATE_STOP_COUNTING = 0x2, | ||
| 566 | STRM_PERFMON_STATE_RESERVED_3 = 0x3, | ||
| 567 | STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, | ||
| 568 | STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, | ||
| 569 | } SPM_PERFMON_STATE; | ||
| 570 | typedef enum CP_PERFMON_STATE { | ||
| 571 | CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, | ||
| 572 | CP_PERFMON_STATE_START_COUNTING = 0x1, | ||
| 573 | CP_PERFMON_STATE_STOP_COUNTING = 0x2, | ||
| 574 | CP_PERFMON_STATE_RESERVED_3 = 0x3, | ||
| 575 | CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, | ||
| 576 | CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, | ||
| 577 | } CP_PERFMON_STATE; | ||
| 578 | typedef enum CP_PERFMON_ENABLE_MODE { | ||
| 579 | CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, | ||
| 580 | CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, | ||
| 581 | CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, | ||
| 582 | CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, | ||
| 583 | } CP_PERFMON_ENABLE_MODE; | ||
| 584 | typedef enum CPG_PERFCOUNT_SEL { | ||
| 585 | CPG_PERF_SEL_ALWAYS_COUNT = 0x0, | ||
| 586 | CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, | ||
| 587 | CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, | ||
| 588 | CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, | ||
| 589 | CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, | ||
| 590 | CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, | ||
| 591 | CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, | ||
| 592 | CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, | ||
| 593 | CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, | ||
| 594 | CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, | ||
| 595 | CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, | ||
| 596 | CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, | ||
| 597 | CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, | ||
| 598 | CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, | ||
| 599 | CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, | ||
| 600 | CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, | ||
| 601 | CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, | ||
| 602 | CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, | ||
| 603 | CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, | ||
| 604 | CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, | ||
| 605 | CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, | ||
| 606 | CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, | ||
| 607 | CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, | ||
| 608 | CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, | ||
| 609 | CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, | ||
| 610 | CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, | ||
| 611 | CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, | ||
| 612 | CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, | ||
| 613 | CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, | ||
| 614 | CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, | ||
| 615 | CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, | ||
| 616 | CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, | ||
| 617 | CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, | ||
| 618 | CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, | ||
| 619 | CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, | ||
| 620 | CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, | ||
| 621 | CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, | ||
| 622 | CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, | ||
| 623 | CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, | ||
| 624 | CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, | ||
| 625 | CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, | ||
| 626 | CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, | ||
| 627 | CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, | ||
| 628 | CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, | ||
| 629 | CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, | ||
| 630 | CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, | ||
| 631 | CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e, | ||
| 632 | CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f, | ||
| 633 | CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30, | ||
| 634 | } CPG_PERFCOUNT_SEL; | ||
| 635 | typedef enum CPF_PERFCOUNT_SEL { | ||
| 636 | CPF_PERF_SEL_ALWAYS_COUNT = 0x0, | ||
| 637 | CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, | ||
| 638 | CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, | ||
| 639 | CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, | ||
| 640 | CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, | ||
| 641 | CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, | ||
| 642 | CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, | ||
| 643 | CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, | ||
| 644 | CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, | ||
| 645 | CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, | ||
| 646 | CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, | ||
| 647 | CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, | ||
| 648 | CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, | ||
| 649 | CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, | ||
| 650 | CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, | ||
| 651 | CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, | ||
| 652 | CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, | ||
| 653 | CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11, | ||
| 654 | CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12, | ||
| 655 | CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13, | ||
| 656 | } CPF_PERFCOUNT_SEL; | ||
| 657 | typedef enum CPC_PERFCOUNT_SEL { | ||
| 658 | CPC_PERF_SEL_ALWAYS_COUNT = 0x0, | ||
| 659 | CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, | ||
| 660 | CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, | ||
| 661 | CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, | ||
| 662 | CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, | ||
| 663 | CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, | ||
| 664 | CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, | ||
| 665 | CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, | ||
| 666 | CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, | ||
| 667 | CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, | ||
| 668 | CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, | ||
| 669 | CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, | ||
| 670 | CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, | ||
| 671 | CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, | ||
| 672 | CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, | ||
| 673 | CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, | ||
| 674 | CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, | ||
| 675 | CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, | ||
| 676 | CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, | ||
| 677 | CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, | ||
| 678 | CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, | ||
| 679 | CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, | ||
| 680 | CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16, | ||
| 681 | CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17, | ||
| 682 | CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18, | ||
| 683 | } CPC_PERFCOUNT_SEL; | ||
| 684 | typedef enum CP_ALPHA_TAG_RAM_SEL { | ||
| 685 | CPG_TAG_RAM = 0x0, | ||
| 686 | CPC_TAG_RAM = 0x1, | ||
| 687 | CPF_TAG_RAM = 0x2, | ||
| 688 | RSV_TAG_RAM = 0x3, | ||
| 689 | } CP_ALPHA_TAG_RAM_SEL; | ||
| 690 | #define SEM_ECC_ERROR 0x0 | ||
| 691 | #define SEM_RESERVED 0x1 | ||
| 692 | #define SEM_FAILED 0x2 | ||
| 693 | #define SEM_PASSED 0x3 | ||
| 694 | #define IQ_QUEUE_SLEEP 0x0 | ||
| 695 | #define IQ_OFFLOAD_RETRY 0x1 | ||
| 696 | #define IQ_SCH_WAVE_MSG 0x2 | ||
| 697 | #define IQ_SEM_REARM 0x3 | ||
| 698 | #define IQ_DEQUEUE_RETRY 0x4 | ||
| 699 | #define IQ_INTR_TYPE_PQ 0x0 | ||
| 700 | #define IQ_INTR_TYPE_IB 0x1 | ||
| 701 | #define IQ_INTR_TYPE_MQD 0x2 | ||
| 702 | #define VMID_SZ 0x4 | ||
| 703 | #define CONFIG_SPACE_START 0x2000 | ||
| 704 | #define CONFIG_SPACE_END 0x9fff | ||
| 705 | #define CONFIG_SPACE1_START 0x2000 | ||
| 706 | #define CONFIG_SPACE1_END 0x2bff | ||
| 707 | #define CONFIG_SPACE2_START 0x3000 | ||
| 708 | #define CONFIG_SPACE2_END 0x9fff | ||
| 709 | #define UCONFIG_SPACE_START 0xc000 | ||
| 710 | #define UCONFIG_SPACE_END 0xffff | ||
| 711 | #define PERSISTENT_SPACE_START 0x2c00 | ||
| 712 | #define PERSISTENT_SPACE_END 0x2fff | ||
| 713 | #define CONTEXT_SPACE_START 0xa000 | ||
| 714 | #define CONTEXT_SPACE_END 0xbfff | ||
| 715 | typedef enum ForceControl { | ||
| 716 | FORCE_OFF = 0x0, | ||
| 717 | FORCE_ENABLE = 0x1, | ||
| 718 | FORCE_DISABLE = 0x2, | ||
| 719 | FORCE_RESERVED = 0x3, | ||
| 720 | } ForceControl; | ||
| 721 | typedef enum ZSamplePosition { | ||
| 722 | Z_SAMPLE_CENTER = 0x0, | ||
| 723 | Z_SAMPLE_CENTROID = 0x1, | ||
| 724 | } ZSamplePosition; | ||
| 725 | typedef enum ZOrder { | ||
| 726 | LATE_Z = 0x0, | ||
| 727 | EARLY_Z_THEN_LATE_Z = 0x1, | ||
| 728 | RE_Z = 0x2, | ||
| 729 | EARLY_Z_THEN_RE_Z = 0x3, | ||
| 730 | } ZOrder; | ||
| 731 | typedef enum ZpassControl { | ||
| 732 | ZPASS_DISABLE = 0x0, | ||
| 733 | ZPASS_SAMPLES = 0x1, | ||
| 734 | ZPASS_PIXELS = 0x2, | ||
| 735 | } ZpassControl; | ||
| 736 | typedef enum ZModeForce { | ||
| 737 | NO_FORCE = 0x0, | ||
| 738 | FORCE_EARLY_Z = 0x1, | ||
| 739 | FORCE_LATE_Z = 0x2, | ||
| 740 | FORCE_RE_Z = 0x3, | ||
| 741 | } ZModeForce; | ||
| 742 | typedef enum ZLimitSumm { | ||
| 743 | FORCE_SUMM_OFF = 0x0, | ||
| 744 | FORCE_SUMM_MINZ = 0x1, | ||
| 745 | FORCE_SUMM_MAXZ = 0x2, | ||
| 746 | FORCE_SUMM_BOTH = 0x3, | ||
| 747 | } ZLimitSumm; | ||
| 748 | typedef enum CompareFrag { | ||
| 749 | FRAG_NEVER = 0x0, | ||
| 750 | FRAG_LESS = 0x1, | ||
| 751 | FRAG_EQUAL = 0x2, | ||
| 752 | FRAG_LEQUAL = 0x3, | ||
| 753 | FRAG_GREATER = 0x4, | ||
| 754 | FRAG_NOTEQUAL = 0x5, | ||
| 755 | FRAG_GEQUAL = 0x6, | ||
| 756 | FRAG_ALWAYS = 0x7, | ||
| 757 | } CompareFrag; | ||
| 758 | typedef enum StencilOp { | ||
| 759 | STENCIL_KEEP = 0x0, | ||
| 760 | STENCIL_ZERO = 0x1, | ||
| 761 | STENCIL_ONES = 0x2, | ||
| 762 | STENCIL_REPLACE_TEST = 0x3, | ||
| 763 | STENCIL_REPLACE_OP = 0x4, | ||
| 764 | STENCIL_ADD_CLAMP = 0x5, | ||
| 765 | STENCIL_SUB_CLAMP = 0x6, | ||
| 766 | STENCIL_INVERT = 0x7, | ||
| 767 | STENCIL_ADD_WRAP = 0x8, | ||
| 768 | STENCIL_SUB_WRAP = 0x9, | ||
| 769 | STENCIL_AND = 0xa, | ||
| 770 | STENCIL_OR = 0xb, | ||
| 771 | STENCIL_XOR = 0xc, | ||
| 772 | STENCIL_NAND = 0xd, | ||
| 773 | STENCIL_NOR = 0xe, | ||
| 774 | STENCIL_XNOR = 0xf, | ||
| 775 | } StencilOp; | ||
| 776 | typedef enum ConservativeZExport { | ||
| 777 | EXPORT_ANY_Z = 0x0, | ||
| 778 | EXPORT_LESS_THAN_Z = 0x1, | ||
| 779 | EXPORT_GREATER_THAN_Z = 0x2, | ||
| 780 | EXPORT_RESERVED = 0x3, | ||
| 781 | } ConservativeZExport; | ||
| 782 | typedef enum DbPSLControl { | ||
| 783 | PSLC_AUTO = 0x0, | ||
| 784 | PSLC_ON_HANG_ONLY = 0x1, | ||
| 785 | PSLC_ASAP = 0x2, | ||
| 786 | PSLC_COUNTDOWN = 0x3, | ||
| 787 | } DbPSLControl; | ||
| 788 | typedef enum PerfCounter_Vals { | ||
| 789 | DB_PERF_SEL_SC_DB_tile_sends = 0x0, | ||
| 790 | DB_PERF_SEL_SC_DB_tile_busy = 0x1, | ||
| 791 | DB_PERF_SEL_SC_DB_tile_stalls = 0x2, | ||
| 792 | DB_PERF_SEL_SC_DB_tile_events = 0x3, | ||
| 793 | DB_PERF_SEL_SC_DB_tile_tiles = 0x4, | ||
| 794 | DB_PERF_SEL_SC_DB_tile_covered = 0x5, | ||
| 795 | DB_PERF_SEL_hiz_tc_read_starved = 0x6, | ||
| 796 | DB_PERF_SEL_hiz_tc_write_stall = 0x7, | ||
| 797 | DB_PERF_SEL_hiz_qtiles_culled = 0x8, | ||
| 798 | DB_PERF_SEL_his_qtiles_culled = 0x9, | ||
| 799 | DB_PERF_SEL_DB_SC_tile_sends = 0xa, | ||
| 800 | DB_PERF_SEL_DB_SC_tile_busy = 0xb, | ||
| 801 | DB_PERF_SEL_DB_SC_tile_stalls = 0xc, | ||
| 802 | DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, | ||
| 803 | DB_PERF_SEL_DB_SC_tile_tiles = 0xe, | ||
| 804 | DB_PERF_SEL_DB_SC_tile_culled = 0xf, | ||
| 805 | DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, | ||
| 806 | DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, | ||
| 807 | DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, | ||
| 808 | DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, | ||
| 809 | DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, | ||
| 810 | DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, | ||
| 811 | DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, | ||
| 812 | DB_PERF_SEL_SC_DB_quad_sends = 0x17, | ||
| 813 | DB_PERF_SEL_SC_DB_quad_busy = 0x18, | ||
| 814 | DB_PERF_SEL_SC_DB_quad_squads = 0x19, | ||
| 815 | DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, | ||
| 816 | DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, | ||
| 817 | DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, | ||
| 818 | DB_PERF_SEL_DB_SC_quad_sends = 0x1d, | ||
| 819 | DB_PERF_SEL_DB_SC_quad_busy = 0x1e, | ||
| 820 | DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, | ||
| 821 | DB_PERF_SEL_DB_SC_quad_tiles = 0x20, | ||
| 822 | DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, | ||
| 823 | DB_PERF_SEL_DB_CB_tile_sends = 0x22, | ||
| 824 | DB_PERF_SEL_DB_CB_tile_busy = 0x23, | ||
| 825 | DB_PERF_SEL_DB_CB_tile_stalls = 0x24, | ||
| 826 | DB_PERF_SEL_SX_DB_quad_sends = 0x25, | ||
| 827 | DB_PERF_SEL_SX_DB_quad_busy = 0x26, | ||
| 828 | DB_PERF_SEL_SX_DB_quad_stalls = 0x27, | ||
| 829 | DB_PERF_SEL_SX_DB_quad_quads = 0x28, | ||
| 830 | DB_PERF_SEL_SX_DB_quad_pixels = 0x29, | ||
| 831 | DB_PERF_SEL_SX_DB_quad_exports = 0x2a, | ||
| 832 | DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, | ||
| 833 | DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, | ||
| 834 | DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, | ||
| 835 | DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, | ||
| 836 | DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, | ||
| 837 | DB_PERF_SEL_tile_rd_sends = 0x30, | ||
| 838 | DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, | ||
| 839 | DB_PERF_SEL_quad_rd_sends = 0x32, | ||
| 840 | DB_PERF_SEL_quad_rd_busy = 0x33, | ||
| 841 | DB_PERF_SEL_quad_rd_mi_stall = 0x34, | ||
| 842 | DB_PERF_SEL_quad_rd_rw_collision = 0x35, | ||
| 843 | DB_PERF_SEL_quad_rd_tag_stall = 0x36, | ||
| 844 | DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, | ||
| 845 | DB_PERF_SEL_quad_rd_panic = 0x38, | ||
| 846 | DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, | ||
| 847 | DB_PERF_SEL_quad_rdret_sends = 0x3a, | ||
| 848 | DB_PERF_SEL_quad_rdret_busy = 0x3b, | ||
| 849 | DB_PERF_SEL_tile_wr_sends = 0x3c, | ||
| 850 | DB_PERF_SEL_tile_wr_acks = 0x3d, | ||
| 851 | DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, | ||
| 852 | DB_PERF_SEL_quad_wr_sends = 0x3f, | ||
| 853 | DB_PERF_SEL_quad_wr_busy = 0x40, | ||
| 854 | DB_PERF_SEL_quad_wr_mi_stall = 0x41, | ||
| 855 | DB_PERF_SEL_quad_wr_coherency_stall = 0x42, | ||
| 856 | DB_PERF_SEL_quad_wr_acks = 0x43, | ||
| 857 | DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, | ||
| 858 | DB_PERF_SEL_Tile_Cache_misses = 0x45, | ||
| 859 | DB_PERF_SEL_Tile_Cache_hits = 0x46, | ||
| 860 | DB_PERF_SEL_Tile_Cache_flushes = 0x47, | ||
| 861 | DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, | ||
| 862 | DB_PERF_SEL_Tile_Cache_starves = 0x49, | ||
| 863 | DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, | ||
| 864 | DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, | ||
| 865 | DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, | ||
| 866 | DB_PERF_SEL_tcp_preloader_reads = 0x4d, | ||
| 867 | DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, | ||
| 868 | DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, | ||
| 869 | DB_PERF_SEL_tcp_preloader_flushes = 0x50, | ||
| 870 | DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, | ||
| 871 | DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, | ||
| 872 | DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, | ||
| 873 | DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, | ||
| 874 | DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, | ||
| 875 | DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, | ||
| 876 | DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, | ||
| 877 | DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, | ||
| 878 | DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, | ||
| 879 | DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, | ||
| 880 | DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, | ||
| 881 | DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, | ||
| 882 | DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, | ||
| 883 | DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, | ||
| 884 | DB_PERF_SEL_Stencil_Cache_misses = 0x5f, | ||
| 885 | DB_PERF_SEL_Stencil_Cache_hits = 0x60, | ||
| 886 | DB_PERF_SEL_Stencil_Cache_flushes = 0x61, | ||
| 887 | DB_PERF_SEL_Stencil_Cache_starves = 0x62, | ||
| 888 | DB_PERF_SEL_Stencil_Cache_frees = 0x63, | ||
| 889 | DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, | ||
| 890 | DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, | ||
| 891 | DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, | ||
| 892 | DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, | ||
| 893 | DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, | ||
| 894 | DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, | ||
| 895 | DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, | ||
| 896 | DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, | ||
| 897 | DB_PERF_SEL_Z_Cache_frees = 0x6c, | ||
| 898 | DB_PERF_SEL_Plane_Cache_misses = 0x6d, | ||
| 899 | DB_PERF_SEL_Plane_Cache_hits = 0x6e, | ||
| 900 | DB_PERF_SEL_Plane_Cache_flushes = 0x6f, | ||
| 901 | DB_PERF_SEL_Plane_Cache_starves = 0x70, | ||
| 902 | DB_PERF_SEL_Plane_Cache_frees = 0x71, | ||
| 903 | DB_PERF_SEL_flush_expanded_stencil = 0x72, | ||
| 904 | DB_PERF_SEL_flush_compressed_stencil = 0x73, | ||
| 905 | DB_PERF_SEL_flush_single_stencil = 0x74, | ||
| 906 | DB_PERF_SEL_planes_flushed = 0x75, | ||
| 907 | DB_PERF_SEL_flush_1plane = 0x76, | ||
| 908 | DB_PERF_SEL_flush_2plane = 0x77, | ||
| 909 | DB_PERF_SEL_flush_3plane = 0x78, | ||
| 910 | DB_PERF_SEL_flush_4plane = 0x79, | ||
| 911 | DB_PERF_SEL_flush_5plane = 0x7a, | ||
| 912 | DB_PERF_SEL_flush_6plane = 0x7b, | ||
| 913 | DB_PERF_SEL_flush_7plane = 0x7c, | ||
| 914 | DB_PERF_SEL_flush_8plane = 0x7d, | ||
| 915 | DB_PERF_SEL_flush_9plane = 0x7e, | ||
| 916 | DB_PERF_SEL_flush_10plane = 0x7f, | ||
| 917 | DB_PERF_SEL_flush_11plane = 0x80, | ||
| 918 | DB_PERF_SEL_flush_12plane = 0x81, | ||
| 919 | DB_PERF_SEL_flush_13plane = 0x82, | ||
| 920 | DB_PERF_SEL_flush_14plane = 0x83, | ||
| 921 | DB_PERF_SEL_flush_15plane = 0x84, | ||
| 922 | DB_PERF_SEL_flush_16plane = 0x85, | ||
| 923 | DB_PERF_SEL_flush_expanded_z = 0x86, | ||
| 924 | DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, | ||
| 925 | DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, | ||
| 926 | DB_PERF_SEL_dk_tile_sends = 0x89, | ||
| 927 | DB_PERF_SEL_dk_tile_busy = 0x8a, | ||
| 928 | DB_PERF_SEL_dk_tile_quad_starves = 0x8b, | ||
| 929 | DB_PERF_SEL_dk_tile_stalls = 0x8c, | ||
| 930 | DB_PERF_SEL_dk_squad_sends = 0x8d, | ||
| 931 | DB_PERF_SEL_dk_squad_busy = 0x8e, | ||
| 932 | DB_PERF_SEL_dk_squad_stalls = 0x8f, | ||
| 933 | DB_PERF_SEL_Op_Pipe_Busy = 0x90, | ||
| 934 | DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, | ||
| 935 | DB_PERF_SEL_qc_busy = 0x92, | ||
| 936 | DB_PERF_SEL_qc_xfc = 0x93, | ||
| 937 | DB_PERF_SEL_qc_conflicts = 0x94, | ||
| 938 | DB_PERF_SEL_qc_full_stall = 0x95, | ||
| 939 | DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, | ||
| 940 | DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, | ||
| 941 | DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, | ||
| 942 | DB_PERF_SEL_tl_busy = 0x99, | ||
| 943 | DB_PERF_SEL_tl_dtc_read_starved = 0x9a, | ||
| 944 | DB_PERF_SEL_tl_z_fetch_stall = 0x9b, | ||
| 945 | DB_PERF_SEL_tl_stencil_stall = 0x9c, | ||
| 946 | DB_PERF_SEL_tl_z_decompress_stall = 0x9d, | ||
| 947 | DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, | ||
| 948 | DB_PERF_SEL_tl_events = 0x9f, | ||
| 949 | DB_PERF_SEL_tl_summarize_squads = 0xa0, | ||
| 950 | DB_PERF_SEL_tl_flush_expand_squads = 0xa1, | ||
| 951 | DB_PERF_SEL_tl_expand_squads = 0xa2, | ||
| 952 | DB_PERF_SEL_tl_preZ_squads = 0xa3, | ||
| 953 | DB_PERF_SEL_tl_postZ_squads = 0xa4, | ||
| 954 | DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, | ||
| 955 | DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, | ||
| 956 | DB_PERF_SEL_tl_tile_ops = 0xa7, | ||
| 957 | DB_PERF_SEL_tl_in_xfc = 0xa8, | ||
| 958 | DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, | ||
| 959 | DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, | ||
| 960 | DB_PERF_SEL_tl_out_xfc = 0xab, | ||
| 961 | DB_PERF_SEL_tl_out_squads = 0xac, | ||
| 962 | DB_PERF_SEL_zf_plane_multicycle = 0xad, | ||
| 963 | DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, | ||
| 964 | DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, | ||
| 965 | DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, | ||
| 966 | DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, | ||
| 967 | DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, | ||
| 968 | DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, | ||
| 969 | DB_PERF_SEL_ts_tc_update_stall = 0xb4, | ||
| 970 | DB_PERF_SEL_sc_kick_start = 0xb5, | ||
| 971 | DB_PERF_SEL_sc_kick_end = 0xb6, | ||
| 972 | DB_PERF_SEL_clock_reg_active = 0xb7, | ||
| 973 | DB_PERF_SEL_clock_main_active = 0xb8, | ||
| 974 | DB_PERF_SEL_clock_mem_export_active = 0xb9, | ||
| 975 | DB_PERF_SEL_esr_ps_out_busy = 0xba, | ||
| 976 | DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, | ||
| 977 | DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, | ||
| 978 | DB_PERF_SEL_etr_out_send = 0xbd, | ||
| 979 | DB_PERF_SEL_etr_out_busy = 0xbe, | ||
| 980 | DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, | ||
| 981 | DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, | ||
| 982 | DB_PERF_SEL_etr_out_esr_stall = 0xc1, | ||
| 983 | DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, | ||
| 984 | DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, | ||
| 985 | DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, | ||
| 986 | DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, | ||
| 987 | DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, | ||
| 988 | DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, | ||
| 989 | DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, | ||
| 990 | DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, | ||
| 991 | DB_PERF_SEL_postzl_sq_pt_stall = 0xca, | ||
| 992 | DB_PERF_SEL_postzl_se_busy = 0xcb, | ||
| 993 | DB_PERF_SEL_postzl_se_stall = 0xcc, | ||
| 994 | DB_PERF_SEL_postzl_partial_launch = 0xcd, | ||
| 995 | DB_PERF_SEL_postzl_full_launch = 0xce, | ||
| 996 | DB_PERF_SEL_postzl_partial_waiting = 0xcf, | ||
| 997 | DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, | ||
| 998 | DB_PERF_SEL_postzl_tile_init_stall = 0xd1, | ||
| 999 | DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, | ||
| 1000 | DB_PERF_SEL_prezl_tile_init_stall = 0xd3, | ||
| 1001 | DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, | ||
| 1002 | DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, | ||
| 1003 | DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, | ||
| 1004 | DB_PERF_SEL_mi_rdreq_busy = 0xd7, | ||
| 1005 | DB_PERF_SEL_mi_rdreq_stall = 0xd8, | ||
| 1006 | DB_PERF_SEL_mi_wrreq_busy = 0xd9, | ||
| 1007 | DB_PERF_SEL_mi_wrreq_stall = 0xda, | ||
| 1008 | DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, | ||
| 1009 | DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, | ||
| 1010 | DB_PERF_SEL_prezl_src_in_sends = 0xdd, | ||
| 1011 | DB_PERF_SEL_prezl_src_in_stall = 0xde, | ||
| 1012 | DB_PERF_SEL_prezl_src_in_squads = 0xdf, | ||
| 1013 | DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, | ||
| 1014 | DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, | ||
| 1015 | DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, | ||
| 1016 | DB_PERF_SEL_prezl_src_out_stall = 0xe3, | ||
| 1017 | DB_PERF_SEL_postzl_src_in_sends = 0xe4, | ||
| 1018 | DB_PERF_SEL_postzl_src_in_stall = 0xe5, | ||
| 1019 | DB_PERF_SEL_postzl_src_in_squads = 0xe6, | ||
| 1020 | DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, | ||
| 1021 | DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, | ||
| 1022 | DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, | ||
| 1023 | DB_PERF_SEL_postzl_src_out_stall = 0xea, | ||
| 1024 | DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, | ||
| 1025 | DB_PERF_SEL_esr_ps_src_in_stall = 0xec, | ||
| 1026 | DB_PERF_SEL_esr_ps_src_in_squads = 0xed, | ||
| 1027 | DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, | ||
| 1028 | DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, | ||
| 1029 | DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, | ||
| 1030 | DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, | ||
| 1031 | DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, | ||
| 1032 | DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, | ||
| 1033 | DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, | ||
| 1034 | DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, | ||
| 1035 | DB_PERF_SEL_flush_compressed = 0xf6, | ||
| 1036 | DB_PERF_SEL_flush_plane_le4 = 0xf7, | ||
| 1037 | DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, | ||
| 1038 | DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, | ||
| 1039 | DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, | ||
| 1040 | DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, | ||
| 1041 | DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, | ||
| 1042 | DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, | ||
| 1043 | DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, | ||
| 1044 | DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, | ||
| 1045 | DB_PERF_SEL_di_dt_stall = 0x100, | ||
| 1046 | DB_PERF_SEL_DB_SC_quad_double_quad = 0x101, | ||
| 1047 | DB_PERF_SEL_SX_DB_quad_export_quads = 0x102, | ||
| 1048 | DB_PERF_SEL_SX_DB_quad_double_format = 0x103, | ||
| 1049 | DB_PERF_SEL_SX_DB_quad_fast_format = 0x104, | ||
| 1050 | DB_PERF_SEL_SX_DB_quad_slow_format = 0x105, | ||
| 1051 | DB_PERF_SEL_DB_CB_lquad_export_quads = 0x106, | ||
| 1052 | DB_PERF_SEL_DB_CB_lquad_double_format = 0x107, | ||
| 1053 | DB_PERF_SEL_DB_CB_lquad_fast_format = 0x108, | ||
| 1054 | DB_PERF_SEL_DB_CB_lquad_slow_format = 0x109, | ||
| 1055 | } PerfCounter_Vals; | ||
| 1056 | typedef enum RingCounterControl { | ||
| 1057 | COUNTER_RING_SPLIT = 0x0, | ||
| 1058 | COUNTER_RING_0 = 0x1, | ||
| 1059 | COUNTER_RING_1 = 0x2, | ||
| 1060 | } RingCounterControl; | ||
| 1061 | typedef enum PixelPipeCounterId { | ||
| 1062 | PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, | ||
| 1063 | PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, | ||
| 1064 | PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, | ||
| 1065 | PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, | ||
| 1066 | PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, | ||
| 1067 | PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, | ||
| 1068 | PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, | ||
| 1069 | PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, | ||
| 1070 | } PixelPipeCounterId; | ||
| 1071 | typedef enum PixelPipeStride { | ||
| 1072 | PIXEL_PIPE_STRIDE_32_BITS = 0x0, | ||
| 1073 | PIXEL_PIPE_STRIDE_64_BITS = 0x1, | ||
| 1074 | PIXEL_PIPE_STRIDE_128_BITS = 0x2, | ||
| 1075 | PIXEL_PIPE_STRIDE_256_BITS = 0x3, | ||
| 1076 | } PixelPipeStride; | ||
| 1077 | typedef enum GB_EDC_DED_MODE { | ||
| 1078 | GB_EDC_DED_MODE_LOG = 0x0, | ||
| 1079 | GB_EDC_DED_MODE_HALT = 0x1, | ||
| 1080 | GB_EDC_DED_MODE_INT_HALT = 0x2, | ||
| 1081 | } GB_EDC_DED_MODE; | ||
| 1082 | #define GB_TILING_CONFIG_TABLE_SIZE 0x20 | ||
| 1083 | #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 | ||
| 1084 | typedef enum GRBM_PERF_SEL { | ||
| 1085 | GRBM_PERF_SEL_COUNT = 0x0, | ||
| 1086 | GRBM_PERF_SEL_USER_DEFINED = 0x1, | ||
| 1087 | GRBM_PERF_SEL_GUI_ACTIVE = 0x2, | ||
| 1088 | GRBM_PERF_SEL_CP_BUSY = 0x3, | ||
| 1089 | GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, | ||
| 1090 | GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, | ||
| 1091 | GRBM_PERF_SEL_CB_BUSY = 0x6, | ||
| 1092 | GRBM_PERF_SEL_DB_BUSY = 0x7, | ||
| 1093 | GRBM_PERF_SEL_PA_BUSY = 0x8, | ||
| 1094 | GRBM_PERF_SEL_SC_BUSY = 0x9, | ||
| 1095 | GRBM_PERF_SEL_RESERVED_6 = 0xa, | ||
| 1096 | GRBM_PERF_SEL_SPI_BUSY = 0xb, | ||
| 1097 | GRBM_PERF_SEL_SX_BUSY = 0xc, | ||
| 1098 | GRBM_PERF_SEL_TA_BUSY = 0xd, | ||
| 1099 | GRBM_PERF_SEL_CB_CLEAN = 0xe, | ||
| 1100 | GRBM_PERF_SEL_DB_CLEAN = 0xf, | ||
| 1101 | GRBM_PERF_SEL_RESERVED_5 = 0x10, | ||
| 1102 | GRBM_PERF_SEL_VGT_BUSY = 0x11, | ||
| 1103 | GRBM_PERF_SEL_RESERVED_4 = 0x12, | ||
| 1104 | GRBM_PERF_SEL_RESERVED_3 = 0x13, | ||
| 1105 | GRBM_PERF_SEL_RESERVED_2 = 0x14, | ||
| 1106 | GRBM_PERF_SEL_RESERVED_1 = 0x15, | ||
| 1107 | GRBM_PERF_SEL_RESERVED_0 = 0x16, | ||
| 1108 | GRBM_PERF_SEL_IA_BUSY = 0x17, | ||
| 1109 | GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, | ||
| 1110 | GRBM_PERF_SEL_GDS_BUSY = 0x19, | ||
| 1111 | GRBM_PERF_SEL_BCI_BUSY = 0x1a, | ||
| 1112 | GRBM_PERF_SEL_RLC_BUSY = 0x1b, | ||
| 1113 | GRBM_PERF_SEL_TC_BUSY = 0x1c, | ||
| 1114 | GRBM_PERF_SEL_CPG_BUSY = 0x1d, | ||
| 1115 | GRBM_PERF_SEL_CPC_BUSY = 0x1e, | ||
| 1116 | GRBM_PERF_SEL_CPF_BUSY = 0x1f, | ||
| 1117 | GRBM_PERF_SEL_WD_BUSY = 0x20, | ||
| 1118 | GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, | ||
| 1119 | } GRBM_PERF_SEL; | ||
| 1120 | typedef enum GRBM_SE0_PERF_SEL { | ||
| 1121 | GRBM_SE0_PERF_SEL_COUNT = 0x0, | ||
| 1122 | GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, | ||
| 1123 | GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, | ||
| 1124 | GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, | ||
| 1125 | GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, | ||
| 1126 | GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, | ||
| 1127 | GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, | ||
| 1128 | GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, | ||
| 1129 | GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, | ||
| 1130 | GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, | ||
| 1131 | GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, | ||
| 1132 | GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, | ||
| 1133 | GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, | ||
| 1134 | GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, | ||
| 1135 | GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, | ||
| 1136 | } GRBM_SE0_PERF_SEL; | ||
| 1137 | typedef enum GRBM_SE1_PERF_SEL { | ||
| 1138 | GRBM_SE1_PERF_SEL_COUNT = 0x0, | ||
| 1139 | GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, | ||
| 1140 | GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, | ||
| 1141 | GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, | ||
| 1142 | GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, | ||
| 1143 | GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, | ||
| 1144 | GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, | ||
| 1145 | GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, | ||
| 1146 | GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, | ||
| 1147 | GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, | ||
| 1148 | GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, | ||
| 1149 | GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, | ||
| 1150 | GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, | ||
| 1151 | GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, | ||
| 1152 | GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, | ||
| 1153 | } GRBM_SE1_PERF_SEL; | ||
| 1154 | typedef enum GRBM_SE2_PERF_SEL { | ||
| 1155 | GRBM_SE2_PERF_SEL_COUNT = 0x0, | ||
| 1156 | GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, | ||
| 1157 | GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, | ||
| 1158 | GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, | ||
| 1159 | GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, | ||
| 1160 | GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, | ||
| 1161 | GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, | ||
| 1162 | GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, | ||
| 1163 | GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, | ||
| 1164 | GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, | ||
| 1165 | GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, | ||
| 1166 | GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, | ||
| 1167 | GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, | ||
| 1168 | GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, | ||
| 1169 | GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, | ||
| 1170 | } GRBM_SE2_PERF_SEL; | ||
| 1171 | typedef enum GRBM_SE3_PERF_SEL { | ||
| 1172 | GRBM_SE3_PERF_SEL_COUNT = 0x0, | ||
| 1173 | GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, | ||
| 1174 | GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, | ||
| 1175 | GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, | ||
| 1176 | GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, | ||
| 1177 | GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, | ||
| 1178 | GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, | ||
| 1179 | GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, | ||
| 1180 | GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, | ||
| 1181 | GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, | ||
| 1182 | GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, | ||
| 1183 | GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, | ||
| 1184 | GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, | ||
| 1185 | GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, | ||
| 1186 | GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, | ||
| 1187 | } GRBM_SE3_PERF_SEL; | ||
| 1188 | typedef enum SU_PERFCNT_SEL { | ||
| 1189 | PERF_PAPC_PASX_REQ = 0x0, | ||
| 1190 | PERF_PAPC_PASX_DISABLE_PIPE = 0x1, | ||
| 1191 | PERF_PAPC_PASX_FIRST_VECTOR = 0x2, | ||
| 1192 | PERF_PAPC_PASX_SECOND_VECTOR = 0x3, | ||
| 1193 | PERF_PAPC_PASX_FIRST_DEAD = 0x4, | ||
| 1194 | PERF_PAPC_PASX_SECOND_DEAD = 0x5, | ||
| 1195 | PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, | ||
| 1196 | PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, | ||
| 1197 | PERF_PAPC_PA_INPUT_PRIM = 0x8, | ||
| 1198 | PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, | ||
| 1199 | PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, | ||
| 1200 | PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, | ||
| 1201 | PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, | ||
| 1202 | PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, | ||
| 1203 | PERF_PAPC_CLPR_CULL_PRIM = 0xe, | ||
| 1204 | PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, | ||
| 1205 | PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, | ||
| 1206 | PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, | ||
| 1207 | PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, | ||
| 1208 | PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, | ||
| 1209 | PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, | ||
| 1210 | PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, | ||
| 1211 | PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, | ||
| 1212 | PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, | ||
| 1213 | PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, | ||
| 1214 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, | ||
| 1215 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, | ||
| 1216 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, | ||
| 1217 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, | ||
| 1218 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, | ||
| 1219 | PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, | ||
| 1220 | PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, | ||
| 1221 | PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, | ||
| 1222 | PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, | ||
| 1223 | PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, | ||
| 1224 | PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, | ||
| 1225 | PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, | ||
| 1226 | PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, | ||
| 1227 | PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, | ||
| 1228 | PERF_PAPC_CLSM_NULL_PRIM = 0x27, | ||
| 1229 | PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, | ||
| 1230 | PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, | ||
| 1231 | PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, | ||
| 1232 | PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, | ||
| 1233 | PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, | ||
| 1234 | PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, | ||
| 1235 | PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, | ||
| 1236 | PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, | ||
| 1237 | PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, | ||
| 1238 | PERF_PAPC_SU_INPUT_PRIM = 0x31, | ||
| 1239 | PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, | ||
| 1240 | PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, | ||
| 1241 | PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, | ||
| 1242 | PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, | ||
| 1243 | PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, | ||
| 1244 | PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, | ||
| 1245 | PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, | ||
| 1246 | PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, | ||
| 1247 | PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, | ||
| 1248 | PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, | ||
| 1249 | PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, | ||
| 1250 | PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, | ||
| 1251 | PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, | ||
| 1252 | PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, | ||
| 1253 | PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, | ||
| 1254 | PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, | ||
| 1255 | PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, | ||
| 1256 | PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, | ||
| 1257 | PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, | ||
| 1258 | PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, | ||
| 1259 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, | ||
| 1260 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, | ||
| 1261 | PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, | ||
| 1262 | PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, | ||
| 1263 | PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, | ||
| 1264 | PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, | ||
| 1265 | PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, | ||
| 1266 | PERF_PAPC_PASX_REQ_IDLE = 0x4d, | ||
| 1267 | PERF_PAPC_PASX_REQ_BUSY = 0x4e, | ||
| 1268 | PERF_PAPC_PASX_REQ_STALLED = 0x4f, | ||
| 1269 | PERF_PAPC_PASX_REC_IDLE = 0x50, | ||
| 1270 | PERF_PAPC_PASX_REC_BUSY = 0x51, | ||
| 1271 | PERF_PAPC_PASX_REC_STARVED_SX = 0x52, | ||
| 1272 | PERF_PAPC_PASX_REC_STALLED = 0x53, | ||
| 1273 | PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, | ||
| 1274 | PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, | ||
| 1275 | PERF_PAPC_CCGSM_IDLE = 0x56, | ||
| 1276 | PERF_PAPC_CCGSM_BUSY = 0x57, | ||
| 1277 | PERF_PAPC_CCGSM_STALLED = 0x58, | ||
| 1278 | PERF_PAPC_CLPRIM_IDLE = 0x59, | ||
| 1279 | PERF_PAPC_CLPRIM_BUSY = 0x5a, | ||
| 1280 | PERF_PAPC_CLPRIM_STALLED = 0x5b, | ||
| 1281 | PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, | ||
| 1282 | PERF_PAPC_CLIPSM_IDLE = 0x5d, | ||
| 1283 | PERF_PAPC_CLIPSM_BUSY = 0x5e, | ||
| 1284 | PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, | ||
| 1285 | PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, | ||
| 1286 | PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, | ||
| 1287 | PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, | ||
| 1288 | PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, | ||
| 1289 | PERF_PAPC_CLIPGA_IDLE = 0x64, | ||
| 1290 | PERF_PAPC_CLIPGA_BUSY = 0x65, | ||
| 1291 | PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, | ||
| 1292 | PERF_PAPC_CLIPGA_STALLED = 0x67, | ||
| 1293 | PERF_PAPC_CLIP_IDLE = 0x68, | ||
| 1294 | PERF_PAPC_CLIP_BUSY = 0x69, | ||
| 1295 | PERF_PAPC_SU_IDLE = 0x6a, | ||
| 1296 | PERF_PAPC_SU_BUSY = 0x6b, | ||
| 1297 | PERF_PAPC_SU_STARVED_CLIP = 0x6c, | ||
| 1298 | PERF_PAPC_SU_STALLED_SC = 0x6d, | ||
| 1299 | PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, | ||
| 1300 | PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, | ||
| 1301 | PERF_PAPC_PA_REG_SCLK_VLD = 0x70, | ||
| 1302 | PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, | ||
| 1303 | PERF_PAPC_PASX_SE0_REQ = 0x72, | ||
| 1304 | PERF_PAPC_PASX_SE1_REQ = 0x73, | ||
| 1305 | PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, | ||
| 1306 | PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, | ||
| 1307 | PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, | ||
| 1308 | PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, | ||
| 1309 | PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, | ||
| 1310 | PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, | ||
| 1311 | PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, | ||
| 1312 | PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, | ||
| 1313 | PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, | ||
| 1314 | PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, | ||
| 1315 | PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, | ||
| 1316 | PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, | ||
| 1317 | PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, | ||
| 1318 | PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, | ||
| 1319 | PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, | ||
| 1320 | PERF_PAPC_SU_SE0_STALLED_SC = 0x83, | ||
| 1321 | PERF_PAPC_SU_SE1_STALLED_SC = 0x84, | ||
| 1322 | PERF_PAPC_SU_SE01_STALLED_SC = 0x85, | ||
| 1323 | PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, | ||
| 1324 | PERF_PAPC_SU_CULLED_PRIM = 0x87, | ||
| 1325 | PERF_PAPC_SU_OUTPUT_EOPG = 0x88, | ||
| 1326 | PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, | ||
| 1327 | PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, | ||
| 1328 | PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, | ||
| 1329 | PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, | ||
| 1330 | PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, | ||
| 1331 | PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, | ||
| 1332 | PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, | ||
| 1333 | PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, | ||
| 1334 | PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, | ||
| 1335 | PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, | ||
| 1336 | PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, | ||
| 1337 | PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, | ||
| 1338 | PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, | ||
| 1339 | PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, | ||
| 1340 | PERF_PAPC_SU_SE2_STALLED_SC = 0x97, | ||
| 1341 | PERF_PAPC_SU_SE3_STALLED_SC = 0x98, | ||
| 1342 | } SU_PERFCNT_SEL; | ||
| 1343 | typedef enum SC_PERFCNT_SEL { | ||
| 1344 | SC_SRPS_WINDOW_VALID = 0x0, | ||
| 1345 | SC_PSSW_WINDOW_VALID = 0x1, | ||
| 1346 | SC_TPQZ_WINDOW_VALID = 0x2, | ||
| 1347 | SC_QZQP_WINDOW_VALID = 0x3, | ||
| 1348 | SC_TRPK_WINDOW_VALID = 0x4, | ||
| 1349 | SC_SRPS_WINDOW_VALID_BUSY = 0x5, | ||
| 1350 | SC_PSSW_WINDOW_VALID_BUSY = 0x6, | ||
| 1351 | SC_TPQZ_WINDOW_VALID_BUSY = 0x7, | ||
| 1352 | SC_QZQP_WINDOW_VALID_BUSY = 0x8, | ||
| 1353 | SC_TRPK_WINDOW_VALID_BUSY = 0x9, | ||
| 1354 | SC_STARVED_BY_PA = 0xa, | ||
| 1355 | SC_STALLED_BY_PRIMFIFO = 0xb, | ||
| 1356 | SC_STALLED_BY_DB_TILE = 0xc, | ||
| 1357 | SC_STARVED_BY_DB_TILE = 0xd, | ||
| 1358 | SC_STALLED_BY_TILEORDERFIFO = 0xe, | ||
| 1359 | SC_STALLED_BY_TILEFIFO = 0xf, | ||
| 1360 | SC_STALLED_BY_DB_QUAD = 0x10, | ||
| 1361 | SC_STARVED_BY_DB_QUAD = 0x11, | ||
| 1362 | SC_STALLED_BY_QUADFIFO = 0x12, | ||
| 1363 | SC_STALLED_BY_BCI = 0x13, | ||
| 1364 | SC_STALLED_BY_SPI = 0x14, | ||
| 1365 | SC_SCISSOR_DISCARD = 0x15, | ||
| 1366 | SC_BB_DISCARD = 0x16, | ||
| 1367 | SC_SUPERTILE_COUNT = 0x17, | ||
| 1368 | SC_SUPERTILE_PER_PRIM_H0 = 0x18, | ||
| 1369 | SC_SUPERTILE_PER_PRIM_H1 = 0x19, | ||
| 1370 | SC_SUPERTILE_PER_PRIM_H2 = 0x1a, | ||
| 1371 | SC_SUPERTILE_PER_PRIM_H3 = 0x1b, | ||
| 1372 | SC_SUPERTILE_PER_PRIM_H4 = 0x1c, | ||
| 1373 | SC_SUPERTILE_PER_PRIM_H5 = 0x1d, | ||
| 1374 | SC_SUPERTILE_PER_PRIM_H6 = 0x1e, | ||
| 1375 | SC_SUPERTILE_PER_PRIM_H7 = 0x1f, | ||
| 1376 | SC_SUPERTILE_PER_PRIM_H8 = 0x20, | ||
| 1377 | SC_SUPERTILE_PER_PRIM_H9 = 0x21, | ||
| 1378 | SC_SUPERTILE_PER_PRIM_H10 = 0x22, | ||
| 1379 | SC_SUPERTILE_PER_PRIM_H11 = 0x23, | ||
| 1380 | SC_SUPERTILE_PER_PRIM_H12 = 0x24, | ||
| 1381 | SC_SUPERTILE_PER_PRIM_H13 = 0x25, | ||
| 1382 | SC_SUPERTILE_PER_PRIM_H14 = 0x26, | ||
| 1383 | SC_SUPERTILE_PER_PRIM_H15 = 0x27, | ||
| 1384 | SC_SUPERTILE_PER_PRIM_H16 = 0x28, | ||
| 1385 | SC_TILE_PER_PRIM_H0 = 0x29, | ||
| 1386 | SC_TILE_PER_PRIM_H1 = 0x2a, | ||
| 1387 | SC_TILE_PER_PRIM_H2 = 0x2b, | ||
| 1388 | SC_TILE_PER_PRIM_H3 = 0x2c, | ||
| 1389 | SC_TILE_PER_PRIM_H4 = 0x2d, | ||
| 1390 | SC_TILE_PER_PRIM_H5 = 0x2e, | ||
| 1391 | SC_TILE_PER_PRIM_H6 = 0x2f, | ||
| 1392 | SC_TILE_PER_PRIM_H7 = 0x30, | ||
| 1393 | SC_TILE_PER_PRIM_H8 = 0x31, | ||
| 1394 | SC_TILE_PER_PRIM_H9 = 0x32, | ||
| 1395 | SC_TILE_PER_PRIM_H10 = 0x33, | ||
| 1396 | SC_TILE_PER_PRIM_H11 = 0x34, | ||
| 1397 | SC_TILE_PER_PRIM_H12 = 0x35, | ||
| 1398 | SC_TILE_PER_PRIM_H13 = 0x36, | ||
| 1399 | SC_TILE_PER_PRIM_H14 = 0x37, | ||
| 1400 | SC_TILE_PER_PRIM_H15 = 0x38, | ||
| 1401 | SC_TILE_PER_PRIM_H16 = 0x39, | ||
| 1402 | SC_TILE_PER_SUPERTILE_H0 = 0x3a, | ||
| 1403 | SC_TILE_PER_SUPERTILE_H1 = 0x3b, | ||
| 1404 | SC_TILE_PER_SUPERTILE_H2 = 0x3c, | ||
| 1405 | SC_TILE_PER_SUPERTILE_H3 = 0x3d, | ||
| 1406 | SC_TILE_PER_SUPERTILE_H4 = 0x3e, | ||
| 1407 | SC_TILE_PER_SUPERTILE_H5 = 0x3f, | ||
| 1408 | SC_TILE_PER_SUPERTILE_H6 = 0x40, | ||
| 1409 | SC_TILE_PER_SUPERTILE_H7 = 0x41, | ||
| 1410 | SC_TILE_PER_SUPERTILE_H8 = 0x42, | ||
| 1411 | SC_TILE_PER_SUPERTILE_H9 = 0x43, | ||
| 1412 | SC_TILE_PER_SUPERTILE_H10 = 0x44, | ||
| 1413 | SC_TILE_PER_SUPERTILE_H11 = 0x45, | ||
| 1414 | SC_TILE_PER_SUPERTILE_H12 = 0x46, | ||
| 1415 | SC_TILE_PER_SUPERTILE_H13 = 0x47, | ||
| 1416 | SC_TILE_PER_SUPERTILE_H14 = 0x48, | ||
| 1417 | SC_TILE_PER_SUPERTILE_H15 = 0x49, | ||
| 1418 | SC_TILE_PER_SUPERTILE_H16 = 0x4a, | ||
| 1419 | SC_TILE_PICKED_H1 = 0x4b, | ||
| 1420 | SC_TILE_PICKED_H2 = 0x4c, | ||
| 1421 | SC_TILE_PICKED_H3 = 0x4d, | ||
| 1422 | SC_TILE_PICKED_H4 = 0x4e, | ||
| 1423 | SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, | ||
| 1424 | SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, | ||
| 1425 | SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, | ||
| 1426 | SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, | ||
| 1427 | SC_QZ0_TILE_COUNT = 0x53, | ||
| 1428 | SC_QZ1_TILE_COUNT = 0x54, | ||
| 1429 | SC_QZ2_TILE_COUNT = 0x55, | ||
| 1430 | SC_QZ3_TILE_COUNT = 0x56, | ||
| 1431 | SC_QZ0_TILE_COVERED_COUNT = 0x57, | ||
| 1432 | SC_QZ1_TILE_COVERED_COUNT = 0x58, | ||
| 1433 | SC_QZ2_TILE_COVERED_COUNT = 0x59, | ||
| 1434 | SC_QZ3_TILE_COVERED_COUNT = 0x5a, | ||
| 1435 | SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, | ||
| 1436 | SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, | ||
| 1437 | SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, | ||
| 1438 | SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, | ||
| 1439 | SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, | ||
| 1440 | SC_QZ0_QUAD_PER_TILE_H1 = 0x60, | ||
| 1441 | SC_QZ0_QUAD_PER_TILE_H2 = 0x61, | ||
| 1442 | SC_QZ0_QUAD_PER_TILE_H3 = 0x62, | ||
| 1443 | SC_QZ0_QUAD_PER_TILE_H4 = 0x63, | ||
| 1444 | SC_QZ0_QUAD_PER_TILE_H5 = 0x64, | ||
| 1445 | SC_QZ0_QUAD_PER_TILE_H6 = 0x65, | ||
| 1446 | SC_QZ0_QUAD_PER_TILE_H7 = 0x66, | ||
| 1447 | SC_QZ0_QUAD_PER_TILE_H8 = 0x67, | ||
| 1448 | SC_QZ0_QUAD_PER_TILE_H9 = 0x68, | ||
| 1449 | SC_QZ0_QUAD_PER_TILE_H10 = 0x69, | ||
| 1450 | SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, | ||
| 1451 | SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, | ||
| 1452 | SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, | ||
| 1453 | SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, | ||
| 1454 | SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, | ||
| 1455 | SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, | ||
| 1456 | SC_QZ1_QUAD_PER_TILE_H0 = 0x70, | ||
| 1457 | SC_QZ1_QUAD_PER_TILE_H1 = 0x71, | ||
| 1458 | SC_QZ1_QUAD_PER_TILE_H2 = 0x72, | ||
| 1459 | SC_QZ1_QUAD_PER_TILE_H3 = 0x73, | ||
| 1460 | SC_QZ1_QUAD_PER_TILE_H4 = 0x74, | ||
| 1461 | SC_QZ1_QUAD_PER_TILE_H5 = 0x75, | ||
| 1462 | SC_QZ1_QUAD_PER_TILE_H6 = 0x76, | ||
| 1463 | SC_QZ1_QUAD_PER_TILE_H7 = 0x77, | ||
| 1464 | SC_QZ1_QUAD_PER_TILE_H8 = 0x78, | ||
| 1465 | SC_QZ1_QUAD_PER_TILE_H9 = 0x79, | ||
| 1466 | SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, | ||
| 1467 | SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, | ||
| 1468 | SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, | ||
| 1469 | SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, | ||
| 1470 | SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, | ||
| 1471 | SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, | ||
| 1472 | SC_QZ1_QUAD_PER_TILE_H16 = 0x80, | ||
| 1473 | SC_QZ2_QUAD_PER_TILE_H0 = 0x81, | ||
| 1474 | SC_QZ2_QUAD_PER_TILE_H1 = 0x82, | ||
| 1475 | SC_QZ2_QUAD_PER_TILE_H2 = 0x83, | ||
| 1476 | SC_QZ2_QUAD_PER_TILE_H3 = 0x84, | ||
| 1477 | SC_QZ2_QUAD_PER_TILE_H4 = 0x85, | ||
| 1478 | SC_QZ2_QUAD_PER_TILE_H5 = 0x86, | ||
| 1479 | SC_QZ2_QUAD_PER_TILE_H6 = 0x87, | ||
| 1480 | SC_QZ2_QUAD_PER_TILE_H7 = 0x88, | ||
| 1481 | SC_QZ2_QUAD_PER_TILE_H8 = 0x89, | ||
| 1482 | SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, | ||
| 1483 | SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, | ||
| 1484 | SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, | ||
| 1485 | SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, | ||
| 1486 | SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, | ||
| 1487 | SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, | ||
| 1488 | SC_QZ2_QUAD_PER_TILE_H15 = 0x90, | ||
| 1489 | SC_QZ2_QUAD_PER_TILE_H16 = 0x91, | ||
| 1490 | SC_QZ3_QUAD_PER_TILE_H0 = 0x92, | ||
| 1491 | SC_QZ3_QUAD_PER_TILE_H1 = 0x93, | ||
| 1492 | SC_QZ3_QUAD_PER_TILE_H2 = 0x94, | ||
| 1493 | SC_QZ3_QUAD_PER_TILE_H3 = 0x95, | ||
| 1494 | SC_QZ3_QUAD_PER_TILE_H4 = 0x96, | ||
| 1495 | SC_QZ3_QUAD_PER_TILE_H5 = 0x97, | ||
| 1496 | SC_QZ3_QUAD_PER_TILE_H6 = 0x98, | ||
| 1497 | SC_QZ3_QUAD_PER_TILE_H7 = 0x99, | ||
| 1498 | SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, | ||
| 1499 | SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, | ||
| 1500 | SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, | ||
| 1501 | SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, | ||
| 1502 | SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, | ||
| 1503 | SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, | ||
| 1504 | SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, | ||
| 1505 | SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, | ||
| 1506 | SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, | ||
| 1507 | SC_QZ0_QUAD_COUNT = 0xa3, | ||
| 1508 | SC_QZ1_QUAD_COUNT = 0xa4, | ||
| 1509 | SC_QZ2_QUAD_COUNT = 0xa5, | ||
| 1510 | SC_QZ3_QUAD_COUNT = 0xa6, | ||
| 1511 | SC_P0_HIZ_TILE_COUNT = 0xa7, | ||
| 1512 | SC_P1_HIZ_TILE_COUNT = 0xa8, | ||
| 1513 | SC_P2_HIZ_TILE_COUNT = 0xa9, | ||
| 1514 | SC_P3_HIZ_TILE_COUNT = 0xaa, | ||
| 1515 | SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, | ||
| 1516 | SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, | ||
| 1517 | SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, | ||
| 1518 | SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, | ||
| 1519 | SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, | ||
| 1520 | SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, | ||
| 1521 | SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, | ||
| 1522 | SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, | ||
| 1523 | SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, | ||
| 1524 | SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, | ||
| 1525 | SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, | ||
| 1526 | SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, | ||
| 1527 | SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, | ||
| 1528 | SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, | ||
| 1529 | SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, | ||
| 1530 | SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, | ||
| 1531 | SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, | ||
| 1532 | SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, | ||
| 1533 | SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, | ||
| 1534 | SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, | ||
| 1535 | SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, | ||
| 1536 | SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, | ||
| 1537 | SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, | ||
| 1538 | SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, | ||
| 1539 | SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, | ||
| 1540 | SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, | ||
| 1541 | SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, | ||
| 1542 | SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, | ||
| 1543 | SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, | ||
| 1544 | SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, | ||
| 1545 | SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, | ||
| 1546 | SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, | ||
| 1547 | SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, | ||
| 1548 | SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, | ||
| 1549 | SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, | ||
| 1550 | SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, | ||
| 1551 | SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, | ||
| 1552 | SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, | ||
| 1553 | SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, | ||
| 1554 | SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, | ||
| 1555 | SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, | ||
| 1556 | SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, | ||
| 1557 | SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, | ||
| 1558 | SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, | ||
| 1559 | SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, | ||
| 1560 | SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, | ||
| 1561 | SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, | ||
| 1562 | SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, | ||
| 1563 | SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, | ||
| 1564 | SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, | ||
| 1565 | SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, | ||
| 1566 | SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, | ||
| 1567 | SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, | ||
| 1568 | SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, | ||
| 1569 | SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, | ||
| 1570 | SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, | ||
| 1571 | SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, | ||
| 1572 | SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, | ||
| 1573 | SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, | ||
| 1574 | SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, | ||
| 1575 | SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, | ||
| 1576 | SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, | ||
| 1577 | SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, | ||
| 1578 | SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, | ||
| 1579 | SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, | ||
| 1580 | SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, | ||
| 1581 | SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, | ||
| 1582 | SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, | ||
| 1583 | SC_P0_HIZ_QUAD_COUNT = 0xef, | ||
| 1584 | SC_P1_HIZ_QUAD_COUNT = 0xf0, | ||
| 1585 | SC_P2_HIZ_QUAD_COUNT = 0xf1, | ||
| 1586 | SC_P3_HIZ_QUAD_COUNT = 0xf2, | ||
| 1587 | SC_P0_DETAIL_QUAD_COUNT = 0xf3, | ||
| 1588 | SC_P1_DETAIL_QUAD_COUNT = 0xf4, | ||
| 1589 | SC_P2_DETAIL_QUAD_COUNT = 0xf5, | ||
| 1590 | SC_P3_DETAIL_QUAD_COUNT = 0xf6, | ||
| 1591 | SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, | ||
| 1592 | SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, | ||
| 1593 | SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, | ||
| 1594 | SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, | ||
| 1595 | SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, | ||
| 1596 | SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, | ||
| 1597 | SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, | ||
| 1598 | SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, | ||
| 1599 | SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, | ||
| 1600 | SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, | ||
| 1601 | SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, | ||
| 1602 | SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, | ||
| 1603 | SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, | ||
| 1604 | SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, | ||
| 1605 | SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, | ||
| 1606 | SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, | ||
| 1607 | SC_EARLYZ_QUAD_COUNT = 0x107, | ||
| 1608 | SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, | ||
| 1609 | SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, | ||
| 1610 | SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, | ||
| 1611 | SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, | ||
| 1612 | SC_PKR_QUAD_PER_ROW_H1 = 0x10c, | ||
| 1613 | SC_PKR_QUAD_PER_ROW_H2 = 0x10d, | ||
| 1614 | SC_PKR_4X2_QUAD_SPLIT = 0x10e, | ||
| 1615 | SC_PKR_4X2_FILL_QUAD = 0x10f, | ||
| 1616 | SC_PKR_END_OF_VECTOR = 0x110, | ||
| 1617 | SC_PKR_CONTROL_XFER = 0x111, | ||
| 1618 | SC_PKR_DBHANG_FORCE_EOV = 0x112, | ||
| 1619 | SC_REG_SCLK_BUSY = 0x113, | ||
| 1620 | SC_GRP0_DYN_SCLK_BUSY = 0x114, | ||
| 1621 | SC_GRP1_DYN_SCLK_BUSY = 0x115, | ||
| 1622 | SC_GRP2_DYN_SCLK_BUSY = 0x116, | ||
| 1623 | SC_GRP3_DYN_SCLK_BUSY = 0x117, | ||
| 1624 | SC_GRP4_DYN_SCLK_BUSY = 0x118, | ||
| 1625 | SC_PA0_SC_DATA_FIFO_RD = 0x119, | ||
| 1626 | SC_PA0_SC_DATA_FIFO_WE = 0x11a, | ||
| 1627 | SC_PA1_SC_DATA_FIFO_RD = 0x11b, | ||
| 1628 | SC_PA1_SC_DATA_FIFO_WE = 0x11c, | ||
| 1629 | SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, | ||
| 1630 | SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, | ||
| 1631 | SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, | ||
| 1632 | SC_PS_ARB_STALLED_FROM_BELOW = 0x120, | ||
| 1633 | SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, | ||
| 1634 | SC_PS_ARB_SC_BUSY = 0x122, | ||
| 1635 | SC_PS_ARB_PA_SC_BUSY = 0x123, | ||
| 1636 | SC_PA2_SC_DATA_FIFO_RD = 0x124, | ||
| 1637 | SC_PA2_SC_DATA_FIFO_WE = 0x125, | ||
| 1638 | SC_PA3_SC_DATA_FIFO_RD = 0x126, | ||
| 1639 | SC_PA3_SC_DATA_FIFO_WE = 0x127, | ||
| 1640 | SC_PA_SC_DEALLOC_0_0_WE = 0x128, | ||
| 1641 | SC_PA_SC_DEALLOC_0_1_WE = 0x129, | ||
| 1642 | SC_PA_SC_DEALLOC_1_0_WE = 0x12a, | ||
| 1643 | SC_PA_SC_DEALLOC_1_1_WE = 0x12b, | ||
| 1644 | SC_PA_SC_DEALLOC_2_0_WE = 0x12c, | ||
| 1645 | SC_PA_SC_DEALLOC_2_1_WE = 0x12d, | ||
| 1646 | SC_PA_SC_DEALLOC_3_0_WE = 0x12e, | ||
| 1647 | SC_PA_SC_DEALLOC_3_1_WE = 0x12f, | ||
| 1648 | SC_PA0_SC_EOP_WE = 0x130, | ||
| 1649 | SC_PA0_SC_EOPG_WE = 0x131, | ||
| 1650 | SC_PA0_SC_EVENT_WE = 0x132, | ||
| 1651 | SC_PA1_SC_EOP_WE = 0x133, | ||
| 1652 | SC_PA1_SC_EOPG_WE = 0x134, | ||
| 1653 | SC_PA1_SC_EVENT_WE = 0x135, | ||
| 1654 | SC_PA2_SC_EOP_WE = 0x136, | ||
| 1655 | SC_PA2_SC_EOPG_WE = 0x137, | ||
| 1656 | SC_PA2_SC_EVENT_WE = 0x138, | ||
| 1657 | SC_PA3_SC_EOP_WE = 0x139, | ||
| 1658 | SC_PA3_SC_EOPG_WE = 0x13a, | ||
| 1659 | SC_PA3_SC_EVENT_WE = 0x13b, | ||
| 1660 | SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, | ||
| 1661 | SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, | ||
| 1662 | SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, | ||
| 1663 | SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, | ||
| 1664 | SC_PS_ARB_EVENT_SYNC_POP = 0x140, | ||
| 1665 | SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, | ||
| 1666 | SC_PA0_SC_FPOV_WE = 0x142, | ||
| 1667 | SC_PA1_SC_FPOV_WE = 0x143, | ||
| 1668 | SC_PA2_SC_FPOV_WE = 0x144, | ||
| 1669 | SC_PA3_SC_FPOV_WE = 0x145, | ||
| 1670 | SC_PA0_SC_LPOV_WE = 0x146, | ||
| 1671 | SC_PA1_SC_LPOV_WE = 0x147, | ||
| 1672 | SC_PA2_SC_LPOV_WE = 0x148, | ||
| 1673 | SC_PA3_SC_LPOV_WE = 0x149, | ||
| 1674 | SC_SC_SPI_DEALLOC_0_0 = 0x14a, | ||
| 1675 | SC_SC_SPI_DEALLOC_0_1 = 0x14b, | ||
| 1676 | SC_SC_SPI_DEALLOC_0_2 = 0x14c, | ||
| 1677 | SC_SC_SPI_DEALLOC_1_0 = 0x14d, | ||
| 1678 | SC_SC_SPI_DEALLOC_1_1 = 0x14e, | ||
| 1679 | SC_SC_SPI_DEALLOC_1_2 = 0x14f, | ||
| 1680 | SC_SC_SPI_DEALLOC_2_0 = 0x150, | ||
| 1681 | SC_SC_SPI_DEALLOC_2_1 = 0x151, | ||
| 1682 | SC_SC_SPI_DEALLOC_2_2 = 0x152, | ||
| 1683 | SC_SC_SPI_DEALLOC_3_0 = 0x153, | ||
| 1684 | SC_SC_SPI_DEALLOC_3_1 = 0x154, | ||
| 1685 | SC_SC_SPI_DEALLOC_3_2 = 0x155, | ||
| 1686 | SC_SC_SPI_FPOV_0 = 0x156, | ||
| 1687 | SC_SC_SPI_FPOV_1 = 0x157, | ||
| 1688 | SC_SC_SPI_FPOV_2 = 0x158, | ||
| 1689 | SC_SC_SPI_FPOV_3 = 0x159, | ||
| 1690 | SC_SC_SPI_EVENT = 0x15a, | ||
| 1691 | SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, | ||
| 1692 | SC_PS_TS_EVENT_FIFO_POP = 0x15c, | ||
| 1693 | SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, | ||
| 1694 | SC_PS_CTX_DONE_FIFO_POP = 0x15e, | ||
| 1695 | SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, | ||
| 1696 | SC_EOP_SYNC_WINDOW = 0x160, | ||
| 1697 | SC_PA0_SC_NULL_WE = 0x161, | ||
| 1698 | SC_PA0_SC_NULL_DEALLOC_WE = 0x162, | ||
| 1699 | SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, | ||
| 1700 | SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, | ||
| 1701 | SC_PA0_SC_DEALLOC_0_RD = 0x165, | ||
| 1702 | SC_PA0_SC_DEALLOC_1_RD = 0x166, | ||
| 1703 | SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, | ||
| 1704 | SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, | ||
| 1705 | SC_PA1_SC_DEALLOC_0_RD = 0x169, | ||
| 1706 | SC_PA1_SC_DEALLOC_1_RD = 0x16a, | ||
| 1707 | SC_PA1_SC_NULL_WE = 0x16b, | ||
| 1708 | SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, | ||
| 1709 | SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, | ||
| 1710 | SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, | ||
| 1711 | SC_PA2_SC_DEALLOC_0_RD = 0x16f, | ||
| 1712 | SC_PA2_SC_DEALLOC_1_RD = 0x170, | ||
| 1713 | SC_PA2_SC_NULL_WE = 0x171, | ||
| 1714 | SC_PA2_SC_NULL_DEALLOC_WE = 0x172, | ||
| 1715 | SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, | ||
| 1716 | SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, | ||
| 1717 | SC_PA3_SC_DEALLOC_0_RD = 0x175, | ||
| 1718 | SC_PA3_SC_DEALLOC_1_RD = 0x176, | ||
| 1719 | SC_PA3_SC_NULL_WE = 0x177, | ||
| 1720 | SC_PA3_SC_NULL_DEALLOC_WE = 0x178, | ||
| 1721 | SC_PS_PA0_SC_FIFO_EMPTY = 0x179, | ||
| 1722 | SC_PS_PA0_SC_FIFO_FULL = 0x17a, | ||
| 1723 | SC_PA0_PS_DATA_SEND = 0x17b, | ||
| 1724 | SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, | ||
| 1725 | SC_PS_PA1_SC_FIFO_FULL = 0x17d, | ||
| 1726 | SC_PA1_PS_DATA_SEND = 0x17e, | ||
| 1727 | SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, | ||
| 1728 | SC_PS_PA2_SC_FIFO_FULL = 0x180, | ||
| 1729 | SC_PA2_PS_DATA_SEND = 0x181, | ||
| 1730 | SC_PS_PA3_SC_FIFO_EMPTY = 0x182, | ||
| 1731 | SC_PS_PA3_SC_FIFO_FULL = 0x183, | ||
| 1732 | SC_PA3_PS_DATA_SEND = 0x184, | ||
| 1733 | SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, | ||
| 1734 | SC_BUSY_CNT_NOT_ZERO = 0x186, | ||
| 1735 | SC_BM_BUSY = 0x187, | ||
| 1736 | SC_BACKEND_BUSY = 0x188, | ||
| 1737 | SC_SCF_SCB_INTERFACE_BUSY = 0x189, | ||
| 1738 | SC_SCB_BUSY = 0x18a, | ||
| 1739 | SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b, | ||
| 1740 | SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c, | ||
| 1741 | } SC_PERFCNT_SEL; | ||
| 1742 | typedef enum SePairXsel { | ||
| 1743 | RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, | ||
| 1744 | RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, | ||
| 1745 | RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, | ||
| 1746 | RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, | ||
| 1747 | } SePairXsel; | ||
| 1748 | typedef enum SePairYsel { | ||
| 1749 | RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, | ||
| 1750 | RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, | ||
| 1751 | RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, | ||
| 1752 | RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, | ||
| 1753 | } SePairYsel; | ||
| 1754 | typedef enum SePairMap { | ||
| 1755 | RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, | ||
| 1756 | RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, | ||
| 1757 | RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, | ||
| 1758 | RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, | ||
| 1759 | } SePairMap; | ||
| 1760 | typedef enum SeXsel { | ||
| 1761 | RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, | ||
| 1762 | RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, | ||
| 1763 | RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, | ||
| 1764 | RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, | ||
| 1765 | } SeXsel; | ||
| 1766 | typedef enum SeYsel { | ||
| 1767 | RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, | ||
| 1768 | RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, | ||
| 1769 | RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, | ||
| 1770 | RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, | ||
| 1771 | } SeYsel; | ||
| 1772 | typedef enum SeMap { | ||
| 1773 | RASTER_CONFIG_SE_MAP_0 = 0x0, | ||
| 1774 | RASTER_CONFIG_SE_MAP_1 = 0x1, | ||
| 1775 | RASTER_CONFIG_SE_MAP_2 = 0x2, | ||
| 1776 | RASTER_CONFIG_SE_MAP_3 = 0x3, | ||
| 1777 | } SeMap; | ||
| 1778 | typedef enum ScXsel { | ||
| 1779 | RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, | ||
| 1780 | RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, | ||
| 1781 | RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, | ||
| 1782 | RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, | ||
| 1783 | } ScXsel; | ||
| 1784 | typedef enum ScYsel { | ||
| 1785 | RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, | ||
| 1786 | RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, | ||
| 1787 | RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, | ||
| 1788 | RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, | ||
| 1789 | } ScYsel; | ||
| 1790 | typedef enum ScMap { | ||
| 1791 | RASTER_CONFIG_SC_MAP_0 = 0x0, | ||
| 1792 | RASTER_CONFIG_SC_MAP_1 = 0x1, | ||
| 1793 | RASTER_CONFIG_SC_MAP_2 = 0x2, | ||
| 1794 | RASTER_CONFIG_SC_MAP_3 = 0x3, | ||
| 1795 | } ScMap; | ||
| 1796 | typedef enum PkrXsel2 { | ||
| 1797 | RASTER_CONFIG_PKR_XSEL2_0 = 0x0, | ||
| 1798 | RASTER_CONFIG_PKR_XSEL2_1 = 0x1, | ||
| 1799 | RASTER_CONFIG_PKR_XSEL2_2 = 0x2, | ||
| 1800 | RASTER_CONFIG_PKR_XSEL2_3 = 0x3, | ||
| 1801 | } PkrXsel2; | ||
| 1802 | typedef enum PkrXsel { | ||
| 1803 | RASTER_CONFIG_PKR_XSEL_0 = 0x0, | ||
| 1804 | RASTER_CONFIG_PKR_XSEL_1 = 0x1, | ||
| 1805 | RASTER_CONFIG_PKR_XSEL_2 = 0x2, | ||
| 1806 | RASTER_CONFIG_PKR_XSEL_3 = 0x3, | ||
| 1807 | } PkrXsel; | ||
| 1808 | typedef enum PkrYsel { | ||
| 1809 | RASTER_CONFIG_PKR_YSEL_0 = 0x0, | ||
| 1810 | RASTER_CONFIG_PKR_YSEL_1 = 0x1, | ||
| 1811 | RASTER_CONFIG_PKR_YSEL_2 = 0x2, | ||
| 1812 | RASTER_CONFIG_PKR_YSEL_3 = 0x3, | ||
| 1813 | } PkrYsel; | ||
| 1814 | typedef enum PkrMap { | ||
| 1815 | RASTER_CONFIG_PKR_MAP_0 = 0x0, | ||
| 1816 | RASTER_CONFIG_PKR_MAP_1 = 0x1, | ||
| 1817 | RASTER_CONFIG_PKR_MAP_2 = 0x2, | ||
| 1818 | RASTER_CONFIG_PKR_MAP_3 = 0x3, | ||
| 1819 | } PkrMap; | ||
| 1820 | typedef enum RbXsel { | ||
| 1821 | RASTER_CONFIG_RB_XSEL_0 = 0x0, | ||
| 1822 | RASTER_CONFIG_RB_XSEL_1 = 0x1, | ||
| 1823 | } RbXsel; | ||
| 1824 | typedef enum RbYsel { | ||
| 1825 | RASTER_CONFIG_RB_YSEL_0 = 0x0, | ||
| 1826 | RASTER_CONFIG_RB_YSEL_1 = 0x1, | ||
| 1827 | } RbYsel; | ||
| 1828 | typedef enum RbXsel2 { | ||
| 1829 | RASTER_CONFIG_RB_XSEL2_0 = 0x0, | ||
| 1830 | RASTER_CONFIG_RB_XSEL2_1 = 0x1, | ||
| 1831 | RASTER_CONFIG_RB_XSEL2_2 = 0x2, | ||
| 1832 | RASTER_CONFIG_RB_XSEL2_3 = 0x3, | ||
| 1833 | } RbXsel2; | ||
| 1834 | typedef enum RbMap { | ||
| 1835 | RASTER_CONFIG_RB_MAP_0 = 0x0, | ||
| 1836 | RASTER_CONFIG_RB_MAP_1 = 0x1, | ||
| 1837 | RASTER_CONFIG_RB_MAP_2 = 0x2, | ||
| 1838 | RASTER_CONFIG_RB_MAP_3 = 0x3, | ||
| 1839 | } RbMap; | ||
| 1840 | typedef enum CSDATA_TYPE { | ||
| 1841 | CSDATA_TYPE_TG = 0x0, | ||
| 1842 | CSDATA_TYPE_STATE = 0x1, | ||
| 1843 | CSDATA_TYPE_EVENT = 0x2, | ||
| 1844 | CSDATA_TYPE_PRIVATE = 0x3, | ||
| 1845 | } CSDATA_TYPE; | ||
| 1846 | #define CSDATA_TYPE_WIDTH 0x2 | ||
| 1847 | #define CSDATA_ADDR_WIDTH 0x7 | ||
| 1848 | #define CSDATA_DATA_WIDTH 0x20 | ||
| 1849 | typedef enum SPI_SAMPLE_CNTL { | ||
| 1850 | CENTROIDS_ONLY = 0x0, | ||
| 1851 | CENTERS_ONLY = 0x1, | ||
| 1852 | CENTROIDS_AND_CENTERS = 0x2, | ||
| 1853 | UNDEF = 0x3, | ||
| 1854 | } SPI_SAMPLE_CNTL; | ||
| 1855 | typedef enum SPI_FOG_MODE { | ||
| 1856 | SPI_FOG_NONE = 0x0, | ||
| 1857 | SPI_FOG_EXP = 0x1, | ||
| 1858 | SPI_FOG_EXP2 = 0x2, | ||
| 1859 | SPI_FOG_LINEAR = 0x3, | ||
| 1860 | } SPI_FOG_MODE; | ||
| 1861 | typedef enum SPI_PNT_SPRITE_OVERRIDE { | ||
| 1862 | SPI_PNT_SPRITE_SEL_0 = 0x0, | ||
| 1863 | SPI_PNT_SPRITE_SEL_1 = 0x1, | ||
| 1864 | SPI_PNT_SPRITE_SEL_S = 0x2, | ||
| 1865 | SPI_PNT_SPRITE_SEL_T = 0x3, | ||
| 1866 | SPI_PNT_SPRITE_SEL_NONE = 0x4, | ||
| 1867 | } SPI_PNT_SPRITE_OVERRIDE; | ||
| 1868 | typedef enum SPI_PERFCNT_SEL { | ||
| 1869 | SPI_PERF_VS_WINDOW_VALID = 0x0, | ||
| 1870 | SPI_PERF_VS_BUSY = 0x1, | ||
| 1871 | SPI_PERF_VS_FIRST_WAVE = 0x2, | ||
| 1872 | SPI_PERF_VS_LAST_WAVE = 0x3, | ||
| 1873 | SPI_PERF_VS_LSHS_DEALLOC = 0x4, | ||
| 1874 | SPI_PERF_VS_PC_STALL = 0x5, | ||
| 1875 | SPI_PERF_VS_POS0_STALL = 0x6, | ||
| 1876 | SPI_PERF_VS_POS1_STALL = 0x7, | ||
| 1877 | SPI_PERF_VS_CRAWLER_STALL = 0x8, | ||
| 1878 | SPI_PERF_VS_EVENT_WAVE = 0x9, | ||
| 1879 | SPI_PERF_VS_WAVE = 0xa, | ||
| 1880 | SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, | ||
| 1881 | SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, | ||
| 1882 | SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, | ||
| 1883 | SPI_PERF_VS_FIRST_SUBGRP = 0xe, | ||
| 1884 | SPI_PERF_VS_LAST_SUBGRP = 0xf, | ||
| 1885 | SPI_PERF_GS_WINDOW_VALID = 0x10, | ||
| 1886 | SPI_PERF_GS_BUSY = 0x11, | ||
| 1887 | SPI_PERF_GS_CRAWLER_STALL = 0x12, | ||
| 1888 | SPI_PERF_GS_EVENT_WAVE = 0x13, | ||
| 1889 | SPI_PERF_GS_WAVE = 0x14, | ||
| 1890 | SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, | ||
| 1891 | SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, | ||
| 1892 | SPI_PERF_GS_FIRST_SUBGRP = 0x17, | ||
| 1893 | SPI_PERF_GS_LAST_SUBGRP = 0x18, | ||
| 1894 | SPI_PERF_ES_WINDOW_VALID = 0x19, | ||
| 1895 | SPI_PERF_ES_BUSY = 0x1a, | ||
| 1896 | SPI_PERF_ES_CRAWLER_STALL = 0x1b, | ||
| 1897 | SPI_PERF_ES_FIRST_WAVE = 0x1c, | ||
| 1898 | SPI_PERF_ES_LAST_WAVE = 0x1d, | ||
| 1899 | SPI_PERF_ES_LSHS_DEALLOC = 0x1e, | ||
| 1900 | SPI_PERF_ES_EVENT_WAVE = 0x1f, | ||
| 1901 | SPI_PERF_ES_WAVE = 0x20, | ||
| 1902 | SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, | ||
| 1903 | SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, | ||
| 1904 | SPI_PERF_ES_FIRST_SUBGRP = 0x23, | ||
| 1905 | SPI_PERF_ES_LAST_SUBGRP = 0x24, | ||
| 1906 | SPI_PERF_HS_WINDOW_VALID = 0x25, | ||
| 1907 | SPI_PERF_HS_BUSY = 0x26, | ||
| 1908 | SPI_PERF_HS_CRAWLER_STALL = 0x27, | ||
| 1909 | SPI_PERF_HS_FIRST_WAVE = 0x28, | ||
| 1910 | SPI_PERF_HS_LAST_WAVE = 0x29, | ||
| 1911 | SPI_PERF_HS_LSHS_DEALLOC = 0x2a, | ||
| 1912 | SPI_PERF_HS_EVENT_WAVE = 0x2b, | ||
| 1913 | SPI_PERF_HS_WAVE = 0x2c, | ||
| 1914 | SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, | ||
| 1915 | SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, | ||
| 1916 | SPI_PERF_LS_WINDOW_VALID = 0x2f, | ||
| 1917 | SPI_PERF_LS_BUSY = 0x30, | ||
| 1918 | SPI_PERF_LS_CRAWLER_STALL = 0x31, | ||
| 1919 | SPI_PERF_LS_FIRST_WAVE = 0x32, | ||
| 1920 | SPI_PERF_LS_LAST_WAVE = 0x33, | ||
| 1921 | SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, | ||
| 1922 | SPI_PERF_LS_EVENT_WAVE = 0x35, | ||
| 1923 | SPI_PERF_LS_WAVE = 0x36, | ||
| 1924 | SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, | ||
| 1925 | SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, | ||
| 1926 | SPI_PERF_CSG_WINDOW_VALID = 0x39, | ||
| 1927 | SPI_PERF_CSG_BUSY = 0x3a, | ||
| 1928 | SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, | ||
| 1929 | SPI_PERF_CSG_CRAWLER_STALL = 0x3c, | ||
| 1930 | SPI_PERF_CSG_EVENT_WAVE = 0x3d, | ||
| 1931 | SPI_PERF_CSG_WAVE = 0x3e, | ||
| 1932 | SPI_PERF_CSN_WINDOW_VALID = 0x3f, | ||
| 1933 | SPI_PERF_CSN_BUSY = 0x40, | ||
| 1934 | SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, | ||
| 1935 | SPI_PERF_CSN_CRAWLER_STALL = 0x42, | ||
| 1936 | SPI_PERF_CSN_EVENT_WAVE = 0x43, | ||
| 1937 | SPI_PERF_CSN_WAVE = 0x44, | ||
| 1938 | SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, | ||
| 1939 | SPI_PERF_PS_CTL_BUSY = 0x46, | ||
| 1940 | SPI_PERF_PS_CTL_ACTIVE = 0x47, | ||
| 1941 | SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, | ||
| 1942 | SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, | ||
| 1943 | SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, | ||
| 1944 | SPI_PERF_PS_CTL_WAVE = 0x4b, | ||
| 1945 | SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, | ||
| 1946 | SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, | ||
| 1947 | SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, | ||
| 1948 | SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, | ||
| 1949 | SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, | ||
| 1950 | SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, | ||
| 1951 | SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, | ||
| 1952 | SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, | ||
| 1953 | SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, | ||
| 1954 | SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, | ||
| 1955 | SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, | ||
| 1956 | SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, | ||
| 1957 | SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, | ||
| 1958 | SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, | ||
| 1959 | SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, | ||
| 1960 | SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, | ||
| 1961 | SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, | ||
| 1962 | SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, | ||
| 1963 | SPI_PERF_LDS0_PC_VALID = 0x5e, | ||
| 1964 | SPI_PERF_LDS1_PC_VALID = 0x5f, | ||
| 1965 | SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, | ||
| 1966 | SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, | ||
| 1967 | SPI_PERF_RA_WR_CTL_FULL = 0x62, | ||
| 1968 | SPI_PERF_RA_REQ_NO_ALLOC = 0x63, | ||
| 1969 | SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, | ||
| 1970 | SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, | ||
| 1971 | SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, | ||
| 1972 | SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, | ||
| 1973 | SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, | ||
| 1974 | SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, | ||
| 1975 | SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, | ||
| 1976 | SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, | ||
| 1977 | SPI_PERF_RA_RES_STALL_PS = 0x6c, | ||
| 1978 | SPI_PERF_RA_RES_STALL_VS = 0x6d, | ||
| 1979 | SPI_PERF_RA_RES_STALL_GS = 0x6e, | ||
| 1980 | SPI_PERF_RA_RES_STALL_ES = 0x6f, | ||
| 1981 | SPI_PERF_RA_RES_STALL_HS = 0x70, | ||
| 1982 | SPI_PERF_RA_RES_STALL_LS = 0x71, | ||
| 1983 | SPI_PERF_RA_RES_STALL_CSG = 0x72, | ||
| 1984 | SPI_PERF_RA_RES_STALL_CSN = 0x73, | ||
| 1985 | SPI_PERF_RA_TMP_STALL_PS = 0x74, | ||
| 1986 | SPI_PERF_RA_TMP_STALL_VS = 0x75, | ||
| 1987 | SPI_PERF_RA_TMP_STALL_GS = 0x76, | ||
| 1988 | SPI_PERF_RA_TMP_STALL_ES = 0x77, | ||
| 1989 | SPI_PERF_RA_TMP_STALL_HS = 0x78, | ||
| 1990 | SPI_PERF_RA_TMP_STALL_LS = 0x79, | ||
| 1991 | SPI_PERF_RA_TMP_STALL_CSG = 0x7a, | ||
| 1992 | SPI_PERF_RA_TMP_STALL_CSN = 0x7b, | ||
| 1993 | SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, | ||
| 1994 | SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, | ||
| 1995 | SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, | ||
| 1996 | SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, | ||
| 1997 | SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, | ||
| 1998 | SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, | ||
| 1999 | SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, | ||
| 2000 | SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, | ||
| 2001 | SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, | ||
| 2002 | SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, | ||
| 2003 | SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, | ||
| 2004 | SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, | ||
| 2005 | SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, | ||
| 2006 | SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, | ||
| 2007 | SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, | ||
| 2008 | SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, | ||
| 2009 | SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, | ||
| 2010 | SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, | ||
| 2011 | SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, | ||
| 2012 | SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, | ||
| 2013 | SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, | ||
| 2014 | SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, | ||
| 2015 | SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, | ||
| 2016 | SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, | ||
| 2017 | SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, | ||
| 2018 | SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, | ||
| 2019 | SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, | ||
| 2020 | SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, | ||
| 2021 | SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, | ||
| 2022 | SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, | ||
| 2023 | SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, | ||
| 2024 | SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, | ||
| 2025 | SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, | ||
| 2026 | SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, | ||
| 2027 | SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, | ||
| 2028 | SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, | ||
| 2029 | SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, | ||
| 2030 | SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, | ||
| 2031 | SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, | ||
| 2032 | SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, | ||
| 2033 | SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, | ||
| 2034 | SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, | ||
| 2035 | SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, | ||
| 2036 | SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, | ||
| 2037 | SPI_PERF_RA_PS_LOCK_NA = 0xa8, | ||
| 2038 | SPI_PERF_RA_VS_LOCK = 0xa9, | ||
| 2039 | SPI_PERF_RA_GS_LOCK = 0xaa, | ||
| 2040 | SPI_PERF_RA_ES_LOCK = 0xab, | ||
| 2041 | SPI_PERF_RA_HS_LOCK = 0xac, | ||
| 2042 | SPI_PERF_RA_LS_LOCK = 0xad, | ||
| 2043 | SPI_PERF_RA_CSG_LOCK = 0xae, | ||
| 2044 | SPI_PERF_RA_CSN_LOCK = 0xaf, | ||
| 2045 | SPI_PERF_RA_RSV_UPD = 0xb0, | ||
| 2046 | SPI_PERF_EXP_ARB_COL_CNT = 0xb1, | ||
| 2047 | SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, | ||
| 2048 | SPI_PERF_EXP_ARB_POS_CNT = 0xb3, | ||
| 2049 | SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, | ||
| 2050 | SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, | ||
| 2051 | SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, | ||
| 2052 | SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, | ||
| 2053 | SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, | ||
| 2054 | SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, | ||
| 2055 | SPI_PERF_NUM_VS_POS_EXPORTS = 0xba, | ||
| 2056 | SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb, | ||
| 2057 | SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc, | ||
| 2058 | SPI_PERF_ES_GRP_FIFO_FULL = 0xbd, | ||
| 2059 | SPI_PERF_GS_GRP_FIFO_FULL = 0xbe, | ||
| 2060 | SPI_PERF_HS_GRP_FIFO_FULL = 0xbf, | ||
| 2061 | SPI_PERF_LS_GRP_FIFO_FULL = 0xc0, | ||
| 2062 | SPI_PERF_VS_ALLOC_CNT = 0xc1, | ||
| 2063 | SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2, | ||
| 2064 | SPI_PERF_PC_ALLOC_CNT = 0xc3, | ||
| 2065 | SPI_PERF_PC_ALLOC_ACCUM = 0xc4, | ||
| 2066 | } SPI_PERFCNT_SEL; | ||
| 2067 | typedef enum SPI_SHADER_FORMAT { | ||
| 2068 | SPI_SHADER_NONE = 0x0, | ||
| 2069 | SPI_SHADER_1COMP = 0x1, | ||
| 2070 | SPI_SHADER_2COMP = 0x2, | ||
| 2071 | SPI_SHADER_4COMPRESS = 0x3, | ||
| 2072 | SPI_SHADER_4COMP = 0x4, | ||
| 2073 | } SPI_SHADER_FORMAT; | ||
| 2074 | typedef enum SPI_SHADER_EX_FORMAT { | ||
| 2075 | SPI_SHADER_ZERO = 0x0, | ||
| 2076 | SPI_SHADER_32_R = 0x1, | ||
| 2077 | SPI_SHADER_32_GR = 0x2, | ||
| 2078 | SPI_SHADER_32_AR = 0x3, | ||
| 2079 | SPI_SHADER_FP16_ABGR = 0x4, | ||
| 2080 | SPI_SHADER_UNORM16_ABGR = 0x5, | ||
| 2081 | SPI_SHADER_SNORM16_ABGR = 0x6, | ||
| 2082 | SPI_SHADER_UINT16_ABGR = 0x7, | ||
| 2083 | SPI_SHADER_SINT16_ABGR = 0x8, | ||
| 2084 | SPI_SHADER_32_ABGR = 0x9, | ||
| 2085 | } SPI_SHADER_EX_FORMAT; | ||
| 2086 | typedef enum CLKGATE_SM_MODE { | ||
| 2087 | ON_SEQ = 0x0, | ||
| 2088 | OFF_SEQ = 0x1, | ||
| 2089 | PROG_SEQ = 0x2, | ||
| 2090 | READ_SEQ = 0x3, | ||
| 2091 | SM_MODE_RESERVED = 0x4, | ||
| 2092 | } CLKGATE_SM_MODE; | ||
| 2093 | typedef enum CLKGATE_BASE_MODE { | ||
| 2094 | MULT_8 = 0x0, | ||
| 2095 | MULT_16 = 0x1, | ||
| 2096 | } CLKGATE_BASE_MODE; | ||
| 2097 | typedef enum SQ_TEX_CLAMP { | ||
| 2098 | SQ_TEX_WRAP = 0x0, | ||
| 2099 | SQ_TEX_MIRROR = 0x1, | ||
| 2100 | SQ_TEX_CLAMP_LAST_TEXEL = 0x2, | ||
| 2101 | SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, | ||
| 2102 | SQ_TEX_CLAMP_HALF_BORDER = 0x4, | ||
| 2103 | SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, | ||
| 2104 | SQ_TEX_CLAMP_BORDER = 0x6, | ||
| 2105 | SQ_TEX_MIRROR_ONCE_BORDER = 0x7, | ||
| 2106 | } SQ_TEX_CLAMP; | ||
| 2107 | typedef enum SQ_TEX_XY_FILTER { | ||
| 2108 | SQ_TEX_XY_FILTER_POINT = 0x0, | ||
| 2109 | SQ_TEX_XY_FILTER_BILINEAR = 0x1, | ||
| 2110 | SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, | ||
| 2111 | SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, | ||
| 2112 | } SQ_TEX_XY_FILTER; | ||
| 2113 | typedef enum SQ_TEX_Z_FILTER { | ||
| 2114 | SQ_TEX_Z_FILTER_NONE = 0x0, | ||
| 2115 | SQ_TEX_Z_FILTER_POINT = 0x1, | ||
| 2116 | SQ_TEX_Z_FILTER_LINEAR = 0x2, | ||
| 2117 | } SQ_TEX_Z_FILTER; | ||
| 2118 | typedef enum SQ_TEX_MIP_FILTER { | ||
| 2119 | SQ_TEX_MIP_FILTER_NONE = 0x0, | ||
| 2120 | SQ_TEX_MIP_FILTER_POINT = 0x1, | ||
| 2121 | SQ_TEX_MIP_FILTER_LINEAR = 0x2, | ||
| 2122 | SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3, | ||
| 2123 | } SQ_TEX_MIP_FILTER; | ||
| 2124 | typedef enum SQ_TEX_ANISO_RATIO { | ||
| 2125 | SQ_TEX_ANISO_RATIO_1 = 0x0, | ||
| 2126 | SQ_TEX_ANISO_RATIO_2 = 0x1, | ||
| 2127 | SQ_TEX_ANISO_RATIO_4 = 0x2, | ||
| 2128 | SQ_TEX_ANISO_RATIO_8 = 0x3, | ||
| 2129 | SQ_TEX_ANISO_RATIO_16 = 0x4, | ||
| 2130 | } SQ_TEX_ANISO_RATIO; | ||
| 2131 | typedef enum SQ_TEX_DEPTH_COMPARE { | ||
| 2132 | SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, | ||
| 2133 | SQ_TEX_DEPTH_COMPARE_LESS = 0x1, | ||
| 2134 | SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, | ||
| 2135 | SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, | ||
| 2136 | SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, | ||
| 2137 | SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, | ||
| 2138 | SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, | ||
| 2139 | SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, | ||
| 2140 | } SQ_TEX_DEPTH_COMPARE; | ||
| 2141 | typedef enum SQ_TEX_BORDER_COLOR { | ||
| 2142 | SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, | ||
| 2143 | SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, | ||
| 2144 | SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, | ||
| 2145 | SQ_TEX_BORDER_COLOR_REGISTER = 0x3, | ||
| 2146 | } SQ_TEX_BORDER_COLOR; | ||
| 2147 | typedef enum SQ_RSRC_BUF_TYPE { | ||
| 2148 | SQ_RSRC_BUF = 0x0, | ||
| 2149 | SQ_RSRC_BUF_RSVD_1 = 0x1, | ||
| 2150 | SQ_RSRC_BUF_RSVD_2 = 0x2, | ||
| 2151 | SQ_RSRC_BUF_RSVD_3 = 0x3, | ||
| 2152 | } SQ_RSRC_BUF_TYPE; | ||
| 2153 | typedef enum SQ_RSRC_IMG_TYPE { | ||
| 2154 | SQ_RSRC_IMG_RSVD_0 = 0x0, | ||
| 2155 | SQ_RSRC_IMG_RSVD_1 = 0x1, | ||
| 2156 | SQ_RSRC_IMG_RSVD_2 = 0x2, | ||
| 2157 | SQ_RSRC_IMG_RSVD_3 = 0x3, | ||
| 2158 | SQ_RSRC_IMG_RSVD_4 = 0x4, | ||
| 2159 | SQ_RSRC_IMG_RSVD_5 = 0x5, | ||
| 2160 | SQ_RSRC_IMG_RSVD_6 = 0x6, | ||
| 2161 | SQ_RSRC_IMG_RSVD_7 = 0x7, | ||
| 2162 | SQ_RSRC_IMG_1D = 0x8, | ||
| 2163 | SQ_RSRC_IMG_2D = 0x9, | ||
| 2164 | SQ_RSRC_IMG_3D = 0xa, | ||
| 2165 | SQ_RSRC_IMG_CUBE = 0xb, | ||
| 2166 | SQ_RSRC_IMG_1D_ARRAY = 0xc, | ||
| 2167 | SQ_RSRC_IMG_2D_ARRAY = 0xd, | ||
| 2168 | SQ_RSRC_IMG_2D_MSAA = 0xe, | ||
| 2169 | SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, | ||
| 2170 | } SQ_RSRC_IMG_TYPE; | ||
| 2171 | typedef enum SQ_RSRC_FLAT_TYPE { | ||
| 2172 | SQ_RSRC_FLAT_RSVD_0 = 0x0, | ||
| 2173 | SQ_RSRC_FLAT = 0x1, | ||
| 2174 | SQ_RSRC_FLAT_RSVD_2 = 0x2, | ||
| 2175 | SQ_RSRC_FLAT_RSVD_3 = 0x3, | ||
| 2176 | } SQ_RSRC_FLAT_TYPE; | ||
| 2177 | typedef enum SQ_IMG_FILTER_TYPE { | ||
| 2178 | SQ_IMG_FILTER_MODE_BLEND = 0x0, | ||
| 2179 | SQ_IMG_FILTER_MODE_MIN = 0x1, | ||
| 2180 | SQ_IMG_FILTER_MODE_MAX = 0x2, | ||
| 2181 | } SQ_IMG_FILTER_TYPE; | ||
| 2182 | typedef enum SQ_SEL_XYZW01 { | ||
| 2183 | SQ_SEL_0 = 0x0, | ||
| 2184 | SQ_SEL_1 = 0x1, | ||
| 2185 | SQ_SEL_RESERVED_0 = 0x2, | ||
| 2186 | SQ_SEL_RESERVED_1 = 0x3, | ||
| 2187 | SQ_SEL_X = 0x4, | ||
| 2188 | SQ_SEL_Y = 0x5, | ||
| 2189 | SQ_SEL_Z = 0x6, | ||
| 2190 | SQ_SEL_W = 0x7, | ||
| 2191 | } SQ_SEL_XYZW01; | ||
| 2192 | typedef enum SQ_WAVE_TYPE { | ||
| 2193 | SQ_WAVE_TYPE_PS = 0x0, | ||
| 2194 | SQ_WAVE_TYPE_VS = 0x1, | ||
| 2195 | SQ_WAVE_TYPE_GS = 0x2, | ||
| 2196 | SQ_WAVE_TYPE_ES = 0x3, | ||
| 2197 | SQ_WAVE_TYPE_HS = 0x4, | ||
| 2198 | SQ_WAVE_TYPE_LS = 0x5, | ||
| 2199 | SQ_WAVE_TYPE_CS = 0x6, | ||
| 2200 | SQ_WAVE_TYPE_PS1 = 0x7, | ||
| 2201 | } SQ_WAVE_TYPE; | ||
| 2202 | typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { | ||
| 2203 | SQ_THREAD_TRACE_TOKEN_MISC = 0x0, | ||
| 2204 | SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, | ||
| 2205 | SQ_THREAD_TRACE_TOKEN_REG = 0x2, | ||
| 2206 | SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, | ||
| 2207 | SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, | ||
| 2208 | SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, | ||
| 2209 | SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, | ||
| 2210 | SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, | ||
| 2211 | SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, | ||
| 2212 | SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, | ||
| 2213 | SQ_THREAD_TRACE_TOKEN_INST = 0xa, | ||
| 2214 | SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, | ||
| 2215 | SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, | ||
| 2216 | SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, | ||
| 2217 | SQ_THREAD_TRACE_TOKEN_PERF = 0xe, | ||
| 2218 | SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, | ||
| 2219 | } SQ_THREAD_TRACE_TOKEN_TYPE; | ||
| 2220 | typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { | ||
| 2221 | SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, | ||
| 2222 | SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, | ||
| 2223 | SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, | ||
| 2224 | SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, | ||
| 2225 | SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, | ||
| 2226 | SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, | ||
| 2227 | SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6, | ||
| 2228 | SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7, | ||
| 2229 | } SQ_THREAD_TRACE_MISC_TOKEN_TYPE; | ||
| 2230 | typedef enum SQ_THREAD_TRACE_INST_TYPE { | ||
| 2231 | SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0, | ||
| 2232 | SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1, | ||
| 2233 | SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, | ||
| 2234 | SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, | ||
| 2235 | SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, | ||
| 2236 | SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5, | ||
| 2237 | SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, | ||
| 2238 | SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, | ||
| 2239 | SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, | ||
| 2240 | SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, | ||
| 2241 | SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, | ||
| 2242 | SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, | ||
| 2243 | SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, | ||
| 2244 | SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, | ||
| 2245 | SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, | ||
| 2246 | SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, | ||
| 2247 | SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10, | ||
| 2248 | SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11, | ||
| 2249 | SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12, | ||
| 2250 | SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13, | ||
| 2251 | SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14, | ||
| 2252 | SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15, | ||
| 2253 | SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16, | ||
| 2254 | SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17, | ||
| 2255 | SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18, | ||
| 2256 | } SQ_THREAD_TRACE_INST_TYPE; | ||
| 2257 | typedef enum SQ_THREAD_TRACE_REG_TYPE { | ||
| 2258 | SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, | ||
| 2259 | SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, | ||
| 2260 | SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, | ||
| 2261 | SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, | ||
| 2262 | SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, | ||
| 2263 | SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, | ||
| 2264 | SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, | ||
| 2265 | SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, | ||
| 2266 | } SQ_THREAD_TRACE_REG_TYPE; | ||
| 2267 | typedef enum SQ_THREAD_TRACE_REG_OP { | ||
| 2268 | SQ_THREAD_TRACE_REG_OP_READ = 0x0, | ||
| 2269 | SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, | ||
| 2270 | } SQ_THREAD_TRACE_REG_OP; | ||
| 2271 | typedef enum SQ_THREAD_TRACE_MODE_SEL { | ||
| 2272 | SQ_THREAD_TRACE_MODE_OFF = 0x0, | ||
| 2273 | SQ_THREAD_TRACE_MODE_ON = 0x1, | ||
| 2274 | } SQ_THREAD_TRACE_MODE_SEL; | ||
| 2275 | typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { | ||
| 2276 | SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, | ||
| 2277 | SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, | ||
| 2278 | SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, | ||
| 2279 | } SQ_THREAD_TRACE_CAPTURE_MODE; | ||
| 2280 | typedef enum SQ_THREAD_TRACE_VM_ID_MASK { | ||
| 2281 | SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, | ||
| 2282 | SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, | ||
| 2283 | SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, | ||
| 2284 | } SQ_THREAD_TRACE_VM_ID_MASK; | ||
| 2285 | typedef enum SQ_THREAD_TRACE_WAVE_MASK { | ||
| 2286 | SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, | ||
| 2287 | SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, | ||
| 2288 | } SQ_THREAD_TRACE_WAVE_MASK; | ||
| 2289 | typedef enum SQ_THREAD_TRACE_ISSUE { | ||
| 2290 | SQ_THREAD_TRACE_ISSUE_NULL = 0x0, | ||
| 2291 | SQ_THREAD_TRACE_ISSUE_STALL = 0x1, | ||
| 2292 | SQ_THREAD_TRACE_ISSUE_INST = 0x2, | ||
| 2293 | SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, | ||
| 2294 | } SQ_THREAD_TRACE_ISSUE; | ||
| 2295 | typedef enum SQ_THREAD_TRACE_ISSUE_MASK { | ||
| 2296 | SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, | ||
| 2297 | SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, | ||
| 2298 | SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, | ||
| 2299 | SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, | ||
| 2300 | } SQ_THREAD_TRACE_ISSUE_MASK; | ||
| 2301 | typedef enum SQ_PERF_SEL { | ||
| 2302 | SQ_PERF_SEL_NONE = 0x0, | ||
| 2303 | SQ_PERF_SEL_ACCUM_PREV = 0x1, | ||
| 2304 | SQ_PERF_SEL_CYCLES = 0x2, | ||
| 2305 | SQ_PERF_SEL_BUSY_CYCLES = 0x3, | ||
| 2306 | SQ_PERF_SEL_WAVES = 0x4, | ||
| 2307 | SQ_PERF_SEL_LEVEL_WAVES = 0x5, | ||
| 2308 | SQ_PERF_SEL_WAVES_EQ_64 = 0x6, | ||
| 2309 | SQ_PERF_SEL_WAVES_LT_64 = 0x7, | ||
| 2310 | SQ_PERF_SEL_WAVES_LT_48 = 0x8, | ||
| 2311 | SQ_PERF_SEL_WAVES_LT_32 = 0x9, | ||
| 2312 | SQ_PERF_SEL_WAVES_LT_16 = 0xa, | ||
| 2313 | SQ_PERF_SEL_WAVES_CU = 0xb, | ||
| 2314 | SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, | ||
| 2315 | SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, | ||
| 2316 | SQ_PERF_SEL_ITEMS = 0xe, | ||
| 2317 | SQ_PERF_SEL_QUADS = 0xf, | ||
| 2318 | SQ_PERF_SEL_EVENTS = 0x10, | ||
| 2319 | SQ_PERF_SEL_SURF_SYNCS = 0x11, | ||
| 2320 | SQ_PERF_SEL_TTRACE_REQS = 0x12, | ||
| 2321 | SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, | ||
| 2322 | SQ_PERF_SEL_TTRACE_STALL = 0x14, | ||
| 2323 | SQ_PERF_SEL_MSG_CNTR = 0x15, | ||
| 2324 | SQ_PERF_SEL_MSG_PERF = 0x16, | ||
| 2325 | SQ_PERF_SEL_MSG_GSCNT = 0x17, | ||
| 2326 | SQ_PERF_SEL_MSG_INTERRUPT = 0x18, | ||
| 2327 | SQ_PERF_SEL_INSTS = 0x19, | ||
| 2328 | SQ_PERF_SEL_INSTS_VALU = 0x1a, | ||
| 2329 | SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, | ||
| 2330 | SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, | ||
| 2331 | SQ_PERF_SEL_INSTS_VMEM = 0x1d, | ||
| 2332 | SQ_PERF_SEL_INSTS_SALU = 0x1e, | ||
| 2333 | SQ_PERF_SEL_INSTS_SMEM = 0x1f, | ||
| 2334 | SQ_PERF_SEL_INSTS_FLAT = 0x20, | ||
| 2335 | SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, | ||
| 2336 | SQ_PERF_SEL_INSTS_LDS = 0x22, | ||
| 2337 | SQ_PERF_SEL_INSTS_GDS = 0x23, | ||
| 2338 | SQ_PERF_SEL_INSTS_EXP = 0x24, | ||
| 2339 | SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, | ||
| 2340 | SQ_PERF_SEL_INSTS_BRANCH = 0x26, | ||
| 2341 | SQ_PERF_SEL_INSTS_SENDMSG = 0x27, | ||
| 2342 | SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, | ||
| 2343 | SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, | ||
| 2344 | SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, | ||
| 2345 | SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, | ||
| 2346 | SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, | ||
| 2347 | SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, | ||
| 2348 | SQ_PERF_SEL_WAVE_CYCLES = 0x2e, | ||
| 2349 | SQ_PERF_SEL_WAVE_READY = 0x2f, | ||
| 2350 | SQ_PERF_SEL_WAIT_CNT_VM = 0x30, | ||
| 2351 | SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, | ||
| 2352 | SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, | ||
| 2353 | SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, | ||
| 2354 | SQ_PERF_SEL_WAIT_BARRIER = 0x34, | ||
| 2355 | SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, | ||
| 2356 | SQ_PERF_SEL_WAIT_SLEEP = 0x36, | ||
| 2357 | SQ_PERF_SEL_WAIT_OTHER = 0x37, | ||
| 2358 | SQ_PERF_SEL_WAIT_ANY = 0x38, | ||
| 2359 | SQ_PERF_SEL_WAIT_TTRACE = 0x39, | ||
| 2360 | SQ_PERF_SEL_WAIT_IFETCH = 0x3a, | ||
| 2361 | SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, | ||
| 2362 | SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, | ||
| 2363 | SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, | ||
| 2364 | SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, | ||
| 2365 | SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, | ||
| 2366 | SQ_PERF_SEL_WAIT_INST_MISC = 0x40, | ||
| 2367 | SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, | ||
| 2368 | SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, | ||
| 2369 | SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, | ||
| 2370 | SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, | ||
| 2371 | SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, | ||
| 2372 | SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, | ||
| 2373 | SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, | ||
| 2374 | SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, | ||
| 2375 | SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, | ||
| 2376 | SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, | ||
| 2377 | SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, | ||
| 2378 | SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, | ||
| 2379 | SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, | ||
| 2380 | SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, | ||
| 2381 | SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, | ||
| 2382 | SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, | ||
| 2383 | SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, | ||
| 2384 | SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, | ||
| 2385 | SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, | ||
| 2386 | SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, | ||
| 2387 | SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, | ||
| 2388 | SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, | ||
| 2389 | SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, | ||
| 2390 | SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, | ||
| 2391 | SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, | ||
| 2392 | SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, | ||
| 2393 | SQ_PERF_SEL_IFETCH = 0x5b, | ||
| 2394 | SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, | ||
| 2395 | SQ_PERF_SEL_CBRANCH_FORK = 0x5d, | ||
| 2396 | SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, | ||
| 2397 | SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, | ||
| 2398 | SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, | ||
| 2399 | SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, | ||
| 2400 | SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, | ||
| 2401 | SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, | ||
| 2402 | SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, | ||
| 2403 | SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, | ||
| 2404 | SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, | ||
| 2405 | SQ_PERF_SEL_VALU_DEP_STALL = 0x67, | ||
| 2406 | SQ_PERF_SEL_VALU_STARVE = 0x68, | ||
| 2407 | SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, | ||
| 2408 | SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, | ||
| 2409 | SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, | ||
| 2410 | SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, | ||
| 2411 | SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, | ||
| 2412 | SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, | ||
| 2413 | SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, | ||
| 2414 | SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, | ||
| 2415 | SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, | ||
| 2416 | SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, | ||
| 2417 | SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, | ||
| 2418 | SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, | ||
| 2419 | SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, | ||
| 2420 | SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, | ||
| 2421 | SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, | ||
| 2422 | SQ_PERF_SEL_SRC_CD_BUSY = 0x78, | ||
| 2423 | SQ_PERF_SEL_PT_POWER_STALL = 0x79, | ||
| 2424 | SQ_PERF_SEL_USER0 = 0x7a, | ||
| 2425 | SQ_PERF_SEL_USER1 = 0x7b, | ||
| 2426 | SQ_PERF_SEL_USER2 = 0x7c, | ||
| 2427 | SQ_PERF_SEL_USER3 = 0x7d, | ||
| 2428 | SQ_PERF_SEL_USER4 = 0x7e, | ||
| 2429 | SQ_PERF_SEL_USER5 = 0x7f, | ||
| 2430 | SQ_PERF_SEL_USER6 = 0x80, | ||
| 2431 | SQ_PERF_SEL_USER7 = 0x81, | ||
| 2432 | SQ_PERF_SEL_USER8 = 0x82, | ||
| 2433 | SQ_PERF_SEL_USER9 = 0x83, | ||
| 2434 | SQ_PERF_SEL_USER10 = 0x84, | ||
| 2435 | SQ_PERF_SEL_USER11 = 0x85, | ||
| 2436 | SQ_PERF_SEL_USER12 = 0x86, | ||
| 2437 | SQ_PERF_SEL_USER13 = 0x87, | ||
| 2438 | SQ_PERF_SEL_USER14 = 0x88, | ||
| 2439 | SQ_PERF_SEL_USER15 = 0x89, | ||
| 2440 | SQ_PERF_SEL_USER_LEVEL0 = 0x8a, | ||
| 2441 | SQ_PERF_SEL_USER_LEVEL1 = 0x8b, | ||
| 2442 | SQ_PERF_SEL_USER_LEVEL2 = 0x8c, | ||
| 2443 | SQ_PERF_SEL_USER_LEVEL3 = 0x8d, | ||
| 2444 | SQ_PERF_SEL_USER_LEVEL4 = 0x8e, | ||
| 2445 | SQ_PERF_SEL_USER_LEVEL5 = 0x8f, | ||
| 2446 | SQ_PERF_SEL_USER_LEVEL6 = 0x90, | ||
| 2447 | SQ_PERF_SEL_USER_LEVEL7 = 0x91, | ||
| 2448 | SQ_PERF_SEL_USER_LEVEL8 = 0x92, | ||
| 2449 | SQ_PERF_SEL_USER_LEVEL9 = 0x93, | ||
| 2450 | SQ_PERF_SEL_USER_LEVEL10 = 0x94, | ||
| 2451 | SQ_PERF_SEL_USER_LEVEL11 = 0x95, | ||
| 2452 | SQ_PERF_SEL_USER_LEVEL12 = 0x96, | ||
| 2453 | SQ_PERF_SEL_USER_LEVEL13 = 0x97, | ||
| 2454 | SQ_PERF_SEL_USER_LEVEL14 = 0x98, | ||
| 2455 | SQ_PERF_SEL_USER_LEVEL15 = 0x99, | ||
| 2456 | SQ_PERF_SEL_POWER_VALU = 0x9a, | ||
| 2457 | SQ_PERF_SEL_POWER_VALU0 = 0x9b, | ||
| 2458 | SQ_PERF_SEL_POWER_VALU1 = 0x9c, | ||
| 2459 | SQ_PERF_SEL_POWER_VALU2 = 0x9d, | ||
| 2460 | SQ_PERF_SEL_POWER_GPR_RD = 0x9e, | ||
| 2461 | SQ_PERF_SEL_POWER_GPR_WR = 0x9f, | ||
| 2462 | SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, | ||
| 2463 | SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, | ||
| 2464 | SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, | ||
| 2465 | SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, | ||
| 2466 | SQ_PERF_SEL_WAVES_RESTORED = 0xa4, | ||
| 2467 | SQ_PERF_SEL_WAVES_SAVED = 0xa5, | ||
| 2468 | SQ_PERF_SEL_DUMMY_LAST = 0xa7, | ||
| 2469 | SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, | ||
| 2470 | SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, | ||
| 2471 | SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, | ||
| 2472 | SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, | ||
| 2473 | SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, | ||
| 2474 | SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, | ||
| 2475 | SQC_PERF_SEL_TC_REQ = 0xae, | ||
| 2476 | SQC_PERF_SEL_TC_INST_REQ = 0xaf, | ||
| 2477 | SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0, | ||
| 2478 | SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1, | ||
| 2479 | SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2, | ||
| 2480 | SQC_PERF_SEL_TC_STALL = 0xb3, | ||
| 2481 | SQC_PERF_SEL_TC_STARVE = 0xb4, | ||
| 2482 | SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5, | ||
| 2483 | SQC_PERF_SEL_ICACHE_REQ = 0xb6, | ||
| 2484 | SQC_PERF_SEL_ICACHE_HITS = 0xb7, | ||
| 2485 | SQC_PERF_SEL_ICACHE_MISSES = 0xb8, | ||
| 2486 | SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9, | ||
| 2487 | SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, | ||
| 2488 | SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, | ||
| 2489 | SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc, | ||
| 2490 | SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd, | ||
| 2491 | SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe, | ||
| 2492 | SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf, | ||
| 2493 | SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0, | ||
| 2494 | SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1, | ||
| 2495 | SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2, | ||
| 2496 | SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3, | ||
| 2497 | SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4, | ||
| 2498 | SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5, | ||
| 2499 | SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6, | ||
| 2500 | SQC_PERF_SEL_DCACHE_REQ = 0xc7, | ||
| 2501 | SQC_PERF_SEL_DCACHE_HITS = 0xc8, | ||
| 2502 | SQC_PERF_SEL_DCACHE_MISSES = 0xc9, | ||
| 2503 | SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca, | ||
| 2504 | SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb, | ||
| 2505 | SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc, | ||
| 2506 | SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd, | ||
| 2507 | SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce, | ||
| 2508 | SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf, | ||
| 2509 | SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, | ||
| 2510 | SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, | ||
| 2511 | SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, | ||
| 2512 | SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, | ||
| 2513 | SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, | ||
| 2514 | SQC_PERF_SEL_DCACHE_WB_INST = 0xd5, | ||
| 2515 | SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6, | ||
| 2516 | SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7, | ||
| 2517 | SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8, | ||
| 2518 | SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9, | ||
| 2519 | SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda, | ||
| 2520 | SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb, | ||
| 2521 | SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc, | ||
| 2522 | SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd, | ||
| 2523 | SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde, | ||
| 2524 | SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf, | ||
| 2525 | SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0, | ||
| 2526 | SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1, | ||
| 2527 | SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2, | ||
| 2528 | SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3, | ||
| 2529 | SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4, | ||
| 2530 | SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5, | ||
| 2531 | SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6, | ||
| 2532 | SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7, | ||
| 2533 | SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8, | ||
| 2534 | SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9, | ||
| 2535 | SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea, | ||
| 2536 | SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb, | ||
| 2537 | SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec, | ||
| 2538 | SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed, | ||
| 2539 | SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee, | ||
| 2540 | SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef, | ||
| 2541 | SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0, | ||
| 2542 | SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1, | ||
| 2543 | SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2, | ||
| 2544 | SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3, | ||
| 2545 | SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4, | ||
| 2546 | SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5, | ||
| 2547 | SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6, | ||
| 2548 | SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7, | ||
| 2549 | SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8, | ||
| 2550 | SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9, | ||
| 2551 | SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa, | ||
| 2552 | SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb, | ||
| 2553 | SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc, | ||
| 2554 | SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd, | ||
| 2555 | SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe, | ||
| 2556 | SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff, | ||
| 2557 | SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100, | ||
| 2558 | SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101, | ||
| 2559 | SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102, | ||
| 2560 | SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103, | ||
| 2561 | SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104, | ||
| 2562 | SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105, | ||
| 2563 | SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106, | ||
| 2564 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107, | ||
| 2565 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108, | ||
| 2566 | SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109, | ||
| 2567 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a, | ||
| 2568 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b, | ||
| 2569 | SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c, | ||
| 2570 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d, | ||
| 2571 | SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e, | ||
| 2572 | SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f, | ||
| 2573 | SQC_PERF_SEL_DUMMY_LAST = 0x110, | ||
| 2574 | SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111, | ||
| 2575 | SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112, | ||
| 2576 | SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113, | ||
| 2577 | SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114, | ||
| 2578 | SQ_PERF_SEL_ATC_XNACK_ALL = 0x115, | ||
| 2579 | SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116, | ||
| 2580 | SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117, | ||
| 2581 | SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118, | ||
| 2582 | SQ_PERF_SEL_IFETCH_XNACK = 0x119, | ||
| 2583 | SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a, | ||
| 2584 | SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b, | ||
| 2585 | SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c, | ||
| 2586 | SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d, | ||
| 2587 | SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e, | ||
| 2588 | SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f, | ||
| 2589 | SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120, | ||
| 2590 | SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121, | ||
| 2591 | SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122, | ||
| 2592 | SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123, | ||
| 2593 | SQ_PERF_SEL_DUMMY_LAST1 = 0x12a, | ||
| 2594 | } SQ_PERF_SEL; | ||
| 2595 | typedef enum SQ_CAC_POWER_SEL { | ||
| 2596 | SQ_CAC_POWER_VALU = 0x0, | ||
| 2597 | SQ_CAC_POWER_VALU0 = 0x1, | ||
| 2598 | SQ_CAC_POWER_VALU1 = 0x2, | ||
| 2599 | SQ_CAC_POWER_VALU2 = 0x3, | ||
| 2600 | SQ_CAC_POWER_GPR_RD = 0x4, | ||
| 2601 | SQ_CAC_POWER_GPR_WR = 0x5, | ||
| 2602 | SQ_CAC_POWER_LDS_BUSY = 0x6, | ||
| 2603 | SQ_CAC_POWER_ALU_BUSY = 0x7, | ||
| 2604 | SQ_CAC_POWER_TEX_BUSY = 0x8, | ||
| 2605 | } SQ_CAC_POWER_SEL; | ||
| 2606 | typedef enum SQ_IND_CMD_CMD { | ||
| 2607 | SQ_IND_CMD_CMD_NULL = 0x0, | ||
| 2608 | SQ_IND_CMD_CMD_SETHALT = 0x1, | ||
| 2609 | SQ_IND_CMD_CMD_SAVECTX = 0x2, | ||
| 2610 | SQ_IND_CMD_CMD_KILL = 0x3, | ||
| 2611 | SQ_IND_CMD_CMD_DEBUG = 0x4, | ||
| 2612 | SQ_IND_CMD_CMD_TRAP = 0x5, | ||
| 2613 | SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6, | ||
| 2614 | } SQ_IND_CMD_CMD; | ||
| 2615 | typedef enum SQ_IND_CMD_MODE { | ||
| 2616 | SQ_IND_CMD_MODE_SINGLE = 0x0, | ||
| 2617 | SQ_IND_CMD_MODE_BROADCAST = 0x1, | ||
| 2618 | SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, | ||
| 2619 | SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, | ||
| 2620 | SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, | ||
| 2621 | } SQ_IND_CMD_MODE; | ||
| 2622 | typedef enum SQ_EDC_INFO_SOURCE { | ||
| 2623 | SQ_EDC_INFO_SOURCE_INVALID = 0x0, | ||
| 2624 | SQ_EDC_INFO_SOURCE_INST = 0x1, | ||
| 2625 | SQ_EDC_INFO_SOURCE_SGPR = 0x2, | ||
| 2626 | SQ_EDC_INFO_SOURCE_VGPR = 0x3, | ||
| 2627 | SQ_EDC_INFO_SOURCE_LDS = 0x4, | ||
| 2628 | SQ_EDC_INFO_SOURCE_GDS = 0x5, | ||
| 2629 | SQ_EDC_INFO_SOURCE_TA = 0x6, | ||
| 2630 | } SQ_EDC_INFO_SOURCE; | ||
| 2631 | typedef enum SQ_ROUND_MODE { | ||
| 2632 | SQ_ROUND_NEAREST_EVEN = 0x0, | ||
| 2633 | SQ_ROUND_PLUS_INFINITY = 0x1, | ||
| 2634 | SQ_ROUND_MINUS_INFINITY = 0x2, | ||
| 2635 | SQ_ROUND_TO_ZERO = 0x3, | ||
| 2636 | } SQ_ROUND_MODE; | ||
| 2637 | typedef enum SQ_INTERRUPT_WORD_ENCODING { | ||
| 2638 | SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, | ||
| 2639 | SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, | ||
| 2640 | SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, | ||
| 2641 | } SQ_INTERRUPT_WORD_ENCODING; | ||
| 2642 | typedef enum ENUM_SQ_EXPORT_RAT_INST { | ||
| 2643 | SQ_EXPORT_RAT_INST_NOP = 0x0, | ||
| 2644 | SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, | ||
| 2645 | SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, | ||
| 2646 | SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, | ||
| 2647 | SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, | ||
| 2648 | SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, | ||
| 2649 | SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, | ||
| 2650 | SQ_EXPORT_RAT_INST_ADD = 0x7, | ||
| 2651 | SQ_EXPORT_RAT_INST_SUB = 0x8, | ||
| 2652 | SQ_EXPORT_RAT_INST_RSUB = 0x9, | ||
| 2653 | SQ_EXPORT_RAT_INST_MIN_INT = 0xa, | ||
| 2654 | SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, | ||
| 2655 | SQ_EXPORT_RAT_INST_MAX_INT = 0xc, | ||
| 2656 | SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, | ||
| 2657 | SQ_EXPORT_RAT_INST_AND = 0xe, | ||
| 2658 | SQ_EXPORT_RAT_INST_OR = 0xf, | ||
| 2659 | SQ_EXPORT_RAT_INST_XOR = 0x10, | ||
| 2660 | SQ_EXPORT_RAT_INST_MSKOR = 0x11, | ||
| 2661 | SQ_EXPORT_RAT_INST_INC_UINT = 0x12, | ||
| 2662 | SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, | ||
| 2663 | SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, | ||
| 2664 | SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, | ||
| 2665 | SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, | ||
| 2666 | SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, | ||
| 2667 | SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, | ||
| 2668 | SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, | ||
| 2669 | SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, | ||
| 2670 | SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, | ||
| 2671 | SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, | ||
| 2672 | SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, | ||
| 2673 | SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, | ||
| 2674 | SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, | ||
| 2675 | SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, | ||
| 2676 | SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, | ||
| 2677 | SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, | ||
| 2678 | SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, | ||
| 2679 | SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, | ||
| 2680 | SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, | ||
| 2681 | SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, | ||
| 2682 | SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, | ||
| 2683 | SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, | ||
| 2684 | SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, | ||
| 2685 | } ENUM_SQ_EXPORT_RAT_INST; | ||
| 2686 | typedef enum SQ_IBUF_ST { | ||
| 2687 | SQ_IBUF_IB_IDLE = 0x0, | ||
| 2688 | SQ_IBUF_IB_INI_WAIT_GNT = 0x1, | ||
| 2689 | SQ_IBUF_IB_INI_WAIT_DRET = 0x2, | ||
| 2690 | SQ_IBUF_IB_LE_4DW = 0x3, | ||
| 2691 | SQ_IBUF_IB_WAIT_DRET = 0x4, | ||
| 2692 | SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, | ||
| 2693 | SQ_IBUF_IB_DRET = 0x6, | ||
| 2694 | SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, | ||
| 2695 | } SQ_IBUF_ST; | ||
| 2696 | typedef enum SQ_INST_STR_ST { | ||
| 2697 | SQ_INST_STR_IB_WAVE_NORML = 0x0, | ||
| 2698 | SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, | ||
| 2699 | SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, | ||
| 2700 | SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, | ||
| 2701 | SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, | ||
| 2702 | SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, | ||
| 2703 | SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, | ||
| 2704 | SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, | ||
| 2705 | } SQ_INST_STR_ST; | ||
| 2706 | typedef enum SQ_WAVE_IB_ECC_ST { | ||
| 2707 | SQ_WAVE_IB_ECC_CLEAN = 0x0, | ||
| 2708 | SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, | ||
| 2709 | SQ_WAVE_IB_ECC_ERR_HALT = 0x2, | ||
| 2710 | SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, | ||
| 2711 | } SQ_WAVE_IB_ECC_ST; | ||
| 2712 | typedef enum SH_MEM_ADDRESS_MODE { | ||
| 2713 | SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0, | ||
| 2714 | SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1, | ||
| 2715 | SH_MEM_ADDRESS_MODE_HSA64 = 0x2, | ||
| 2716 | SH_MEM_ADDRESS_MODE_HSA32 = 0x3, | ||
| 2717 | } SH_MEM_ADDRESS_MODE; | ||
| 2718 | typedef enum SH_MEM_ALIGNMENT_MODE { | ||
| 2719 | SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, | ||
| 2720 | SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, | ||
| 2721 | SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, | ||
| 2722 | SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, | ||
| 2723 | } SH_MEM_ALIGNMENT_MODE; | ||
| 2724 | typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { | ||
| 2725 | SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18, | ||
| 2726 | SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19, | ||
| 2727 | } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; | ||
| 2728 | #define SQ_WAVE_TYPE_PS0 0x0 | ||
| 2729 | #define SQIND_GLOBAL_REGS_OFFSET 0x0 | ||
| 2730 | #define SQIND_GLOBAL_REGS_SIZE 0x8 | ||
| 2731 | #define SQIND_LOCAL_REGS_OFFSET 0x8 | ||
| 2732 | #define SQIND_LOCAL_REGS_SIZE 0x8 | ||
| 2733 | #define SQIND_WAVE_HWREGS_OFFSET 0x10 | ||
| 2734 | #define SQIND_WAVE_HWREGS_SIZE 0x1f0 | ||
| 2735 | #define SQIND_WAVE_SGPRS_OFFSET 0x200 | ||
| 2736 | #define SQIND_WAVE_SGPRS_SIZE 0x200 | ||
| 2737 | #define SQ_GFXDEC_BEGIN 0xa000 | ||
| 2738 | #define SQ_GFXDEC_END 0xc000 | ||
| 2739 | #define SQ_GFXDEC_STATE_ID_SHIFT 0xa | ||
| 2740 | #define SQDEC_BEGIN 0x2300 | ||
| 2741 | #define SQDEC_END 0x23ff | ||
| 2742 | #define SQPERFSDEC_BEGIN 0xd9c0 | ||
| 2743 | #define SQPERFSDEC_END 0xda40 | ||
| 2744 | #define SQPERFDDEC_BEGIN 0xd1c0 | ||
| 2745 | #define SQPERFDDEC_END 0xd240 | ||
| 2746 | #define SQGFXUDEC_BEGIN 0xc330 | ||
| 2747 | #define SQGFXUDEC_END 0xc380 | ||
| 2748 | #define SQPWRDEC_BEGIN 0xf08c | ||
| 2749 | #define SQPWRDEC_END 0xf094 | ||
| 2750 | #define SQ_DISPATCHER_GFX_MIN 0x10 | ||
| 2751 | #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 | ||
| 2752 | #define SQ_MAX_PGM_SGPRS 0x68 | ||
| 2753 | #define SQ_MAX_PGM_VGPRS 0x100 | ||
| 2754 | #define SQ_THREAD_TRACE_TIME_UNIT 0x4 | ||
| 2755 | #define SQ_EX_MODE_EXCP_VALU_BASE 0x0 | ||
| 2756 | #define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 | ||
| 2757 | #define SQ_EX_MODE_EXCP_INVALID 0x0 | ||
| 2758 | #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 | ||
| 2759 | #define SQ_EX_MODE_EXCP_DIV0 0x2 | ||
| 2760 | #define SQ_EX_MODE_EXCP_OVERFLOW 0x3 | ||
| 2761 | #define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 | ||
| 2762 | #define SQ_EX_MODE_EXCP_INEXACT 0x5 | ||
| 2763 | #define SQ_EX_MODE_EXCP_INT_DIV0 0x6 | ||
| 2764 | #define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 | ||
| 2765 | #define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 | ||
| 2766 | #define INST_ID_PRIV_START 0x80000000 | ||
| 2767 | #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 | ||
| 2768 | #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 | ||
| 2769 | #define INST_ID_HW_TRAP 0xfffffff2 | ||
| 2770 | #define INST_ID_KILL_SEQ 0xfffffff3 | ||
| 2771 | #define INST_ID_SPI_WREXEC 0xfffffff4 | ||
| 2772 | #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe | ||
| 2773 | #define SQ_ENC_SOP1_BITS 0xbe800000 | ||
| 2774 | #define SQ_ENC_SOP1_MASK 0xff800000 | ||
| 2775 | #define SQ_ENC_SOP1_FIELD 0x17d | ||
| 2776 | #define SQ_ENC_SOPC_BITS 0xbf000000 | ||
| 2777 | #define SQ_ENC_SOPC_MASK 0xff800000 | ||
| 2778 | #define SQ_ENC_SOPC_FIELD 0x17e | ||
| 2779 | #define SQ_ENC_SOPP_BITS 0xbf800000 | ||
| 2780 | #define SQ_ENC_SOPP_MASK 0xff800000 | ||
| 2781 | #define SQ_ENC_SOPP_FIELD 0x17f | ||
| 2782 | #define SQ_ENC_SOPK_BITS 0xb0000000 | ||
| 2783 | #define SQ_ENC_SOPK_MASK 0xf0000000 | ||
| 2784 | #define SQ_ENC_SOPK_FIELD 0xb | ||
| 2785 | #define SQ_ENC_SOP2_BITS 0x80000000 | ||
| 2786 | #define SQ_ENC_SOP2_MASK 0xc0000000 | ||
| 2787 | #define SQ_ENC_SOP2_FIELD 0x2 | ||
| 2788 | #define SQ_ENC_SMEM_BITS 0xc0000000 | ||
| 2789 | #define SQ_ENC_SMEM_MASK 0xfc000000 | ||
| 2790 | #define SQ_ENC_SMEM_FIELD 0x30 | ||
| 2791 | #define SQ_ENC_VOP1_BITS 0x7e000000 | ||
| 2792 | #define SQ_ENC_VOP1_MASK 0xfe000000 | ||
| 2793 | #define SQ_ENC_VOP1_FIELD 0x3f | ||
| 2794 | #define SQ_ENC_VOPC_BITS 0x7c000000 | ||
| 2795 | #define SQ_ENC_VOPC_MASK 0xfe000000 | ||
| 2796 | #define SQ_ENC_VOPC_FIELD 0x3e | ||
| 2797 | #define SQ_ENC_VOP2_BITS 0x0 | ||
| 2798 | #define SQ_ENC_VOP2_MASK 0x80000000 | ||
| 2799 | #define SQ_ENC_VOP2_FIELD 0x0 | ||
| 2800 | #define SQ_ENC_VINTRP_BITS 0xd4000000 | ||
| 2801 | #define SQ_ENC_VINTRP_MASK 0xfc000000 | ||
| 2802 | #define SQ_ENC_VINTRP_FIELD 0x35 | ||
| 2803 | #define SQ_ENC_VOP3_BITS 0xd0000000 | ||
| 2804 | #define SQ_ENC_VOP3_MASK 0xfc000000 | ||
| 2805 | #define SQ_ENC_VOP3_FIELD 0x34 | ||
| 2806 | #define SQ_ENC_DS_BITS 0xd8000000 | ||
| 2807 | #define SQ_ENC_DS_MASK 0xfc000000 | ||
| 2808 | #define SQ_ENC_DS_FIELD 0x36 | ||
| 2809 | #define SQ_ENC_MUBUF_BITS 0xe0000000 | ||
| 2810 | #define SQ_ENC_MUBUF_MASK 0xfc000000 | ||
| 2811 | #define SQ_ENC_MUBUF_FIELD 0x38 | ||
| 2812 | #define SQ_ENC_MTBUF_BITS 0xe8000000 | ||
| 2813 | #define SQ_ENC_MTBUF_MASK 0xfc000000 | ||
| 2814 | #define SQ_ENC_MTBUF_FIELD 0x3a | ||
| 2815 | #define SQ_ENC_MIMG_BITS 0xf0000000 | ||
| 2816 | #define SQ_ENC_MIMG_MASK 0xfc000000 | ||
| 2817 | #define SQ_ENC_MIMG_FIELD 0x3c | ||
| 2818 | #define SQ_ENC_EXP_BITS 0xc4000000 | ||
| 2819 | #define SQ_ENC_EXP_MASK 0xfc000000 | ||
| 2820 | #define SQ_ENC_EXP_FIELD 0x31 | ||
| 2821 | #define SQ_ENC_FLAT_BITS 0xdc000000 | ||
| 2822 | #define SQ_ENC_FLAT_MASK 0xfc000000 | ||
| 2823 | #define SQ_ENC_FLAT_FIELD 0x37 | ||
| 2824 | #define SQ_V_OP3_INTRP_OFFSET 0x274 | ||
| 2825 | #define SQ_WAITCNT_VM_SHIFT 0x0 | ||
| 2826 | #define SQ_SENDMSG_STREAMID_SIZE 0x2 | ||
| 2827 | #define SQ_V_OPC_COUNT 0x100 | ||
| 2828 | #define SQ_V_OP3_INTRP_COUNT 0xc | ||
| 2829 | #define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100 | ||
| 2830 | #define SQ_HWREG_OFFSET_SIZE 0x5 | ||
| 2831 | #define SQ_HWREG_OFFSET_SHIFT 0x6 | ||
| 2832 | #define SQ_V_OP3_3IN_OFFSET 0x1c0 | ||
| 2833 | #define SQ_NUM_ATTR 0x21 | ||
| 2834 | #define SQ_NUM_VGPR 0x100 | ||
| 2835 | #define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4 | ||
| 2836 | #define SQ_SENDMSG_MSG_SIZE 0x4 | ||
| 2837 | #define SQ_NUM_TTMP 0xc | ||
| 2838 | #define SQ_HWREG_ID_SIZE 0x6 | ||
| 2839 | #define SQ_SENDMSG_GSOP_SIZE 0x2 | ||
| 2840 | #define SQ_NUM_SGPR 0x66 | ||
| 2841 | #define SQ_EXP_NUM_MRT 0x8 | ||
| 2842 | #define SQ_SENDMSG_SYSTEM_SIZE 0x3 | ||
| 2843 | #define SQ_WAITCNT_LGKM_SHIFT 0x8 | ||
| 2844 | #define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40 | ||
| 2845 | #define SQ_V_OP3_3IN_COUNT 0xb0 | ||
| 2846 | #define SQ_V_INTRP_COUNT 0x4 | ||
| 2847 | #define SQ_WAITCNT_EXP_SIZE 0x3 | ||
| 2848 | #define SQ_SENDMSG_SYSTEM_SHIFT 0x4 | ||
| 2849 | #define SQ_EXP_NUM_GDS 0x5 | ||
| 2850 | #define SQ_HWREG_SIZE_SHIFT 0xb | ||
| 2851 | #define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0 | ||
| 2852 | #define SQ_V_OP3_2IN_COUNT 0x80 | ||
| 2853 | #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270 | ||
| 2854 | #define SQ_SENDMSG_MSG_SHIFT 0x0 | ||
| 2855 | #define SQ_WAITCNT_EXP_SHIFT 0x4 | ||
| 2856 | #define SQ_WAITCNT_VM_SIZE 0x4 | ||
| 2857 | #define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140 | ||
| 2858 | #define SQ_SENDMSG_GSOP_SHIFT 0x4 | ||
| 2859 | #define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80 | ||
| 2860 | #define SQ_SRC_VGPR_BIT 0x100 | ||
| 2861 | #define SQ_V_OP2_COUNT 0x40 | ||
| 2862 | #define SQ_EXP_NUM_PARAM 0x20 | ||
| 2863 | #define SQ_V_OP1_COUNT 0x80 | ||
| 2864 | #define SQ_SENDMSG_STREAMID_SHIFT 0x8 | ||
| 2865 | #define SQ_V_OP3_2IN_OFFSET 0x280 | ||
| 2866 | #define SQ_WAITCNT_LGKM_SIZE 0x4 | ||
| 2867 | #define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100 | ||
| 2868 | #define SQ_EXP_NUM_POS 0x4 | ||
| 2869 | #define SQ_HWREG_SIZE_SIZE 0x5 | ||
| 2870 | #define SQ_HWREG_ID_SHIFT 0x0 | ||
| 2871 | #define SQ_S_MOV_B32 0x0 | ||
| 2872 | #define SQ_S_MOV_B64 0x1 | ||
| 2873 | #define SQ_S_CMOV_B32 0x2 | ||
| 2874 | #define SQ_S_CMOV_B64 0x3 | ||
| 2875 | #define SQ_S_NOT_B32 0x4 | ||
| 2876 | #define SQ_S_NOT_B64 0x5 | ||
| 2877 | #define SQ_S_WQM_B32 0x6 | ||
| 2878 | #define SQ_S_WQM_B64 0x7 | ||
| 2879 | #define SQ_S_BREV_B32 0x8 | ||
| 2880 | #define SQ_S_BREV_B64 0x9 | ||
| 2881 | #define SQ_S_BCNT0_I32_B32 0xa | ||
| 2882 | #define SQ_S_BCNT0_I32_B64 0xb | ||
| 2883 | #define SQ_S_BCNT1_I32_B32 0xc | ||
| 2884 | #define SQ_S_BCNT1_I32_B64 0xd | ||
| 2885 | #define SQ_S_FF0_I32_B32 0xe | ||
| 2886 | #define SQ_S_FF0_I32_B64 0xf | ||
| 2887 | #define SQ_S_FF1_I32_B32 0x10 | ||
| 2888 | #define SQ_S_FF1_I32_B64 0x11 | ||
| 2889 | #define SQ_S_FLBIT_I32_B32 0x12 | ||
| 2890 | #define SQ_S_FLBIT_I32_B64 0x13 | ||
| 2891 | #define SQ_S_FLBIT_I32 0x14 | ||
| 2892 | #define SQ_S_FLBIT_I32_I64 0x15 | ||
| 2893 | #define SQ_S_SEXT_I32_I8 0x16 | ||
| 2894 | #define SQ_S_SEXT_I32_I16 0x17 | ||
| 2895 | #define SQ_S_BITSET0_B32 0x18 | ||
| 2896 | #define SQ_S_BITSET0_B64 0x19 | ||
| 2897 | #define SQ_S_BITSET1_B32 0x1a | ||
| 2898 | #define SQ_S_BITSET1_B64 0x1b | ||
| 2899 | #define SQ_S_GETPC_B64 0x1c | ||
| 2900 | #define SQ_S_SETPC_B64 0x1d | ||
| 2901 | #define SQ_S_SWAPPC_B64 0x1e | ||
| 2902 | #define SQ_S_RFE_B64 0x1f | ||
| 2903 | #define SQ_S_AND_SAVEEXEC_B64 0x20 | ||
| 2904 | #define SQ_S_OR_SAVEEXEC_B64 0x21 | ||
| 2905 | #define SQ_S_XOR_SAVEEXEC_B64 0x22 | ||
| 2906 | #define SQ_S_ANDN2_SAVEEXEC_B64 0x23 | ||
| 2907 | #define SQ_S_ORN2_SAVEEXEC_B64 0x24 | ||
| 2908 | #define SQ_S_NAND_SAVEEXEC_B64 0x25 | ||
| 2909 | #define SQ_S_NOR_SAVEEXEC_B64 0x26 | ||
| 2910 | #define SQ_S_XNOR_SAVEEXEC_B64 0x27 | ||
| 2911 | #define SQ_S_QUADMASK_B32 0x28 | ||
| 2912 | #define SQ_S_QUADMASK_B64 0x29 | ||
| 2913 | #define SQ_S_MOVRELS_B32 0x2a | ||
| 2914 | #define SQ_S_MOVRELS_B64 0x2b | ||
| 2915 | #define SQ_S_MOVRELD_B32 0x2c | ||
| 2916 | #define SQ_S_MOVRELD_B64 0x2d | ||
| 2917 | #define SQ_S_CBRANCH_JOIN 0x2e | ||
| 2918 | #define SQ_S_MOV_REGRD_B32 0x2f | ||
| 2919 | #define SQ_S_ABS_I32 0x30 | ||
| 2920 | #define SQ_S_MOV_FED_B32 0x31 | ||
| 2921 | #define SQ_S_SET_GPR_IDX_IDX 0x32 | ||
| 2922 | #define SQ_ATTR0 0x0 | ||
| 2923 | #define SQ_S_MOVK_I32 0x0 | ||
| 2924 | #define SQ_S_CMOVK_I32 0x1 | ||
| 2925 | #define SQ_S_CMPK_EQ_I32 0x2 | ||
| 2926 | #define SQ_S_CMPK_LG_I32 0x3 | ||
| 2927 | #define SQ_S_CMPK_GT_I32 0x4 | ||
| 2928 | #define SQ_S_CMPK_GE_I32 0x5 | ||
| 2929 | #define SQ_S_CMPK_LT_I32 0x6 | ||
| 2930 | #define SQ_S_CMPK_LE_I32 0x7 | ||
| 2931 | #define SQ_S_CMPK_EQ_U32 0x8 | ||
| 2932 | #define SQ_S_CMPK_LG_U32 0x9 | ||
| 2933 | #define SQ_S_CMPK_GT_U32 0xa | ||
| 2934 | #define SQ_S_CMPK_GE_U32 0xb | ||
| 2935 | #define SQ_S_CMPK_LT_U32 0xc | ||
| 2936 | #define SQ_S_CMPK_LE_U32 0xd | ||
| 2937 | #define SQ_S_ADDK_I32 0xe | ||
| 2938 | #define SQ_S_MULK_I32 0xf | ||
| 2939 | #define SQ_S_CBRANCH_I_FORK 0x10 | ||
| 2940 | #define SQ_S_GETREG_B32 0x11 | ||
| 2941 | #define SQ_S_SETREG_B32 0x12 | ||
| 2942 | #define SQ_S_GETREG_REGRD_B32 0x13 | ||
| 2943 | #define SQ_S_SETREG_IMM32_B32 0x14 | ||
| 2944 | #define SQ_TBA_LO 0x6c | ||
| 2945 | #define SQ_TBA_HI 0x6d | ||
| 2946 | #define SQ_TMA_LO 0x6e | ||
| 2947 | #define SQ_TMA_HI 0x6f | ||
| 2948 | #define SQ_TTMP0 0x70 | ||
| 2949 | #define SQ_TTMP1 0x71 | ||
| 2950 | #define SQ_TTMP2 0x72 | ||
| 2951 | #define SQ_TTMP3 0x73 | ||
| 2952 | #define SQ_TTMP4 0x74 | ||
| 2953 | #define SQ_TTMP5 0x75 | ||
| 2954 | #define SQ_TTMP6 0x76 | ||
| 2955 | #define SQ_TTMP7 0x77 | ||
| 2956 | #define SQ_TTMP8 0x78 | ||
| 2957 | #define SQ_TTMP9 0x79 | ||
| 2958 | #define SQ_TTMP10 0x7a | ||
| 2959 | #define SQ_TTMP11 0x7b | ||
| 2960 | #define SQ_VGPR0 0x0 | ||
| 2961 | #define SQ_EXP 0x0 | ||
| 2962 | #define SQ_EXP_MRT0 0x0 | ||
| 2963 | #define SQ_EXP_MRTZ 0x8 | ||
| 2964 | #define SQ_EXP_NULL 0x9 | ||
| 2965 | #define SQ_EXP_POS0 0xc | ||
| 2966 | #define SQ_EXP_PARAM0 0x20 | ||
| 2967 | #define SQ_CNT1 0x0 | ||
| 2968 | #define SQ_CNT2 0x1 | ||
| 2969 | #define SQ_CNT3 0x2 | ||
| 2970 | #define SQ_CNT4 0x3 | ||
| 2971 | #define SQ_S_LOAD_DWORD 0x0 | ||
| 2972 | #define SQ_S_LOAD_DWORDX2 0x1 | ||
| 2973 | #define SQ_S_LOAD_DWORDX4 0x2 | ||
| 2974 | #define SQ_S_LOAD_DWORDX8 0x3 | ||
| 2975 | #define SQ_S_LOAD_DWORDX16 0x4 | ||
| 2976 | #define SQ_S_BUFFER_LOAD_DWORD 0x8 | ||
| 2977 | #define SQ_S_BUFFER_LOAD_DWORDX2 0x9 | ||
| 2978 | #define SQ_S_BUFFER_LOAD_DWORDX4 0xa | ||
| 2979 | #define SQ_S_BUFFER_LOAD_DWORDX8 0xb | ||
| 2980 | #define SQ_S_BUFFER_LOAD_DWORDX16 0xc | ||
| 2981 | #define SQ_S_STORE_DWORD 0x10 | ||
| 2982 | #define SQ_S_STORE_DWORDX2 0x11 | ||
| 2983 | #define SQ_S_STORE_DWORDX4 0x12 | ||
| 2984 | #define SQ_S_BUFFER_STORE_DWORD 0x18 | ||
| 2985 | #define SQ_S_BUFFER_STORE_DWORDX2 0x19 | ||
| 2986 | #define SQ_S_BUFFER_STORE_DWORDX4 0x1a | ||
| 2987 | #define SQ_S_DCACHE_INV 0x20 | ||
| 2988 | #define SQ_S_DCACHE_WB 0x21 | ||
| 2989 | #define SQ_S_DCACHE_INV_VOL 0x22 | ||
| 2990 | #define SQ_S_DCACHE_WB_VOL 0x23 | ||
| 2991 | #define SQ_S_MEMTIME 0x24 | ||
| 2992 | #define SQ_S_MEMREALTIME 0x25 | ||
| 2993 | #define SQ_S_ATC_PROBE 0x26 | ||
| 2994 | #define SQ_S_ATC_PROBE_BUFFER 0x27 | ||
| 2995 | #define SQ_S_BUFFER_ATOMIC_SWAP 0x40 | ||
| 2996 | #define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41 | ||
| 2997 | #define SQ_S_BUFFER_ATOMIC_ADD 0x42 | ||
| 2998 | #define SQ_S_BUFFER_ATOMIC_SUB 0x43 | ||
| 2999 | #define SQ_S_BUFFER_ATOMIC_SMIN 0x44 | ||
| 3000 | #define SQ_S_BUFFER_ATOMIC_UMIN 0x45 | ||
| 3001 | #define SQ_S_BUFFER_ATOMIC_SMAX 0x46 | ||
| 3002 | #define SQ_S_BUFFER_ATOMIC_UMAX 0x47 | ||
| 3003 | #define SQ_S_BUFFER_ATOMIC_AND 0x48 | ||
| 3004 | #define SQ_S_BUFFER_ATOMIC_OR 0x49 | ||
| 3005 | #define SQ_S_BUFFER_ATOMIC_XOR 0x4a | ||
| 3006 | #define SQ_S_BUFFER_ATOMIC_INC 0x4b | ||
| 3007 | #define SQ_S_BUFFER_ATOMIC_DEC 0x4c | ||
| 3008 | #define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60 | ||
| 3009 | #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61 | ||
| 3010 | #define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62 | ||
| 3011 | #define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63 | ||
| 3012 | #define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64 | ||
| 3013 | #define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65 | ||
| 3014 | #define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66 | ||
| 3015 | #define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67 | ||
| 3016 | #define SQ_S_BUFFER_ATOMIC_AND_X2 0x68 | ||
| 3017 | #define SQ_S_BUFFER_ATOMIC_OR_X2 0x69 | ||
| 3018 | #define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a | ||
| 3019 | #define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b | ||
| 3020 | #define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c | ||
| 3021 | #define SQ_F 0x0 | ||
| 3022 | #define SQ_LT 0x1 | ||
| 3023 | #define SQ_EQ 0x2 | ||
| 3024 | #define SQ_LE 0x3 | ||
| 3025 | #define SQ_GT 0x4 | ||
| 3026 | #define SQ_LG 0x5 | ||
| 3027 | #define SQ_GE 0x6 | ||
| 3028 | #define SQ_O 0x7 | ||
| 3029 | #define SQ_U 0x8 | ||
| 3030 | #define SQ_NGE 0x9 | ||
| 3031 | #define SQ_NLG 0xa | ||
| 3032 | #define SQ_NGT 0xb | ||
| 3033 | #define SQ_NLE 0xc | ||
| 3034 | #define SQ_NEQ 0xd | ||
| 3035 | #define SQ_NLT 0xe | ||
| 3036 | #define SQ_TRU 0xf | ||
| 3037 | #define SQ_V_CMP_CLASS_F32 0x10 | ||
| 3038 | #define SQ_V_CMPX_CLASS_F32 0x11 | ||
| 3039 | #define SQ_V_CMP_CLASS_F64 0x12 | ||
| 3040 | #define SQ_V_CMPX_CLASS_F64 0x13 | ||
| 3041 | #define SQ_V_CMP_CLASS_F16 0x14 | ||
| 3042 | #define SQ_V_CMPX_CLASS_F16 0x15 | ||
| 3043 | #define SQ_V_CMP_F_F16 0x20 | ||
| 3044 | #define SQ_V_CMP_LT_F16 0x21 | ||
| 3045 | #define SQ_V_CMP_EQ_F16 0x22 | ||
| 3046 | #define SQ_V_CMP_LE_F16 0x23 | ||
| 3047 | #define SQ_V_CMP_GT_F16 0x24 | ||
| 3048 | #define SQ_V_CMP_LG_F16 0x25 | ||
| 3049 | #define SQ_V_CMP_GE_F16 0x26 | ||
| 3050 | #define SQ_V_CMP_O_F16 0x27 | ||
| 3051 | #define SQ_V_CMP_U_F16 0x28 | ||
| 3052 | #define SQ_V_CMP_NGE_F16 0x29 | ||
| 3053 | #define SQ_V_CMP_NLG_F16 0x2a | ||
| 3054 | #define SQ_V_CMP_NGT_F16 0x2b | ||
| 3055 | #define SQ_V_CMP_NLE_F16 0x2c | ||
| 3056 | #define SQ_V_CMP_NEQ_F16 0x2d | ||
| 3057 | #define SQ_V_CMP_NLT_F16 0x2e | ||
| 3058 | #define SQ_V_CMP_TRU_F16 0x2f | ||
| 3059 | #define SQ_V_CMPX_F_F16 0x30 | ||
| 3060 | #define SQ_V_CMPX_LT_F16 0x31 | ||
| 3061 | #define SQ_V_CMPX_EQ_F16 0x32 | ||
| 3062 | #define SQ_V_CMPX_LE_F16 0x33 | ||
| 3063 | #define SQ_V_CMPX_GT_F16 0x34 | ||
| 3064 | #define SQ_V_CMPX_LG_F16 0x35 | ||
| 3065 | #define SQ_V_CMPX_GE_F16 0x36 | ||
| 3066 | #define SQ_V_CMPX_O_F16 0x37 | ||
| 3067 | #define SQ_V_CMPX_U_F16 0x38 | ||
| 3068 | #define SQ_V_CMPX_NGE_F16 0x39 | ||
| 3069 | #define SQ_V_CMPX_NLG_F16 0x3a | ||
| 3070 | #define SQ_V_CMPX_NGT_F16 0x3b | ||
| 3071 | #define SQ_V_CMPX_NLE_F16 0x3c | ||
| 3072 | #define SQ_V_CMPX_NEQ_F16 0x3d | ||
| 3073 | #define SQ_V_CMPX_NLT_F16 0x3e | ||
| 3074 | #define SQ_V_CMPX_TRU_F16 0x3f | ||
| 3075 | #define SQ_V_CMP_F_F32 0x40 | ||
| 3076 | #define SQ_V_CMP_LT_F32 0x41 | ||
| 3077 | #define SQ_V_CMP_EQ_F32 0x42 | ||
| 3078 | #define SQ_V_CMP_LE_F32 0x43 | ||
| 3079 | #define SQ_V_CMP_GT_F32 0x44 | ||
| 3080 | #define SQ_V_CMP_LG_F32 0x45 | ||
| 3081 | #define SQ_V_CMP_GE_F32 0x46 | ||
| 3082 | #define SQ_V_CMP_O_F32 0x47 | ||
| 3083 | #define SQ_V_CMP_U_F32 0x48 | ||
| 3084 | #define SQ_V_CMP_NGE_F32 0x49 | ||
| 3085 | #define SQ_V_CMP_NLG_F32 0x4a | ||
| 3086 | #define SQ_V_CMP_NGT_F32 0x4b | ||
| 3087 | #define SQ_V_CMP_NLE_F32 0x4c | ||
| 3088 | #define SQ_V_CMP_NEQ_F32 0x4d | ||
| 3089 | #define SQ_V_CMP_NLT_F32 0x4e | ||
| 3090 | #define SQ_V_CMP_TRU_F32 0x4f | ||
| 3091 | #define SQ_V_CMPX_F_F32 0x50 | ||
| 3092 | #define SQ_V_CMPX_LT_F32 0x51 | ||
| 3093 | #define SQ_V_CMPX_EQ_F32 0x52 | ||
| 3094 | #define SQ_V_CMPX_LE_F32 0x53 | ||
| 3095 | #define SQ_V_CMPX_GT_F32 0x54 | ||
| 3096 | #define SQ_V_CMPX_LG_F32 0x55 | ||
| 3097 | #define SQ_V_CMPX_GE_F32 0x56 | ||
| 3098 | #define SQ_V_CMPX_O_F32 0x57 | ||
| 3099 | #define SQ_V_CMPX_U_F32 0x58 | ||
| 3100 | #define SQ_V_CMPX_NGE_F32 0x59 | ||
| 3101 | #define SQ_V_CMPX_NLG_F32 0x5a | ||
| 3102 | #define SQ_V_CMPX_NGT_F32 0x5b | ||
| 3103 | #define SQ_V_CMPX_NLE_F32 0x5c | ||
| 3104 | #define SQ_V_CMPX_NEQ_F32 0x5d | ||
| 3105 | #define SQ_V_CMPX_NLT_F32 0x5e | ||
| 3106 | #define SQ_V_CMPX_TRU_F32 0x5f | ||
| 3107 | #define SQ_V_CMP_F_F64 0x60 | ||
| 3108 | #define SQ_V_CMP_LT_F64 0x61 | ||
| 3109 | #define SQ_V_CMP_EQ_F64 0x62 | ||
| 3110 | #define SQ_V_CMP_LE_F64 0x63 | ||
| 3111 | #define SQ_V_CMP_GT_F64 0x64 | ||
| 3112 | #define SQ_V_CMP_LG_F64 0x65 | ||
| 3113 | #define SQ_V_CMP_GE_F64 0x66 | ||
| 3114 | #define SQ_V_CMP_O_F64 0x67 | ||
| 3115 | #define SQ_V_CMP_U_F64 0x68 | ||
| 3116 | #define SQ_V_CMP_NGE_F64 0x69 | ||
| 3117 | #define SQ_V_CMP_NLG_F64 0x6a | ||
| 3118 | #define SQ_V_CMP_NGT_F64 0x6b | ||
| 3119 | #define SQ_V_CMP_NLE_F64 0x6c | ||
| 3120 | #define SQ_V_CMP_NEQ_F64 0x6d | ||
| 3121 | #define SQ_V_CMP_NLT_F64 0x6e | ||
| 3122 | #define SQ_V_CMP_TRU_F64 0x6f | ||
| 3123 | #define SQ_V_CMPX_F_F64 0x70 | ||
| 3124 | #define SQ_V_CMPX_LT_F64 0x71 | ||
| 3125 | #define SQ_V_CMPX_EQ_F64 0x72 | ||
| 3126 | #define SQ_V_CMPX_LE_F64 0x73 | ||
| 3127 | #define SQ_V_CMPX_GT_F64 0x74 | ||
| 3128 | #define SQ_V_CMPX_LG_F64 0x75 | ||
| 3129 | #define SQ_V_CMPX_GE_F64 0x76 | ||
| 3130 | #define SQ_V_CMPX_O_F64 0x77 | ||
| 3131 | #define SQ_V_CMPX_U_F64 0x78 | ||
| 3132 | #define SQ_V_CMPX_NGE_F64 0x79 | ||
| 3133 | #define SQ_V_CMPX_NLG_F64 0x7a | ||
| 3134 | #define SQ_V_CMPX_NGT_F64 0x7b | ||
| 3135 | #define SQ_V_CMPX_NLE_F64 0x7c | ||
| 3136 | #define SQ_V_CMPX_NEQ_F64 0x7d | ||
| 3137 | #define SQ_V_CMPX_NLT_F64 0x7e | ||
| 3138 | #define SQ_V_CMPX_TRU_F64 0x7f | ||
| 3139 | #define SQ_V_CMP_F_I16 0xa0 | ||
| 3140 | #define SQ_V_CMP_LT_I16 0xa1 | ||
| 3141 | #define SQ_V_CMP_EQ_I16 0xa2 | ||
| 3142 | #define SQ_V_CMP_LE_I16 0xa3 | ||
| 3143 | #define SQ_V_CMP_GT_I16 0xa4 | ||
| 3144 | #define SQ_V_CMP_NE_I16 0xa5 | ||
| 3145 | #define SQ_V_CMP_GE_I16 0xa6 | ||
| 3146 | #define SQ_V_CMP_T_I16 0xa7 | ||
| 3147 | #define SQ_V_CMP_F_U16 0xa8 | ||
| 3148 | #define SQ_V_CMP_LT_U16 0xa9 | ||
| 3149 | #define SQ_V_CMP_EQ_U16 0xaa | ||
| 3150 | #define SQ_V_CMP_LE_U16 0xab | ||
| 3151 | #define SQ_V_CMP_GT_U16 0xac | ||
| 3152 | #define SQ_V_CMP_NE_U16 0xad | ||
| 3153 | #define SQ_V_CMP_GE_U16 0xae | ||
| 3154 | #define SQ_V_CMP_T_U16 0xaf | ||
| 3155 | #define SQ_V_CMPX_F_I16 0xb0 | ||
| 3156 | #define SQ_V_CMPX_LT_I16 0xb1 | ||
| 3157 | #define SQ_V_CMPX_EQ_I16 0xb2 | ||
| 3158 | #define SQ_V_CMPX_LE_I16 0xb3 | ||
| 3159 | #define SQ_V_CMPX_GT_I16 0xb4 | ||
| 3160 | #define SQ_V_CMPX_NE_I16 0xb5 | ||
| 3161 | #define SQ_V_CMPX_GE_I16 0xb6 | ||
| 3162 | #define SQ_V_CMPX_T_I16 0xb7 | ||
| 3163 | #define SQ_V_CMPX_F_U16 0xb8 | ||
| 3164 | #define SQ_V_CMPX_LT_U16 0xb9 | ||
| 3165 | #define SQ_V_CMPX_EQ_U16 0xba | ||
| 3166 | #define SQ_V_CMPX_LE_U16 0xbb | ||
| 3167 | #define SQ_V_CMPX_GT_U16 0xbc | ||
| 3168 | #define SQ_V_CMPX_NE_U16 0xbd | ||
| 3169 | #define SQ_V_CMPX_GE_U16 0xbe | ||
| 3170 | #define SQ_V_CMPX_T_U16 0xbf | ||
| 3171 | #define SQ_V_CMP_F_I32 0xc0 | ||
| 3172 | #define SQ_V_CMP_LT_I32 0xc1 | ||
| 3173 | #define SQ_V_CMP_EQ_I32 0xc2 | ||
| 3174 | #define SQ_V_CMP_LE_I32 0xc3 | ||
| 3175 | #define SQ_V_CMP_GT_I32 0xc4 | ||
| 3176 | #define SQ_V_CMP_NE_I32 0xc5 | ||
| 3177 | #define SQ_V_CMP_GE_I32 0xc6 | ||
| 3178 | #define SQ_V_CMP_T_I32 0xc7 | ||
| 3179 | #define SQ_V_CMP_F_U32 0xc8 | ||
| 3180 | #define SQ_V_CMP_LT_U32 0xc9 | ||
| 3181 | #define SQ_V_CMP_EQ_U32 0xca | ||
| 3182 | #define SQ_V_CMP_LE_U32 0xcb | ||
| 3183 | #define SQ_V_CMP_GT_U32 0xcc | ||
| 3184 | #define SQ_V_CMP_NE_U32 0xcd | ||
| 3185 | #define SQ_V_CMP_GE_U32 0xce | ||
| 3186 | #define SQ_V_CMP_T_U32 0xcf | ||
| 3187 | #define SQ_V_CMPX_F_I32 0xd0 | ||
| 3188 | #define SQ_V_CMPX_LT_I32 0xd1 | ||
| 3189 | #define SQ_V_CMPX_EQ_I32 0xd2 | ||
| 3190 | #define SQ_V_CMPX_LE_I32 0xd3 | ||
| 3191 | #define SQ_V_CMPX_GT_I32 0xd4 | ||
| 3192 | #define SQ_V_CMPX_NE_I32 0xd5 | ||
| 3193 | #define SQ_V_CMPX_GE_I32 0xd6 | ||
| 3194 | #define SQ_V_CMPX_T_I32 0xd7 | ||
| 3195 | #define SQ_V_CMPX_F_U32 0xd8 | ||
| 3196 | #define SQ_V_CMPX_LT_U32 0xd9 | ||
| 3197 | #define SQ_V_CMPX_EQ_U32 0xda | ||
| 3198 | #define SQ_V_CMPX_LE_U32 0xdb | ||
| 3199 | #define SQ_V_CMPX_GT_U32 0xdc | ||
| 3200 | #define SQ_V_CMPX_NE_U32 0xdd | ||
| 3201 | #define SQ_V_CMPX_GE_U32 0xde | ||
| 3202 | #define SQ_V_CMPX_T_U32 0xdf | ||
| 3203 | #define SQ_V_CMP_F_I64 0xe0 | ||
| 3204 | #define SQ_V_CMP_LT_I64 0xe1 | ||
| 3205 | #define SQ_V_CMP_EQ_I64 0xe2 | ||
| 3206 | #define SQ_V_CMP_LE_I64 0xe3 | ||
| 3207 | #define SQ_V_CMP_GT_I64 0xe4 | ||
| 3208 | #define SQ_V_CMP_NE_I64 0xe5 | ||
| 3209 | #define SQ_V_CMP_GE_I64 0xe6 | ||
| 3210 | #define SQ_V_CMP_T_I64 0xe7 | ||
| 3211 | #define SQ_V_CMP_F_U64 0xe8 | ||
| 3212 | #define SQ_V_CMP_LT_U64 0xe9 | ||
| 3213 | #define SQ_V_CMP_EQ_U64 0xea | ||
| 3214 | #define SQ_V_CMP_LE_U64 0xeb | ||
| 3215 | #define SQ_V_CMP_GT_U64 0xec | ||
| 3216 | #define SQ_V_CMP_NE_U64 0xed | ||
| 3217 | #define SQ_V_CMP_GE_U64 0xee | ||
| 3218 | #define SQ_V_CMP_T_U64 0xef | ||
| 3219 | #define SQ_V_CMPX_F_I64 0xf0 | ||
| 3220 | #define SQ_V_CMPX_LT_I64 0xf1 | ||
| 3221 | #define SQ_V_CMPX_EQ_I64 0xf2 | ||
| 3222 | #define SQ_V_CMPX_LE_I64 0xf3 | ||
| 3223 | #define SQ_V_CMPX_GT_I64 0xf4 | ||
| 3224 | #define SQ_V_CMPX_NE_I64 0xf5 | ||
| 3225 | #define SQ_V_CMPX_GE_I64 0xf6 | ||
| 3226 | #define SQ_V_CMPX_T_I64 0xf7 | ||
| 3227 | #define SQ_V_CMPX_F_U64 0xf8 | ||
| 3228 | #define SQ_V_CMPX_LT_U64 0xf9 | ||
| 3229 | #define SQ_V_CMPX_EQ_U64 0xfa | ||
| 3230 | #define SQ_V_CMPX_LE_U64 0xfb | ||
| 3231 | #define SQ_V_CMPX_GT_U64 0xfc | ||
| 3232 | #define SQ_V_CMPX_NE_U64 0xfd | ||
| 3233 | #define SQ_V_CMPX_GE_U64 0xfe | ||
| 3234 | #define SQ_V_CMPX_T_U64 0xff | ||
| 3235 | #define SQ_L1 0x1 | ||
| 3236 | #define SQ_L2 0x2 | ||
| 3237 | #define SQ_L3 0x3 | ||
| 3238 | #define SQ_L4 0x4 | ||
| 3239 | #define SQ_L5 0x5 | ||
| 3240 | #define SQ_L6 0x6 | ||
| 3241 | #define SQ_L7 0x7 | ||
| 3242 | #define SQ_L8 0x8 | ||
| 3243 | #define SQ_L9 0x9 | ||
| 3244 | #define SQ_L10 0xa | ||
| 3245 | #define SQ_L11 0xb | ||
| 3246 | #define SQ_L12 0xc | ||
| 3247 | #define SQ_L13 0xd | ||
| 3248 | #define SQ_L14 0xe | ||
| 3249 | #define SQ_L15 0xf | ||
| 3250 | #define SQ_SGPR0 0x0 | ||
| 3251 | #define SQ_SDWA_UNUSED_PAD 0x0 | ||
| 3252 | #define SQ_SDWA_UNUSED_SEXT 0x1 | ||
| 3253 | #define SQ_SDWA_UNUSED_PRESERVE 0x2 | ||
| 3254 | #define SQ_F 0x0 | ||
| 3255 | #define SQ_LT 0x1 | ||
| 3256 | #define SQ_EQ 0x2 | ||
| 3257 | #define SQ_LE 0x3 | ||
| 3258 | #define SQ_GT 0x4 | ||
| 3259 | #define SQ_NE 0x5 | ||
| 3260 | #define SQ_GE 0x6 | ||
| 3261 | #define SQ_T 0x7 | ||
| 3262 | #define SQ_SRC_64_INT 0xc0 | ||
| 3263 | #define SQ_SRC_M_1_INT 0xc1 | ||
| 3264 | #define SQ_SRC_M_2_INT 0xc2 | ||
| 3265 | #define SQ_SRC_M_3_INT 0xc3 | ||
| 3266 | #define SQ_SRC_M_4_INT 0xc4 | ||
| 3267 | #define SQ_SRC_M_5_INT 0xc5 | ||
| 3268 | #define SQ_SRC_M_6_INT 0xc6 | ||
| 3269 | #define SQ_SRC_M_7_INT 0xc7 | ||
| 3270 | #define SQ_SRC_M_8_INT 0xc8 | ||
| 3271 | #define SQ_SRC_M_9_INT 0xc9 | ||
| 3272 | #define SQ_SRC_M_10_INT 0xca | ||
| 3273 | #define SQ_SRC_M_11_INT 0xcb | ||
| 3274 | #define SQ_SRC_M_12_INT 0xcc | ||
| 3275 | #define SQ_SRC_M_13_INT 0xcd | ||
| 3276 | #define SQ_SRC_M_14_INT 0xce | ||
| 3277 | #define SQ_SRC_M_15_INT 0xcf | ||
| 3278 | #define SQ_SRC_M_16_INT 0xd0 | ||
| 3279 | #define SQ_SRC_0_5 0xf0 | ||
| 3280 | #define SQ_SRC_M_0_5 0xf1 | ||
| 3281 | #define SQ_SRC_1 0xf2 | ||
| 3282 | #define SQ_SRC_M_1 0xf3 | ||
| 3283 | #define SQ_SRC_2 0xf4 | ||
| 3284 | #define SQ_SRC_M_2 0xf5 | ||
| 3285 | #define SQ_SRC_4 0xf6 | ||
| 3286 | #define SQ_SRC_M_4 0xf7 | ||
| 3287 | #define SQ_SRC_INV_2PI 0xf8 | ||
| 3288 | #define SQ_SRC_0 0x80 | ||
| 3289 | #define SQ_SRC_1_INT 0x81 | ||
| 3290 | #define SQ_SRC_2_INT 0x82 | ||
| 3291 | #define SQ_SRC_3_INT 0x83 | ||
| 3292 | #define SQ_SRC_4_INT 0x84 | ||
| 3293 | #define SQ_SRC_5_INT 0x85 | ||
| 3294 | #define SQ_SRC_6_INT 0x86 | ||
| 3295 | #define SQ_SRC_7_INT 0x87 | ||
| 3296 | #define SQ_SRC_8_INT 0x88 | ||
| 3297 | #define SQ_SRC_9_INT 0x89 | ||
| 3298 | #define SQ_SRC_10_INT 0x8a | ||
| 3299 | #define SQ_SRC_11_INT 0x8b | ||
| 3300 | #define SQ_SRC_12_INT 0x8c | ||
| 3301 | #define SQ_SRC_13_INT 0x8d | ||
| 3302 | #define SQ_SRC_14_INT 0x8e | ||
| 3303 | #define SQ_SRC_15_INT 0x8f | ||
| 3304 | #define SQ_SRC_16_INT 0x90 | ||
| 3305 | #define SQ_SRC_17_INT 0x91 | ||
| 3306 | #define SQ_SRC_18_INT 0x92 | ||
| 3307 | #define SQ_SRC_19_INT 0x93 | ||
| 3308 | #define SQ_SRC_20_INT 0x94 | ||
| 3309 | #define SQ_SRC_21_INT 0x95 | ||
| 3310 | #define SQ_SRC_22_INT 0x96 | ||
| 3311 | #define SQ_SRC_23_INT 0x97 | ||
| 3312 | #define SQ_SRC_24_INT 0x98 | ||
| 3313 | #define SQ_SRC_25_INT 0x99 | ||
| 3314 | #define SQ_SRC_26_INT 0x9a | ||
| 3315 | #define SQ_SRC_27_INT 0x9b | ||
| 3316 | #define SQ_SRC_28_INT 0x9c | ||
| 3317 | #define SQ_SRC_29_INT 0x9d | ||
| 3318 | #define SQ_SRC_30_INT 0x9e | ||
| 3319 | #define SQ_SRC_31_INT 0x9f | ||
| 3320 | #define SQ_SRC_32_INT 0xa0 | ||
| 3321 | #define SQ_SRC_33_INT 0xa1 | ||
| 3322 | #define SQ_SRC_34_INT 0xa2 | ||
| 3323 | #define SQ_SRC_35_INT 0xa3 | ||
| 3324 | #define SQ_SRC_36_INT 0xa4 | ||
| 3325 | #define SQ_SRC_37_INT 0xa5 | ||
| 3326 | #define SQ_SRC_38_INT 0xa6 | ||
| 3327 | #define SQ_SRC_39_INT 0xa7 | ||
| 3328 | #define SQ_SRC_40_INT 0xa8 | ||
| 3329 | #define SQ_SRC_41_INT 0xa9 | ||
| 3330 | #define SQ_SRC_42_INT 0xaa | ||
| 3331 | #define SQ_SRC_43_INT 0xab | ||
| 3332 | #define SQ_SRC_44_INT 0xac | ||
| 3333 | #define SQ_SRC_45_INT 0xad | ||
| 3334 | #define SQ_SRC_46_INT 0xae | ||
| 3335 | #define SQ_SRC_47_INT 0xaf | ||
| 3336 | #define SQ_SRC_48_INT 0xb0 | ||
| 3337 | #define SQ_SRC_49_INT 0xb1 | ||
| 3338 | #define SQ_SRC_50_INT 0xb2 | ||
| 3339 | #define SQ_SRC_51_INT 0xb3 | ||
| 3340 | #define SQ_SRC_52_INT 0xb4 | ||
| 3341 | #define SQ_SRC_53_INT 0xb5 | ||
| 3342 | #define SQ_SRC_54_INT 0xb6 | ||
| 3343 | #define SQ_SRC_55_INT 0xb7 | ||
| 3344 | #define SQ_SRC_56_INT 0xb8 | ||
| 3345 | #define SQ_SRC_57_INT 0xb9 | ||
| 3346 | #define SQ_SRC_58_INT 0xba | ||
| 3347 | #define SQ_SRC_59_INT 0xbb | ||
| 3348 | #define SQ_SRC_60_INT 0xbc | ||
| 3349 | #define SQ_SRC_61_INT 0xbd | ||
| 3350 | #define SQ_SRC_62_INT 0xbe | ||
| 3351 | #define SQ_SRC_63_INT 0xbf | ||
| 3352 | #define SQ_DS_ADD_U32 0x0 | ||
| 3353 | #define SQ_DS_SUB_U32 0x1 | ||
| 3354 | #define SQ_DS_RSUB_U32 0x2 | ||
| 3355 | #define SQ_DS_INC_U32 0x3 | ||
| 3356 | #define SQ_DS_DEC_U32 0x4 | ||
| 3357 | #define SQ_DS_MIN_I32 0x5 | ||
| 3358 | #define SQ_DS_MAX_I32 0x6 | ||
| 3359 | #define SQ_DS_MIN_U32 0x7 | ||
| 3360 | #define SQ_DS_MAX_U32 0x8 | ||
| 3361 | #define SQ_DS_AND_B32 0x9 | ||
| 3362 | #define SQ_DS_OR_B32 0xa | ||
| 3363 | #define SQ_DS_XOR_B32 0xb | ||
| 3364 | #define SQ_DS_MSKOR_B32 0xc | ||
| 3365 | #define SQ_DS_WRITE_B32 0xd | ||
| 3366 | #define SQ_DS_WRITE2_B32 0xe | ||
| 3367 | #define SQ_DS_WRITE2ST64_B32 0xf | ||
| 3368 | #define SQ_DS_CMPST_B32 0x10 | ||
| 3369 | #define SQ_DS_CMPST_F32 0x11 | ||
| 3370 | #define SQ_DS_MIN_F32 0x12 | ||
| 3371 | #define SQ_DS_MAX_F32 0x13 | ||
| 3372 | #define SQ_DS_NOP 0x14 | ||
| 3373 | #define SQ_DS_ADD_F32 0x15 | ||
| 3374 | #define SQ_DS_WRITE_B8 0x1e | ||
| 3375 | #define SQ_DS_WRITE_B16 0x1f | ||
| 3376 | #define SQ_DS_ADD_RTN_U32 0x20 | ||
| 3377 | #define SQ_DS_SUB_RTN_U32 0x21 | ||
| 3378 | #define SQ_DS_RSUB_RTN_U32 0x22 | ||
| 3379 | #define SQ_DS_INC_RTN_U32 0x23 | ||
| 3380 | #define SQ_DS_DEC_RTN_U32 0x24 | ||
| 3381 | #define SQ_DS_MIN_RTN_I32 0x25 | ||
| 3382 | #define SQ_DS_MAX_RTN_I32 0x26 | ||
| 3383 | #define SQ_DS_MIN_RTN_U32 0x27 | ||
| 3384 | #define SQ_DS_MAX_RTN_U32 0x28 | ||
| 3385 | #define SQ_DS_AND_RTN_B32 0x29 | ||
| 3386 | #define SQ_DS_OR_RTN_B32 0x2a | ||
| 3387 | #define SQ_DS_XOR_RTN_B32 0x2b | ||
| 3388 | #define SQ_DS_MSKOR_RTN_B32 0x2c | ||
| 3389 | #define SQ_DS_WRXCHG_RTN_B32 0x2d | ||
| 3390 | #define SQ_DS_WRXCHG2_RTN_B32 0x2e | ||
| 3391 | #define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f | ||
| 3392 | #define SQ_DS_CMPST_RTN_B32 0x30 | ||
| 3393 | #define SQ_DS_CMPST_RTN_F32 0x31 | ||
| 3394 | #define SQ_DS_MIN_RTN_F32 0x32 | ||
| 3395 | #define SQ_DS_MAX_RTN_F32 0x33 | ||
| 3396 | #define SQ_DS_WRAP_RTN_B32 0x34 | ||
| 3397 | #define SQ_DS_ADD_RTN_F32 0x35 | ||
| 3398 | #define SQ_DS_READ_B32 0x36 | ||
| 3399 | #define SQ_DS_READ2_B32 0x37 | ||
| 3400 | #define SQ_DS_READ2ST64_B32 0x38 | ||
| 3401 | #define SQ_DS_READ_I8 0x39 | ||
| 3402 | #define SQ_DS_READ_U8 0x3a | ||
| 3403 | #define SQ_DS_READ_I16 0x3b | ||
| 3404 | #define SQ_DS_READ_U16 0x3c | ||
| 3405 | #define SQ_DS_SWIZZLE_B32 0x3d | ||
| 3406 | #define SQ_DS_PERMUTE_B32 0x3e | ||
| 3407 | #define SQ_DS_BPERMUTE_B32 0x3f | ||
| 3408 | #define SQ_DS_ADD_U64 0x40 | ||
| 3409 | #define SQ_DS_SUB_U64 0x41 | ||
| 3410 | #define SQ_DS_RSUB_U64 0x42 | ||
| 3411 | #define SQ_DS_INC_U64 0x43 | ||
| 3412 | #define SQ_DS_DEC_U64 0x44 | ||
| 3413 | #define SQ_DS_MIN_I64 0x45 | ||
| 3414 | #define SQ_DS_MAX_I64 0x46 | ||
| 3415 | #define SQ_DS_MIN_U64 0x47 | ||
| 3416 | #define SQ_DS_MAX_U64 0x48 | ||
| 3417 | #define SQ_DS_AND_B64 0x49 | ||
| 3418 | #define SQ_DS_OR_B64 0x4a | ||
| 3419 | #define SQ_DS_XOR_B64 0x4b | ||
| 3420 | #define SQ_DS_MSKOR_B64 0x4c | ||
| 3421 | #define SQ_DS_WRITE_B64 0x4d | ||
| 3422 | #define SQ_DS_WRITE2_B64 0x4e | ||
| 3423 | #define SQ_DS_WRITE2ST64_B64 0x4f | ||
| 3424 | #define SQ_DS_CMPST_B64 0x50 | ||
| 3425 | #define SQ_DS_CMPST_F64 0x51 | ||
| 3426 | #define SQ_DS_MIN_F64 0x52 | ||
| 3427 | #define SQ_DS_MAX_F64 0x53 | ||
| 3428 | #define SQ_DS_ADD_RTN_U64 0x60 | ||
| 3429 | #define SQ_DS_SUB_RTN_U64 0x61 | ||
| 3430 | #define SQ_DS_RSUB_RTN_U64 0x62 | ||
| 3431 | #define SQ_DS_INC_RTN_U64 0x63 | ||
| 3432 | #define SQ_DS_DEC_RTN_U64 0x64 | ||
| 3433 | #define SQ_DS_MIN_RTN_I64 0x65 | ||
| 3434 | #define SQ_DS_MAX_RTN_I64 0x66 | ||
| 3435 | #define SQ_DS_MIN_RTN_U64 0x67 | ||
| 3436 | #define SQ_DS_MAX_RTN_U64 0x68 | ||
| 3437 | #define SQ_DS_AND_RTN_B64 0x69 | ||
| 3438 | #define SQ_DS_OR_RTN_B64 0x6a | ||
| 3439 | #define SQ_DS_XOR_RTN_B64 0x6b | ||
| 3440 | #define SQ_DS_MSKOR_RTN_B64 0x6c | ||
| 3441 | #define SQ_DS_WRXCHG_RTN_B64 0x6d | ||
| 3442 | #define SQ_DS_WRXCHG2_RTN_B64 0x6e | ||
| 3443 | #define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f | ||
| 3444 | #define SQ_DS_CMPST_RTN_B64 0x70 | ||
| 3445 | #define SQ_DS_CMPST_RTN_F64 0x71 | ||
| 3446 | #define SQ_DS_MIN_RTN_F64 0x72 | ||
| 3447 | #define SQ_DS_MAX_RTN_F64 0x73 | ||
| 3448 | #define SQ_DS_READ_B64 0x76 | ||
| 3449 | #define SQ_DS_READ2_B64 0x77 | ||
| 3450 | #define SQ_DS_READ2ST64_B64 0x78 | ||
| 3451 | #define SQ_DS_CONDXCHG32_RTN_B64 0x7e | ||
| 3452 | #define SQ_DS_ADD_SRC2_U32 0x80 | ||
| 3453 | #define SQ_DS_SUB_SRC2_U32 0x81 | ||
| 3454 | #define SQ_DS_RSUB_SRC2_U32 0x82 | ||
| 3455 | #define SQ_DS_INC_SRC2_U32 0x83 | ||
| 3456 | #define SQ_DS_DEC_SRC2_U32 0x84 | ||
| 3457 | #define SQ_DS_MIN_SRC2_I32 0x85 | ||
| 3458 | #define SQ_DS_MAX_SRC2_I32 0x86 | ||
| 3459 | #define SQ_DS_MIN_SRC2_U32 0x87 | ||
| 3460 | #define SQ_DS_MAX_SRC2_U32 0x88 | ||
| 3461 | #define SQ_DS_AND_SRC2_B32 0x89 | ||
| 3462 | #define SQ_DS_OR_SRC2_B32 0x8a | ||
| 3463 | #define SQ_DS_XOR_SRC2_B32 0x8b | ||
| 3464 | #define SQ_DS_WRITE_SRC2_B32 0x8d | ||
| 3465 | #define SQ_DS_MIN_SRC2_F32 0x92 | ||
| 3466 | #define SQ_DS_MAX_SRC2_F32 0x93 | ||
| 3467 | #define SQ_DS_ADD_SRC2_F32 0x95 | ||
| 3468 | #define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98 | ||
| 3469 | #define SQ_DS_GWS_INIT 0x99 | ||
| 3470 | #define SQ_DS_GWS_SEMA_V 0x9a | ||
| 3471 | #define SQ_DS_GWS_SEMA_BR 0x9b | ||
| 3472 | #define SQ_DS_GWS_SEMA_P 0x9c | ||
| 3473 | #define SQ_DS_GWS_BARRIER 0x9d | ||
| 3474 | #define SQ_DS_CONSUME 0xbd | ||
| 3475 | #define SQ_DS_APPEND 0xbe | ||
| 3476 | #define SQ_DS_ORDERED_COUNT 0xbf | ||
| 3477 | #define SQ_DS_ADD_SRC2_U64 0xc0 | ||
| 3478 | #define SQ_DS_SUB_SRC2_U64 0xc1 | ||
| 3479 | #define SQ_DS_RSUB_SRC2_U64 0xc2 | ||
| 3480 | #define SQ_DS_INC_SRC2_U64 0xc3 | ||
| 3481 | #define SQ_DS_DEC_SRC2_U64 0xc4 | ||
| 3482 | #define SQ_DS_MIN_SRC2_I64 0xc5 | ||
| 3483 | #define SQ_DS_MAX_SRC2_I64 0xc6 | ||
| 3484 | #define SQ_DS_MIN_SRC2_U64 0xc7 | ||
| 3485 | #define SQ_DS_MAX_SRC2_U64 0xc8 | ||
| 3486 | #define SQ_DS_AND_SRC2_B64 0xc9 | ||
| 3487 | #define SQ_DS_OR_SRC2_B64 0xca | ||
| 3488 | #define SQ_DS_XOR_SRC2_B64 0xcb | ||
| 3489 | #define SQ_DS_WRITE_SRC2_B64 0xcd | ||
| 3490 | #define SQ_DS_MIN_SRC2_F64 0xd2 | ||
| 3491 | #define SQ_DS_MAX_SRC2_F64 0xd3 | ||
| 3492 | #define SQ_DS_WRITE_B96 0xde | ||
| 3493 | #define SQ_DS_WRITE_B128 0xdf | ||
| 3494 | #define SQ_DS_CONDXCHG32_RTN_B128 0xfd | ||
| 3495 | #define SQ_DS_READ_B96 0xfe | ||
| 3496 | #define SQ_DS_READ_B128 0xff | ||
| 3497 | #define SQ_BUFFER_LOAD_FORMAT_X 0x0 | ||
| 3498 | #define SQ_BUFFER_LOAD_FORMAT_XY 0x1 | ||
| 3499 | #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 | ||
| 3500 | #define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 | ||
| 3501 | #define SQ_BUFFER_STORE_FORMAT_X 0x4 | ||
| 3502 | #define SQ_BUFFER_STORE_FORMAT_XY 0x5 | ||
| 3503 | #define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 | ||
| 3504 | #define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 | ||
| 3505 | #define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8 | ||
| 3506 | #define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9 | ||
| 3507 | #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa | ||
| 3508 | #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb | ||
| 3509 | #define SQ_BUFFER_STORE_FORMAT_D16_X 0xc | ||
| 3510 | #define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd | ||
| 3511 | #define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe | ||
| 3512 | #define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf | ||
| 3513 | #define SQ_BUFFER_LOAD_UBYTE 0x10 | ||
| 3514 | #define SQ_BUFFER_LOAD_SBYTE 0x11 | ||
| 3515 | #define SQ_BUFFER_LOAD_USHORT 0x12 | ||
| 3516 | #define SQ_BUFFER_LOAD_SSHORT 0x13 | ||
| 3517 | #define SQ_BUFFER_LOAD_DWORD 0x14 | ||
| 3518 | #define SQ_BUFFER_LOAD_DWORDX2 0x15 | ||
| 3519 | #define SQ_BUFFER_LOAD_DWORDX3 0x16 | ||
| 3520 | #define SQ_BUFFER_LOAD_DWORDX4 0x17 | ||
| 3521 | #define SQ_BUFFER_STORE_BYTE 0x18 | ||
| 3522 | #define SQ_BUFFER_STORE_SHORT 0x1a | ||
| 3523 | #define SQ_BUFFER_STORE_DWORD 0x1c | ||
| 3524 | #define SQ_BUFFER_STORE_DWORDX2 0x1d | ||
| 3525 | #define SQ_BUFFER_STORE_DWORDX3 0x1e | ||
| 3526 | #define SQ_BUFFER_STORE_DWORDX4 0x1f | ||
| 3527 | #define SQ_BUFFER_STORE_LDS_DWORD 0x3d | ||
| 3528 | #define SQ_BUFFER_WBINVL1 0x3e | ||
| 3529 | #define SQ_BUFFER_WBINVL1_VOL 0x3f | ||
| 3530 | #define SQ_BUFFER_ATOMIC_SWAP 0x40 | ||
| 3531 | #define SQ_BUFFER_ATOMIC_CMPSWAP 0x41 | ||
| 3532 | #define SQ_BUFFER_ATOMIC_ADD 0x42 | ||
| 3533 | #define SQ_BUFFER_ATOMIC_SUB 0x43 | ||
| 3534 | #define SQ_BUFFER_ATOMIC_SMIN 0x44 | ||
| 3535 | #define SQ_BUFFER_ATOMIC_UMIN 0x45 | ||
| 3536 | #define SQ_BUFFER_ATOMIC_SMAX 0x46 | ||
| 3537 | #define SQ_BUFFER_ATOMIC_UMAX 0x47 | ||
| 3538 | #define SQ_BUFFER_ATOMIC_AND 0x48 | ||
| 3539 | #define SQ_BUFFER_ATOMIC_OR 0x49 | ||
| 3540 | #define SQ_BUFFER_ATOMIC_XOR 0x4a | ||
| 3541 | #define SQ_BUFFER_ATOMIC_INC 0x4b | ||
| 3542 | #define SQ_BUFFER_ATOMIC_DEC 0x4c | ||
| 3543 | #define SQ_BUFFER_ATOMIC_SWAP_X2 0x60 | ||
| 3544 | #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61 | ||
| 3545 | #define SQ_BUFFER_ATOMIC_ADD_X2 0x62 | ||
| 3546 | #define SQ_BUFFER_ATOMIC_SUB_X2 0x63 | ||
| 3547 | #define SQ_BUFFER_ATOMIC_SMIN_X2 0x64 | ||
| 3548 | #define SQ_BUFFER_ATOMIC_UMIN_X2 0x65 | ||
| 3549 | #define SQ_BUFFER_ATOMIC_SMAX_X2 0x66 | ||
| 3550 | #define SQ_BUFFER_ATOMIC_UMAX_X2 0x67 | ||
| 3551 | #define SQ_BUFFER_ATOMIC_AND_X2 0x68 | ||
| 3552 | #define SQ_BUFFER_ATOMIC_OR_X2 0x69 | ||
| 3553 | #define SQ_BUFFER_ATOMIC_XOR_X2 0x6a | ||
| 3554 | #define SQ_BUFFER_ATOMIC_INC_X2 0x6b | ||
| 3555 | #define SQ_BUFFER_ATOMIC_DEC_X2 0x6c | ||
| 3556 | #define SQ_EXEC_LO 0x7e | ||
| 3557 | #define SQ_EXEC_HI 0x7f | ||
| 3558 | #define SQ_SRC_SCC 0xfd | ||
| 3559 | #define SQ_OMOD_OFF 0x0 | ||
| 3560 | #define SQ_OMOD_M2 0x1 | ||
| 3561 | #define SQ_OMOD_M4 0x2 | ||
| 3562 | #define SQ_OMOD_D2 0x3 | ||
| 3563 | #define SQ_DPP_QUAD_PERM 0x0 | ||
| 3564 | #define SQ_DPP_ROW_SL1 0x101 | ||
| 3565 | #define SQ_DPP_ROW_SL2 0x102 | ||
| 3566 | #define SQ_DPP_ROW_SL3 0x103 | ||
| 3567 | #define SQ_DPP_ROW_SL4 0x104 | ||
| 3568 | #define SQ_DPP_ROW_SL5 0x105 | ||
| 3569 | #define SQ_DPP_ROW_SL6 0x106 | ||
| 3570 | #define SQ_DPP_ROW_SL7 0x107 | ||
| 3571 | #define SQ_DPP_ROW_SL8 0x108 | ||
| 3572 | #define SQ_DPP_ROW_SL9 0x109 | ||
| 3573 | #define SQ_DPP_ROW_SL10 0x10a | ||
| 3574 | #define SQ_DPP_ROW_SL11 0x10b | ||
| 3575 | #define SQ_DPP_ROW_SL12 0x10c | ||
| 3576 | #define SQ_DPP_ROW_SL13 0x10d | ||
| 3577 | #define SQ_DPP_ROW_SL14 0x10e | ||
| 3578 | #define SQ_DPP_ROW_SL15 0x10f | ||
| 3579 | #define SQ_DPP_ROW_SR1 0x111 | ||
| 3580 | #define SQ_DPP_ROW_SR2 0x112 | ||
| 3581 | #define SQ_DPP_ROW_SR3 0x113 | ||
| 3582 | #define SQ_DPP_ROW_SR4 0x114 | ||
| 3583 | #define SQ_DPP_ROW_SR5 0x115 | ||
| 3584 | #define SQ_DPP_ROW_SR6 0x116 | ||
| 3585 | #define SQ_DPP_ROW_SR7 0x117 | ||
| 3586 | #define SQ_DPP_ROW_SR8 0x118 | ||
| 3587 | #define SQ_DPP_ROW_SR9 0x119 | ||
| 3588 | #define SQ_DPP_ROW_SR10 0x11a | ||
| 3589 | #define SQ_DPP_ROW_SR11 0x11b | ||
| 3590 | #define SQ_DPP_ROW_SR12 0x11c | ||
| 3591 | #define SQ_DPP_ROW_SR13 0x11d | ||
| 3592 | #define SQ_DPP_ROW_SR14 0x11e | ||
| 3593 | #define SQ_DPP_ROW_SR15 0x11f | ||
| 3594 | #define SQ_DPP_ROW_RR1 0x121 | ||
| 3595 | #define SQ_DPP_ROW_RR2 0x122 | ||
| 3596 | #define SQ_DPP_ROW_RR3 0x123 | ||
| 3597 | #define SQ_DPP_ROW_RR4 0x124 | ||
| 3598 | #define SQ_DPP_ROW_RR5 0x125 | ||
| 3599 | #define SQ_DPP_ROW_RR6 0x126 | ||
| 3600 | #define SQ_DPP_ROW_RR7 0x127 | ||
| 3601 | #define SQ_DPP_ROW_RR8 0x128 | ||
| 3602 | #define SQ_DPP_ROW_RR9 0x129 | ||
| 3603 | #define SQ_DPP_ROW_RR10 0x12a | ||
| 3604 | #define SQ_DPP_ROW_RR11 0x12b | ||
| 3605 | #define SQ_DPP_ROW_RR12 0x12c | ||
| 3606 | #define SQ_DPP_ROW_RR13 0x12d | ||
| 3607 | #define SQ_DPP_ROW_RR14 0x12e | ||
| 3608 | #define SQ_DPP_ROW_RR15 0x12f | ||
| 3609 | #define SQ_DPP_WF_SL1 0x130 | ||
| 3610 | #define SQ_DPP_WF_RL1 0x134 | ||
| 3611 | #define SQ_DPP_WF_SR1 0x138 | ||
| 3612 | #define SQ_DPP_WF_RR1 0x13c | ||
| 3613 | #define SQ_DPP_ROW_MIRROR 0x140 | ||
| 3614 | #define SQ_DPP_ROW_HALF_MIRROR 0x141 | ||
| 3615 | #define SQ_DPP_ROW_BCAST15 0x142 | ||
| 3616 | #define SQ_DPP_ROW_BCAST31 0x143 | ||
| 3617 | #define SQ_EXP_GDS0 0x18 | ||
| 3618 | #define SQ_GS_OP_NOP 0x0 | ||
| 3619 | #define SQ_GS_OP_CUT 0x1 | ||
| 3620 | #define SQ_GS_OP_EMIT 0x2 | ||
| 3621 | #define SQ_GS_OP_EMIT_CUT 0x3 | ||
| 3622 | #define SQ_IMAGE_LOAD 0x0 | ||
| 3623 | #define SQ_IMAGE_LOAD_MIP 0x1 | ||
| 3624 | #define SQ_IMAGE_LOAD_PCK 0x2 | ||
| 3625 | #define SQ_IMAGE_LOAD_PCK_SGN 0x3 | ||
| 3626 | #define SQ_IMAGE_LOAD_MIP_PCK 0x4 | ||
| 3627 | #define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 | ||
| 3628 | #define SQ_IMAGE_STORE 0x8 | ||
| 3629 | #define SQ_IMAGE_STORE_MIP 0x9 | ||
| 3630 | #define SQ_IMAGE_STORE_PCK 0xa | ||
| 3631 | #define SQ_IMAGE_STORE_MIP_PCK 0xb | ||
| 3632 | #define SQ_IMAGE_GET_RESINFO 0xe | ||
| 3633 | #define SQ_IMAGE_ATOMIC_SWAP 0x10 | ||
| 3634 | #define SQ_IMAGE_ATOMIC_CMPSWAP 0x11 | ||
| 3635 | #define SQ_IMAGE_ATOMIC_ADD 0x12 | ||
| 3636 | #define SQ_IMAGE_ATOMIC_SUB 0x13 | ||
| 3637 | #define SQ_IMAGE_ATOMIC_SMIN 0x14 | ||
| 3638 | #define SQ_IMAGE_ATOMIC_UMIN 0x15 | ||
| 3639 | #define SQ_IMAGE_ATOMIC_SMAX 0x16 | ||
| 3640 | #define SQ_IMAGE_ATOMIC_UMAX 0x17 | ||
| 3641 | #define SQ_IMAGE_ATOMIC_AND 0x18 | ||
| 3642 | #define SQ_IMAGE_ATOMIC_OR 0x19 | ||
| 3643 | #define SQ_IMAGE_ATOMIC_XOR 0x1a | ||
| 3644 | #define SQ_IMAGE_ATOMIC_INC 0x1b | ||
| 3645 | #define SQ_IMAGE_ATOMIC_DEC 0x1c | ||
| 3646 | #define SQ_IMAGE_SAMPLE 0x20 | ||
| 3647 | #define SQ_IMAGE_SAMPLE_CL 0x21 | ||
| 3648 | #define SQ_IMAGE_SAMPLE_D 0x22 | ||
| 3649 | #define SQ_IMAGE_SAMPLE_D_CL 0x23 | ||
| 3650 | #define SQ_IMAGE_SAMPLE_L 0x24 | ||
| 3651 | #define SQ_IMAGE_SAMPLE_B 0x25 | ||
| 3652 | #define SQ_IMAGE_SAMPLE_B_CL 0x26 | ||
| 3653 | #define SQ_IMAGE_SAMPLE_LZ 0x27 | ||
| 3654 | #define SQ_IMAGE_SAMPLE_C 0x28 | ||
| 3655 | #define SQ_IMAGE_SAMPLE_C_CL 0x29 | ||
| 3656 | #define SQ_IMAGE_SAMPLE_C_D 0x2a | ||
| 3657 | #define SQ_IMAGE_SAMPLE_C_D_CL 0x2b | ||
| 3658 | #define SQ_IMAGE_SAMPLE_C_L 0x2c | ||
| 3659 | #define SQ_IMAGE_SAMPLE_C_B 0x2d | ||
| 3660 | #define SQ_IMAGE_SAMPLE_C_B_CL 0x2e | ||
| 3661 | #define SQ_IMAGE_SAMPLE_C_LZ 0x2f | ||
| 3662 | #define SQ_IMAGE_SAMPLE_O 0x30 | ||
| 3663 | #define SQ_IMAGE_SAMPLE_CL_O 0x31 | ||
| 3664 | #define SQ_IMAGE_SAMPLE_D_O 0x32 | ||
| 3665 | #define SQ_IMAGE_SAMPLE_D_CL_O 0x33 | ||
| 3666 | #define SQ_IMAGE_SAMPLE_L_O 0x34 | ||
| 3667 | #define SQ_IMAGE_SAMPLE_B_O 0x35 | ||
| 3668 | #define SQ_IMAGE_SAMPLE_B_CL_O 0x36 | ||
| 3669 | #define SQ_IMAGE_SAMPLE_LZ_O 0x37 | ||
| 3670 | #define SQ_IMAGE_SAMPLE_C_O 0x38 | ||
| 3671 | #define SQ_IMAGE_SAMPLE_C_CL_O 0x39 | ||
| 3672 | #define SQ_IMAGE_SAMPLE_C_D_O 0x3a | ||
| 3673 | #define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b | ||
| 3674 | #define SQ_IMAGE_SAMPLE_C_L_O 0x3c | ||
| 3675 | #define SQ_IMAGE_SAMPLE_C_B_O 0x3d | ||
| 3676 | #define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e | ||
| 3677 | #define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f | ||
| 3678 | #define SQ_IMAGE_GATHER4 0x40 | ||
| 3679 | #define SQ_IMAGE_GATHER4_CL 0x41 | ||
| 3680 | #define SQ_IMAGE_GATHER4_L 0x44 | ||
| 3681 | #define SQ_IMAGE_GATHER4_B 0x45 | ||
| 3682 | #define SQ_IMAGE_GATHER4_B_CL 0x46 | ||
| 3683 | #define SQ_IMAGE_GATHER4_LZ 0x47 | ||
| 3684 | #define SQ_IMAGE_GATHER4_C 0x48 | ||
| 3685 | #define SQ_IMAGE_GATHER4_C_CL 0x49 | ||
| 3686 | #define SQ_IMAGE_GATHER4_C_L 0x4c | ||
| 3687 | #define SQ_IMAGE_GATHER4_C_B 0x4d | ||
| 3688 | #define SQ_IMAGE_GATHER4_C_B_CL 0x4e | ||
| 3689 | #define SQ_IMAGE_GATHER4_C_LZ 0x4f | ||
| 3690 | #define SQ_IMAGE_GATHER4_O 0x50 | ||
| 3691 | #define SQ_IMAGE_GATHER4_CL_O 0x51 | ||
| 3692 | #define SQ_IMAGE_GATHER4_L_O 0x54 | ||
| 3693 | #define SQ_IMAGE_GATHER4_B_O 0x55 | ||
| 3694 | #define SQ_IMAGE_GATHER4_B_CL_O 0x56 | ||
| 3695 | #define SQ_IMAGE_GATHER4_LZ_O 0x57 | ||
| 3696 | #define SQ_IMAGE_GATHER4_C_O 0x58 | ||
| 3697 | #define SQ_IMAGE_GATHER4_C_CL_O 0x59 | ||
| 3698 | #define SQ_IMAGE_GATHER4_C_L_O 0x5c | ||
| 3699 | #define SQ_IMAGE_GATHER4_C_B_O 0x5d | ||
| 3700 | #define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e | ||
| 3701 | #define SQ_IMAGE_GATHER4_C_LZ_O 0x5f | ||
| 3702 | #define SQ_IMAGE_GET_LOD 0x60 | ||
| 3703 | #define SQ_IMAGE_SAMPLE_CD 0x68 | ||
| 3704 | #define SQ_IMAGE_SAMPLE_CD_CL 0x69 | ||
| 3705 | #define SQ_IMAGE_SAMPLE_C_CD 0x6a | ||
| 3706 | #define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b | ||
| 3707 | #define SQ_IMAGE_SAMPLE_CD_O 0x6c | ||
| 3708 | #define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d | ||
| 3709 | #define SQ_IMAGE_SAMPLE_C_CD_O 0x6e | ||
| 3710 | #define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f | ||
| 3711 | #define SQ_IMAGE_RSRC256 0x7e | ||
| 3712 | #define SQ_IMAGE_SAMPLER 0x7f | ||
| 3713 | #define SQ_SRC_VCCZ 0xfb | ||
| 3714 | #define SQ_SRC_VGPR0 0x100 | ||
| 3715 | #define SQ_SDWA_BYTE_0 0x0 | ||
| 3716 | #define SQ_SDWA_BYTE_1 0x1 | ||
| 3717 | #define SQ_SDWA_BYTE_2 0x2 | ||
| 3718 | #define SQ_SDWA_BYTE_3 0x3 | ||
| 3719 | #define SQ_SDWA_WORD_0 0x4 | ||
| 3720 | #define SQ_SDWA_WORD_1 0x5 | ||
| 3721 | #define SQ_SDWA_DWORD 0x6 | ||
| 3722 | #define SQ_XNACK_MASK_LO 0x68 | ||
| 3723 | #define SQ_XNACK_MASK_HI 0x69 | ||
| 3724 | #define SQ_TBUFFER_LOAD_FORMAT_X 0x0 | ||
| 3725 | #define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 | ||
| 3726 | #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 | ||
| 3727 | #define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 | ||
| 3728 | #define SQ_TBUFFER_STORE_FORMAT_X 0x4 | ||
| 3729 | #define SQ_TBUFFER_STORE_FORMAT_XY 0x5 | ||
| 3730 | #define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 | ||
| 3731 | #define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 | ||
| 3732 | #define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8 | ||
| 3733 | #define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9 | ||
| 3734 | #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa | ||
| 3735 | #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb | ||
| 3736 | #define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc | ||
| 3737 | #define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd | ||
| 3738 | #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe | ||
| 3739 | #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf | ||
| 3740 | #define SQ_CHAN_X 0x0 | ||
| 3741 | #define SQ_CHAN_Y 0x1 | ||
| 3742 | #define SQ_CHAN_Z 0x2 | ||
| 3743 | #define SQ_CHAN_W 0x3 | ||
| 3744 | #define SQ_V_NOP 0x0 | ||
| 3745 | #define SQ_V_MOV_B32 0x1 | ||
| 3746 | #define SQ_V_READFIRSTLANE_B32 0x2 | ||
| 3747 | #define SQ_V_CVT_I32_F64 0x3 | ||
| 3748 | #define SQ_V_CVT_F64_I32 0x4 | ||
| 3749 | #define SQ_V_CVT_F32_I32 0x5 | ||
| 3750 | #define SQ_V_CVT_F32_U32 0x6 | ||
| 3751 | #define SQ_V_CVT_U32_F32 0x7 | ||
| 3752 | #define SQ_V_CVT_I32_F32 0x8 | ||
| 3753 | #define SQ_V_MOV_FED_B32 0x9 | ||
| 3754 | #define SQ_V_CVT_F16_F32 0xa | ||
| 3755 | #define SQ_V_CVT_F32_F16 0xb | ||
| 3756 | #define SQ_V_CVT_RPI_I32_F32 0xc | ||
| 3757 | #define SQ_V_CVT_FLR_I32_F32 0xd | ||
| 3758 | #define SQ_V_CVT_OFF_F32_I4 0xe | ||
| 3759 | #define SQ_V_CVT_F32_F64 0xf | ||
| 3760 | #define SQ_V_CVT_F64_F32 0x10 | ||
| 3761 | #define SQ_V_CVT_F32_UBYTE0 0x11 | ||
| 3762 | #define SQ_V_CVT_F32_UBYTE1 0x12 | ||
| 3763 | #define SQ_V_CVT_F32_UBYTE2 0x13 | ||
| 3764 | #define SQ_V_CVT_F32_UBYTE3 0x14 | ||
| 3765 | #define SQ_V_CVT_U32_F64 0x15 | ||
| 3766 | #define SQ_V_CVT_F64_U32 0x16 | ||
| 3767 | #define SQ_V_TRUNC_F64 0x17 | ||
| 3768 | #define SQ_V_CEIL_F64 0x18 | ||
| 3769 | #define SQ_V_RNDNE_F64 0x19 | ||
| 3770 | #define SQ_V_FLOOR_F64 0x1a | ||
| 3771 | #define SQ_V_FRACT_F32 0x1b | ||
| 3772 | #define SQ_V_TRUNC_F32 0x1c | ||
| 3773 | #define SQ_V_CEIL_F32 0x1d | ||
| 3774 | #define SQ_V_RNDNE_F32 0x1e | ||
| 3775 | #define SQ_V_FLOOR_F32 0x1f | ||
| 3776 | #define SQ_V_EXP_F32 0x20 | ||
| 3777 | #define SQ_V_LOG_F32 0x21 | ||
| 3778 | #define SQ_V_RCP_F32 0x22 | ||
| 3779 | #define SQ_V_RCP_IFLAG_F32 0x23 | ||
| 3780 | #define SQ_V_RSQ_F32 0x24 | ||
| 3781 | #define SQ_V_RCP_F64 0x25 | ||
| 3782 | #define SQ_V_RSQ_F64 0x26 | ||
| 3783 | #define SQ_V_SQRT_F32 0x27 | ||
| 3784 | #define SQ_V_SQRT_F64 0x28 | ||
| 3785 | #define SQ_V_SIN_F32 0x29 | ||
| 3786 | #define SQ_V_COS_F32 0x2a | ||
| 3787 | #define SQ_V_NOT_B32 0x2b | ||
| 3788 | #define SQ_V_BFREV_B32 0x2c | ||
| 3789 | #define SQ_V_FFBH_U32 0x2d | ||
| 3790 | #define SQ_V_FFBL_B32 0x2e | ||
| 3791 | #define SQ_V_FFBH_I32 0x2f | ||
| 3792 | #define SQ_V_FREXP_EXP_I32_F64 0x30 | ||
| 3793 | #define SQ_V_FREXP_MANT_F64 0x31 | ||
| 3794 | #define SQ_V_FRACT_F64 0x32 | ||
| 3795 | #define SQ_V_FREXP_EXP_I32_F32 0x33 | ||
| 3796 | #define SQ_V_FREXP_MANT_F32 0x34 | ||
| 3797 | #define SQ_V_CLREXCP 0x35 | ||
| 3798 | #define SQ_V_MOVRELD_B32 0x36 | ||
| 3799 | #define SQ_V_MOVRELS_B32 0x37 | ||
| 3800 | #define SQ_V_MOVRELSD_B32 0x38 | ||
| 3801 | #define SQ_V_CVT_F16_U16 0x39 | ||
| 3802 | #define SQ_V_CVT_F16_I16 0x3a | ||
| 3803 | #define SQ_V_CVT_U16_F16 0x3b | ||
| 3804 | #define SQ_V_CVT_I16_F16 0x3c | ||
| 3805 | #define SQ_V_RCP_F16 0x3d | ||
| 3806 | #define SQ_V_SQRT_F16 0x3e | ||
| 3807 | #define SQ_V_RSQ_F16 0x3f | ||
| 3808 | #define SQ_V_LOG_F16 0x40 | ||
| 3809 | #define SQ_V_EXP_F16 0x41 | ||
| 3810 | #define SQ_V_FREXP_MANT_F16 0x42 | ||
| 3811 | #define SQ_V_FREXP_EXP_I16_F16 0x43 | ||
| 3812 | #define SQ_V_FLOOR_F16 0x44 | ||
| 3813 | #define SQ_V_CEIL_F16 0x45 | ||
| 3814 | #define SQ_V_TRUNC_F16 0x46 | ||
| 3815 | #define SQ_V_RNDNE_F16 0x47 | ||
| 3816 | #define SQ_V_FRACT_F16 0x48 | ||
| 3817 | #define SQ_V_SIN_F16 0x49 | ||
| 3818 | #define SQ_V_COS_F16 0x4a | ||
| 3819 | #define SQ_V_EXP_LEGACY_F32 0x4b | ||
| 3820 | #define SQ_V_LOG_LEGACY_F32 0x4c | ||
| 3821 | #define SQ_V_CVT_NORM_I16_F16 0x4d | ||
| 3822 | #define SQ_V_CVT_NORM_U16_F16 0x4e | ||
| 3823 | #define SQ_SRC_SDWA 0xf9 | ||
| 3824 | #define SQ_V_OPC_OFFSET 0x0 | ||
| 3825 | #define SQ_V_OP2_OFFSET 0x100 | ||
| 3826 | #define SQ_V_OP1_OFFSET 0x140 | ||
| 3827 | #define SQ_V_INTRP_OFFSET 0x270 | ||
| 3828 | #define SQ_V_INTERP_P1_F32 0x0 | ||
| 3829 | #define SQ_V_INTERP_P2_F32 0x1 | ||
| 3830 | #define SQ_V_INTERP_MOV_F32 0x2 | ||
| 3831 | #define SQ_S_NOP 0x0 | ||
| 3832 | #define SQ_S_ENDPGM 0x1 | ||
| 3833 | #define SQ_S_BRANCH 0x2 | ||
| 3834 | #define SQ_S_WAKEUP 0x3 | ||
| 3835 | #define SQ_S_CBRANCH_SCC0 0x4 | ||
| 3836 | #define SQ_S_CBRANCH_SCC1 0x5 | ||
| 3837 | #define SQ_S_CBRANCH_VCCZ 0x6 | ||
| 3838 | #define SQ_S_CBRANCH_VCCNZ 0x7 | ||
| 3839 | #define SQ_S_CBRANCH_EXECZ 0x8 | ||
| 3840 | #define SQ_S_CBRANCH_EXECNZ 0x9 | ||
| 3841 | #define SQ_S_BARRIER 0xa | ||
| 3842 | #define SQ_S_SETKILL 0xb | ||
| 3843 | #define SQ_S_WAITCNT 0xc | ||
| 3844 | #define SQ_S_SETHALT 0xd | ||
| 3845 | #define SQ_S_SLEEP 0xe | ||
| 3846 | #define SQ_S_SETPRIO 0xf | ||
| 3847 | #define SQ_S_SENDMSG 0x10 | ||
| 3848 | #define SQ_S_SENDMSGHALT 0x11 | ||
| 3849 | #define SQ_S_TRAP 0x12 | ||
| 3850 | #define SQ_S_ICACHE_INV 0x13 | ||
| 3851 | #define SQ_S_INCPERFLEVEL 0x14 | ||
| 3852 | #define SQ_S_DECPERFLEVEL 0x15 | ||
| 3853 | #define SQ_S_TTRACEDATA 0x16 | ||
| 3854 | #define SQ_S_CBRANCH_CDBGSYS 0x17 | ||
| 3855 | #define SQ_S_CBRANCH_CDBGUSER 0x18 | ||
| 3856 | #define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 | ||
| 3857 | #define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a | ||
| 3858 | #define SQ_S_ENDPGM_SAVED 0x1b | ||
| 3859 | #define SQ_S_SET_GPR_IDX_OFF 0x1c | ||
| 3860 | #define SQ_S_SET_GPR_IDX_MODE 0x1d | ||
| 3861 | #define SQ_SRC_DPP 0xfa | ||
| 3862 | #define SQ_SRC_LITERAL 0xff | ||
| 3863 | #define SQ_VCC_LO 0x6a | ||
| 3864 | #define SQ_VCC_HI 0x6b | ||
| 3865 | #define SQ_PARAM_P10 0x0 | ||
| 3866 | #define SQ_PARAM_P20 0x1 | ||
| 3867 | #define SQ_PARAM_P0 0x2 | ||
| 3868 | #define SQ_SRC_LDS_DIRECT 0xfe | ||
| 3869 | #define SQ_V_CNDMASK_B32 0x0 | ||
| 3870 | #define SQ_V_ADD_F32 0x1 | ||
| 3871 | #define SQ_V_SUB_F32 0x2 | ||
| 3872 | #define SQ_V_SUBREV_F32 0x3 | ||
| 3873 | #define SQ_V_MUL_LEGACY_F32 0x4 | ||
| 3874 | #define SQ_V_MUL_F32 0x5 | ||
| 3875 | #define SQ_V_MUL_I32_I24 0x6 | ||
| 3876 | #define SQ_V_MUL_HI_I32_I24 0x7 | ||
| 3877 | #define SQ_V_MUL_U32_U24 0x8 | ||
| 3878 | #define SQ_V_MUL_HI_U32_U24 0x9 | ||
| 3879 | #define SQ_V_MIN_F32 0xa | ||
| 3880 | #define SQ_V_MAX_F32 0xb | ||
| 3881 | #define SQ_V_MIN_I32 0xc | ||
| 3882 | #define SQ_V_MAX_I32 0xd | ||
| 3883 | #define SQ_V_MIN_U32 0xe | ||
| 3884 | #define SQ_V_MAX_U32 0xf | ||
| 3885 | #define SQ_V_LSHRREV_B32 0x10 | ||
| 3886 | #define SQ_V_ASHRREV_I32 0x11 | ||
| 3887 | #define SQ_V_LSHLREV_B32 0x12 | ||
| 3888 | #define SQ_V_AND_B32 0x13 | ||
| 3889 | #define SQ_V_OR_B32 0x14 | ||
| 3890 | #define SQ_V_XOR_B32 0x15 | ||
| 3891 | #define SQ_V_MAC_F32 0x16 | ||
| 3892 | #define SQ_V_MADMK_F32 0x17 | ||
| 3893 | #define SQ_V_MADAK_F32 0x18 | ||
| 3894 | #define SQ_V_ADD_U32 0x19 | ||
| 3895 | #define SQ_V_SUB_U32 0x1a | ||
| 3896 | #define SQ_V_SUBREV_U32 0x1b | ||
| 3897 | #define SQ_V_ADDC_U32 0x1c | ||
| 3898 | #define SQ_V_SUBB_U32 0x1d | ||
| 3899 | #define SQ_V_SUBBREV_U32 0x1e | ||
| 3900 | #define SQ_V_ADD_F16 0x1f | ||
| 3901 | #define SQ_V_SUB_F16 0x20 | ||
| 3902 | #define SQ_V_SUBREV_F16 0x21 | ||
| 3903 | #define SQ_V_MUL_F16 0x22 | ||
| 3904 | #define SQ_V_MAC_F16 0x23 | ||
| 3905 | #define SQ_V_MADMK_F16 0x24 | ||
| 3906 | #define SQ_V_MADAK_F16 0x25 | ||
| 3907 | #define SQ_V_ADD_U16 0x26 | ||
| 3908 | #define SQ_V_SUB_U16 0x27 | ||
| 3909 | #define SQ_V_SUBREV_U16 0x28 | ||
| 3910 | #define SQ_V_MUL_LO_U16 0x29 | ||
| 3911 | #define SQ_V_LSHLREV_B16 0x2a | ||
| 3912 | #define SQ_V_LSHRREV_B16 0x2b | ||
| 3913 | #define SQ_V_ASHRREV_I16 0x2c | ||
| 3914 | #define SQ_V_MAX_F16 0x2d | ||
| 3915 | #define SQ_V_MIN_F16 0x2e | ||
| 3916 | #define SQ_V_MAX_U16 0x2f | ||
| 3917 | #define SQ_V_MAX_I16 0x30 | ||
| 3918 | #define SQ_V_MIN_U16 0x31 | ||
| 3919 | #define SQ_V_MIN_I16 0x32 | ||
| 3920 | #define SQ_V_LDEXP_F16 0x33 | ||
| 3921 | #define SQ_FLAT_LOAD_UBYTE 0x10 | ||
| 3922 | #define SQ_FLAT_LOAD_SBYTE 0x11 | ||
| 3923 | #define SQ_FLAT_LOAD_USHORT 0x12 | ||
| 3924 | #define SQ_FLAT_LOAD_SSHORT 0x13 | ||
| 3925 | #define SQ_FLAT_LOAD_DWORD 0x14 | ||
| 3926 | #define SQ_FLAT_LOAD_DWORDX2 0x15 | ||
| 3927 | #define SQ_FLAT_LOAD_DWORDX3 0x16 | ||
| 3928 | #define SQ_FLAT_LOAD_DWORDX4 0x17 | ||
| 3929 | #define SQ_FLAT_STORE_BYTE 0x18 | ||
| 3930 | #define SQ_FLAT_STORE_SHORT 0x1a | ||
| 3931 | #define SQ_FLAT_STORE_DWORD 0x1c | ||
| 3932 | #define SQ_FLAT_STORE_DWORDX2 0x1d | ||
| 3933 | #define SQ_FLAT_STORE_DWORDX3 0x1e | ||
| 3934 | #define SQ_FLAT_STORE_DWORDX4 0x1f | ||
| 3935 | #define SQ_FLAT_ATOMIC_SWAP 0x40 | ||
| 3936 | #define SQ_FLAT_ATOMIC_CMPSWAP 0x41 | ||
| 3937 | #define SQ_FLAT_ATOMIC_ADD 0x42 | ||
| 3938 | #define SQ_FLAT_ATOMIC_SUB 0x43 | ||
| 3939 | #define SQ_FLAT_ATOMIC_SMIN 0x44 | ||
| 3940 | #define SQ_FLAT_ATOMIC_UMIN 0x45 | ||
| 3941 | #define SQ_FLAT_ATOMIC_SMAX 0x46 | ||
| 3942 | #define SQ_FLAT_ATOMIC_UMAX 0x47 | ||
| 3943 | #define SQ_FLAT_ATOMIC_AND 0x48 | ||
| 3944 | #define SQ_FLAT_ATOMIC_OR 0x49 | ||
| 3945 | #define SQ_FLAT_ATOMIC_XOR 0x4a | ||
| 3946 | #define SQ_FLAT_ATOMIC_INC 0x4b | ||
| 3947 | #define SQ_FLAT_ATOMIC_DEC 0x4c | ||
| 3948 | #define SQ_FLAT_ATOMIC_SWAP_X2 0x60 | ||
| 3949 | #define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61 | ||
| 3950 | #define SQ_FLAT_ATOMIC_ADD_X2 0x62 | ||
| 3951 | #define SQ_FLAT_ATOMIC_SUB_X2 0x63 | ||
| 3952 | #define SQ_FLAT_ATOMIC_SMIN_X2 0x64 | ||
| 3953 | #define SQ_FLAT_ATOMIC_UMIN_X2 0x65 | ||
| 3954 | #define SQ_FLAT_ATOMIC_SMAX_X2 0x66 | ||
| 3955 | #define SQ_FLAT_ATOMIC_UMAX_X2 0x67 | ||
| 3956 | #define SQ_FLAT_ATOMIC_AND_X2 0x68 | ||
| 3957 | #define SQ_FLAT_ATOMIC_OR_X2 0x69 | ||
| 3958 | #define SQ_FLAT_ATOMIC_XOR_X2 0x6a | ||
| 3959 | #define SQ_FLAT_ATOMIC_INC_X2 0x6b | ||
| 3960 | #define SQ_FLAT_ATOMIC_DEC_X2 0x6c | ||
| 3961 | #define SQ_S_CMP_EQ_I32 0x0 | ||
| 3962 | #define SQ_S_CMP_LG_I32 0x1 | ||
| 3963 | #define SQ_S_CMP_GT_I32 0x2 | ||
| 3964 | #define SQ_S_CMP_GE_I32 0x3 | ||
| 3965 | #define SQ_S_CMP_LT_I32 0x4 | ||
| 3966 | #define SQ_S_CMP_LE_I32 0x5 | ||
| 3967 | #define SQ_S_CMP_EQ_U32 0x6 | ||
| 3968 | #define SQ_S_CMP_LG_U32 0x7 | ||
| 3969 | #define SQ_S_CMP_GT_U32 0x8 | ||
| 3970 | #define SQ_S_CMP_GE_U32 0x9 | ||
| 3971 | #define SQ_S_CMP_LT_U32 0xa | ||
| 3972 | #define SQ_S_CMP_LE_U32 0xb | ||
| 3973 | #define SQ_S_BITCMP0_B32 0xc | ||
| 3974 | #define SQ_S_BITCMP1_B32 0xd | ||
| 3975 | #define SQ_S_BITCMP0_B64 0xe | ||
| 3976 | #define SQ_S_BITCMP1_B64 0xf | ||
| 3977 | #define SQ_S_SETVSKIP 0x10 | ||
| 3978 | #define SQ_S_SET_GPR_IDX_ON 0x11 | ||
| 3979 | #define SQ_S_CMP_EQ_U64 0x12 | ||
| 3980 | #define SQ_S_CMP_LG_U64 0x13 | ||
| 3981 | #define SQ_M0 0x7c | ||
| 3982 | #define SQ_V_MAD_LEGACY_F32 0x1c0 | ||
| 3983 | #define SQ_V_MAD_F32 0x1c1 | ||
| 3984 | #define SQ_V_MAD_I32_I24 0x1c2 | ||
| 3985 | #define SQ_V_MAD_U32_U24 0x1c3 | ||
| 3986 | #define SQ_V_CUBEID_F32 0x1c4 | ||
| 3987 | #define SQ_V_CUBESC_F32 0x1c5 | ||
| 3988 | #define SQ_V_CUBETC_F32 0x1c6 | ||
| 3989 | #define SQ_V_CUBEMA_F32 0x1c7 | ||
| 3990 | #define SQ_V_BFE_U32 0x1c8 | ||
| 3991 | #define SQ_V_BFE_I32 0x1c9 | ||
| 3992 | #define SQ_V_BFI_B32 0x1ca | ||
| 3993 | #define SQ_V_FMA_F32 0x1cb | ||
| 3994 | #define SQ_V_FMA_F64 0x1cc | ||
| 3995 | #define SQ_V_LERP_U8 0x1cd | ||
| 3996 | #define SQ_V_ALIGNBIT_B32 0x1ce | ||
| 3997 | #define SQ_V_ALIGNBYTE_B32 0x1cf | ||
| 3998 | #define SQ_V_MIN3_F32 0x1d0 | ||
| 3999 | #define SQ_V_MIN3_I32 0x1d1 | ||
| 4000 | #define SQ_V_MIN3_U32 0x1d2 | ||
| 4001 | #define SQ_V_MAX3_F32 0x1d3 | ||
| 4002 | #define SQ_V_MAX3_I32 0x1d4 | ||
| 4003 | #define SQ_V_MAX3_U32 0x1d5 | ||
| 4004 | #define SQ_V_MED3_F32 0x1d6 | ||
| 4005 | #define SQ_V_MED3_I32 0x1d7 | ||
| 4006 | #define SQ_V_MED3_U32 0x1d8 | ||
| 4007 | #define SQ_V_SAD_U8 0x1d9 | ||
| 4008 | #define SQ_V_SAD_HI_U8 0x1da | ||
| 4009 | #define SQ_V_SAD_U16 0x1db | ||
| 4010 | #define SQ_V_SAD_U32 0x1dc | ||
| 4011 | #define SQ_V_CVT_PK_U8_F32 0x1dd | ||
| 4012 | #define SQ_V_DIV_FIXUP_F32 0x1de | ||
| 4013 | #define SQ_V_DIV_FIXUP_F64 0x1df | ||
| 4014 | #define SQ_V_DIV_SCALE_F32 0x1e0 | ||
| 4015 | #define SQ_V_DIV_SCALE_F64 0x1e1 | ||
| 4016 | #define SQ_V_DIV_FMAS_F32 0x1e2 | ||
| 4017 | #define SQ_V_DIV_FMAS_F64 0x1e3 | ||
| 4018 | #define SQ_V_MSAD_U8 0x1e4 | ||
| 4019 | #define SQ_V_QSAD_PK_U16_U8 0x1e5 | ||
| 4020 | #define SQ_V_MQSAD_PK_U16_U8 0x1e6 | ||
| 4021 | #define SQ_V_MQSAD_U32_U8 0x1e7 | ||
| 4022 | #define SQ_V_MAD_U64_U32 0x1e8 | ||
| 4023 | #define SQ_V_MAD_I64_I32 0x1e9 | ||
| 4024 | #define SQ_V_MAD_F16 0x1ea | ||
| 4025 | #define SQ_V_MAD_U16 0x1eb | ||
| 4026 | #define SQ_V_MAD_I16 0x1ec | ||
| 4027 | #define SQ_V_PERM_B32 0x1ed | ||
| 4028 | #define SQ_V_FMA_F16 0x1ee | ||
| 4029 | #define SQ_V_DIV_FIXUP_F16 0x1ef | ||
| 4030 | #define SQ_V_CVT_PKACCUM_U8_F32 0x1f0 | ||
| 4031 | #define SQ_V_INTERP_P1LL_F16 0x274 | ||
| 4032 | #define SQ_V_INTERP_P1LV_F16 0x275 | ||
| 4033 | #define SQ_V_INTERP_P2_F16 0x276 | ||
| 4034 | #define SQ_V_ADD_F64 0x280 | ||
| 4035 | #define SQ_V_MUL_F64 0x281 | ||
| 4036 | #define SQ_V_MIN_F64 0x282 | ||
| 4037 | #define SQ_V_MAX_F64 0x283 | ||
| 4038 | #define SQ_V_LDEXP_F64 0x284 | ||
| 4039 | #define SQ_V_MUL_LO_U32 0x285 | ||
| 4040 | #define SQ_V_MUL_HI_U32 0x286 | ||
| 4041 | #define SQ_V_MUL_HI_I32 0x287 | ||
| 4042 | #define SQ_V_LDEXP_F32 0x288 | ||
| 4043 | #define SQ_V_READLANE_B32 0x289 | ||
| 4044 | #define SQ_V_WRITELANE_B32 0x28a | ||
| 4045 | #define SQ_V_BCNT_U32_B32 0x28b | ||
| 4046 | #define SQ_V_MBCNT_LO_U32_B32 0x28c | ||
| 4047 | #define SQ_V_MBCNT_HI_U32_B32 0x28d | ||
| 4048 | #define SQ_V_MAC_LEGACY_F32 0x28e | ||
| 4049 | #define SQ_V_LSHLREV_B64 0x28f | ||
| 4050 | #define SQ_V_LSHRREV_B64 0x290 | ||
| 4051 | #define SQ_V_ASHRREV_I64 0x291 | ||
| 4052 | #define SQ_V_TRIG_PREOP_F64 0x292 | ||
| 4053 | #define SQ_V_BFM_B32 0x293 | ||
| 4054 | #define SQ_V_CVT_PKNORM_I16_F32 0x294 | ||
| 4055 | #define SQ_V_CVT_PKNORM_U16_F32 0x295 | ||
| 4056 | #define SQ_V_CVT_PKRTZ_F16_F32 0x296 | ||
| 4057 | #define SQ_V_CVT_PK_U16_U32 0x297 | ||
| 4058 | #define SQ_V_CVT_PK_I16_I32 0x298 | ||
| 4059 | #define SQ_V_CVT_PKNORM_I16_F16 0x299 | ||
| 4060 | #define SQ_V_CVT_PKNORM_U16_F16 0x29a | ||
| 4061 | #define SQ_VCC_ALL 0x0 | ||
| 4062 | #define SQ_SRC_EXECZ 0xfc | ||
| 4063 | #define SQ_FLAT_SCRATCH_LO 0x66 | ||
| 4064 | #define SQ_FLAT_SCRATCH_HI 0x67 | ||
| 4065 | #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 | ||
| 4066 | #define SQ_SYSMSG_OP_REG_RD 0x2 | ||
| 4067 | #define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 | ||
| 4068 | #define SQ_SYSMSG_OP_TTRACE_PC 0x4 | ||
| 4069 | #define SQ_HW_REG_MODE 0x1 | ||
| 4070 | #define SQ_HW_REG_STATUS 0x2 | ||
| 4071 | #define SQ_HW_REG_TRAPSTS 0x3 | ||
| 4072 | #define SQ_HW_REG_HW_ID 0x4 | ||
| 4073 | #define SQ_HW_REG_GPR_ALLOC 0x5 | ||
| 4074 | #define SQ_HW_REG_LDS_ALLOC 0x6 | ||
| 4075 | #define SQ_HW_REG_IB_STS 0x7 | ||
| 4076 | #define SQ_HW_REG_PC_LO 0x8 | ||
| 4077 | #define SQ_HW_REG_PC_HI 0x9 | ||
| 4078 | #define SQ_HW_REG_INST_DW0 0xa | ||
| 4079 | #define SQ_HW_REG_INST_DW1 0xb | ||
| 4080 | #define SQ_HW_REG_IB_DBG0 0xc | ||
| 4081 | #define SQ_HW_REG_IB_DBG1 0xd | ||
| 4082 | #define SQ_DPP_BOUND_OFF 0x0 | ||
| 4083 | #define SQ_DPP_BOUND_ZERO 0x1 | ||
| 4084 | #define SQ_R1 0x1 | ||
| 4085 | #define SQ_R2 0x2 | ||
| 4086 | #define SQ_R3 0x3 | ||
| 4087 | #define SQ_R4 0x4 | ||
| 4088 | #define SQ_R5 0x5 | ||
| 4089 | #define SQ_R6 0x6 | ||
| 4090 | #define SQ_R7 0x7 | ||
| 4091 | #define SQ_R8 0x8 | ||
| 4092 | #define SQ_R9 0x9 | ||
| 4093 | #define SQ_R10 0xa | ||
| 4094 | #define SQ_R11 0xb | ||
| 4095 | #define SQ_R12 0xc | ||
| 4096 | #define SQ_R13 0xd | ||
| 4097 | #define SQ_R14 0xe | ||
| 4098 | #define SQ_R15 0xf | ||
| 4099 | #define SQ_S_ADD_U32 0x0 | ||
| 4100 | #define SQ_S_SUB_U32 0x1 | ||
| 4101 | #define SQ_S_ADD_I32 0x2 | ||
| 4102 | #define SQ_S_SUB_I32 0x3 | ||
| 4103 | #define SQ_S_ADDC_U32 0x4 | ||
| 4104 | #define SQ_S_SUBB_U32 0x5 | ||
| 4105 | #define SQ_S_MIN_I32 0x6 | ||
| 4106 | #define SQ_S_MIN_U32 0x7 | ||
| 4107 | #define SQ_S_MAX_I32 0x8 | ||
| 4108 | #define SQ_S_MAX_U32 0x9 | ||
| 4109 | #define SQ_S_CSELECT_B32 0xa | ||
| 4110 | #define SQ_S_CSELECT_B64 0xb | ||
| 4111 | #define SQ_S_AND_B32 0xc | ||
| 4112 | #define SQ_S_AND_B64 0xd | ||
| 4113 | #define SQ_S_OR_B32 0xe | ||
| 4114 | #define SQ_S_OR_B64 0xf | ||
| 4115 | #define SQ_S_XOR_B32 0x10 | ||
| 4116 | #define SQ_S_XOR_B64 0x11 | ||
| 4117 | #define SQ_S_ANDN2_B32 0x12 | ||
| 4118 | #define SQ_S_ANDN2_B64 0x13 | ||
| 4119 | #define SQ_S_ORN2_B32 0x14 | ||
| 4120 | #define SQ_S_ORN2_B64 0x15 | ||
| 4121 | #define SQ_S_NAND_B32 0x16 | ||
| 4122 | #define SQ_S_NAND_B64 0x17 | ||
| 4123 | #define SQ_S_NOR_B32 0x18 | ||
| 4124 | #define SQ_S_NOR_B64 0x19 | ||
| 4125 | #define SQ_S_XNOR_B32 0x1a | ||
| 4126 | #define SQ_S_XNOR_B64 0x1b | ||
| 4127 | #define SQ_S_LSHL_B32 0x1c | ||
| 4128 | #define SQ_S_LSHL_B64 0x1d | ||
| 4129 | #define SQ_S_LSHR_B32 0x1e | ||
| 4130 | #define SQ_S_LSHR_B64 0x1f | ||
| 4131 | #define SQ_S_ASHR_I32 0x20 | ||
| 4132 | #define SQ_S_ASHR_I64 0x21 | ||
| 4133 | #define SQ_S_BFM_B32 0x22 | ||
| 4134 | #define SQ_S_BFM_B64 0x23 | ||
| 4135 | #define SQ_S_MUL_I32 0x24 | ||
| 4136 | #define SQ_S_BFE_U32 0x25 | ||
| 4137 | #define SQ_S_BFE_I32 0x26 | ||
| 4138 | #define SQ_S_BFE_U64 0x27 | ||
| 4139 | #define SQ_S_BFE_I64 0x28 | ||
| 4140 | #define SQ_S_CBRANCH_G_FORK 0x29 | ||
| 4141 | #define SQ_S_ABSDIFF_I32 0x2a | ||
| 4142 | #define SQ_S_RFE_RESTORE_B64 0x2b | ||
| 4143 | #define SQ_MSG_INTERRUPT 0x1 | ||
| 4144 | #define SQ_MSG_GS 0x2 | ||
| 4145 | #define SQ_MSG_GS_DONE 0x3 | ||
| 4146 | #define SQ_MSG_SAVEWAVE 0x4 | ||
| 4147 | #define SQ_MSG_SYSMSG 0xf | ||
| 4148 | typedef enum SX_BLEND_OPT { | ||
| 4149 | BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x0, | ||
| 4150 | BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x1, | ||
| 4151 | BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x2, | ||
| 4152 | BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x3, | ||
| 4153 | BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x4, | ||
| 4154 | BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x5, | ||
| 4155 | BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x6, | ||
| 4156 | BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x7, | ||
| 4157 | } SX_BLEND_OPT; | ||
| 4158 | typedef enum SX_OPT_COMB_FCN { | ||
| 4159 | OPT_COMB_NONE = 0x0, | ||
| 4160 | OPT_COMB_ADD = 0x1, | ||
| 4161 | OPT_COMB_SUBTRACT = 0x2, | ||
| 4162 | OPT_COMB_MIN = 0x3, | ||
| 4163 | OPT_COMB_MAX = 0x4, | ||
| 4164 | OPT_COMB_REVSUBTRACT = 0x5, | ||
| 4165 | OPT_COMB_BLEND_DISABLED = 0x6, | ||
| 4166 | OPT_COMB_SAFE_ADD = 0x7, | ||
| 4167 | } SX_OPT_COMB_FCN; | ||
| 4168 | typedef enum SX_DOWNCONVERT_FORMAT { | ||
| 4169 | SX_RT_EXPORT_NO_CONVERSION = 0x0, | ||
| 4170 | SX_RT_EXPORT_32_R = 0x1, | ||
| 4171 | SX_RT_EXPORT_32_A = 0x2, | ||
| 4172 | SX_RT_EXPORT_10_11_11 = 0x3, | ||
| 4173 | SX_RT_EXPORT_2_10_10_10 = 0x4, | ||
| 4174 | SX_RT_EXPORT_8_8_8_8 = 0x5, | ||
| 4175 | SX_RT_EXPORT_5_6_5 = 0x6, | ||
| 4176 | SX_RT_EXPORT_1_5_5_5 = 0x7, | ||
| 4177 | SX_RT_EXPORT_4_4_4_4 = 0x8, | ||
| 4178 | SX_RT_EXPORT_16_16_GR = 0x9, | ||
| 4179 | SX_RT_EXPORT_16_16_AR = 0xa, | ||
| 4180 | } SX_DOWNCONVERT_FORMAT; | ||
| 4181 | typedef enum TEX_BORDER_COLOR_TYPE { | ||
| 4182 | TEX_BorderColor_TransparentBlack = 0x0, | ||
| 4183 | TEX_BorderColor_OpaqueBlack = 0x1, | ||
| 4184 | TEX_BorderColor_OpaqueWhite = 0x2, | ||
| 4185 | TEX_BorderColor_Register = 0x3, | ||
| 4186 | } TEX_BORDER_COLOR_TYPE; | ||
| 4187 | typedef enum TEX_CHROMA_KEY { | ||
| 4188 | TEX_ChromaKey_Disabled = 0x0, | ||
| 4189 | TEX_ChromaKey_Kill = 0x1, | ||
| 4190 | TEX_ChromaKey_Blend = 0x2, | ||
| 4191 | TEX_ChromaKey_RESERVED_3 = 0x3, | ||
| 4192 | } TEX_CHROMA_KEY; | ||
| 4193 | typedef enum TEX_CLAMP { | ||
| 4194 | TEX_Clamp_Repeat = 0x0, | ||
| 4195 | TEX_Clamp_Mirror = 0x1, | ||
| 4196 | TEX_Clamp_ClampToLast = 0x2, | ||
| 4197 | TEX_Clamp_MirrorOnceToLast = 0x3, | ||
| 4198 | TEX_Clamp_ClampHalfToBorder = 0x4, | ||
| 4199 | TEX_Clamp_MirrorOnceHalfToBorder = 0x5, | ||
| 4200 | TEX_Clamp_ClampToBorder = 0x6, | ||
| 4201 | TEX_Clamp_MirrorOnceToBorder = 0x7, | ||
| 4202 | } TEX_CLAMP; | ||
| 4203 | typedef enum TEX_COORD_TYPE { | ||
| 4204 | TEX_CoordType_Unnormalized = 0x0, | ||
| 4205 | TEX_CoordType_Normalized = 0x1, | ||
| 4206 | } TEX_COORD_TYPE; | ||
| 4207 | typedef enum TEX_DEPTH_COMPARE_FUNCTION { | ||
| 4208 | TEX_DepthCompareFunction_Never = 0x0, | ||
| 4209 | TEX_DepthCompareFunction_Less = 0x1, | ||
| 4210 | TEX_DepthCompareFunction_Equal = 0x2, | ||
| 4211 | TEX_DepthCompareFunction_LessEqual = 0x3, | ||
| 4212 | TEX_DepthCompareFunction_Greater = 0x4, | ||
| 4213 | TEX_DepthCompareFunction_NotEqual = 0x5, | ||
| 4214 | TEX_DepthCompareFunction_GreaterEqual = 0x6, | ||
| 4215 | TEX_DepthCompareFunction_Always = 0x7, | ||
| 4216 | } TEX_DEPTH_COMPARE_FUNCTION; | ||
| 4217 | typedef enum TEX_DIM { | ||
| 4218 | TEX_Dim_1D = 0x0, | ||
| 4219 | TEX_Dim_2D = 0x1, | ||
| 4220 | TEX_Dim_3D = 0x2, | ||
| 4221 | TEX_Dim_CubeMap = 0x3, | ||
| 4222 | TEX_Dim_1DArray = 0x4, | ||
| 4223 | TEX_Dim_2DArray = 0x5, | ||
| 4224 | TEX_Dim_2D_MSAA = 0x6, | ||
| 4225 | TEX_Dim_2DArray_MSAA = 0x7, | ||
| 4226 | } TEX_DIM; | ||
| 4227 | typedef enum TEX_FORMAT_COMP { | ||
| 4228 | TEX_FormatComp_Unsigned = 0x0, | ||
| 4229 | TEX_FormatComp_Signed = 0x1, | ||
| 4230 | TEX_FormatComp_UnsignedBiased = 0x2, | ||
| 4231 | TEX_FormatComp_RESERVED_3 = 0x3, | ||
| 4232 | } TEX_FORMAT_COMP; | ||
| 4233 | typedef enum TEX_MAX_ANISO_RATIO { | ||
| 4234 | TEX_MaxAnisoRatio_1to1 = 0x0, | ||
| 4235 | TEX_MaxAnisoRatio_2to1 = 0x1, | ||
| 4236 | TEX_MaxAnisoRatio_4to1 = 0x2, | ||
| 4237 | TEX_MaxAnisoRatio_8to1 = 0x3, | ||
| 4238 | TEX_MaxAnisoRatio_16to1 = 0x4, | ||
| 4239 | TEX_MaxAnisoRatio_RESERVED_5 = 0x5, | ||
| 4240 | TEX_MaxAnisoRatio_RESERVED_6 = 0x6, | ||
| 4241 | TEX_MaxAnisoRatio_RESERVED_7 = 0x7, | ||
| 4242 | } TEX_MAX_ANISO_RATIO; | ||
| 4243 | typedef enum TEX_MIP_FILTER { | ||
| 4244 | TEX_MipFilter_None = 0x0, | ||
| 4245 | TEX_MipFilter_Point = 0x1, | ||
| 4246 | TEX_MipFilter_Linear = 0x2, | ||
| 4247 | TEX_MipFilter_Point_Aniso_Adj = 0x3, | ||
| 4248 | } TEX_MIP_FILTER; | ||
| 4249 | typedef enum TEX_REQUEST_SIZE { | ||
| 4250 | TEX_RequestSize_32B = 0x0, | ||
| 4251 | TEX_RequestSize_64B = 0x1, | ||
| 4252 | TEX_RequestSize_128B = 0x2, | ||
| 4253 | TEX_RequestSize_2X64B = 0x3, | ||
| 4254 | } TEX_REQUEST_SIZE; | ||
| 4255 | typedef enum TEX_SAMPLER_TYPE { | ||
| 4256 | TEX_SamplerType_Invalid = 0x0, | ||
| 4257 | TEX_SamplerType_Valid = 0x1, | ||
| 4258 | } TEX_SAMPLER_TYPE; | ||
| 4259 | typedef enum TEX_XY_FILTER { | ||
| 4260 | TEX_XYFilter_Point = 0x0, | ||
| 4261 | TEX_XYFilter_Linear = 0x1, | ||
| 4262 | TEX_XYFilter_AnisoPoint = 0x2, | ||
| 4263 | TEX_XYFilter_AnisoLinear = 0x3, | ||
| 4264 | } TEX_XY_FILTER; | ||
| 4265 | typedef enum TEX_Z_FILTER { | ||
| 4266 | TEX_ZFilter_None = 0x0, | ||
| 4267 | TEX_ZFilter_Point = 0x1, | ||
| 4268 | TEX_ZFilter_Linear = 0x2, | ||
| 4269 | TEX_ZFilter_RESERVED_3 = 0x3, | ||
| 4270 | } TEX_Z_FILTER; | ||
| 4271 | typedef enum VTX_CLAMP { | ||
| 4272 | VTX_Clamp_ClampToZero = 0x0, | ||
| 4273 | VTX_Clamp_ClampToNAN = 0x1, | ||
| 4274 | } VTX_CLAMP; | ||
| 4275 | typedef enum VTX_FETCH_TYPE { | ||
| 4276 | VTX_FetchType_VertexData = 0x0, | ||
| 4277 | VTX_FetchType_InstanceData = 0x1, | ||
| 4278 | VTX_FetchType_NoIndexOffset = 0x2, | ||
| 4279 | VTX_FetchType_RESERVED_3 = 0x3, | ||
| 4280 | } VTX_FETCH_TYPE; | ||
| 4281 | typedef enum VTX_FORMAT_COMP_ALL { | ||
| 4282 | VTX_FormatCompAll_Unsigned = 0x0, | ||
| 4283 | VTX_FormatCompAll_Signed = 0x1, | ||
| 4284 | } VTX_FORMAT_COMP_ALL; | ||
| 4285 | typedef enum VTX_MEM_REQUEST_SIZE { | ||
| 4286 | VTX_MemRequestSize_32B = 0x0, | ||
| 4287 | VTX_MemRequestSize_64B = 0x1, | ||
| 4288 | } VTX_MEM_REQUEST_SIZE; | ||
| 4289 | typedef enum TVX_DATA_FORMAT { | ||
| 4290 | TVX_FMT_INVALID = 0x0, | ||
| 4291 | TVX_FMT_8 = 0x1, | ||
| 4292 | TVX_FMT_4_4 = 0x2, | ||
| 4293 | TVX_FMT_3_3_2 = 0x3, | ||
| 4294 | TVX_FMT_RESERVED_4 = 0x4, | ||
| 4295 | TVX_FMT_16 = 0x5, | ||
| 4296 | TVX_FMT_16_FLOAT = 0x6, | ||
| 4297 | TVX_FMT_8_8 = 0x7, | ||
| 4298 | TVX_FMT_5_6_5 = 0x8, | ||
| 4299 | TVX_FMT_6_5_5 = 0x9, | ||
| 4300 | TVX_FMT_1_5_5_5 = 0xa, | ||
| 4301 | TVX_FMT_4_4_4_4 = 0xb, | ||
| 4302 | TVX_FMT_5_5_5_1 = 0xc, | ||
| 4303 | TVX_FMT_32 = 0xd, | ||
| 4304 | TVX_FMT_32_FLOAT = 0xe, | ||
| 4305 | TVX_FMT_16_16 = 0xf, | ||
| 4306 | TVX_FMT_16_16_FLOAT = 0x10, | ||
| 4307 | TVX_FMT_8_24 = 0x11, | ||
| 4308 | TVX_FMT_8_24_FLOAT = 0x12, | ||
| 4309 | TVX_FMT_24_8 = 0x13, | ||
| 4310 | TVX_FMT_24_8_FLOAT = 0x14, | ||
| 4311 | TVX_FMT_10_11_11 = 0x15, | ||
| 4312 | TVX_FMT_10_11_11_FLOAT = 0x16, | ||
| 4313 | TVX_FMT_11_11_10 = 0x17, | ||
| 4314 | TVX_FMT_11_11_10_FLOAT = 0x18, | ||
| 4315 | TVX_FMT_2_10_10_10 = 0x19, | ||
| 4316 | TVX_FMT_8_8_8_8 = 0x1a, | ||
| 4317 | TVX_FMT_10_10_10_2 = 0x1b, | ||
| 4318 | TVX_FMT_X24_8_32_FLOAT = 0x1c, | ||
| 4319 | TVX_FMT_32_32 = 0x1d, | ||
| 4320 | TVX_FMT_32_32_FLOAT = 0x1e, | ||
| 4321 | TVX_FMT_16_16_16_16 = 0x1f, | ||
| 4322 | TVX_FMT_16_16_16_16_FLOAT = 0x20, | ||
| 4323 | TVX_FMT_RESERVED_33 = 0x21, | ||
| 4324 | TVX_FMT_32_32_32_32 = 0x22, | ||
| 4325 | TVX_FMT_32_32_32_32_FLOAT = 0x23, | ||
| 4326 | TVX_FMT_RESERVED_36 = 0x24, | ||
| 4327 | TVX_FMT_1 = 0x25, | ||
| 4328 | TVX_FMT_1_REVERSED = 0x26, | ||
| 4329 | TVX_FMT_GB_GR = 0x27, | ||
| 4330 | TVX_FMT_BG_RG = 0x28, | ||
| 4331 | TVX_FMT_32_AS_8 = 0x29, | ||
| 4332 | TVX_FMT_32_AS_8_8 = 0x2a, | ||
| 4333 | TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, | ||
| 4334 | TVX_FMT_8_8_8 = 0x2c, | ||
| 4335 | TVX_FMT_16_16_16 = 0x2d, | ||
| 4336 | TVX_FMT_16_16_16_FLOAT = 0x2e, | ||
| 4337 | TVX_FMT_32_32_32 = 0x2f, | ||
| 4338 | TVX_FMT_32_32_32_FLOAT = 0x30, | ||
| 4339 | TVX_FMT_BC1 = 0x31, | ||
| 4340 | TVX_FMT_BC2 = 0x32, | ||
| 4341 | TVX_FMT_BC3 = 0x33, | ||
| 4342 | TVX_FMT_BC4 = 0x34, | ||
| 4343 | TVX_FMT_BC5 = 0x35, | ||
| 4344 | TVX_FMT_APC0 = 0x36, | ||
| 4345 | TVX_FMT_APC1 = 0x37, | ||
| 4346 | TVX_FMT_APC2 = 0x38, | ||
| 4347 | TVX_FMT_APC3 = 0x39, | ||
| 4348 | TVX_FMT_APC4 = 0x3a, | ||
| 4349 | TVX_FMT_APC5 = 0x3b, | ||
| 4350 | TVX_FMT_APC6 = 0x3c, | ||
| 4351 | TVX_FMT_APC7 = 0x3d, | ||
| 4352 | TVX_FMT_CTX1 = 0x3e, | ||
| 4353 | TVX_FMT_RESERVED_63 = 0x3f, | ||
| 4354 | } TVX_DATA_FORMAT; | ||
| 4355 | typedef enum TVX_DST_SEL { | ||
| 4356 | TVX_DstSel_X = 0x0, | ||
| 4357 | TVX_DstSel_Y = 0x1, | ||
| 4358 | TVX_DstSel_Z = 0x2, | ||
| 4359 | TVX_DstSel_W = 0x3, | ||
| 4360 | TVX_DstSel_0f = 0x4, | ||
| 4361 | TVX_DstSel_1f = 0x5, | ||
| 4362 | TVX_DstSel_RESERVED_6 = 0x6, | ||
| 4363 | TVX_DstSel_Mask = 0x7, | ||
| 4364 | } TVX_DST_SEL; | ||
| 4365 | typedef enum TVX_ENDIAN_SWAP { | ||
| 4366 | TVX_EndianSwap_None = 0x0, | ||
| 4367 | TVX_EndianSwap_8in16 = 0x1, | ||
| 4368 | TVX_EndianSwap_8in32 = 0x2, | ||
| 4369 | TVX_EndianSwap_8in64 = 0x3, | ||
| 4370 | } TVX_ENDIAN_SWAP; | ||
| 4371 | typedef enum TVX_INST { | ||
| 4372 | TVX_Inst_NormalVertexFetch = 0x0, | ||
| 4373 | TVX_Inst_SemanticVertexFetch = 0x1, | ||
| 4374 | TVX_Inst_RESERVED_2 = 0x2, | ||
| 4375 | TVX_Inst_LD = 0x3, | ||
| 4376 | TVX_Inst_GetTextureResInfo = 0x4, | ||
| 4377 | TVX_Inst_GetNumberOfSamples = 0x5, | ||
| 4378 | TVX_Inst_GetLOD = 0x6, | ||
| 4379 | TVX_Inst_GetGradientsH = 0x7, | ||
| 4380 | TVX_Inst_GetGradientsV = 0x8, | ||
| 4381 | TVX_Inst_SetTextureOffsets = 0x9, | ||
| 4382 | TVX_Inst_KeepGradients = 0xa, | ||
| 4383 | TVX_Inst_SetGradientsH = 0xb, | ||
| 4384 | TVX_Inst_SetGradientsV = 0xc, | ||
| 4385 | TVX_Inst_Pass = 0xd, | ||
| 4386 | TVX_Inst_GetBufferResInfo = 0xe, | ||
| 4387 | TVX_Inst_RESERVED_15 = 0xf, | ||
| 4388 | TVX_Inst_Sample = 0x10, | ||
| 4389 | TVX_Inst_Sample_L = 0x11, | ||
| 4390 | TVX_Inst_Sample_LB = 0x12, | ||
| 4391 | TVX_Inst_Sample_LZ = 0x13, | ||
| 4392 | TVX_Inst_Sample_G = 0x14, | ||
| 4393 | TVX_Inst_Gather4 = 0x15, | ||
| 4394 | TVX_Inst_Sample_G_LB = 0x16, | ||
| 4395 | TVX_Inst_Gather4_O = 0x17, | ||
| 4396 | TVX_Inst_Sample_C = 0x18, | ||
| 4397 | TVX_Inst_Sample_C_L = 0x19, | ||
| 4398 | TVX_Inst_Sample_C_LB = 0x1a, | ||
| 4399 | TVX_Inst_Sample_C_LZ = 0x1b, | ||
| 4400 | TVX_Inst_Sample_C_G = 0x1c, | ||
| 4401 | TVX_Inst_Gather4_C = 0x1d, | ||
| 4402 | TVX_Inst_Sample_C_G_LB = 0x1e, | ||
| 4403 | TVX_Inst_Gather4_C_O = 0x1f, | ||
| 4404 | } TVX_INST; | ||
| 4405 | typedef enum TVX_NUM_FORMAT_ALL { | ||
| 4406 | TVX_NumFormatAll_Norm = 0x0, | ||
| 4407 | TVX_NumFormatAll_Int = 0x1, | ||
| 4408 | TVX_NumFormatAll_Scaled = 0x2, | ||
| 4409 | TVX_NumFormatAll_RESERVED_3 = 0x3, | ||
| 4410 | } TVX_NUM_FORMAT_ALL; | ||
| 4411 | typedef enum TVX_SRC_SEL { | ||
| 4412 | TVX_SrcSel_X = 0x0, | ||
| 4413 | TVX_SrcSel_Y = 0x1, | ||
| 4414 | TVX_SrcSel_Z = 0x2, | ||
| 4415 | TVX_SrcSel_W = 0x3, | ||
| 4416 | TVX_SrcSel_0f = 0x4, | ||
| 4417 | TVX_SrcSel_1f = 0x5, | ||
| 4418 | } TVX_SRC_SEL; | ||
| 4419 | typedef enum TVX_SRF_MODE_ALL { | ||
| 4420 | TVX_SRFModeAll_ZCMO = 0x0, | ||
| 4421 | TVX_SRFModeAll_NZ = 0x1, | ||
| 4422 | } TVX_SRF_MODE_ALL; | ||
| 4423 | typedef enum TVX_TYPE { | ||
| 4424 | TVX_Type_InvalidTextureResource = 0x0, | ||
| 4425 | TVX_Type_InvalidVertexBuffer = 0x1, | ||
| 4426 | TVX_Type_ValidTextureResource = 0x2, | ||
| 4427 | TVX_Type_ValidVertexBuffer = 0x3, | ||
| 4428 | } TVX_TYPE; | ||
| 4429 | typedef enum TC_OP_MASKS { | ||
| 4430 | TC_OP_MASK_FLUSH_DENROM = 0x8, | ||
| 4431 | TC_OP_MASK_64 = 0x20, | ||
| 4432 | TC_OP_MASK_NO_RTN = 0x40, | ||
| 4433 | } TC_OP_MASKS; | ||
| 4434 | typedef enum TC_OP { | ||
| 4435 | TC_OP_READ = 0x0, | ||
| 4436 | TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, | ||
| 4437 | TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, | ||
| 4438 | TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, | ||
| 4439 | TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, | ||
| 4440 | TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, | ||
| 4441 | TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, | ||
| 4442 | TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, | ||
| 4443 | TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, | ||
| 4444 | TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, | ||
| 4445 | TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, | ||
| 4446 | TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, | ||
| 4447 | TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, | ||
| 4448 | TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, | ||
| 4449 | TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, | ||
| 4450 | TC_OP_ATOMIC_ADD_RTN_32 = 0xf, | ||
| 4451 | TC_OP_ATOMIC_SUB_RTN_32 = 0x10, | ||
| 4452 | TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, | ||
| 4453 | TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, | ||
| 4454 | TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, | ||
| 4455 | TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, | ||
| 4456 | TC_OP_ATOMIC_AND_RTN_32 = 0x15, | ||
| 4457 | TC_OP_ATOMIC_OR_RTN_32 = 0x16, | ||
| 4458 | TC_OP_ATOMIC_XOR_RTN_32 = 0x17, | ||
| 4459 | TC_OP_ATOMIC_INC_RTN_32 = 0x18, | ||
| 4460 | TC_OP_ATOMIC_DEC_RTN_32 = 0x19, | ||
| 4461 | TC_OP_WBINVL1_VOL = 0x1a, | ||
| 4462 | TC_OP_WBINVL1_SD = 0x1b, | ||
| 4463 | TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c, | ||
| 4464 | TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d, | ||
| 4465 | TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e, | ||
| 4466 | TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f, | ||
| 4467 | TC_OP_WRITE = 0x20, | ||
| 4468 | TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, | ||
| 4469 | TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, | ||
| 4470 | TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, | ||
| 4471 | TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, | ||
| 4472 | TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, | ||
| 4473 | TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, | ||
| 4474 | TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, | ||
| 4475 | TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, | ||
| 4476 | TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, | ||
| 4477 | TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, | ||
| 4478 | TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, | ||
| 4479 | TC_OP_WBINVL2_SD = 0x2c, | ||
| 4480 | TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d, | ||
| 4481 | TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e, | ||
| 4482 | TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, | ||
| 4483 | TC_OP_ATOMIC_SUB_RTN_64 = 0x30, | ||
| 4484 | TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, | ||
| 4485 | TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, | ||
| 4486 | TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, | ||
| 4487 | TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, | ||
| 4488 | TC_OP_ATOMIC_AND_RTN_64 = 0x35, | ||
| 4489 | TC_OP_ATOMIC_OR_RTN_64 = 0x36, | ||
| 4490 | TC_OP_ATOMIC_XOR_RTN_64 = 0x37, | ||
| 4491 | TC_OP_ATOMIC_INC_RTN_64 = 0x38, | ||
| 4492 | TC_OP_ATOMIC_DEC_RTN_64 = 0x39, | ||
| 4493 | TC_OP_WBL2_NC = 0x3a, | ||
| 4494 | TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, | ||
| 4495 | TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, | ||
| 4496 | TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, | ||
| 4497 | TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, | ||
| 4498 | TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, | ||
| 4499 | TC_OP_WBINVL1 = 0x40, | ||
| 4500 | TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, | ||
| 4501 | TC_OP_ATOMIC_FMIN_32 = 0x42, | ||
| 4502 | TC_OP_ATOMIC_FMAX_32 = 0x43, | ||
| 4503 | TC_OP_RESERVED_FOP_32_0 = 0x44, | ||
| 4504 | TC_OP_RESERVED_FOP_32_1 = 0x45, | ||
| 4505 | TC_OP_RESERVED_FOP_32_2 = 0x46, | ||
| 4506 | TC_OP_ATOMIC_SWAP_32 = 0x47, | ||
| 4507 | TC_OP_ATOMIC_CMPSWAP_32 = 0x48, | ||
| 4508 | TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, | ||
| 4509 | TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, | ||
| 4510 | TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, | ||
| 4511 | TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, | ||
| 4512 | TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, | ||
| 4513 | TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, | ||
| 4514 | TC_OP_ATOMIC_ADD_32 = 0x4f, | ||
| 4515 | TC_OP_ATOMIC_SUB_32 = 0x50, | ||
| 4516 | TC_OP_ATOMIC_SMIN_32 = 0x51, | ||
| 4517 | TC_OP_ATOMIC_UMIN_32 = 0x52, | ||
| 4518 | TC_OP_ATOMIC_SMAX_32 = 0x53, | ||
| 4519 | TC_OP_ATOMIC_UMAX_32 = 0x54, | ||
| 4520 | TC_OP_ATOMIC_AND_32 = 0x55, | ||
| 4521 | TC_OP_ATOMIC_OR_32 = 0x56, | ||
| 4522 | TC_OP_ATOMIC_XOR_32 = 0x57, | ||
| 4523 | TC_OP_ATOMIC_INC_32 = 0x58, | ||
| 4524 | TC_OP_ATOMIC_DEC_32 = 0x59, | ||
| 4525 | TC_OP_INVL2_NC = 0x5a, | ||
| 4526 | TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, | ||
| 4527 | TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, | ||
| 4528 | TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, | ||
| 4529 | TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, | ||
| 4530 | TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, | ||
| 4531 | TC_OP_WBINVL2 = 0x60, | ||
| 4532 | TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, | ||
| 4533 | TC_OP_ATOMIC_FMIN_64 = 0x62, | ||
| 4534 | TC_OP_ATOMIC_FMAX_64 = 0x63, | ||
| 4535 | TC_OP_RESERVED_FOP_64_0 = 0x64, | ||
| 4536 | TC_OP_RESERVED_FOP_64_1 = 0x65, | ||
| 4537 | TC_OP_RESERVED_FOP_64_2 = 0x66, | ||
| 4538 | TC_OP_ATOMIC_SWAP_64 = 0x67, | ||
| 4539 | TC_OP_ATOMIC_CMPSWAP_64 = 0x68, | ||
| 4540 | TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, | ||
| 4541 | TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, | ||
| 4542 | TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, | ||
| 4543 | TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, | ||
| 4544 | TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, | ||
| 4545 | TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, | ||
| 4546 | TC_OP_ATOMIC_ADD_64 = 0x6f, | ||
| 4547 | TC_OP_ATOMIC_SUB_64 = 0x70, | ||
| 4548 | TC_OP_ATOMIC_SMIN_64 = 0x71, | ||
| 4549 | TC_OP_ATOMIC_UMIN_64 = 0x72, | ||
| 4550 | TC_OP_ATOMIC_SMAX_64 = 0x73, | ||
| 4551 | TC_OP_ATOMIC_UMAX_64 = 0x74, | ||
| 4552 | TC_OP_ATOMIC_AND_64 = 0x75, | ||
| 4553 | TC_OP_ATOMIC_OR_64 = 0x76, | ||
| 4554 | TC_OP_ATOMIC_XOR_64 = 0x77, | ||
| 4555 | TC_OP_ATOMIC_INC_64 = 0x78, | ||
| 4556 | TC_OP_ATOMIC_DEC_64 = 0x79, | ||
| 4557 | TC_OP_WBINVL2_NC = 0x7a, | ||
| 4558 | TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, | ||
| 4559 | TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, | ||
| 4560 | TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, | ||
| 4561 | TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, | ||
| 4562 | TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, | ||
| 4563 | } TC_OP; | ||
| 4564 | typedef enum TC_CHUB_REQ_CREDITS_ENUM { | ||
| 4565 | TC_CHUB_REQ_CREDITS = 0x10, | ||
| 4566 | } TC_CHUB_REQ_CREDITS_ENUM; | ||
| 4567 | typedef enum CHUB_TC_RET_CREDITS_ENUM { | ||
| 4568 | CHUB_TC_RET_CREDITS = 0x20, | ||
| 4569 | } CHUB_TC_RET_CREDITS_ENUM; | ||
| 4570 | typedef enum TC_NACKS { | ||
| 4571 | TC_NACK_NO_FAULT = 0x0, | ||
| 4572 | TC_NACK_PAGE_FAULT = 0x1, | ||
| 4573 | TC_NACK_PROTECTION_FAULT = 0x2, | ||
| 4574 | TC_NACK_DATA_ERROR = 0x3, | ||
| 4575 | } TC_NACKS; | ||
| 4576 | typedef enum TCC_PERF_SEL { | ||
| 4577 | TCC_PERF_SEL_NONE = 0x0, | ||
| 4578 | TCC_PERF_SEL_CYCLE = 0x1, | ||
| 4579 | TCC_PERF_SEL_BUSY = 0x2, | ||
| 4580 | TCC_PERF_SEL_REQ = 0x3, | ||
| 4581 | TCC_PERF_SEL_STREAMING_REQ = 0x4, | ||
| 4582 | TCC_PERF_SEL_EXE_REQ = 0x5, | ||
| 4583 | TCC_PERF_SEL_COMPRESSED_REQ = 0x6, | ||
| 4584 | TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7, | ||
| 4585 | TCC_PERF_SEL_METADATA_REQ = 0x8, | ||
| 4586 | TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9, | ||
| 4587 | TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa, | ||
| 4588 | TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb, | ||
| 4589 | TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc, | ||
| 4590 | TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd, | ||
| 4591 | TCC_PERF_SEL_PROBE = 0xe, | ||
| 4592 | TCC_PERF_SEL_READ = 0xf, | ||
| 4593 | TCC_PERF_SEL_WRITE = 0x10, | ||
| 4594 | TCC_PERF_SEL_ATOMIC = 0x11, | ||
| 4595 | TCC_PERF_SEL_HIT = 0x12, | ||
| 4596 | TCC_PERF_SEL_MISS = 0x13, | ||
| 4597 | TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14, | ||
| 4598 | TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15, | ||
| 4599 | TCC_PERF_SEL_WRITEBACK = 0x16, | ||
| 4600 | TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17, | ||
| 4601 | TCC_PERF_SEL_SRC_FIFO_FULL = 0x18, | ||
| 4602 | TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19, | ||
| 4603 | TCC_PERF_SEL_MC_WRREQ = 0x1a, | ||
| 4604 | TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b, | ||
| 4605 | TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c, | ||
| 4606 | TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d, | ||
| 4607 | TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e, | ||
| 4608 | TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f, | ||
| 4609 | TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20, | ||
| 4610 | TCC_PERF_SEL_MC_ATOMIC = 0x21, | ||
| 4611 | TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22, | ||
| 4612 | TCC_PERF_SEL_MC_RDREQ = 0x23, | ||
| 4613 | TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24, | ||
| 4614 | TCC_PERF_SEL_MC_RDREQ_MDC = 0x25, | ||
| 4615 | TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26, | ||
| 4616 | TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27, | ||
| 4617 | TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28, | ||
| 4618 | TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29, | ||
| 4619 | TCC_PERF_SEL_TAG_STALL = 0x2a, | ||
| 4620 | TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b, | ||
| 4621 | TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c, | ||
| 4622 | TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d, | ||
| 4623 | TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e, | ||
| 4624 | TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f, | ||
| 4625 | TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30, | ||
| 4626 | TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31, | ||
| 4627 | TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32, | ||
| 4628 | TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33, | ||
| 4629 | TCC_PERF_SEL_BUBBLE = 0x34, | ||
| 4630 | TCC_PERF_SEL_RETURN_ACK = 0x35, | ||
| 4631 | TCC_PERF_SEL_RETURN_DATA = 0x36, | ||
| 4632 | TCC_PERF_SEL_RETURN_HOLE = 0x37, | ||
| 4633 | TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38, | ||
| 4634 | TCC_PERF_SEL_IB_REQ = 0x39, | ||
| 4635 | TCC_PERF_SEL_IB_STALL = 0x3a, | ||
| 4636 | TCC_PERF_SEL_IB_TAG_STALL = 0x3b, | ||
| 4637 | TCC_PERF_SEL_IB_MDC_STALL = 0x3c, | ||
| 4638 | TCC_PERF_SEL_TCA_LEVEL = 0x3d, | ||
| 4639 | TCC_PERF_SEL_HOLE_LEVEL = 0x3e, | ||
| 4640 | TCC_PERF_SEL_MC_RDRET_NACK = 0x3f, | ||
| 4641 | TCC_PERF_SEL_MC_WRRET_NACK = 0x40, | ||
| 4642 | TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41, | ||
| 4643 | TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42, | ||
| 4644 | TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43, | ||
| 4645 | TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44, | ||
| 4646 | TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45, | ||
| 4647 | TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46, | ||
| 4648 | TCC_PERF_SEL_NORMAL_EVICT = 0x47, | ||
| 4649 | TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48, | ||
| 4650 | TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49, | ||
| 4651 | TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a, | ||
| 4652 | TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b, | ||
| 4653 | TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c, | ||
| 4654 | TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d, | ||
| 4655 | TCC_PERF_SEL_PROBE_EVICT = 0x4e, | ||
| 4656 | TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f, | ||
| 4657 | TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50, | ||
| 4658 | TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51, | ||
| 4659 | TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52, | ||
| 4660 | TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53, | ||
| 4661 | TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54, | ||
| 4662 | TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55, | ||
| 4663 | TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56, | ||
| 4664 | TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57, | ||
| 4665 | TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58, | ||
| 4666 | TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59, | ||
| 4667 | TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a, | ||
| 4668 | TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b, | ||
| 4669 | TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c, | ||
| 4670 | TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d, | ||
| 4671 | TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e, | ||
| 4672 | TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f, | ||
| 4673 | TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60, | ||
| 4674 | TCC_PERF_SEL_MDC_REQ = 0x61, | ||
| 4675 | TCC_PERF_SEL_MDC_LEVEL = 0x62, | ||
| 4676 | TCC_PERF_SEL_MDC_TAG_HIT = 0x63, | ||
| 4677 | TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64, | ||
| 4678 | TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65, | ||
| 4679 | TCC_PERF_SEL_MDC_TAG_STALL = 0x66, | ||
| 4680 | TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67, | ||
| 4681 | TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68, | ||
| 4682 | TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69, | ||
| 4683 | TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a, | ||
| 4684 | TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b, | ||
| 4685 | TCC_PERF_SEL_CLIENT0_REQ = 0x80, | ||
| 4686 | TCC_PERF_SEL_CLIENT1_REQ = 0x81, | ||
| 4687 | TCC_PERF_SEL_CLIENT2_REQ = 0x82, | ||
| 4688 | TCC_PERF_SEL_CLIENT3_REQ = 0x83, | ||
| 4689 | TCC_PERF_SEL_CLIENT4_REQ = 0x84, | ||
| 4690 | TCC_PERF_SEL_CLIENT5_REQ = 0x85, | ||
| 4691 | TCC_PERF_SEL_CLIENT6_REQ = 0x86, | ||
| 4692 | TCC_PERF_SEL_CLIENT7_REQ = 0x87, | ||
| 4693 | TCC_PERF_SEL_CLIENT8_REQ = 0x88, | ||
| 4694 | TCC_PERF_SEL_CLIENT9_REQ = 0x89, | ||
| 4695 | TCC_PERF_SEL_CLIENT10_REQ = 0x8a, | ||
| 4696 | TCC_PERF_SEL_CLIENT11_REQ = 0x8b, | ||
| 4697 | TCC_PERF_SEL_CLIENT12_REQ = 0x8c, | ||
| 4698 | TCC_PERF_SEL_CLIENT13_REQ = 0x8d, | ||
| 4699 | TCC_PERF_SEL_CLIENT14_REQ = 0x8e, | ||
| 4700 | TCC_PERF_SEL_CLIENT15_REQ = 0x8f, | ||
| 4701 | TCC_PERF_SEL_CLIENT16_REQ = 0x90, | ||
| 4702 | TCC_PERF_SEL_CLIENT17_REQ = 0x91, | ||
| 4703 | TCC_PERF_SEL_CLIENT18_REQ = 0x92, | ||
| 4704 | TCC_PERF_SEL_CLIENT19_REQ = 0x93, | ||
| 4705 | TCC_PERF_SEL_CLIENT20_REQ = 0x94, | ||
| 4706 | TCC_PERF_SEL_CLIENT21_REQ = 0x95, | ||
| 4707 | TCC_PERF_SEL_CLIENT22_REQ = 0x96, | ||
| 4708 | TCC_PERF_SEL_CLIENT23_REQ = 0x97, | ||
| 4709 | TCC_PERF_SEL_CLIENT24_REQ = 0x98, | ||
| 4710 | TCC_PERF_SEL_CLIENT25_REQ = 0x99, | ||
| 4711 | TCC_PERF_SEL_CLIENT26_REQ = 0x9a, | ||
| 4712 | TCC_PERF_SEL_CLIENT27_REQ = 0x9b, | ||
| 4713 | TCC_PERF_SEL_CLIENT28_REQ = 0x9c, | ||
| 4714 | TCC_PERF_SEL_CLIENT29_REQ = 0x9d, | ||
| 4715 | TCC_PERF_SEL_CLIENT30_REQ = 0x9e, | ||
| 4716 | TCC_PERF_SEL_CLIENT31_REQ = 0x9f, | ||
| 4717 | TCC_PERF_SEL_CLIENT32_REQ = 0xa0, | ||
| 4718 | TCC_PERF_SEL_CLIENT33_REQ = 0xa1, | ||
| 4719 | TCC_PERF_SEL_CLIENT34_REQ = 0xa2, | ||
| 4720 | TCC_PERF_SEL_CLIENT35_REQ = 0xa3, | ||
| 4721 | TCC_PERF_SEL_CLIENT36_REQ = 0xa4, | ||
| 4722 | TCC_PERF_SEL_CLIENT37_REQ = 0xa5, | ||
| 4723 | TCC_PERF_SEL_CLIENT38_REQ = 0xa6, | ||
| 4724 | TCC_PERF_SEL_CLIENT39_REQ = 0xa7, | ||
| 4725 | TCC_PERF_SEL_CLIENT40_REQ = 0xa8, | ||
| 4726 | TCC_PERF_SEL_CLIENT41_REQ = 0xa9, | ||
| 4727 | TCC_PERF_SEL_CLIENT42_REQ = 0xaa, | ||
| 4728 | TCC_PERF_SEL_CLIENT43_REQ = 0xab, | ||
| 4729 | TCC_PERF_SEL_CLIENT44_REQ = 0xac, | ||
| 4730 | TCC_PERF_SEL_CLIENT45_REQ = 0xad, | ||
| 4731 | TCC_PERF_SEL_CLIENT46_REQ = 0xae, | ||
| 4732 | TCC_PERF_SEL_CLIENT47_REQ = 0xaf, | ||
| 4733 | TCC_PERF_SEL_CLIENT48_REQ = 0xb0, | ||
| 4734 | TCC_PERF_SEL_CLIENT49_REQ = 0xb1, | ||
| 4735 | TCC_PERF_SEL_CLIENT50_REQ = 0xb2, | ||
| 4736 | TCC_PERF_SEL_CLIENT51_REQ = 0xb3, | ||
| 4737 | TCC_PERF_SEL_CLIENT52_REQ = 0xb4, | ||
| 4738 | TCC_PERF_SEL_CLIENT53_REQ = 0xb5, | ||
| 4739 | TCC_PERF_SEL_CLIENT54_REQ = 0xb6, | ||
| 4740 | TCC_PERF_SEL_CLIENT55_REQ = 0xb7, | ||
| 4741 | TCC_PERF_SEL_CLIENT56_REQ = 0xb8, | ||
| 4742 | TCC_PERF_SEL_CLIENT57_REQ = 0xb9, | ||
| 4743 | TCC_PERF_SEL_CLIENT58_REQ = 0xba, | ||
| 4744 | TCC_PERF_SEL_CLIENT59_REQ = 0xbb, | ||
| 4745 | TCC_PERF_SEL_CLIENT60_REQ = 0xbc, | ||
| 4746 | TCC_PERF_SEL_CLIENT61_REQ = 0xbd, | ||
| 4747 | TCC_PERF_SEL_CLIENT62_REQ = 0xbe, | ||
| 4748 | TCC_PERF_SEL_CLIENT63_REQ = 0xbf, | ||
| 4749 | TCC_PERF_SEL_CLIENT64_REQ = 0xc0, | ||
| 4750 | TCC_PERF_SEL_CLIENT65_REQ = 0xc1, | ||
| 4751 | TCC_PERF_SEL_CLIENT66_REQ = 0xc2, | ||
| 4752 | TCC_PERF_SEL_CLIENT67_REQ = 0xc3, | ||
| 4753 | TCC_PERF_SEL_CLIENT68_REQ = 0xc4, | ||
| 4754 | TCC_PERF_SEL_CLIENT69_REQ = 0xc5, | ||
| 4755 | TCC_PERF_SEL_CLIENT70_REQ = 0xc6, | ||
| 4756 | TCC_PERF_SEL_CLIENT71_REQ = 0xc7, | ||
| 4757 | TCC_PERF_SEL_CLIENT72_REQ = 0xc8, | ||
| 4758 | TCC_PERF_SEL_CLIENT73_REQ = 0xc9, | ||
| 4759 | TCC_PERF_SEL_CLIENT74_REQ = 0xca, | ||
| 4760 | TCC_PERF_SEL_CLIENT75_REQ = 0xcb, | ||
| 4761 | TCC_PERF_SEL_CLIENT76_REQ = 0xcc, | ||
| 4762 | TCC_PERF_SEL_CLIENT77_REQ = 0xcd, | ||
| 4763 | TCC_PERF_SEL_CLIENT78_REQ = 0xce, | ||
| 4764 | TCC_PERF_SEL_CLIENT79_REQ = 0xcf, | ||
| 4765 | TCC_PERF_SEL_CLIENT80_REQ = 0xd0, | ||
| 4766 | TCC_PERF_SEL_CLIENT81_REQ = 0xd1, | ||
| 4767 | TCC_PERF_SEL_CLIENT82_REQ = 0xd2, | ||
| 4768 | TCC_PERF_SEL_CLIENT83_REQ = 0xd3, | ||
| 4769 | TCC_PERF_SEL_CLIENT84_REQ = 0xd4, | ||
| 4770 | TCC_PERF_SEL_CLIENT85_REQ = 0xd5, | ||
| 4771 | TCC_PERF_SEL_CLIENT86_REQ = 0xd6, | ||
| 4772 | TCC_PERF_SEL_CLIENT87_REQ = 0xd7, | ||
| 4773 | TCC_PERF_SEL_CLIENT88_REQ = 0xd8, | ||
| 4774 | TCC_PERF_SEL_CLIENT89_REQ = 0xd9, | ||
| 4775 | TCC_PERF_SEL_CLIENT90_REQ = 0xda, | ||
| 4776 | TCC_PERF_SEL_CLIENT91_REQ = 0xdb, | ||
| 4777 | TCC_PERF_SEL_CLIENT92_REQ = 0xdc, | ||
| 4778 | TCC_PERF_SEL_CLIENT93_REQ = 0xdd, | ||
| 4779 | TCC_PERF_SEL_CLIENT94_REQ = 0xde, | ||
| 4780 | TCC_PERF_SEL_CLIENT95_REQ = 0xdf, | ||
| 4781 | TCC_PERF_SEL_CLIENT96_REQ = 0xe0, | ||
| 4782 | TCC_PERF_SEL_CLIENT97_REQ = 0xe1, | ||
| 4783 | TCC_PERF_SEL_CLIENT98_REQ = 0xe2, | ||
| 4784 | TCC_PERF_SEL_CLIENT99_REQ = 0xe3, | ||
| 4785 | TCC_PERF_SEL_CLIENT100_REQ = 0xe4, | ||
| 4786 | TCC_PERF_SEL_CLIENT101_REQ = 0xe5, | ||
| 4787 | TCC_PERF_SEL_CLIENT102_REQ = 0xe6, | ||
| 4788 | TCC_PERF_SEL_CLIENT103_REQ = 0xe7, | ||
| 4789 | TCC_PERF_SEL_CLIENT104_REQ = 0xe8, | ||
| 4790 | TCC_PERF_SEL_CLIENT105_REQ = 0xe9, | ||
| 4791 | TCC_PERF_SEL_CLIENT106_REQ = 0xea, | ||
| 4792 | TCC_PERF_SEL_CLIENT107_REQ = 0xeb, | ||
| 4793 | TCC_PERF_SEL_CLIENT108_REQ = 0xec, | ||
| 4794 | TCC_PERF_SEL_CLIENT109_REQ = 0xed, | ||
| 4795 | TCC_PERF_SEL_CLIENT110_REQ = 0xee, | ||
| 4796 | TCC_PERF_SEL_CLIENT111_REQ = 0xef, | ||
| 4797 | TCC_PERF_SEL_CLIENT112_REQ = 0xf0, | ||
| 4798 | TCC_PERF_SEL_CLIENT113_REQ = 0xf1, | ||
| 4799 | TCC_PERF_SEL_CLIENT114_REQ = 0xf2, | ||
| 4800 | TCC_PERF_SEL_CLIENT115_REQ = 0xf3, | ||
| 4801 | TCC_PERF_SEL_CLIENT116_REQ = 0xf4, | ||
| 4802 | TCC_PERF_SEL_CLIENT117_REQ = 0xf5, | ||
| 4803 | TCC_PERF_SEL_CLIENT118_REQ = 0xf6, | ||
| 4804 | TCC_PERF_SEL_CLIENT119_REQ = 0xf7, | ||
| 4805 | TCC_PERF_SEL_CLIENT120_REQ = 0xf8, | ||
| 4806 | TCC_PERF_SEL_CLIENT121_REQ = 0xf9, | ||
| 4807 | TCC_PERF_SEL_CLIENT122_REQ = 0xfa, | ||
| 4808 | TCC_PERF_SEL_CLIENT123_REQ = 0xfb, | ||
| 4809 | TCC_PERF_SEL_CLIENT124_REQ = 0xfc, | ||
| 4810 | TCC_PERF_SEL_CLIENT125_REQ = 0xfd, | ||
| 4811 | TCC_PERF_SEL_CLIENT126_REQ = 0xfe, | ||
| 4812 | TCC_PERF_SEL_CLIENT127_REQ = 0xff, | ||
| 4813 | } TCC_PERF_SEL; | ||
| 4814 | typedef enum TCA_PERF_SEL { | ||
| 4815 | TCA_PERF_SEL_NONE = 0x0, | ||
| 4816 | TCA_PERF_SEL_CYCLE = 0x1, | ||
| 4817 | TCA_PERF_SEL_BUSY = 0x2, | ||
| 4818 | TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, | ||
| 4819 | TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, | ||
| 4820 | TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, | ||
| 4821 | TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, | ||
| 4822 | TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, | ||
| 4823 | TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, | ||
| 4824 | TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, | ||
| 4825 | TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, | ||
| 4826 | TCA_PERF_SEL_REQ_TCC0 = 0xb, | ||
| 4827 | TCA_PERF_SEL_REQ_TCC1 = 0xc, | ||
| 4828 | TCA_PERF_SEL_REQ_TCC2 = 0xd, | ||
| 4829 | TCA_PERF_SEL_REQ_TCC3 = 0xe, | ||
| 4830 | TCA_PERF_SEL_REQ_TCC4 = 0xf, | ||
| 4831 | TCA_PERF_SEL_REQ_TCC5 = 0x10, | ||
| 4832 | TCA_PERF_SEL_REQ_TCC6 = 0x11, | ||
| 4833 | TCA_PERF_SEL_REQ_TCC7 = 0x12, | ||
| 4834 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, | ||
| 4835 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, | ||
| 4836 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, | ||
| 4837 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, | ||
| 4838 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, | ||
| 4839 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, | ||
| 4840 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, | ||
| 4841 | TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, | ||
| 4842 | TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, | ||
| 4843 | TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, | ||
| 4844 | TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, | ||
| 4845 | TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, | ||
| 4846 | TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, | ||
| 4847 | TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, | ||
| 4848 | TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, | ||
| 4849 | TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, | ||
| 4850 | } TCA_PERF_SEL; | ||
| 4851 | typedef enum TA_TC_ADDR_MODES { | ||
| 4852 | TA_TC_ADDR_MODE_DEFAULT = 0x0, | ||
| 4853 | TA_TC_ADDR_MODE_COMP0 = 0x1, | ||
| 4854 | TA_TC_ADDR_MODE_COMP1 = 0x2, | ||
| 4855 | TA_TC_ADDR_MODE_COMP2 = 0x3, | ||
| 4856 | TA_TC_ADDR_MODE_COMP3 = 0x4, | ||
| 4857 | TA_TC_ADDR_MODE_UNALIGNED = 0x5, | ||
| 4858 | TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, | ||
| 4859 | } TA_TC_ADDR_MODES; | ||
| 4860 | typedef enum TA_PERFCOUNT_SEL { | ||
| 4861 | TA_PERF_SEL_NULL = 0x0, | ||
| 4862 | TA_PERF_SEL_sh_fifo_busy = 0x1, | ||
| 4863 | TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, | ||
| 4864 | TA_PERF_SEL_sh_fifo_addr_busy = 0x3, | ||
| 4865 | TA_PERF_SEL_sh_fifo_data_busy = 0x4, | ||
| 4866 | TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, | ||
| 4867 | TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, | ||
| 4868 | TA_PERF_SEL_gradient_busy = 0x7, | ||
| 4869 | TA_PERF_SEL_gradient_fifo_busy = 0x8, | ||
| 4870 | TA_PERF_SEL_lod_busy = 0x9, | ||
| 4871 | TA_PERF_SEL_lod_fifo_busy = 0xa, | ||
| 4872 | TA_PERF_SEL_addresser_busy = 0xb, | ||
| 4873 | TA_PERF_SEL_addresser_fifo_busy = 0xc, | ||
| 4874 | TA_PERF_SEL_aligner_busy = 0xd, | ||
| 4875 | TA_PERF_SEL_write_path_busy = 0xe, | ||
| 4876 | TA_PERF_SEL_ta_busy = 0xf, | ||
| 4877 | TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, | ||
| 4878 | TA_PERF_SEL_sp_ta_addr_cycles = 0x11, | ||
| 4879 | TA_PERF_SEL_sp_ta_data_cycles = 0x12, | ||
| 4880 | TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, | ||
| 4881 | TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, | ||
| 4882 | TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, | ||
| 4883 | TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, | ||
| 4884 | TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, | ||
| 4885 | TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, | ||
| 4886 | TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, | ||
| 4887 | TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, | ||
| 4888 | TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, | ||
| 4889 | TA_PERF_SEL_RESERVED_28 = 0x1c, | ||
| 4890 | TA_PERF_SEL_RESERVED_29 = 0x1d, | ||
| 4891 | TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, | ||
| 4892 | TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, | ||
| 4893 | TA_PERF_SEL_total_wavefronts = 0x20, | ||
| 4894 | TA_PERF_SEL_gradient_cycles = 0x21, | ||
| 4895 | TA_PERF_SEL_walker_cycles = 0x22, | ||
| 4896 | TA_PERF_SEL_aligner_cycles = 0x23, | ||
| 4897 | TA_PERF_SEL_image_wavefronts = 0x24, | ||
| 4898 | TA_PERF_SEL_image_read_wavefronts = 0x25, | ||
| 4899 | TA_PERF_SEL_image_write_wavefronts = 0x26, | ||
| 4900 | TA_PERF_SEL_image_atomic_wavefronts = 0x27, | ||
| 4901 | TA_PERF_SEL_image_total_cycles = 0x28, | ||
| 4902 | TA_PERF_SEL_RESERVED_41 = 0x29, | ||
| 4903 | TA_PERF_SEL_RESERVED_42 = 0x2a, | ||
| 4904 | TA_PERF_SEL_RESERVED_43 = 0x2b, | ||
| 4905 | TA_PERF_SEL_buffer_wavefronts = 0x2c, | ||
| 4906 | TA_PERF_SEL_buffer_read_wavefronts = 0x2d, | ||
| 4907 | TA_PERF_SEL_buffer_write_wavefronts = 0x2e, | ||
| 4908 | TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, | ||
| 4909 | TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, | ||
| 4910 | TA_PERF_SEL_buffer_total_cycles = 0x31, | ||
| 4911 | TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, | ||
| 4912 | TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, | ||
| 4913 | TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, | ||
| 4914 | TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, | ||
| 4915 | TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, | ||
| 4916 | TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, | ||
| 4917 | TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, | ||
| 4918 | TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, | ||
| 4919 | TA_PERF_SEL_addresser_stalled_cycles = 0x3a, | ||
| 4920 | TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, | ||
| 4921 | TA_PERF_SEL_aniso_stalled_cycles = 0x3c, | ||
| 4922 | TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, | ||
| 4923 | TA_PERF_SEL_deriv_stalled_cycles = 0x3e, | ||
| 4924 | TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, | ||
| 4925 | TA_PERF_SEL_color_1_cycle_pixels = 0x40, | ||
| 4926 | TA_PERF_SEL_color_2_cycle_pixels = 0x41, | ||
| 4927 | TA_PERF_SEL_color_3_cycle_pixels = 0x42, | ||
| 4928 | TA_PERF_SEL_color_4_cycle_pixels = 0x43, | ||
| 4929 | TA_PERF_SEL_mip_1_cycle_pixels = 0x44, | ||
| 4930 | TA_PERF_SEL_mip_2_cycle_pixels = 0x45, | ||
| 4931 | TA_PERF_SEL_vol_1_cycle_pixels = 0x46, | ||
| 4932 | TA_PERF_SEL_vol_2_cycle_pixels = 0x47, | ||
| 4933 | TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, | ||
| 4934 | TA_PERF_SEL_mipmap_lod_0_samples = 0x49, | ||
| 4935 | TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, | ||
| 4936 | TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, | ||
| 4937 | TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, | ||
| 4938 | TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, | ||
| 4939 | TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, | ||
| 4940 | TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, | ||
| 4941 | TA_PERF_SEL_mipmap_lod_7_samples = 0x50, | ||
| 4942 | TA_PERF_SEL_mipmap_lod_8_samples = 0x51, | ||
| 4943 | TA_PERF_SEL_mipmap_lod_9_samples = 0x52, | ||
| 4944 | TA_PERF_SEL_mipmap_lod_10_samples = 0x53, | ||
| 4945 | TA_PERF_SEL_mipmap_lod_11_samples = 0x54, | ||
| 4946 | TA_PERF_SEL_mipmap_lod_12_samples = 0x55, | ||
| 4947 | TA_PERF_SEL_mipmap_lod_13_samples = 0x56, | ||
| 4948 | TA_PERF_SEL_mipmap_lod_14_samples = 0x57, | ||
| 4949 | TA_PERF_SEL_mipmap_invalid_samples = 0x58, | ||
| 4950 | TA_PERF_SEL_aniso_1_cycle_quads = 0x59, | ||
| 4951 | TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, | ||
| 4952 | TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, | ||
| 4953 | TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, | ||
| 4954 | TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, | ||
| 4955 | TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, | ||
| 4956 | TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, | ||
| 4957 | TA_PERF_SEL_aniso_14_cycle_quads = 0x60, | ||
| 4958 | TA_PERF_SEL_aniso_16_cycle_quads = 0x61, | ||
| 4959 | TA_PERF_SEL_write_path_input_cycles = 0x62, | ||
| 4960 | TA_PERF_SEL_write_path_output_cycles = 0x63, | ||
| 4961 | TA_PERF_SEL_flat_wavefronts = 0x64, | ||
| 4962 | TA_PERF_SEL_flat_read_wavefronts = 0x65, | ||
| 4963 | TA_PERF_SEL_flat_write_wavefronts = 0x66, | ||
| 4964 | TA_PERF_SEL_flat_atomic_wavefronts = 0x67, | ||
| 4965 | TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, | ||
| 4966 | TA_PERF_SEL_reg_sclk_vld = 0x69, | ||
| 4967 | TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, | ||
| 4968 | TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, | ||
| 4969 | TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, | ||
| 4970 | TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, | ||
| 4971 | TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, | ||
| 4972 | TA_PERF_SEL_xnack_on_phase0 = 0x6f, | ||
| 4973 | TA_PERF_SEL_xnack_on_phase1 = 0x70, | ||
| 4974 | TA_PERF_SEL_xnack_on_phase2 = 0x71, | ||
| 4975 | TA_PERF_SEL_xnack_on_phase3 = 0x72, | ||
| 4976 | TA_PERF_SEL_first_xnack_on_phase0 = 0x73, | ||
| 4977 | TA_PERF_SEL_first_xnack_on_phase1 = 0x74, | ||
| 4978 | TA_PERF_SEL_first_xnack_on_phase2 = 0x75, | ||
| 4979 | TA_PERF_SEL_first_xnack_on_phase3 = 0x76, | ||
| 4980 | } TA_PERFCOUNT_SEL; | ||
| 4981 | typedef enum TD_PERFCOUNT_SEL { | ||
| 4982 | TD_PERF_SEL_none = 0x0, | ||
| 4983 | TD_PERF_SEL_td_busy = 0x1, | ||
| 4984 | TD_PERF_SEL_input_busy = 0x2, | ||
| 4985 | TD_PERF_SEL_output_busy = 0x3, | ||
| 4986 | TD_PERF_SEL_lerp_busy = 0x4, | ||
| 4987 | TD_PERF_SEL_reg_sclk_vld = 0x5, | ||
| 4988 | TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, | ||
| 4989 | TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, | ||
| 4990 | TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, | ||
| 4991 | TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, | ||
| 4992 | TD_PERF_SEL_tc_td_fifo_full = 0xa, | ||
| 4993 | TD_PERF_SEL_constant_state_full = 0xb, | ||
| 4994 | TD_PERF_SEL_sample_state_full = 0xc, | ||
| 4995 | TD_PERF_SEL_output_fifo_full = 0xd, | ||
| 4996 | TD_PERF_SEL_RESERVED_14 = 0xe, | ||
| 4997 | TD_PERF_SEL_tc_stall = 0xf, | ||
| 4998 | TD_PERF_SEL_pc_stall = 0x10, | ||
| 4999 | TD_PERF_SEL_gds_stall = 0x11, | ||
| 5000 | TD_PERF_SEL_RESERVED_18 = 0x12, | ||
| 5001 | TD_PERF_SEL_RESERVED_19 = 0x13, | ||
| 5002 | TD_PERF_SEL_gather4_wavefront = 0x14, | ||
| 5003 | TD_PERF_SEL_sample_c_wavefront = 0x15, | ||
| 5004 | TD_PERF_SEL_load_wavefront = 0x16, | ||
| 5005 | TD_PERF_SEL_atomic_wavefront = 0x17, | ||
| 5006 | TD_PERF_SEL_store_wavefront = 0x18, | ||
| 5007 | TD_PERF_SEL_ldfptr_wavefront = 0x19, | ||
| 5008 | TD_PERF_SEL_RESERVED_26 = 0x1a, | ||
| 5009 | TD_PERF_SEL_RESERVED_27 = 0x1b, | ||
| 5010 | TD_PERF_SEL_d16_en_wavefront = 0x1c, | ||
| 5011 | TD_PERF_SEL_bicubic_filter_wavefront = 0x1d, | ||
| 5012 | TD_PERF_SEL_bypass_filter_wavefront = 0x1e, | ||
| 5013 | TD_PERF_SEL_min_max_filter_wavefront = 0x1f, | ||
| 5014 | TD_PERF_SEL_coalescable_wavefront = 0x20, | ||
| 5015 | TD_PERF_SEL_coalesced_phase = 0x21, | ||
| 5016 | TD_PERF_SEL_four_phase_wavefront = 0x22, | ||
| 5017 | TD_PERF_SEL_eight_phase_wavefront = 0x23, | ||
| 5018 | TD_PERF_SEL_sixteen_phase_wavefront = 0x24, | ||
| 5019 | TD_PERF_SEL_four_phase_forward_wavefront = 0x25, | ||
| 5020 | TD_PERF_SEL_write_ack_wavefront = 0x26, | ||
| 5021 | TD_PERF_SEL_RESERVED_39 = 0x27, | ||
| 5022 | TD_PERF_SEL_user_defined_border = 0x28, | ||
| 5023 | TD_PERF_SEL_white_border = 0x29, | ||
| 5024 | TD_PERF_SEL_opaque_black_border = 0x2a, | ||
| 5025 | TD_PERF_SEL_RESERVED_43 = 0x2b, | ||
| 5026 | TD_PERF_SEL_RESERVED_44 = 0x2c, | ||
| 5027 | TD_PERF_SEL_nack = 0x2d, | ||
| 5028 | TD_PERF_SEL_td_sp_traffic = 0x2e, | ||
| 5029 | TD_PERF_SEL_consume_gds_traffic = 0x2f, | ||
| 5030 | TD_PERF_SEL_addresscmd_poison = 0x30, | ||
| 5031 | TD_PERF_SEL_data_poison = 0x31, | ||
| 5032 | TD_PERF_SEL_start_cycle_0 = 0x32, | ||
| 5033 | TD_PERF_SEL_start_cycle_1 = 0x33, | ||
| 5034 | TD_PERF_SEL_start_cycle_2 = 0x34, | ||
| 5035 | TD_PERF_SEL_start_cycle_3 = 0x35, | ||
| 5036 | TD_PERF_SEL_null_cycle_output = 0x36, | ||
| 5037 | TD_PERF_SEL_d16_data_packed = 0x37, | ||
| 5038 | } TD_PERFCOUNT_SEL; | ||
| 5039 | typedef enum TCP_PERFCOUNT_SELECT { | ||
| 5040 | TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, | ||
| 5041 | TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, | ||
| 5042 | TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, | ||
| 5043 | TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, | ||
| 5044 | TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, | ||
| 5045 | TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, | ||
| 5046 | TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, | ||
| 5047 | TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, | ||
| 5048 | TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, | ||
| 5049 | TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, | ||
| 5050 | TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, | ||
| 5051 | TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, | ||
| 5052 | TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, | ||
| 5053 | TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, | ||
| 5054 | TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, | ||
| 5055 | TCP_PERF_SEL_HOLE_READ_STALL = 0xf, | ||
| 5056 | TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, | ||
| 5057 | TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, | ||
| 5058 | TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, | ||
| 5059 | TCP_PERF_SEL_TCP_LATENCY = 0x13, | ||
| 5060 | TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, | ||
| 5061 | TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, | ||
| 5062 | TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, | ||
| 5063 | TCP_PERF_SEL_TCC_READ_REQ = 0x17, | ||
| 5064 | TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, | ||
| 5065 | TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, | ||
| 5066 | TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, | ||
| 5067 | TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, | ||
| 5068 | TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, | ||
| 5069 | TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, | ||
| 5070 | TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, | ||
| 5071 | TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, | ||
| 5072 | TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, | ||
| 5073 | TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, | ||
| 5074 | TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, | ||
| 5075 | TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, | ||
| 5076 | TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, | ||
| 5077 | TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, | ||
| 5078 | TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, | ||
| 5079 | TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, | ||
| 5080 | TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, | ||
| 5081 | TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, | ||
| 5082 | TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, | ||
| 5083 | TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, | ||
| 5084 | TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, | ||
| 5085 | TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, | ||
| 5086 | TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, | ||
| 5087 | TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, | ||
| 5088 | TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, | ||
| 5089 | TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, | ||
| 5090 | TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, | ||
| 5091 | TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, | ||
| 5092 | TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, | ||
| 5093 | TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, | ||
| 5094 | TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, | ||
| 5095 | TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, | ||
| 5096 | TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, | ||
| 5097 | TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, | ||
| 5098 | TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, | ||
| 5099 | TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, | ||
| 5100 | TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, | ||
| 5101 | TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, | ||
| 5102 | TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, | ||
| 5103 | TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, | ||
| 5104 | TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, | ||
| 5105 | TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, | ||
| 5106 | TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, | ||
| 5107 | TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, | ||
| 5108 | TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, | ||
| 5109 | TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, | ||
| 5110 | TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, | ||
| 5111 | TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, | ||
| 5112 | TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, | ||
| 5113 | TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, | ||
| 5114 | TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, | ||
| 5115 | TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, | ||
| 5116 | TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, | ||
| 5117 | TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, | ||
| 5118 | TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, | ||
| 5119 | TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, | ||
| 5120 | TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, | ||
| 5121 | TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, | ||
| 5122 | TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, | ||
| 5123 | TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, | ||
| 5124 | TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, | ||
| 5125 | TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, | ||
| 5126 | TCP_PERF_SEL_ARR_1D_THICK = 0x56, | ||
| 5127 | TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, | ||
| 5128 | TCP_PERF_SEL_ARR_2D_THICK = 0x58, | ||
| 5129 | TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, | ||
| 5130 | TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, | ||
| 5131 | TCP_PERF_SEL_ARR_3D_THICK = 0x5b, | ||
| 5132 | TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, | ||
| 5133 | TCP_PERF_SEL_DIM_1D = 0x5d, | ||
| 5134 | TCP_PERF_SEL_DIM_2D = 0x5e, | ||
| 5135 | TCP_PERF_SEL_DIM_3D = 0x5f, | ||
| 5136 | TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, | ||
| 5137 | TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, | ||
| 5138 | TCP_PERF_SEL_DIM_2D_MSAA = 0x62, | ||
| 5139 | TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, | ||
| 5140 | TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, | ||
| 5141 | TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, | ||
| 5142 | TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, | ||
| 5143 | TCP_PERF_SEL_TAGRAM0_REQ = 0x67, | ||
| 5144 | TCP_PERF_SEL_TAGRAM1_REQ = 0x68, | ||
| 5145 | TCP_PERF_SEL_TAGRAM2_REQ = 0x69, | ||
| 5146 | TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, | ||
| 5147 | TCP_PERF_SEL_GATE_EN1 = 0x6b, | ||
| 5148 | TCP_PERF_SEL_GATE_EN2 = 0x6c, | ||
| 5149 | TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, | ||
| 5150 | TCP_PERF_SEL_TCC_REQ = 0x6e, | ||
| 5151 | TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, | ||
| 5152 | TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, | ||
| 5153 | TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, | ||
| 5154 | TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, | ||
| 5155 | TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, | ||
| 5156 | TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, | ||
| 5157 | TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, | ||
| 5158 | TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, | ||
| 5159 | TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, | ||
| 5160 | TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, | ||
| 5161 | TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, | ||
| 5162 | TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, | ||
| 5163 | TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, | ||
| 5164 | TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, | ||
| 5165 | TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, | ||
| 5166 | TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, | ||
| 5167 | TCP_PERF_SEL_TOTAL_READ = 0x7f, | ||
| 5168 | TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, | ||
| 5169 | TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, | ||
| 5170 | TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, | ||
| 5171 | TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, | ||
| 5172 | TCP_PERF_SEL_TOTAL_NON_READ = 0x84, | ||
| 5173 | TCP_PERF_SEL_TOTAL_WRITE = 0x85, | ||
| 5174 | TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, | ||
| 5175 | TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, | ||
| 5176 | TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, | ||
| 5177 | TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, | ||
| 5178 | TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, | ||
| 5179 | TCP_PERF_SEL_THIN_MICROTILING = 0x8b, | ||
| 5180 | TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, | ||
| 5181 | TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, | ||
| 5182 | TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, | ||
| 5183 | TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, | ||
| 5184 | TCP_PERF_SEL_ARR_PRT_THICK = 0x90, | ||
| 5185 | TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, | ||
| 5186 | TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, | ||
| 5187 | TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, | ||
| 5188 | TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, | ||
| 5189 | TCP_PERF_SEL_UNALIGNED = 0x95, | ||
| 5190 | TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, | ||
| 5191 | TCP_PERF_SEL_THICK_MICROTILING = 0x97, | ||
| 5192 | TCP_PERF_SEL_ATC = 0x98, | ||
| 5193 | TCP_PERF_SEL_POWER_STALL = 0x99, | ||
| 5194 | TCP_PERF_SEL_RESERVED_154 = 0x9a, | ||
| 5195 | TCP_PERF_SEL_TCC_LRU_REQ = 0x9b, | ||
| 5196 | TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c, | ||
| 5197 | TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d, | ||
| 5198 | TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e, | ||
| 5199 | TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f, | ||
| 5200 | TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0, | ||
| 5201 | TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1, | ||
| 5202 | TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2, | ||
| 5203 | TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3, | ||
| 5204 | TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4, | ||
| 5205 | TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5, | ||
| 5206 | TCP_PERF_SEL_TCC_DCC_REQ = 0xa6, | ||
| 5207 | TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7, | ||
| 5208 | TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8, | ||
| 5209 | TCP_PERF_SEL_VOLATILE = 0xa9, | ||
| 5210 | TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa, | ||
| 5211 | TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab, | ||
| 5212 | TCP_PERF_SEL_SHOOTDOWN = 0xac, | ||
| 5213 | TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad, | ||
| 5214 | TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae, | ||
| 5215 | TCP_PERF_SEL_GATCL1_REQUEST = 0xaf, | ||
| 5216 | TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0, | ||
| 5217 | TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1, | ||
| 5218 | TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2, | ||
| 5219 | TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3, | ||
| 5220 | TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4, | ||
| 5221 | TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5, | ||
| 5222 | TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6, | ||
| 5223 | TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0xb7, | ||
| 5224 | TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0xb8, | ||
| 5225 | TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0xb9, | ||
| 5226 | TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0xba, | ||
| 5227 | TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0xbb, | ||
| 5228 | TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0xbc, | ||
| 5229 | TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0xbd, | ||
| 5230 | TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0xbe, | ||
| 5231 | TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0xbf, | ||
| 5232 | TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0xc0, | ||
| 5233 | TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0xc1, | ||
| 5234 | TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0xc2, | ||
| 5235 | TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0xc3, | ||
| 5236 | } TCP_PERFCOUNT_SELECT; | ||
| 5237 | typedef enum TCP_CACHE_POLICIES { | ||
| 5238 | TCP_CACHE_POLICY_MISS_LRU = 0x0, | ||
| 5239 | TCP_CACHE_POLICY_MISS_EVICT = 0x1, | ||
| 5240 | TCP_CACHE_POLICY_HIT_LRU = 0x2, | ||
| 5241 | TCP_CACHE_POLICY_HIT_EVICT = 0x3, | ||
| 5242 | } TCP_CACHE_POLICIES; | ||
| 5243 | typedef enum TCP_CACHE_STORE_POLICIES { | ||
| 5244 | TCP_CACHE_STORE_POLICY_WT_LRU = 0x0, | ||
| 5245 | TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1, | ||
| 5246 | } TCP_CACHE_STORE_POLICIES; | ||
| 5247 | typedef enum TCP_WATCH_MODES { | ||
| 5248 | TCP_WATCH_MODE_READ = 0x0, | ||
| 5249 | TCP_WATCH_MODE_NONREAD = 0x1, | ||
| 5250 | TCP_WATCH_MODE_ATOMIC = 0x2, | ||
| 5251 | TCP_WATCH_MODE_ALL = 0x3, | ||
| 5252 | } TCP_WATCH_MODES; | ||
| 5253 | typedef enum TCP_DSM_DATA_SEL { | ||
| 5254 | TCP_DSM_DISABLE = 0x0, | ||
| 5255 | TCP_DSM_SEL0 = 0x1, | ||
| 5256 | TCP_DSM_SEL1 = 0x2, | ||
| 5257 | TCP_DSM_SEL_BOTH = 0x3, | ||
| 5258 | } TCP_DSM_DATA_SEL; | ||
| 5259 | typedef enum TCP_DSM_SINGLE_WRITE { | ||
| 5260 | TCP_DSM_SINGLE_WRITE_EN = 0x1, | ||
| 5261 | } TCP_DSM_SINGLE_WRITE; | ||
| 5262 | typedef enum VGT_OUT_PRIM_TYPE { | ||
| 5263 | VGT_OUT_POINT = 0x0, | ||
| 5264 | VGT_OUT_LINE = 0x1, | ||
| 5265 | VGT_OUT_TRI = 0x2, | ||
| 5266 | VGT_OUT_RECT_V0 = 0x3, | ||
| 5267 | VGT_OUT_RECT_V1 = 0x4, | ||
| 5268 | VGT_OUT_RECT_V2 = 0x5, | ||
| 5269 | VGT_OUT_RECT_V3 = 0x6, | ||
| 5270 | VGT_OUT_RESERVED = 0x7, | ||
| 5271 | VGT_TE_QUAD = 0x8, | ||
| 5272 | VGT_TE_PRIM_INDEX_LINE = 0x9, | ||
| 5273 | VGT_TE_PRIM_INDEX_TRI = 0xa, | ||
| 5274 | VGT_TE_PRIM_INDEX_QUAD = 0xb, | ||
| 5275 | VGT_OUT_LINE_ADJ = 0xc, | ||
| 5276 | VGT_OUT_TRI_ADJ = 0xd, | ||
| 5277 | VGT_OUT_PATCH = 0xe, | ||
| 5278 | } VGT_OUT_PRIM_TYPE; | ||
| 5279 | typedef enum VGT_DI_PRIM_TYPE { | ||
| 5280 | DI_PT_NONE = 0x0, | ||
| 5281 | DI_PT_POINTLIST = 0x1, | ||
| 5282 | DI_PT_LINELIST = 0x2, | ||
| 5283 | DI_PT_LINESTRIP = 0x3, | ||
| 5284 | DI_PT_TRILIST = 0x4, | ||
| 5285 | DI_PT_TRIFAN = 0x5, | ||
| 5286 | DI_PT_TRISTRIP = 0x6, | ||
| 5287 | DI_PT_UNUSED_0 = 0x7, | ||
| 5288 | DI_PT_UNUSED_1 = 0x8, | ||
| 5289 | DI_PT_PATCH = 0x9, | ||
| 5290 | DI_PT_LINELIST_ADJ = 0xa, | ||
| 5291 | DI_PT_LINESTRIP_ADJ = 0xb, | ||
| 5292 | DI_PT_TRILIST_ADJ = 0xc, | ||
| 5293 | DI_PT_TRISTRIP_ADJ = 0xd, | ||
| 5294 | DI_PT_UNUSED_3 = 0xe, | ||
| 5295 | DI_PT_UNUSED_4 = 0xf, | ||
| 5296 | DI_PT_TRI_WITH_WFLAGS = 0x10, | ||
| 5297 | DI_PT_RECTLIST = 0x11, | ||
| 5298 | DI_PT_LINELOOP = 0x12, | ||
| 5299 | DI_PT_QUADLIST = 0x13, | ||
| 5300 | DI_PT_QUADSTRIP = 0x14, | ||
| 5301 | DI_PT_POLYGON = 0x15, | ||
| 5302 | DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, | ||
| 5303 | DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, | ||
| 5304 | DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, | ||
| 5305 | DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, | ||
| 5306 | DI_PT_2D_FILL_RECT_LIST = 0x1a, | ||
| 5307 | DI_PT_2D_LINE_STRIP = 0x1b, | ||
| 5308 | DI_PT_2D_TRI_STRIP = 0x1c, | ||
| 5309 | } VGT_DI_PRIM_TYPE; | ||
| 5310 | typedef enum VGT_DI_SOURCE_SELECT { | ||
| 5311 | DI_SRC_SEL_DMA = 0x0, | ||
| 5312 | DI_SRC_SEL_IMMEDIATE = 0x1, | ||
| 5313 | DI_SRC_SEL_AUTO_INDEX = 0x2, | ||
| 5314 | DI_SRC_SEL_RESERVED = 0x3, | ||
| 5315 | } VGT_DI_SOURCE_SELECT; | ||
| 5316 | typedef enum VGT_DI_MAJOR_MODE_SELECT { | ||
| 5317 | DI_MAJOR_MODE_0 = 0x0, | ||
| 5318 | DI_MAJOR_MODE_1 = 0x1, | ||
| 5319 | } VGT_DI_MAJOR_MODE_SELECT; | ||
| 5320 | typedef enum VGT_DI_INDEX_SIZE { | ||
| 5321 | DI_INDEX_SIZE_16_BIT = 0x0, | ||
| 5322 | DI_INDEX_SIZE_32_BIT = 0x1, | ||
| 5323 | DI_INDEX_SIZE_8_BIT = 0x2, | ||
| 5324 | } VGT_DI_INDEX_SIZE; | ||
| 5325 | typedef enum VGT_EVENT_TYPE { | ||
| 5326 | Reserved_0x00 = 0x0, | ||
| 5327 | SAMPLE_STREAMOUTSTATS1 = 0x1, | ||
| 5328 | SAMPLE_STREAMOUTSTATS2 = 0x2, | ||
| 5329 | SAMPLE_STREAMOUTSTATS3 = 0x3, | ||
| 5330 | CACHE_FLUSH_TS = 0x4, | ||
| 5331 | CONTEXT_DONE = 0x5, | ||
| 5332 | CACHE_FLUSH = 0x6, | ||
| 5333 | CS_PARTIAL_FLUSH = 0x7, | ||
| 5334 | VGT_STREAMOUT_SYNC = 0x8, | ||
| 5335 | Reserved_0x09 = 0x9, | ||
| 5336 | VGT_STREAMOUT_RESET = 0xa, | ||
| 5337 | END_OF_PIPE_INCR_DE = 0xb, | ||
| 5338 | END_OF_PIPE_IB_END = 0xc, | ||
| 5339 | RST_PIX_CNT = 0xd, | ||
| 5340 | Reserved_0x0E = 0xe, | ||
| 5341 | VS_PARTIAL_FLUSH = 0xf, | ||
| 5342 | PS_PARTIAL_FLUSH = 0x10, | ||
| 5343 | FLUSH_HS_OUTPUT = 0x11, | ||
| 5344 | FLUSH_LS_OUTPUT = 0x12, | ||
| 5345 | Reserved_0x13 = 0x13, | ||
| 5346 | CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, | ||
| 5347 | ZPASS_DONE = 0x15, | ||
| 5348 | CACHE_FLUSH_AND_INV_EVENT = 0x16, | ||
| 5349 | PERFCOUNTER_START = 0x17, | ||
| 5350 | PERFCOUNTER_STOP = 0x18, | ||
| 5351 | PIPELINESTAT_START = 0x19, | ||
| 5352 | PIPELINESTAT_STOP = 0x1a, | ||
| 5353 | PERFCOUNTER_SAMPLE = 0x1b, | ||
| 5354 | FLUSH_ES_OUTPUT = 0x1c, | ||
| 5355 | FLUSH_GS_OUTPUT = 0x1d, | ||
| 5356 | SAMPLE_PIPELINESTAT = 0x1e, | ||
| 5357 | SO_VGTSTREAMOUT_FLUSH = 0x1f, | ||
| 5358 | SAMPLE_STREAMOUTSTATS = 0x20, | ||
| 5359 | RESET_VTX_CNT = 0x21, | ||
| 5360 | BLOCK_CONTEXT_DONE = 0x22, | ||
| 5361 | CS_CONTEXT_DONE = 0x23, | ||
| 5362 | VGT_FLUSH = 0x24, | ||
| 5363 | TGID_ROLLOVER = 0x25, | ||
| 5364 | SQ_NON_EVENT = 0x26, | ||
| 5365 | SC_SEND_DB_VPZ = 0x27, | ||
| 5366 | BOTTOM_OF_PIPE_TS = 0x28, | ||
| 5367 | FLUSH_SX_TS = 0x29, | ||
| 5368 | DB_CACHE_FLUSH_AND_INV = 0x2a, | ||
| 5369 | FLUSH_AND_INV_DB_DATA_TS = 0x2b, | ||
| 5370 | FLUSH_AND_INV_DB_META = 0x2c, | ||
| 5371 | FLUSH_AND_INV_CB_DATA_TS = 0x2d, | ||
| 5372 | FLUSH_AND_INV_CB_META = 0x2e, | ||
| 5373 | CS_DONE = 0x2f, | ||
| 5374 | PS_DONE = 0x30, | ||
| 5375 | FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, | ||
| 5376 | SX_CB_RAT_ACK_REQUEST = 0x32, | ||
| 5377 | THREAD_TRACE_START = 0x33, | ||
| 5378 | THREAD_TRACE_STOP = 0x34, | ||
| 5379 | THREAD_TRACE_MARKER = 0x35, | ||
| 5380 | THREAD_TRACE_FLUSH = 0x36, | ||
| 5381 | THREAD_TRACE_FINISH = 0x37, | ||
| 5382 | PIXEL_PIPE_STAT_CONTROL = 0x38, | ||
| 5383 | PIXEL_PIPE_STAT_DUMP = 0x39, | ||
| 5384 | PIXEL_PIPE_STAT_RESET = 0x3a, | ||
| 5385 | CONTEXT_SUSPEND = 0x3b, | ||
| 5386 | OFFCHIP_HS_DEALLOC = 0x3c, | ||
| 5387 | } VGT_EVENT_TYPE; | ||
| 5388 | typedef enum VGT_DMA_SWAP_MODE { | ||
| 5389 | VGT_DMA_SWAP_NONE = 0x0, | ||
| 5390 | VGT_DMA_SWAP_16_BIT = 0x1, | ||
| 5391 | VGT_DMA_SWAP_32_BIT = 0x2, | ||
| 5392 | VGT_DMA_SWAP_WORD = 0x3, | ||
| 5393 | } VGT_DMA_SWAP_MODE; | ||
| 5394 | typedef enum VGT_INDEX_TYPE_MODE { | ||
| 5395 | VGT_INDEX_16 = 0x0, | ||
| 5396 | VGT_INDEX_32 = 0x1, | ||
| 5397 | VGT_INDEX_8 = 0x2, | ||
| 5398 | } VGT_INDEX_TYPE_MODE; | ||
| 5399 | typedef enum VGT_DMA_BUF_TYPE { | ||
| 5400 | VGT_DMA_BUF_MEM = 0x0, | ||
| 5401 | VGT_DMA_BUF_RING = 0x1, | ||
| 5402 | VGT_DMA_BUF_SETUP = 0x2, | ||
| 5403 | VGT_DMA_PTR_UPDATE = 0x3, | ||
| 5404 | } VGT_DMA_BUF_TYPE; | ||
| 5405 | typedef enum VGT_OUTPATH_SELECT { | ||
| 5406 | VGT_OUTPATH_VTX_REUSE = 0x0, | ||
| 5407 | VGT_OUTPATH_TESS_EN = 0x1, | ||
| 5408 | VGT_OUTPATH_PASSTHRU = 0x2, | ||
| 5409 | VGT_OUTPATH_GS_BLOCK = 0x3, | ||
| 5410 | VGT_OUTPATH_HS_BLOCK = 0x4, | ||
| 5411 | } VGT_OUTPATH_SELECT; | ||
| 5412 | typedef enum VGT_GRP_PRIM_TYPE { | ||
| 5413 | VGT_GRP_3D_POINT = 0x0, | ||
| 5414 | VGT_GRP_3D_LINE = 0x1, | ||
| 5415 | VGT_GRP_3D_TRI = 0x2, | ||
| 5416 | VGT_GRP_3D_RECT = 0x3, | ||
| 5417 | VGT_GRP_3D_QUAD = 0x4, | ||
| 5418 | VGT_GRP_2D_COPY_RECT_V0 = 0x5, | ||
| 5419 | VGT_GRP_2D_COPY_RECT_V1 = 0x6, | ||
| 5420 | VGT_GRP_2D_COPY_RECT_V2 = 0x7, | ||
| 5421 | VGT_GRP_2D_COPY_RECT_V3 = 0x8, | ||
| 5422 | VGT_GRP_2D_FILL_RECT = 0x9, | ||
| 5423 | VGT_GRP_2D_LINE = 0xa, | ||
| 5424 | VGT_GRP_2D_TRI = 0xb, | ||
| 5425 | VGT_GRP_PRIM_INDEX_LINE = 0xc, | ||
| 5426 | VGT_GRP_PRIM_INDEX_TRI = 0xd, | ||
| 5427 | VGT_GRP_PRIM_INDEX_QUAD = 0xe, | ||
| 5428 | VGT_GRP_3D_LINE_ADJ = 0xf, | ||
| 5429 | VGT_GRP_3D_TRI_ADJ = 0x10, | ||
| 5430 | VGT_GRP_3D_PATCH = 0x11, | ||
| 5431 | } VGT_GRP_PRIM_TYPE; | ||
| 5432 | typedef enum VGT_GRP_PRIM_ORDER { | ||
| 5433 | VGT_GRP_LIST = 0x0, | ||
| 5434 | VGT_GRP_STRIP = 0x1, | ||
| 5435 | VGT_GRP_FAN = 0x2, | ||
| 5436 | VGT_GRP_LOOP = 0x3, | ||
| 5437 | VGT_GRP_POLYGON = 0x4, | ||
| 5438 | } VGT_GRP_PRIM_ORDER; | ||
| 5439 | typedef enum VGT_GROUP_CONV_SEL { | ||
| 5440 | VGT_GRP_INDEX_16 = 0x0, | ||
| 5441 | VGT_GRP_INDEX_32 = 0x1, | ||
| 5442 | VGT_GRP_UINT_16 = 0x2, | ||
| 5443 | VGT_GRP_UINT_32 = 0x3, | ||
| 5444 | VGT_GRP_SINT_16 = 0x4, | ||
| 5445 | VGT_GRP_SINT_32 = 0x5, | ||
| 5446 | VGT_GRP_FLOAT_32 = 0x6, | ||
| 5447 | VGT_GRP_AUTO_PRIM = 0x7, | ||
| 5448 | VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, | ||
| 5449 | } VGT_GROUP_CONV_SEL; | ||
| 5450 | typedef enum VGT_GS_MODE_TYPE { | ||
| 5451 | GS_OFF = 0x0, | ||
| 5452 | GS_SCENARIO_A = 0x1, | ||
| 5453 | GS_SCENARIO_B = 0x2, | ||
| 5454 | GS_SCENARIO_G = 0x3, | ||
| 5455 | GS_SCENARIO_C = 0x4, | ||
| 5456 | SPRITE_EN = 0x5, | ||
| 5457 | } VGT_GS_MODE_TYPE; | ||
| 5458 | typedef enum VGT_GS_CUT_MODE { | ||
| 5459 | GS_CUT_1024 = 0x0, | ||
| 5460 | GS_CUT_512 = 0x1, | ||
| 5461 | GS_CUT_256 = 0x2, | ||
| 5462 | GS_CUT_128 = 0x3, | ||
| 5463 | } VGT_GS_CUT_MODE; | ||
| 5464 | typedef enum VGT_GS_OUTPRIM_TYPE { | ||
| 5465 | POINTLIST = 0x0, | ||
| 5466 | LINESTRIP = 0x1, | ||
| 5467 | TRISTRIP = 0x2, | ||
| 5468 | } VGT_GS_OUTPRIM_TYPE; | ||
| 5469 | typedef enum VGT_CACHE_INVALID_MODE { | ||
| 5470 | VC_ONLY = 0x0, | ||
| 5471 | TC_ONLY = 0x1, | ||
| 5472 | VC_AND_TC = 0x2, | ||
| 5473 | } VGT_CACHE_INVALID_MODE; | ||
| 5474 | typedef enum VGT_TESS_TYPE { | ||
| 5475 | TESS_ISOLINE = 0x0, | ||
| 5476 | TESS_TRIANGLE = 0x1, | ||
| 5477 | TESS_QUAD = 0x2, | ||
| 5478 | } VGT_TESS_TYPE; | ||
| 5479 | typedef enum VGT_TESS_PARTITION { | ||
| 5480 | PART_INTEGER = 0x0, | ||
| 5481 | PART_POW2 = 0x1, | ||
| 5482 | PART_FRAC_ODD = 0x2, | ||
| 5483 | PART_FRAC_EVEN = 0x3, | ||
| 5484 | } VGT_TESS_PARTITION; | ||
| 5485 | typedef enum VGT_TESS_TOPOLOGY { | ||
| 5486 | OUTPUT_POINT = 0x0, | ||
| 5487 | OUTPUT_LINE = 0x1, | ||
| 5488 | OUTPUT_TRIANGLE_CW = 0x2, | ||
| 5489 | OUTPUT_TRIANGLE_CCW = 0x3, | ||
| 5490 | } VGT_TESS_TOPOLOGY; | ||
| 5491 | typedef enum VGT_RDREQ_POLICY { | ||
| 5492 | VGT_POLICY_LRU = 0x0, | ||
| 5493 | VGT_POLICY_STREAM = 0x1, | ||
| 5494 | } VGT_RDREQ_POLICY; | ||
| 5495 | typedef enum VGT_DIST_MODE { | ||
| 5496 | NO_DIST = 0x0, | ||
| 5497 | PATCHES = 0x1, | ||
| 5498 | DONUTS = 0x2, | ||
| 5499 | } VGT_DIST_MODE; | ||
| 5500 | typedef enum VGT_STAGES_LS_EN { | ||
| 5501 | LS_STAGE_OFF = 0x0, | ||
| 5502 | LS_STAGE_ON = 0x1, | ||
| 5503 | CS_STAGE_ON = 0x2, | ||
| 5504 | RESERVED_LS = 0x3, | ||
| 5505 | } VGT_STAGES_LS_EN; | ||
| 5506 | typedef enum VGT_STAGES_HS_EN { | ||
| 5507 | HS_STAGE_OFF = 0x0, | ||
| 5508 | HS_STAGE_ON = 0x1, | ||
| 5509 | } VGT_STAGES_HS_EN; | ||
| 5510 | typedef enum VGT_STAGES_ES_EN { | ||
| 5511 | ES_STAGE_OFF = 0x0, | ||
| 5512 | ES_STAGE_DS = 0x1, | ||
| 5513 | ES_STAGE_REAL = 0x2, | ||
| 5514 | RESERVED_ES = 0x3, | ||
| 5515 | } VGT_STAGES_ES_EN; | ||
| 5516 | typedef enum VGT_STAGES_GS_EN { | ||
| 5517 | GS_STAGE_OFF = 0x0, | ||
| 5518 | GS_STAGE_ON = 0x1, | ||
| 5519 | } VGT_STAGES_GS_EN; | ||
| 5520 | typedef enum VGT_STAGES_VS_EN { | ||
| 5521 | VS_STAGE_REAL = 0x0, | ||
| 5522 | VS_STAGE_DS = 0x1, | ||
| 5523 | VS_STAGE_COPY_SHADER = 0x2, | ||
| 5524 | RESERVED_VS = 0x3, | ||
| 5525 | } VGT_STAGES_VS_EN; | ||
| 5526 | typedef enum VGT_PERFCOUNT_SELECT { | ||
| 5527 | vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, | ||
| 5528 | vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, | ||
| 5529 | vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, | ||
| 5530 | vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, | ||
| 5531 | vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, | ||
| 5532 | vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, | ||
| 5533 | vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, | ||
| 5534 | vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, | ||
| 5535 | vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, | ||
| 5536 | vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, | ||
| 5537 | vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, | ||
| 5538 | vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, | ||
| 5539 | vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, | ||
| 5540 | vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, | ||
| 5541 | vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, | ||
| 5542 | vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, | ||
| 5543 | vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, | ||
| 5544 | vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, | ||
| 5545 | vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, | ||
| 5546 | vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, | ||
| 5547 | vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, | ||
| 5548 | vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, | ||
| 5549 | vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, | ||
| 5550 | vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, | ||
| 5551 | vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, | ||
| 5552 | vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, | ||
| 5553 | vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, | ||
| 5554 | vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, | ||
| 5555 | vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, | ||
| 5556 | vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, | ||
| 5557 | vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, | ||
| 5558 | vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, | ||
| 5559 | vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, | ||
| 5560 | vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, | ||
| 5561 | vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, | ||
| 5562 | vgt_perf_VGT_PA_CLIPP_SEND = 0x23, | ||
| 5563 | vgt_perf_VGT_PA_CLIPP_EOP = 0x24, | ||
| 5564 | vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, | ||
| 5565 | vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, | ||
| 5566 | vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, | ||
| 5567 | vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, | ||
| 5568 | vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, | ||
| 5569 | vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, | ||
| 5570 | vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, | ||
| 5571 | vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, | ||
| 5572 | vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, | ||
| 5573 | vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, | ||
| 5574 | vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, | ||
| 5575 | vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, | ||
| 5576 | vgt_perf_vsvert_ds_send = 0x31, | ||
| 5577 | vgt_perf_vsvert_api_send = 0x32, | ||
| 5578 | vgt_perf_hs_tif_stall = 0x33, | ||
| 5579 | vgt_perf_hs_input_stall = 0x34, | ||
| 5580 | vgt_perf_hs_interface_stall = 0x35, | ||
| 5581 | vgt_perf_hs_tfm_stall = 0x36, | ||
| 5582 | vgt_perf_te11_starved = 0x37, | ||
| 5583 | vgt_perf_gs_event_stall = 0x38, | ||
| 5584 | vgt_perf_vgt_pa_clipp_send_not_event = 0x39, | ||
| 5585 | vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, | ||
| 5586 | vgt_perf_reused_es_indices = 0x3b, | ||
| 5587 | vgt_perf_vs_cache_hits = 0x3c, | ||
| 5588 | vgt_perf_gs_cache_hits = 0x3d, | ||
| 5589 | vgt_perf_ds_cache_hits = 0x3e, | ||
| 5590 | vgt_perf_total_cache_hits = 0x3f, | ||
| 5591 | vgt_perf_vgt_busy = 0x40, | ||
| 5592 | vgt_perf_vgt_gs_busy = 0x41, | ||
| 5593 | vgt_perf_esvert_stalled_es_tbl = 0x42, | ||
| 5594 | vgt_perf_esvert_stalled_gs_tbl = 0x43, | ||
| 5595 | vgt_perf_esvert_stalled_gs_event = 0x44, | ||
| 5596 | vgt_perf_esvert_stalled_gsprim = 0x45, | ||
| 5597 | vgt_perf_gsprim_stalled_es_tbl = 0x46, | ||
| 5598 | vgt_perf_gsprim_stalled_gs_tbl = 0x47, | ||
| 5599 | vgt_perf_gsprim_stalled_gs_event = 0x48, | ||
| 5600 | vgt_perf_gsprim_stalled_esvert = 0x49, | ||
| 5601 | vgt_perf_esthread_stalled_es_rb_full = 0x4a, | ||
| 5602 | vgt_perf_esthread_stalled_spi_bp = 0x4b, | ||
| 5603 | vgt_perf_counters_avail_stalled = 0x4c, | ||
| 5604 | vgt_perf_gs_rb_space_avail_stalled = 0x4d, | ||
| 5605 | vgt_perf_gs_issue_rtr_stalled = 0x4e, | ||
| 5606 | vgt_perf_gsthread_stalled = 0x4f, | ||
| 5607 | vgt_perf_strmout_stalled = 0x50, | ||
| 5608 | vgt_perf_wait_for_es_done_stalled = 0x51, | ||
| 5609 | vgt_perf_cm_stalled_by_gog = 0x52, | ||
| 5610 | vgt_perf_cm_reading_stalled = 0x53, | ||
| 5611 | vgt_perf_cm_stalled_by_gsfetch_done = 0x54, | ||
| 5612 | vgt_perf_gog_vs_tbl_stalled = 0x55, | ||
| 5613 | vgt_perf_gog_out_indx_stalled = 0x56, | ||
| 5614 | vgt_perf_gog_out_prim_stalled = 0x57, | ||
| 5615 | vgt_perf_waveid_stalled = 0x58, | ||
| 5616 | vgt_perf_gog_busy = 0x59, | ||
| 5617 | vgt_perf_reused_vs_indices = 0x5a, | ||
| 5618 | vgt_perf_sclk_reg_vld_event = 0x5b, | ||
| 5619 | vgt_perf_vs_conflicting_indices = 0x5c, | ||
| 5620 | vgt_perf_sclk_core_vld_event = 0x5d, | ||
| 5621 | vgt_perf_hswave_stalled = 0x5e, | ||
| 5622 | vgt_perf_sclk_gs_vld_event = 0x5f, | ||
| 5623 | vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, | ||
| 5624 | vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, | ||
| 5625 | vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, | ||
| 5626 | vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, | ||
| 5627 | vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, | ||
| 5628 | vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, | ||
| 5629 | vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, | ||
| 5630 | vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, | ||
| 5631 | vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, | ||
| 5632 | vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, | ||
| 5633 | vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, | ||
| 5634 | vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, | ||
| 5635 | vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, | ||
| 5636 | vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, | ||
| 5637 | vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, | ||
| 5638 | vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, | ||
| 5639 | vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, | ||
| 5640 | vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, | ||
| 5641 | vgt_perf_ds_prims = 0x72, | ||
| 5642 | vgt_perf_ls_thread_groups = 0x73, | ||
| 5643 | vgt_perf_hs_thread_groups = 0x74, | ||
| 5644 | vgt_perf_es_thread_groups = 0x75, | ||
| 5645 | vgt_perf_vs_thread_groups = 0x76, | ||
| 5646 | vgt_perf_ls_done_latency = 0x77, | ||
| 5647 | vgt_perf_hs_done_latency = 0x78, | ||
| 5648 | vgt_perf_es_done_latency = 0x79, | ||
| 5649 | vgt_perf_gs_done_latency = 0x7a, | ||
| 5650 | vgt_perf_vgt_hs_busy = 0x7b, | ||
| 5651 | vgt_perf_vgt_te11_busy = 0x7c, | ||
| 5652 | vgt_perf_ls_flush = 0x7d, | ||
| 5653 | vgt_perf_hs_flush = 0x7e, | ||
| 5654 | vgt_perf_es_flush = 0x7f, | ||
| 5655 | vgt_perf_vgt_pa_clipp_eopg = 0x80, | ||
| 5656 | vgt_perf_ls_done = 0x81, | ||
| 5657 | vgt_perf_hs_done = 0x82, | ||
| 5658 | vgt_perf_es_done = 0x83, | ||
| 5659 | vgt_perf_gs_done = 0x84, | ||
| 5660 | vgt_perf_vsfetch_done = 0x85, | ||
| 5661 | vgt_perf_gs_done_received = 0x86, | ||
| 5662 | vgt_perf_es_ring_high_water_mark = 0x87, | ||
| 5663 | vgt_perf_gs_ring_high_water_mark = 0x88, | ||
| 5664 | vgt_perf_vs_table_high_water_mark = 0x89, | ||
| 5665 | vgt_perf_hs_tgs_active_high_water_mark = 0x8a, | ||
| 5666 | vgt_perf_pa_clipp_dealloc = 0x8b, | ||
| 5667 | vgt_perf_cut_mem_flush_stalled = 0x8c, | ||
| 5668 | vgt_perf_vsvert_work_received = 0x8d, | ||
| 5669 | vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e, | ||
| 5670 | vgt_perf_te11_con_starved_after_work = 0x8f, | ||
| 5671 | vgt_perf_hs_waiting_on_ls_done_stall = 0x90, | ||
| 5672 | vgt_spi_vsvert_valid = 0x91, | ||
| 5673 | } VGT_PERFCOUNT_SELECT; | ||
| 5674 | typedef enum IA_PERFCOUNT_SELECT { | ||
| 5675 | ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, | ||
| 5676 | ia_perf_dma_data_fifo_full = 0x1, | ||
| 5677 | ia_perf_RESERVED1 = 0x2, | ||
| 5678 | ia_perf_RESERVED2 = 0x3, | ||
| 5679 | ia_perf_RESERVED3 = 0x4, | ||
| 5680 | ia_perf_RESERVED4 = 0x5, | ||
| 5681 | ia_perf_RESERVED5 = 0x6, | ||
| 5682 | ia_perf_MC_LAT_BIN_0 = 0x7, | ||
| 5683 | ia_perf_MC_LAT_BIN_1 = 0x8, | ||
| 5684 | ia_perf_MC_LAT_BIN_2 = 0x9, | ||
| 5685 | ia_perf_MC_LAT_BIN_3 = 0xa, | ||
| 5686 | ia_perf_MC_LAT_BIN_4 = 0xb, | ||
| 5687 | ia_perf_MC_LAT_BIN_5 = 0xc, | ||
| 5688 | ia_perf_MC_LAT_BIN_6 = 0xd, | ||
| 5689 | ia_perf_MC_LAT_BIN_7 = 0xe, | ||
| 5690 | ia_perf_ia_busy = 0xf, | ||
| 5691 | ia_perf_ia_sclk_reg_vld_event = 0x10, | ||
| 5692 | ia_perf_RESERVED6 = 0x11, | ||
| 5693 | ia_perf_ia_sclk_core_vld_event = 0x12, | ||
| 5694 | ia_perf_RESERVED7 = 0x13, | ||
| 5695 | ia_perf_ia_dma_return = 0x14, | ||
| 5696 | ia_perf_ia_stalled = 0x15, | ||
| 5697 | ia_perf_shift_starved_pipe0_event = 0x16, | ||
| 5698 | ia_perf_shift_starved_pipe1_event = 0x17, | ||
| 5699 | } IA_PERFCOUNT_SELECT; | ||
| 5700 | typedef enum WD_PERFCOUNT_SELECT { | ||
| 5701 | wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, | ||
| 5702 | wd_perf_RBIU_DR_FIFO_STARVED = 0x1, | ||
| 5703 | wd_perf_RBIU_DR_FIFO_STALLED = 0x2, | ||
| 5704 | wd_perf_RBIU_DI_FIFO_STARVED = 0x3, | ||
| 5705 | wd_perf_RBIU_DI_FIFO_STALLED = 0x4, | ||
| 5706 | wd_perf_wd_busy = 0x5, | ||
| 5707 | wd_perf_wd_sclk_reg_vld_event = 0x6, | ||
| 5708 | wd_perf_wd_sclk_input_vld_event = 0x7, | ||
| 5709 | wd_perf_wd_sclk_core_vld_event = 0x8, | ||
| 5710 | wd_perf_wd_stalled = 0x9, | ||
| 5711 | wd_perf_inside_tf_bin_0 = 0xa, | ||
| 5712 | wd_perf_inside_tf_bin_1 = 0xb, | ||
| 5713 | wd_perf_inside_tf_bin_2 = 0xc, | ||
| 5714 | wd_perf_inside_tf_bin_3 = 0xd, | ||
| 5715 | wd_perf_inside_tf_bin_4 = 0xe, | ||
| 5716 | wd_perf_inside_tf_bin_5 = 0xf, | ||
| 5717 | wd_perf_inside_tf_bin_6 = 0x10, | ||
| 5718 | wd_perf_inside_tf_bin_7 = 0x11, | ||
| 5719 | wd_perf_inside_tf_bin_8 = 0x12, | ||
| 5720 | wd_perf_tfreq_lat_bin_0 = 0x13, | ||
| 5721 | wd_perf_tfreq_lat_bin_1 = 0x14, | ||
| 5722 | wd_perf_tfreq_lat_bin_2 = 0x15, | ||
| 5723 | wd_perf_tfreq_lat_bin_3 = 0x16, | ||
| 5724 | wd_perf_tfreq_lat_bin_4 = 0x17, | ||
| 5725 | wd_perf_tfreq_lat_bin_5 = 0x18, | ||
| 5726 | wd_perf_tfreq_lat_bin_6 = 0x19, | ||
| 5727 | wd_perf_tfreq_lat_bin_7 = 0x1a, | ||
| 5728 | wd_starved_on_hs_done = 0x1b, | ||
| 5729 | wd_perf_se0_hs_done_latency = 0x1c, | ||
| 5730 | wd_perf_se1_hs_done_latency = 0x1d, | ||
| 5731 | wd_perf_se2_hs_done_latency = 0x1e, | ||
| 5732 | wd_perf_se3_hs_done_latency = 0x1f, | ||
| 5733 | wd_perf_hs_done_se0 = 0x20, | ||
| 5734 | wd_perf_hs_done_se1 = 0x21, | ||
| 5735 | wd_perf_hs_done_se2 = 0x22, | ||
| 5736 | wd_perf_hs_done_se3 = 0x23, | ||
| 5737 | wd_perf_null_patches = 0x24, | ||
| 5738 | } WD_PERFCOUNT_SELECT; | ||
| 5739 | typedef enum WD_IA_DRAW_TYPE { | ||
| 5740 | WD_IA_DRAW_TYPE_DI_MM0 = 0x0, | ||
| 5741 | WD_IA_DRAW_TYPE_DI_MM1 = 0x1, | ||
| 5742 | WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, | ||
| 5743 | WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, | ||
| 5744 | WD_IA_DRAW_TYPE_MIN_INDX = 0x4, | ||
| 5745 | WD_IA_DRAW_TYPE_MAX_INDX = 0x5, | ||
| 5746 | WD_IA_DRAW_TYPE_INDX_OFF = 0x6, | ||
| 5747 | WD_IA_DRAW_TYPE_IMM_DATA = 0x7, | ||
| 5748 | } WD_IA_DRAW_TYPE; | ||
| 5749 | typedef enum WD_IA_DRAW_SOURCE { | ||
| 5750 | WD_IA_DRAW_SOURCE_DMA = 0x0, | ||
| 5751 | WD_IA_DRAW_SOURCE_IMMD = 0x1, | ||
| 5752 | WD_IA_DRAW_SOURCE_AUTO = 0x2, | ||
| 5753 | WD_IA_DRAW_SOURCE_OPAQ = 0x3, | ||
| 5754 | } WD_IA_DRAW_SOURCE; | ||
| 5755 | #define GSTHREADID_SIZE 0x2 | ||
| 5756 | typedef enum DebugBlockId { | ||
| 5757 | DBG_BLOCK_ID_RESERVED = 0x0, | ||
| 5758 | DBG_BLOCK_ID_DBG = 0x1, | ||
| 5759 | DBG_BLOCK_ID_VMC = 0x2, | ||
| 5760 | DBG_BLOCK_ID_PDMA = 0x3, | ||
| 5761 | DBG_BLOCK_ID_CG = 0x4, | ||
| 5762 | DBG_BLOCK_ID_SRBM = 0x5, | ||
| 5763 | DBG_BLOCK_ID_GRBM = 0x6, | ||
| 5764 | DBG_BLOCK_ID_RLC = 0x7, | ||
| 5765 | DBG_BLOCK_ID_CSC = 0x8, | ||
| 5766 | DBG_BLOCK_ID_SEM = 0x9, | ||
| 5767 | DBG_BLOCK_ID_IH = 0xa, | ||
| 5768 | DBG_BLOCK_ID_SC = 0xb, | ||
| 5769 | DBG_BLOCK_ID_SQ = 0xc, | ||
| 5770 | DBG_BLOCK_ID_UVDU = 0xd, | ||
| 5771 | DBG_BLOCK_ID_SQA = 0xe, | ||
| 5772 | DBG_BLOCK_ID_SDMA0 = 0xf, | ||
| 5773 | DBG_BLOCK_ID_SDMA1 = 0x10, | ||
| 5774 | DBG_BLOCK_ID_SPIM = 0x11, | ||
| 5775 | DBG_BLOCK_ID_GDS = 0x12, | ||
| 5776 | DBG_BLOCK_ID_VC0 = 0x13, | ||
| 5777 | DBG_BLOCK_ID_VC1 = 0x14, | ||
| 5778 | DBG_BLOCK_ID_PA0 = 0x15, | ||
| 5779 | DBG_BLOCK_ID_PA1 = 0x16, | ||
| 5780 | DBG_BLOCK_ID_CP0 = 0x17, | ||
| 5781 | DBG_BLOCK_ID_CP1 = 0x18, | ||
| 5782 | DBG_BLOCK_ID_CP2 = 0x19, | ||
| 5783 | DBG_BLOCK_ID_XBR = 0x1a, | ||
| 5784 | DBG_BLOCK_ID_UVDM = 0x1b, | ||
| 5785 | DBG_BLOCK_ID_VGT0 = 0x1c, | ||
| 5786 | DBG_BLOCK_ID_VGT1 = 0x1d, | ||
| 5787 | DBG_BLOCK_ID_IA = 0x1e, | ||
| 5788 | DBG_BLOCK_ID_SXM0 = 0x1f, | ||
| 5789 | DBG_BLOCK_ID_SXM1 = 0x20, | ||
| 5790 | DBG_BLOCK_ID_SCT0 = 0x21, | ||
| 5791 | DBG_BLOCK_ID_SCT1 = 0x22, | ||
| 5792 | DBG_BLOCK_ID_SPM0 = 0x23, | ||
| 5793 | DBG_BLOCK_ID_SPM1 = 0x24, | ||
| 5794 | DBG_BLOCK_ID_UNUSED0 = 0x25, | ||
| 5795 | DBG_BLOCK_ID_UNUSED1 = 0x26, | ||
| 5796 | DBG_BLOCK_ID_TCAA = 0x27, | ||
| 5797 | DBG_BLOCK_ID_TCAB = 0x28, | ||
| 5798 | DBG_BLOCK_ID_TCCA = 0x29, | ||
| 5799 | DBG_BLOCK_ID_TCCB = 0x2a, | ||
| 5800 | DBG_BLOCK_ID_MCC0 = 0x2b, | ||
| 5801 | DBG_BLOCK_ID_MCC1 = 0x2c, | ||
| 5802 | DBG_BLOCK_ID_MCC2 = 0x2d, | ||
| 5803 | DBG_BLOCK_ID_MCC3 = 0x2e, | ||
| 5804 | DBG_BLOCK_ID_SXS0 = 0x2f, | ||
| 5805 | DBG_BLOCK_ID_SXS1 = 0x30, | ||
| 5806 | DBG_BLOCK_ID_SXS2 = 0x31, | ||
| 5807 | DBG_BLOCK_ID_SXS3 = 0x32, | ||
| 5808 | DBG_BLOCK_ID_SXS4 = 0x33, | ||
| 5809 | DBG_BLOCK_ID_SXS5 = 0x34, | ||
| 5810 | DBG_BLOCK_ID_SXS6 = 0x35, | ||
| 5811 | DBG_BLOCK_ID_SXS7 = 0x36, | ||
| 5812 | DBG_BLOCK_ID_SXS8 = 0x37, | ||
| 5813 | DBG_BLOCK_ID_SXS9 = 0x38, | ||
| 5814 | DBG_BLOCK_ID_BCI0 = 0x39, | ||
| 5815 | DBG_BLOCK_ID_BCI1 = 0x3a, | ||
| 5816 | DBG_BLOCK_ID_BCI2 = 0x3b, | ||
| 5817 | DBG_BLOCK_ID_BCI3 = 0x3c, | ||
| 5818 | DBG_BLOCK_ID_MCB = 0x3d, | ||
| 5819 | DBG_BLOCK_ID_UNUSED6 = 0x3e, | ||
| 5820 | DBG_BLOCK_ID_SQA00 = 0x3f, | ||
| 5821 | DBG_BLOCK_ID_SQA01 = 0x40, | ||
| 5822 | DBG_BLOCK_ID_SQA02 = 0x41, | ||
| 5823 | DBG_BLOCK_ID_SQA10 = 0x42, | ||
| 5824 | DBG_BLOCK_ID_SQA11 = 0x43, | ||
| 5825 | DBG_BLOCK_ID_SQA12 = 0x44, | ||
| 5826 | DBG_BLOCK_ID_UNUSED7 = 0x45, | ||
| 5827 | DBG_BLOCK_ID_UNUSED8 = 0x46, | ||
| 5828 | DBG_BLOCK_ID_SQB00 = 0x47, | ||
| 5829 | DBG_BLOCK_ID_SQB01 = 0x48, | ||
| 5830 | DBG_BLOCK_ID_SQB10 = 0x49, | ||
| 5831 | DBG_BLOCK_ID_SQB11 = 0x4a, | ||
| 5832 | DBG_BLOCK_ID_SQ00 = 0x4b, | ||
| 5833 | DBG_BLOCK_ID_SQ01 = 0x4c, | ||
| 5834 | DBG_BLOCK_ID_SQ10 = 0x4d, | ||
| 5835 | DBG_BLOCK_ID_SQ11 = 0x4e, | ||
| 5836 | DBG_BLOCK_ID_CB00 = 0x4f, | ||
| 5837 | DBG_BLOCK_ID_CB01 = 0x50, | ||
| 5838 | DBG_BLOCK_ID_CB02 = 0x51, | ||
| 5839 | DBG_BLOCK_ID_CB03 = 0x52, | ||
| 5840 | DBG_BLOCK_ID_CB04 = 0x53, | ||
| 5841 | DBG_BLOCK_ID_UNUSED9 = 0x54, | ||
| 5842 | DBG_BLOCK_ID_UNUSED10 = 0x55, | ||
| 5843 | DBG_BLOCK_ID_UNUSED11 = 0x56, | ||
| 5844 | DBG_BLOCK_ID_CB10 = 0x57, | ||
| 5845 | DBG_BLOCK_ID_CB11 = 0x58, | ||
| 5846 | DBG_BLOCK_ID_CB12 = 0x59, | ||
| 5847 | DBG_BLOCK_ID_CB13 = 0x5a, | ||
| 5848 | DBG_BLOCK_ID_CB14 = 0x5b, | ||
| 5849 | DBG_BLOCK_ID_UNUSED12 = 0x5c, | ||
| 5850 | DBG_BLOCK_ID_UNUSED13 = 0x5d, | ||
| 5851 | DBG_BLOCK_ID_UNUSED14 = 0x5e, | ||
| 5852 | DBG_BLOCK_ID_TCP0 = 0x5f, | ||
| 5853 | DBG_BLOCK_ID_TCP1 = 0x60, | ||
| 5854 | DBG_BLOCK_ID_TCP2 = 0x61, | ||
| 5855 | DBG_BLOCK_ID_TCP3 = 0x62, | ||
| 5856 | DBG_BLOCK_ID_TCP4 = 0x63, | ||
| 5857 | DBG_BLOCK_ID_TCP5 = 0x64, | ||
| 5858 | DBG_BLOCK_ID_TCP6 = 0x65, | ||
| 5859 | DBG_BLOCK_ID_TCP7 = 0x66, | ||
| 5860 | DBG_BLOCK_ID_TCP8 = 0x67, | ||
| 5861 | DBG_BLOCK_ID_TCP9 = 0x68, | ||
| 5862 | DBG_BLOCK_ID_TCP10 = 0x69, | ||
| 5863 | DBG_BLOCK_ID_TCP11 = 0x6a, | ||
| 5864 | DBG_BLOCK_ID_TCP12 = 0x6b, | ||
| 5865 | DBG_BLOCK_ID_TCP13 = 0x6c, | ||
| 5866 | DBG_BLOCK_ID_TCP14 = 0x6d, | ||
| 5867 | DBG_BLOCK_ID_TCP15 = 0x6e, | ||
| 5868 | DBG_BLOCK_ID_TCP16 = 0x6f, | ||
| 5869 | DBG_BLOCK_ID_TCP17 = 0x70, | ||
| 5870 | DBG_BLOCK_ID_TCP18 = 0x71, | ||
| 5871 | DBG_BLOCK_ID_TCP19 = 0x72, | ||
| 5872 | DBG_BLOCK_ID_TCP20 = 0x73, | ||
| 5873 | DBG_BLOCK_ID_TCP21 = 0x74, | ||
| 5874 | DBG_BLOCK_ID_TCP22 = 0x75, | ||
| 5875 | DBG_BLOCK_ID_TCP23 = 0x76, | ||
| 5876 | DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, | ||
| 5877 | DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, | ||
| 5878 | DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, | ||
| 5879 | DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, | ||
| 5880 | DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, | ||
| 5881 | DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, | ||
| 5882 | DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, | ||
| 5883 | DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, | ||
| 5884 | DBG_BLOCK_ID_DB00 = 0x7f, | ||
| 5885 | DBG_BLOCK_ID_DB01 = 0x80, | ||
| 5886 | DBG_BLOCK_ID_DB02 = 0x81, | ||
| 5887 | DBG_BLOCK_ID_DB03 = 0x82, | ||
| 5888 | DBG_BLOCK_ID_DB04 = 0x83, | ||
| 5889 | DBG_BLOCK_ID_UNUSED15 = 0x84, | ||
| 5890 | DBG_BLOCK_ID_UNUSED16 = 0x85, | ||
| 5891 | DBG_BLOCK_ID_UNUSED17 = 0x86, | ||
| 5892 | DBG_BLOCK_ID_DB10 = 0x87, | ||
| 5893 | DBG_BLOCK_ID_DB11 = 0x88, | ||
| 5894 | DBG_BLOCK_ID_DB12 = 0x89, | ||
| 5895 | DBG_BLOCK_ID_DB13 = 0x8a, | ||
| 5896 | DBG_BLOCK_ID_DB14 = 0x8b, | ||
| 5897 | DBG_BLOCK_ID_UNUSED18 = 0x8c, | ||
| 5898 | DBG_BLOCK_ID_UNUSED19 = 0x8d, | ||
| 5899 | DBG_BLOCK_ID_UNUSED20 = 0x8e, | ||
| 5900 | DBG_BLOCK_ID_TCC0 = 0x8f, | ||
| 5901 | DBG_BLOCK_ID_TCC1 = 0x90, | ||
| 5902 | DBG_BLOCK_ID_TCC2 = 0x91, | ||
| 5903 | DBG_BLOCK_ID_TCC3 = 0x92, | ||
| 5904 | DBG_BLOCK_ID_TCC4 = 0x93, | ||
| 5905 | DBG_BLOCK_ID_TCC5 = 0x94, | ||
| 5906 | DBG_BLOCK_ID_TCC6 = 0x95, | ||
| 5907 | DBG_BLOCK_ID_TCC7 = 0x96, | ||
| 5908 | DBG_BLOCK_ID_SPS00 = 0x97, | ||
| 5909 | DBG_BLOCK_ID_SPS01 = 0x98, | ||
| 5910 | DBG_BLOCK_ID_SPS02 = 0x99, | ||
| 5911 | DBG_BLOCK_ID_SPS10 = 0x9a, | ||
| 5912 | DBG_BLOCK_ID_SPS11 = 0x9b, | ||
| 5913 | DBG_BLOCK_ID_SPS12 = 0x9c, | ||
| 5914 | DBG_BLOCK_ID_UNUSED21 = 0x9d, | ||
| 5915 | DBG_BLOCK_ID_UNUSED22 = 0x9e, | ||
| 5916 | DBG_BLOCK_ID_TA00 = 0x9f, | ||
| 5917 | DBG_BLOCK_ID_TA01 = 0xa0, | ||
| 5918 | DBG_BLOCK_ID_TA02 = 0xa1, | ||
| 5919 | DBG_BLOCK_ID_TA03 = 0xa2, | ||
| 5920 | DBG_BLOCK_ID_TA04 = 0xa3, | ||
| 5921 | DBG_BLOCK_ID_TA05 = 0xa4, | ||
| 5922 | DBG_BLOCK_ID_TA06 = 0xa5, | ||
| 5923 | DBG_BLOCK_ID_TA07 = 0xa6, | ||
| 5924 | DBG_BLOCK_ID_TA08 = 0xa7, | ||
| 5925 | DBG_BLOCK_ID_TA09 = 0xa8, | ||
| 5926 | DBG_BLOCK_ID_TA0A = 0xa9, | ||
| 5927 | DBG_BLOCK_ID_TA0B = 0xaa, | ||
| 5928 | DBG_BLOCK_ID_UNUSED23 = 0xab, | ||
| 5929 | DBG_BLOCK_ID_UNUSED24 = 0xac, | ||
| 5930 | DBG_BLOCK_ID_UNUSED25 = 0xad, | ||
| 5931 | DBG_BLOCK_ID_UNUSED26 = 0xae, | ||
| 5932 | DBG_BLOCK_ID_TA10 = 0xaf, | ||
| 5933 | DBG_BLOCK_ID_TA11 = 0xb0, | ||
| 5934 | DBG_BLOCK_ID_TA12 = 0xb1, | ||
| 5935 | DBG_BLOCK_ID_TA13 = 0xb2, | ||
| 5936 | DBG_BLOCK_ID_TA14 = 0xb3, | ||
| 5937 | DBG_BLOCK_ID_TA15 = 0xb4, | ||
| 5938 | DBG_BLOCK_ID_TA16 = 0xb5, | ||
| 5939 | DBG_BLOCK_ID_TA17 = 0xb6, | ||
| 5940 | DBG_BLOCK_ID_TA18 = 0xb7, | ||
| 5941 | DBG_BLOCK_ID_TA19 = 0xb8, | ||
| 5942 | DBG_BLOCK_ID_TA1A = 0xb9, | ||
| 5943 | DBG_BLOCK_ID_TA1B = 0xba, | ||
| 5944 | DBG_BLOCK_ID_UNUSED27 = 0xbb, | ||
| 5945 | DBG_BLOCK_ID_UNUSED28 = 0xbc, | ||
| 5946 | DBG_BLOCK_ID_UNUSED29 = 0xbd, | ||
| 5947 | DBG_BLOCK_ID_UNUSED30 = 0xbe, | ||
| 5948 | DBG_BLOCK_ID_TD00 = 0xbf, | ||
| 5949 | DBG_BLOCK_ID_TD01 = 0xc0, | ||
| 5950 | DBG_BLOCK_ID_TD02 = 0xc1, | ||
| 5951 | DBG_BLOCK_ID_TD03 = 0xc2, | ||
| 5952 | DBG_BLOCK_ID_TD04 = 0xc3, | ||
| 5953 | DBG_BLOCK_ID_TD05 = 0xc4, | ||
| 5954 | DBG_BLOCK_ID_TD06 = 0xc5, | ||
| 5955 | DBG_BLOCK_ID_TD07 = 0xc6, | ||
| 5956 | DBG_BLOCK_ID_TD08 = 0xc7, | ||
| 5957 | DBG_BLOCK_ID_TD09 = 0xc8, | ||
| 5958 | DBG_BLOCK_ID_TD0A = 0xc9, | ||
| 5959 | DBG_BLOCK_ID_TD0B = 0xca, | ||
| 5960 | DBG_BLOCK_ID_UNUSED31 = 0xcb, | ||
| 5961 | DBG_BLOCK_ID_UNUSED32 = 0xcc, | ||
| 5962 | DBG_BLOCK_ID_UNUSED33 = 0xcd, | ||
| 5963 | DBG_BLOCK_ID_UNUSED34 = 0xce, | ||
| 5964 | DBG_BLOCK_ID_TD10 = 0xcf, | ||
| 5965 | DBG_BLOCK_ID_TD11 = 0xd0, | ||
| 5966 | DBG_BLOCK_ID_TD12 = 0xd1, | ||
| 5967 | DBG_BLOCK_ID_TD13 = 0xd2, | ||
| 5968 | DBG_BLOCK_ID_TD14 = 0xd3, | ||
| 5969 | DBG_BLOCK_ID_TD15 = 0xd4, | ||
| 5970 | DBG_BLOCK_ID_TD16 = 0xd5, | ||
| 5971 | DBG_BLOCK_ID_TD17 = 0xd6, | ||
| 5972 | DBG_BLOCK_ID_TD18 = 0xd7, | ||
| 5973 | DBG_BLOCK_ID_TD19 = 0xd8, | ||
| 5974 | DBG_BLOCK_ID_TD1A = 0xd9, | ||
| 5975 | DBG_BLOCK_ID_TD1B = 0xda, | ||
| 5976 | DBG_BLOCK_ID_UNUSED35 = 0xdb, | ||
| 5977 | DBG_BLOCK_ID_UNUSED36 = 0xdc, | ||
| 5978 | DBG_BLOCK_ID_UNUSED37 = 0xdd, | ||
| 5979 | DBG_BLOCK_ID_UNUSED38 = 0xde, | ||
| 5980 | DBG_BLOCK_ID_LDS00 = 0xdf, | ||
| 5981 | DBG_BLOCK_ID_LDS01 = 0xe0, | ||
| 5982 | DBG_BLOCK_ID_LDS02 = 0xe1, | ||
| 5983 | DBG_BLOCK_ID_LDS03 = 0xe2, | ||
| 5984 | DBG_BLOCK_ID_LDS04 = 0xe3, | ||
| 5985 | DBG_BLOCK_ID_LDS05 = 0xe4, | ||
| 5986 | DBG_BLOCK_ID_LDS06 = 0xe5, | ||
| 5987 | DBG_BLOCK_ID_LDS07 = 0xe6, | ||
| 5988 | DBG_BLOCK_ID_LDS08 = 0xe7, | ||
| 5989 | DBG_BLOCK_ID_LDS09 = 0xe8, | ||
| 5990 | DBG_BLOCK_ID_LDS0A = 0xe9, | ||
| 5991 | DBG_BLOCK_ID_LDS0B = 0xea, | ||
| 5992 | DBG_BLOCK_ID_UNUSED39 = 0xeb, | ||
| 5993 | DBG_BLOCK_ID_UNUSED40 = 0xec, | ||
| 5994 | DBG_BLOCK_ID_UNUSED41 = 0xed, | ||
| 5995 | DBG_BLOCK_ID_UNUSED42 = 0xee, | ||
| 5996 | DBG_BLOCK_ID_LDS10 = 0xef, | ||
| 5997 | DBG_BLOCK_ID_LDS11 = 0xf0, | ||
| 5998 | DBG_BLOCK_ID_LDS12 = 0xf1, | ||
| 5999 | DBG_BLOCK_ID_LDS13 = 0xf2, | ||
| 6000 | DBG_BLOCK_ID_LDS14 = 0xf3, | ||
| 6001 | DBG_BLOCK_ID_LDS15 = 0xf4, | ||
| 6002 | DBG_BLOCK_ID_LDS16 = 0xf5, | ||
| 6003 | DBG_BLOCK_ID_LDS17 = 0xf6, | ||
| 6004 | DBG_BLOCK_ID_LDS18 = 0xf7, | ||
| 6005 | DBG_BLOCK_ID_LDS19 = 0xf8, | ||
| 6006 | DBG_BLOCK_ID_LDS1A = 0xf9, | ||
| 6007 | DBG_BLOCK_ID_LDS1B = 0xfa, | ||
| 6008 | DBG_BLOCK_ID_UNUSED43 = 0xfb, | ||
| 6009 | DBG_BLOCK_ID_UNUSED44 = 0xfc, | ||
| 6010 | DBG_BLOCK_ID_UNUSED45 = 0xfd, | ||
| 6011 | DBG_BLOCK_ID_UNUSED46 = 0xfe, | ||
| 6012 | } DebugBlockId; | ||
| 6013 | typedef enum DebugBlockId_BY2 { | ||
| 6014 | DBG_BLOCK_ID_RESERVED_BY2 = 0x0, | ||
| 6015 | DBG_BLOCK_ID_VMC_BY2 = 0x1, | ||
| 6016 | DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, | ||
| 6017 | DBG_BLOCK_ID_GRBM_BY2 = 0x3, | ||
| 6018 | DBG_BLOCK_ID_CSC_BY2 = 0x4, | ||
| 6019 | DBG_BLOCK_ID_IH_BY2 = 0x5, | ||
| 6020 | DBG_BLOCK_ID_SQ_BY2 = 0x6, | ||
| 6021 | DBG_BLOCK_ID_UVD_BY2 = 0x7, | ||
| 6022 | DBG_BLOCK_ID_SDMA0_BY2 = 0x8, | ||
| 6023 | DBG_BLOCK_ID_SPIM_BY2 = 0x9, | ||
| 6024 | DBG_BLOCK_ID_VC0_BY2 = 0xa, | ||
| 6025 | DBG_BLOCK_ID_PA_BY2 = 0xb, | ||
| 6026 | DBG_BLOCK_ID_CP0_BY2 = 0xc, | ||
| 6027 | DBG_BLOCK_ID_CP2_BY2 = 0xd, | ||
| 6028 | DBG_BLOCK_ID_PC0_BY2 = 0xe, | ||
| 6029 | DBG_BLOCK_ID_BCI0_BY2 = 0xf, | ||
| 6030 | DBG_BLOCK_ID_SXM0_BY2 = 0x10, | ||
| 6031 | DBG_BLOCK_ID_SCT0_BY2 = 0x11, | ||
| 6032 | DBG_BLOCK_ID_SPM0_BY2 = 0x12, | ||
| 6033 | DBG_BLOCK_ID_BCI2_BY2 = 0x13, | ||
| 6034 | DBG_BLOCK_ID_TCA_BY2 = 0x14, | ||
| 6035 | DBG_BLOCK_ID_TCCA_BY2 = 0x15, | ||
| 6036 | DBG_BLOCK_ID_MCC_BY2 = 0x16, | ||
| 6037 | DBG_BLOCK_ID_MCC2_BY2 = 0x17, | ||
| 6038 | DBG_BLOCK_ID_MCD_BY2 = 0x18, | ||
| 6039 | DBG_BLOCK_ID_MCD2_BY2 = 0x19, | ||
| 6040 | DBG_BLOCK_ID_MCD4_BY2 = 0x1a, | ||
| 6041 | DBG_BLOCK_ID_MCB_BY2 = 0x1b, | ||
| 6042 | DBG_BLOCK_ID_SQA_BY2 = 0x1c, | ||
| 6043 | DBG_BLOCK_ID_SQA02_BY2 = 0x1d, | ||
| 6044 | DBG_BLOCK_ID_SQA11_BY2 = 0x1e, | ||
| 6045 | DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, | ||
| 6046 | DBG_BLOCK_ID_SQB_BY2 = 0x20, | ||
| 6047 | DBG_BLOCK_ID_SQB10_BY2 = 0x21, | ||
| 6048 | DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, | ||
| 6049 | DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, | ||
| 6050 | DBG_BLOCK_ID_CB_BY2 = 0x24, | ||
| 6051 | DBG_BLOCK_ID_CB02_BY2 = 0x25, | ||
| 6052 | DBG_BLOCK_ID_CB10_BY2 = 0x26, | ||
| 6053 | DBG_BLOCK_ID_CB12_BY2 = 0x27, | ||
| 6054 | DBG_BLOCK_ID_SXS_BY2 = 0x28, | ||
| 6055 | DBG_BLOCK_ID_SXS2_BY2 = 0x29, | ||
| 6056 | DBG_BLOCK_ID_SXS4_BY2 = 0x2a, | ||
| 6057 | DBG_BLOCK_ID_SXS6_BY2 = 0x2b, | ||
| 6058 | DBG_BLOCK_ID_DB_BY2 = 0x2c, | ||
| 6059 | DBG_BLOCK_ID_DB02_BY2 = 0x2d, | ||
| 6060 | DBG_BLOCK_ID_DB10_BY2 = 0x2e, | ||
| 6061 | DBG_BLOCK_ID_DB12_BY2 = 0x2f, | ||
| 6062 | DBG_BLOCK_ID_TCP_BY2 = 0x30, | ||
| 6063 | DBG_BLOCK_ID_TCP2_BY2 = 0x31, | ||
| 6064 | DBG_BLOCK_ID_TCP4_BY2 = 0x32, | ||
| 6065 | DBG_BLOCK_ID_TCP6_BY2 = 0x33, | ||
| 6066 | DBG_BLOCK_ID_TCP8_BY2 = 0x34, | ||
| 6067 | DBG_BLOCK_ID_TCP10_BY2 = 0x35, | ||
| 6068 | DBG_BLOCK_ID_TCP12_BY2 = 0x36, | ||
| 6069 | DBG_BLOCK_ID_TCP14_BY2 = 0x37, | ||
| 6070 | DBG_BLOCK_ID_TCP16_BY2 = 0x38, | ||
| 6071 | DBG_BLOCK_ID_TCP18_BY2 = 0x39, | ||
| 6072 | DBG_BLOCK_ID_TCP20_BY2 = 0x3a, | ||
| 6073 | DBG_BLOCK_ID_TCP22_BY2 = 0x3b, | ||
| 6074 | DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, | ||
| 6075 | DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, | ||
| 6076 | DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, | ||
| 6077 | DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, | ||
| 6078 | DBG_BLOCK_ID_TCC_BY2 = 0x40, | ||
| 6079 | DBG_BLOCK_ID_TCC2_BY2 = 0x41, | ||
| 6080 | DBG_BLOCK_ID_TCC4_BY2 = 0x42, | ||
| 6081 | DBG_BLOCK_ID_TCC6_BY2 = 0x43, | ||
| 6082 | DBG_BLOCK_ID_SPS_BY2 = 0x44, | ||
| 6083 | DBG_BLOCK_ID_SPS02_BY2 = 0x45, | ||
| 6084 | DBG_BLOCK_ID_SPS11_BY2 = 0x46, | ||
| 6085 | DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, | ||
| 6086 | DBG_BLOCK_ID_TA_BY2 = 0x48, | ||
| 6087 | DBG_BLOCK_ID_TA02_BY2 = 0x49, | ||
| 6088 | DBG_BLOCK_ID_TA04_BY2 = 0x4a, | ||
| 6089 | DBG_BLOCK_ID_TA06_BY2 = 0x4b, | ||
| 6090 | DBG_BLOCK_ID_TA08_BY2 = 0x4c, | ||
| 6091 | DBG_BLOCK_ID_TA0A_BY2 = 0x4d, | ||
| 6092 | DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, | ||
| 6093 | DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, | ||
| 6094 | DBG_BLOCK_ID_TA10_BY2 = 0x50, | ||
| 6095 | DBG_BLOCK_ID_TA12_BY2 = 0x51, | ||
| 6096 | DBG_BLOCK_ID_TA14_BY2 = 0x52, | ||
| 6097 | DBG_BLOCK_ID_TA16_BY2 = 0x53, | ||
| 6098 | DBG_BLOCK_ID_TA18_BY2 = 0x54, | ||
| 6099 | DBG_BLOCK_ID_TA1A_BY2 = 0x55, | ||
| 6100 | DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, | ||
| 6101 | DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, | ||
| 6102 | DBG_BLOCK_ID_TD_BY2 = 0x58, | ||
| 6103 | DBG_BLOCK_ID_TD02_BY2 = 0x59, | ||
| 6104 | DBG_BLOCK_ID_TD04_BY2 = 0x5a, | ||
| 6105 | DBG_BLOCK_ID_TD06_BY2 = 0x5b, | ||
| 6106 | DBG_BLOCK_ID_TD08_BY2 = 0x5c, | ||
| 6107 | DBG_BLOCK_ID_TD0A_BY2 = 0x5d, | ||
| 6108 | DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, | ||
| 6109 | DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, | ||
| 6110 | DBG_BLOCK_ID_TD10_BY2 = 0x60, | ||
| 6111 | DBG_BLOCK_ID_TD12_BY2 = 0x61, | ||
| 6112 | DBG_BLOCK_ID_TD14_BY2 = 0x62, | ||
| 6113 | DBG_BLOCK_ID_TD16_BY2 = 0x63, | ||
| 6114 | DBG_BLOCK_ID_TD18_BY2 = 0x64, | ||
| 6115 | DBG_BLOCK_ID_TD1A_BY2 = 0x65, | ||
| 6116 | DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, | ||
| 6117 | DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, | ||
| 6118 | DBG_BLOCK_ID_LDS_BY2 = 0x68, | ||
| 6119 | DBG_BLOCK_ID_LDS02_BY2 = 0x69, | ||
| 6120 | DBG_BLOCK_ID_LDS04_BY2 = 0x6a, | ||
| 6121 | DBG_BLOCK_ID_LDS06_BY2 = 0x6b, | ||
| 6122 | DBG_BLOCK_ID_LDS08_BY2 = 0x6c, | ||
| 6123 | DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, | ||
| 6124 | DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, | ||
| 6125 | DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, | ||
| 6126 | DBG_BLOCK_ID_LDS10_BY2 = 0x70, | ||
| 6127 | DBG_BLOCK_ID_LDS12_BY2 = 0x71, | ||
| 6128 | DBG_BLOCK_ID_LDS14_BY2 = 0x72, | ||
| 6129 | DBG_BLOCK_ID_LDS16_BY2 = 0x73, | ||
| 6130 | DBG_BLOCK_ID_LDS18_BY2 = 0x74, | ||
| 6131 | DBG_BLOCK_ID_LDS1A_BY2 = 0x75, | ||
| 6132 | DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, | ||
| 6133 | DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, | ||
| 6134 | } DebugBlockId_BY2; | ||
| 6135 | typedef enum DebugBlockId_BY4 { | ||
| 6136 | DBG_BLOCK_ID_RESERVED_BY4 = 0x0, | ||
| 6137 | DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, | ||
| 6138 | DBG_BLOCK_ID_CSC_BY4 = 0x2, | ||
| 6139 | DBG_BLOCK_ID_SQ_BY4 = 0x3, | ||
| 6140 | DBG_BLOCK_ID_SDMA0_BY4 = 0x4, | ||
| 6141 | DBG_BLOCK_ID_VC0_BY4 = 0x5, | ||
| 6142 | DBG_BLOCK_ID_CP0_BY4 = 0x6, | ||
| 6143 | DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, | ||
| 6144 | DBG_BLOCK_ID_SXM0_BY4 = 0x8, | ||
| 6145 | DBG_BLOCK_ID_SPM0_BY4 = 0x9, | ||
| 6146 | DBG_BLOCK_ID_TCAA_BY4 = 0xa, | ||
| 6147 | DBG_BLOCK_ID_MCC_BY4 = 0xb, | ||
| 6148 | DBG_BLOCK_ID_MCD_BY4 = 0xc, | ||
| 6149 | DBG_BLOCK_ID_MCD4_BY4 = 0xd, | ||
| 6150 | DBG_BLOCK_ID_SQA_BY4 = 0xe, | ||
| 6151 | DBG_BLOCK_ID_SQA11_BY4 = 0xf, | ||
| 6152 | DBG_BLOCK_ID_SQB_BY4 = 0x10, | ||
| 6153 | DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, | ||
| 6154 | DBG_BLOCK_ID_CB_BY4 = 0x12, | ||
| 6155 | DBG_BLOCK_ID_CB10_BY4 = 0x13, | ||
| 6156 | DBG_BLOCK_ID_SXS_BY4 = 0x14, | ||
| 6157 | DBG_BLOCK_ID_SXS4_BY4 = 0x15, | ||
| 6158 | DBG_BLOCK_ID_DB_BY4 = 0x16, | ||
| 6159 | DBG_BLOCK_ID_DB10_BY4 = 0x17, | ||
| 6160 | DBG_BLOCK_ID_TCP_BY4 = 0x18, | ||
| 6161 | DBG_BLOCK_ID_TCP4_BY4 = 0x19, | ||
| 6162 | DBG_BLOCK_ID_TCP8_BY4 = 0x1a, | ||
| 6163 | DBG_BLOCK_ID_TCP12_BY4 = 0x1b, | ||
| 6164 | DBG_BLOCK_ID_TCP16_BY4 = 0x1c, | ||
| 6165 | DBG_BLOCK_ID_TCP20_BY4 = 0x1d, | ||
| 6166 | DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, | ||
| 6167 | DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, | ||
| 6168 | DBG_BLOCK_ID_TCC_BY4 = 0x20, | ||
| 6169 | DBG_BLOCK_ID_TCC4_BY4 = 0x21, | ||
| 6170 | DBG_BLOCK_ID_SPS_BY4 = 0x22, | ||
| 6171 | DBG_BLOCK_ID_SPS11_BY4 = 0x23, | ||
| 6172 | DBG_BLOCK_ID_TA_BY4 = 0x24, | ||
| 6173 | DBG_BLOCK_ID_TA04_BY4 = 0x25, | ||
| 6174 | DBG_BLOCK_ID_TA08_BY4 = 0x26, | ||
| 6175 | DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, | ||
| 6176 | DBG_BLOCK_ID_TA10_BY4 = 0x28, | ||
| 6177 | DBG_BLOCK_ID_TA14_BY4 = 0x29, | ||
| 6178 | DBG_BLOCK_ID_TA18_BY4 = 0x2a, | ||
| 6179 | DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, | ||
| 6180 | DBG_BLOCK_ID_TD_BY4 = 0x2c, | ||
| 6181 | DBG_BLOCK_ID_TD04_BY4 = 0x2d, | ||
| 6182 | DBG_BLOCK_ID_TD08_BY4 = 0x2e, | ||
| 6183 | DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, | ||
| 6184 | DBG_BLOCK_ID_TD10_BY4 = 0x30, | ||
| 6185 | DBG_BLOCK_ID_TD14_BY4 = 0x31, | ||
| 6186 | DBG_BLOCK_ID_TD18_BY4 = 0x32, | ||
| 6187 | DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, | ||
| 6188 | DBG_BLOCK_ID_LDS_BY4 = 0x34, | ||
| 6189 | DBG_BLOCK_ID_LDS04_BY4 = 0x35, | ||
| 6190 | DBG_BLOCK_ID_LDS08_BY4 = 0x36, | ||
| 6191 | DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, | ||
| 6192 | DBG_BLOCK_ID_LDS10_BY4 = 0x38, | ||
| 6193 | DBG_BLOCK_ID_LDS14_BY4 = 0x39, | ||
| 6194 | DBG_BLOCK_ID_LDS18_BY4 = 0x3a, | ||
| 6195 | DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, | ||
| 6196 | } DebugBlockId_BY4; | ||
| 6197 | typedef enum DebugBlockId_BY8 { | ||
| 6198 | DBG_BLOCK_ID_RESERVED_BY8 = 0x0, | ||
| 6199 | DBG_BLOCK_ID_CSC_BY8 = 0x1, | ||
| 6200 | DBG_BLOCK_ID_SDMA0_BY8 = 0x2, | ||
| 6201 | DBG_BLOCK_ID_CP0_BY8 = 0x3, | ||
| 6202 | DBG_BLOCK_ID_SXM0_BY8 = 0x4, | ||
| 6203 | DBG_BLOCK_ID_TCA_BY8 = 0x5, | ||
| 6204 | DBG_BLOCK_ID_MCD_BY8 = 0x6, | ||
| 6205 | DBG_BLOCK_ID_SQA_BY8 = 0x7, | ||
| 6206 | DBG_BLOCK_ID_SQB_BY8 = 0x8, | ||
| 6207 | DBG_BLOCK_ID_CB_BY8 = 0x9, | ||
| 6208 | DBG_BLOCK_ID_SXS_BY8 = 0xa, | ||
| 6209 | DBG_BLOCK_ID_DB_BY8 = 0xb, | ||
| 6210 | DBG_BLOCK_ID_TCP_BY8 = 0xc, | ||
| 6211 | DBG_BLOCK_ID_TCP8_BY8 = 0xd, | ||
| 6212 | DBG_BLOCK_ID_TCP16_BY8 = 0xe, | ||
| 6213 | DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, | ||
| 6214 | DBG_BLOCK_ID_TCC_BY8 = 0x10, | ||
| 6215 | DBG_BLOCK_ID_SPS_BY8 = 0x11, | ||
| 6216 | DBG_BLOCK_ID_TA_BY8 = 0x12, | ||
| 6217 | DBG_BLOCK_ID_TA08_BY8 = 0x13, | ||
| 6218 | DBG_BLOCK_ID_TA10_BY8 = 0x14, | ||
| 6219 | DBG_BLOCK_ID_TA18_BY8 = 0x15, | ||
| 6220 | DBG_BLOCK_ID_TD_BY8 = 0x16, | ||
| 6221 | DBG_BLOCK_ID_TD08_BY8 = 0x17, | ||
| 6222 | DBG_BLOCK_ID_TD10_BY8 = 0x18, | ||
| 6223 | DBG_BLOCK_ID_TD18_BY8 = 0x19, | ||
| 6224 | DBG_BLOCK_ID_LDS_BY8 = 0x1a, | ||
| 6225 | DBG_BLOCK_ID_LDS08_BY8 = 0x1b, | ||
| 6226 | DBG_BLOCK_ID_LDS10_BY8 = 0x1c, | ||
| 6227 | DBG_BLOCK_ID_LDS18_BY8 = 0x1d, | ||
| 6228 | } DebugBlockId_BY8; | ||
| 6229 | typedef enum DebugBlockId_BY16 { | ||
| 6230 | DBG_BLOCK_ID_RESERVED_BY16 = 0x0, | ||
| 6231 | DBG_BLOCK_ID_SDMA0_BY16 = 0x1, | ||
| 6232 | DBG_BLOCK_ID_SXM_BY16 = 0x2, | ||
| 6233 | DBG_BLOCK_ID_MCD_BY16 = 0x3, | ||
| 6234 | DBG_BLOCK_ID_SQB_BY16 = 0x4, | ||
| 6235 | DBG_BLOCK_ID_SXS_BY16 = 0x5, | ||
| 6236 | DBG_BLOCK_ID_TCP_BY16 = 0x6, | ||
| 6237 | DBG_BLOCK_ID_TCP16_BY16 = 0x7, | ||
| 6238 | DBG_BLOCK_ID_TCC_BY16 = 0x8, | ||
| 6239 | DBG_BLOCK_ID_TA_BY16 = 0x9, | ||
| 6240 | DBG_BLOCK_ID_TA10_BY16 = 0xa, | ||
| 6241 | DBG_BLOCK_ID_TD_BY16 = 0xb, | ||
| 6242 | DBG_BLOCK_ID_TD10_BY16 = 0xc, | ||
| 6243 | DBG_BLOCK_ID_LDS_BY16 = 0xd, | ||
| 6244 | DBG_BLOCK_ID_LDS10_BY16 = 0xe, | ||
| 6245 | } DebugBlockId_BY16; | ||
| 6246 | typedef enum SurfaceEndian { | ||
| 6247 | ENDIAN_NONE = 0x0, | ||
| 6248 | ENDIAN_8IN16 = 0x1, | ||
| 6249 | ENDIAN_8IN32 = 0x2, | ||
| 6250 | ENDIAN_8IN64 = 0x3, | ||
| 6251 | } SurfaceEndian; | ||
| 6252 | typedef enum ArrayMode { | ||
| 6253 | ARRAY_LINEAR_GENERAL = 0x0, | ||
| 6254 | ARRAY_LINEAR_ALIGNED = 0x1, | ||
| 6255 | ARRAY_1D_TILED_THIN1 = 0x2, | ||
| 6256 | ARRAY_1D_TILED_THICK = 0x3, | ||
| 6257 | ARRAY_2D_TILED_THIN1 = 0x4, | ||
| 6258 | ARRAY_PRT_TILED_THIN1 = 0x5, | ||
| 6259 | ARRAY_PRT_2D_TILED_THIN1 = 0x6, | ||
| 6260 | ARRAY_2D_TILED_THICK = 0x7, | ||
| 6261 | ARRAY_2D_TILED_XTHICK = 0x8, | ||
| 6262 | ARRAY_PRT_TILED_THICK = 0x9, | ||
| 6263 | ARRAY_PRT_2D_TILED_THICK = 0xa, | ||
| 6264 | ARRAY_PRT_3D_TILED_THIN1 = 0xb, | ||
| 6265 | ARRAY_3D_TILED_THIN1 = 0xc, | ||
| 6266 | ARRAY_3D_TILED_THICK = 0xd, | ||
| 6267 | ARRAY_3D_TILED_XTHICK = 0xe, | ||
| 6268 | ARRAY_PRT_3D_TILED_THICK = 0xf, | ||
| 6269 | } ArrayMode; | ||
| 6270 | typedef enum PipeTiling { | ||
| 6271 | CONFIG_1_PIPE = 0x0, | ||
| 6272 | CONFIG_2_PIPE = 0x1, | ||
| 6273 | CONFIG_4_PIPE = 0x2, | ||
| 6274 | CONFIG_8_PIPE = 0x3, | ||
| 6275 | } PipeTiling; | ||
| 6276 | typedef enum BankTiling { | ||
| 6277 | CONFIG_4_BANK = 0x0, | ||
| 6278 | CONFIG_8_BANK = 0x1, | ||
| 6279 | } BankTiling; | ||
| 6280 | typedef enum GroupInterleave { | ||
| 6281 | CONFIG_256B_GROUP = 0x0, | ||
| 6282 | CONFIG_512B_GROUP = 0x1, | ||
| 6283 | } GroupInterleave; | ||
| 6284 | typedef enum RowTiling { | ||
| 6285 | CONFIG_1KB_ROW = 0x0, | ||
| 6286 | CONFIG_2KB_ROW = 0x1, | ||
| 6287 | CONFIG_4KB_ROW = 0x2, | ||
| 6288 | CONFIG_8KB_ROW = 0x3, | ||
| 6289 | CONFIG_1KB_ROW_OPT = 0x4, | ||
| 6290 | CONFIG_2KB_ROW_OPT = 0x5, | ||
| 6291 | CONFIG_4KB_ROW_OPT = 0x6, | ||
| 6292 | CONFIG_8KB_ROW_OPT = 0x7, | ||
| 6293 | } RowTiling; | ||
| 6294 | typedef enum BankSwapBytes { | ||
| 6295 | CONFIG_128B_SWAPS = 0x0, | ||
| 6296 | CONFIG_256B_SWAPS = 0x1, | ||
| 6297 | CONFIG_512B_SWAPS = 0x2, | ||
| 6298 | CONFIG_1KB_SWAPS = 0x3, | ||
| 6299 | } BankSwapBytes; | ||
| 6300 | typedef enum SampleSplitBytes { | ||
| 6301 | CONFIG_1KB_SPLIT = 0x0, | ||
| 6302 | CONFIG_2KB_SPLIT = 0x1, | ||
| 6303 | CONFIG_4KB_SPLIT = 0x2, | ||
| 6304 | CONFIG_8KB_SPLIT = 0x3, | ||
| 6305 | } SampleSplitBytes; | ||
| 6306 | typedef enum NumPipes { | ||
| 6307 | ADDR_CONFIG_1_PIPE = 0x0, | ||
| 6308 | ADDR_CONFIG_2_PIPE = 0x1, | ||
| 6309 | ADDR_CONFIG_4_PIPE = 0x2, | ||
| 6310 | ADDR_CONFIG_8_PIPE = 0x3, | ||
| 6311 | } NumPipes; | ||
| 6312 | typedef enum PipeInterleaveSize { | ||
| 6313 | ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, | ||
| 6314 | ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, | ||
| 6315 | } PipeInterleaveSize; | ||
| 6316 | typedef enum BankInterleaveSize { | ||
| 6317 | ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, | ||
| 6318 | ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, | ||
| 6319 | ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, | ||
| 6320 | ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, | ||
| 6321 | } BankInterleaveSize; | ||
| 6322 | typedef enum NumShaderEngines { | ||
| 6323 | ADDR_CONFIG_1_SHADER_ENGINE = 0x0, | ||
| 6324 | ADDR_CONFIG_2_SHADER_ENGINE = 0x1, | ||
| 6325 | } NumShaderEngines; | ||
| 6326 | typedef enum ShaderEngineTileSize { | ||
| 6327 | ADDR_CONFIG_SE_TILE_16 = 0x0, | ||
| 6328 | ADDR_CONFIG_SE_TILE_32 = 0x1, | ||
| 6329 | } ShaderEngineTileSize; | ||
| 6330 | typedef enum NumGPUs { | ||
| 6331 | ADDR_CONFIG_1_GPU = 0x0, | ||
| 6332 | ADDR_CONFIG_2_GPU = 0x1, | ||
| 6333 | ADDR_CONFIG_4_GPU = 0x2, | ||
| 6334 | } NumGPUs; | ||
| 6335 | typedef enum MultiGPUTileSize { | ||
| 6336 | ADDR_CONFIG_GPU_TILE_16 = 0x0, | ||
| 6337 | ADDR_CONFIG_GPU_TILE_32 = 0x1, | ||
| 6338 | ADDR_CONFIG_GPU_TILE_64 = 0x2, | ||
| 6339 | ADDR_CONFIG_GPU_TILE_128 = 0x3, | ||
| 6340 | } MultiGPUTileSize; | ||
| 6341 | typedef enum RowSize { | ||
| 6342 | ADDR_CONFIG_1KB_ROW = 0x0, | ||
| 6343 | ADDR_CONFIG_2KB_ROW = 0x1, | ||
| 6344 | ADDR_CONFIG_4KB_ROW = 0x2, | ||
| 6345 | } RowSize; | ||
| 6346 | typedef enum NumLowerPipes { | ||
| 6347 | ADDR_CONFIG_1_LOWER_PIPES = 0x0, | ||
| 6348 | ADDR_CONFIG_2_LOWER_PIPES = 0x1, | ||
| 6349 | } NumLowerPipes; | ||
| 6350 | typedef enum ColorTransform { | ||
| 6351 | DCC_CT_AUTO = 0x0, | ||
| 6352 | DCC_CT_NONE = 0x1, | ||
| 6353 | ABGR_TO_A_BG_G_RB = 0x2, | ||
| 6354 | BGRA_TO_BG_G_RB_A = 0x3, | ||
| 6355 | } ColorTransform; | ||
| 6356 | typedef enum CompareRef { | ||
| 6357 | REF_NEVER = 0x0, | ||
| 6358 | REF_LESS = 0x1, | ||
| 6359 | REF_EQUAL = 0x2, | ||
| 6360 | REF_LEQUAL = 0x3, | ||
| 6361 | REF_GREATER = 0x4, | ||
| 6362 | REF_NOTEQUAL = 0x5, | ||
| 6363 | REF_GEQUAL = 0x6, | ||
| 6364 | REF_ALWAYS = 0x7, | ||
| 6365 | } CompareRef; | ||
| 6366 | typedef enum ReadSize { | ||
| 6367 | READ_256_BITS = 0x0, | ||
| 6368 | READ_512_BITS = 0x1, | ||
| 6369 | } ReadSize; | ||
| 6370 | typedef enum DepthFormat { | ||
| 6371 | DEPTH_INVALID = 0x0, | ||
| 6372 | DEPTH_16 = 0x1, | ||
| 6373 | DEPTH_X8_24 = 0x2, | ||
| 6374 | DEPTH_8_24 = 0x3, | ||
| 6375 | DEPTH_X8_24_FLOAT = 0x4, | ||
| 6376 | DEPTH_8_24_FLOAT = 0x5, | ||
| 6377 | DEPTH_32_FLOAT = 0x6, | ||
| 6378 | DEPTH_X24_8_32_FLOAT = 0x7, | ||
| 6379 | } DepthFormat; | ||
| 6380 | typedef enum ZFormat { | ||
| 6381 | Z_INVALID = 0x0, | ||
| 6382 | Z_16 = 0x1, | ||
| 6383 | Z_24 = 0x2, | ||
| 6384 | Z_32_FLOAT = 0x3, | ||
| 6385 | } ZFormat; | ||
| 6386 | typedef enum StencilFormat { | ||
| 6387 | STENCIL_INVALID = 0x0, | ||
| 6388 | STENCIL_8 = 0x1, | ||
| 6389 | } StencilFormat; | ||
| 6390 | typedef enum CmaskMode { | ||
| 6391 | CMASK_CLEAR_NONE = 0x0, | ||
| 6392 | CMASK_CLEAR_ONE = 0x1, | ||
| 6393 | CMASK_CLEAR_ALL = 0x2, | ||
| 6394 | CMASK_ANY_EXPANDED = 0x3, | ||
| 6395 | CMASK_ALPHA0_FRAG1 = 0x4, | ||
| 6396 | CMASK_ALPHA0_FRAG2 = 0x5, | ||
| 6397 | CMASK_ALPHA0_FRAG4 = 0x6, | ||
| 6398 | CMASK_ALPHA0_FRAGS = 0x7, | ||
| 6399 | CMASK_ALPHA1_FRAG1 = 0x8, | ||
| 6400 | CMASK_ALPHA1_FRAG2 = 0x9, | ||
| 6401 | CMASK_ALPHA1_FRAG4 = 0xa, | ||
| 6402 | CMASK_ALPHA1_FRAGS = 0xb, | ||
| 6403 | CMASK_ALPHAX_FRAG1 = 0xc, | ||
| 6404 | CMASK_ALPHAX_FRAG2 = 0xd, | ||
| 6405 | CMASK_ALPHAX_FRAG4 = 0xe, | ||
| 6406 | CMASK_ALPHAX_FRAGS = 0xf, | ||
| 6407 | } CmaskMode; | ||
| 6408 | typedef enum QuadExportFormat { | ||
| 6409 | EXPORT_UNUSED = 0x0, | ||
| 6410 | EXPORT_32_R = 0x1, | ||
| 6411 | EXPORT_32_GR = 0x2, | ||
| 6412 | EXPORT_32_AR = 0x3, | ||
| 6413 | EXPORT_FP16_ABGR = 0x4, | ||
| 6414 | EXPORT_UNSIGNED16_ABGR = 0x5, | ||
| 6415 | EXPORT_SIGNED16_ABGR = 0x6, | ||
| 6416 | EXPORT_32_ABGR = 0x7, | ||
| 6417 | EXPORT_32BPP_8PIX = 0x8, | ||
| 6418 | EXPORT_16_16_UNSIGNED_8PIX = 0x9, | ||
| 6419 | EXPORT_16_16_SIGNED_8PIX = 0xa, | ||
| 6420 | EXPORT_16_16_FLOAT_8PIX = 0xb, | ||
| 6421 | } QuadExportFormat; | ||
| 6422 | typedef enum QuadExportFormatOld { | ||
| 6423 | EXPORT_4P_32BPC_ABGR = 0x0, | ||
| 6424 | EXPORT_4P_16BPC_ABGR = 0x1, | ||
| 6425 | EXPORT_4P_32BPC_GR = 0x2, | ||
| 6426 | EXPORT_4P_32BPC_AR = 0x3, | ||
| 6427 | EXPORT_2P_32BPC_ABGR = 0x4, | ||
| 6428 | EXPORT_8P_32BPC_R = 0x5, | ||
| 6429 | } QuadExportFormatOld; | ||
| 6430 | typedef enum ColorFormat { | ||
| 6431 | COLOR_INVALID = 0x0, | ||
| 6432 | COLOR_8 = 0x1, | ||
| 6433 | COLOR_16 = 0x2, | ||
| 6434 | COLOR_8_8 = 0x3, | ||
| 6435 | COLOR_32 = 0x4, | ||
| 6436 | COLOR_16_16 = 0x5, | ||
| 6437 | COLOR_10_11_11 = 0x6, | ||
| 6438 | COLOR_11_11_10 = 0x7, | ||
| 6439 | COLOR_10_10_10_2 = 0x8, | ||
| 6440 | COLOR_2_10_10_10 = 0x9, | ||
| 6441 | COLOR_8_8_8_8 = 0xa, | ||
| 6442 | COLOR_32_32 = 0xb, | ||
| 6443 | COLOR_16_16_16_16 = 0xc, | ||
| 6444 | COLOR_RESERVED_13 = 0xd, | ||
| 6445 | COLOR_32_32_32_32 = 0xe, | ||
| 6446 | COLOR_RESERVED_15 = 0xf, | ||
| 6447 | COLOR_5_6_5 = 0x10, | ||
| 6448 | COLOR_1_5_5_5 = 0x11, | ||
| 6449 | COLOR_5_5_5_1 = 0x12, | ||
| 6450 | COLOR_4_4_4_4 = 0x13, | ||
| 6451 | COLOR_8_24 = 0x14, | ||
| 6452 | COLOR_24_8 = 0x15, | ||
| 6453 | COLOR_X24_8_32_FLOAT = 0x16, | ||
| 6454 | COLOR_RESERVED_23 = 0x17, | ||
| 6455 | COLOR_RESERVED_24 = 0x18, | ||
| 6456 | COLOR_RESERVED_25 = 0x19, | ||
| 6457 | COLOR_RESERVED_26 = 0x1a, | ||
| 6458 | COLOR_RESERVED_27 = 0x1b, | ||
| 6459 | COLOR_RESERVED_28 = 0x1c, | ||
| 6460 | COLOR_RESERVED_29 = 0x1d, | ||
| 6461 | COLOR_RESERVED_30 = 0x1e, | ||
| 6462 | } ColorFormat; | ||
| 6463 | typedef enum SurfaceFormat { | ||
| 6464 | FMT_INVALID = 0x0, | ||
| 6465 | FMT_8 = 0x1, | ||
| 6466 | FMT_16 = 0x2, | ||
| 6467 | FMT_8_8 = 0x3, | ||
| 6468 | FMT_32 = 0x4, | ||
| 6469 | FMT_16_16 = 0x5, | ||
| 6470 | FMT_10_11_11 = 0x6, | ||
| 6471 | FMT_11_11_10 = 0x7, | ||
| 6472 | FMT_10_10_10_2 = 0x8, | ||
| 6473 | FMT_2_10_10_10 = 0x9, | ||
| 6474 | FMT_8_8_8_8 = 0xa, | ||
| 6475 | FMT_32_32 = 0xb, | ||
| 6476 | FMT_16_16_16_16 = 0xc, | ||
| 6477 | FMT_32_32_32 = 0xd, | ||
| 6478 | FMT_32_32_32_32 = 0xe, | ||
| 6479 | FMT_RESERVED_4 = 0xf, | ||
| 6480 | FMT_5_6_5 = 0x10, | ||
| 6481 | FMT_1_5_5_5 = 0x11, | ||
| 6482 | FMT_5_5_5_1 = 0x12, | ||
| 6483 | FMT_4_4_4_4 = 0x13, | ||
| 6484 | FMT_8_24 = 0x14, | ||
| 6485 | FMT_24_8 = 0x15, | ||
| 6486 | FMT_X24_8_32_FLOAT = 0x16, | ||
| 6487 | FMT_RESERVED_33 = 0x17, | ||
| 6488 | FMT_11_11_10_FLOAT = 0x18, | ||
| 6489 | FMT_16_FLOAT = 0x19, | ||
| 6490 | FMT_32_FLOAT = 0x1a, | ||
| 6491 | FMT_16_16_FLOAT = 0x1b, | ||
| 6492 | FMT_8_24_FLOAT = 0x1c, | ||
| 6493 | FMT_24_8_FLOAT = 0x1d, | ||
| 6494 | FMT_32_32_FLOAT = 0x1e, | ||
| 6495 | FMT_10_11_11_FLOAT = 0x1f, | ||
| 6496 | FMT_16_16_16_16_FLOAT = 0x20, | ||
| 6497 | FMT_3_3_2 = 0x21, | ||
| 6498 | FMT_6_5_5 = 0x22, | ||
| 6499 | FMT_32_32_32_32_FLOAT = 0x23, | ||
| 6500 | FMT_RESERVED_36 = 0x24, | ||
| 6501 | FMT_1 = 0x25, | ||
| 6502 | FMT_1_REVERSED = 0x26, | ||
| 6503 | FMT_GB_GR = 0x27, | ||
| 6504 | FMT_BG_RG = 0x28, | ||
| 6505 | FMT_32_AS_8 = 0x29, | ||
| 6506 | FMT_32_AS_8_8 = 0x2a, | ||
| 6507 | FMT_5_9_9_9_SHAREDEXP = 0x2b, | ||
| 6508 | FMT_8_8_8 = 0x2c, | ||
| 6509 | FMT_16_16_16 = 0x2d, | ||
| 6510 | FMT_16_16_16_FLOAT = 0x2e, | ||
| 6511 | FMT_4_4 = 0x2f, | ||
| 6512 | FMT_32_32_32_FLOAT = 0x30, | ||
| 6513 | FMT_BC1 = 0x31, | ||
| 6514 | FMT_BC2 = 0x32, | ||
| 6515 | FMT_BC3 = 0x33, | ||
| 6516 | FMT_BC4 = 0x34, | ||
| 6517 | FMT_BC5 = 0x35, | ||
| 6518 | FMT_BC6 = 0x36, | ||
| 6519 | FMT_BC7 = 0x37, | ||
| 6520 | FMT_32_AS_32_32_32_32 = 0x38, | ||
| 6521 | FMT_APC3 = 0x39, | ||
| 6522 | FMT_APC4 = 0x3a, | ||
| 6523 | FMT_APC5 = 0x3b, | ||
| 6524 | FMT_APC6 = 0x3c, | ||
| 6525 | FMT_APC7 = 0x3d, | ||
| 6526 | FMT_CTX1 = 0x3e, | ||
| 6527 | FMT_RESERVED_63 = 0x3f, | ||
| 6528 | } SurfaceFormat; | ||
| 6529 | typedef enum BUF_DATA_FORMAT { | ||
| 6530 | BUF_DATA_FORMAT_INVALID = 0x0, | ||
| 6531 | BUF_DATA_FORMAT_8 = 0x1, | ||
| 6532 | BUF_DATA_FORMAT_16 = 0x2, | ||
| 6533 | BUF_DATA_FORMAT_8_8 = 0x3, | ||
| 6534 | BUF_DATA_FORMAT_32 = 0x4, | ||
| 6535 | BUF_DATA_FORMAT_16_16 = 0x5, | ||
| 6536 | BUF_DATA_FORMAT_10_11_11 = 0x6, | ||
| 6537 | BUF_DATA_FORMAT_11_11_10 = 0x7, | ||
| 6538 | BUF_DATA_FORMAT_10_10_10_2 = 0x8, | ||
| 6539 | BUF_DATA_FORMAT_2_10_10_10 = 0x9, | ||
| 6540 | BUF_DATA_FORMAT_8_8_8_8 = 0xa, | ||
| 6541 | BUF_DATA_FORMAT_32_32 = 0xb, | ||
| 6542 | BUF_DATA_FORMAT_16_16_16_16 = 0xc, | ||
| 6543 | BUF_DATA_FORMAT_32_32_32 = 0xd, | ||
| 6544 | BUF_DATA_FORMAT_32_32_32_32 = 0xe, | ||
| 6545 | BUF_DATA_FORMAT_RESERVED_15 = 0xf, | ||
| 6546 | } BUF_DATA_FORMAT; | ||
| 6547 | typedef enum IMG_DATA_FORMAT { | ||
| 6548 | IMG_DATA_FORMAT_INVALID = 0x0, | ||
| 6549 | IMG_DATA_FORMAT_8 = 0x1, | ||
| 6550 | IMG_DATA_FORMAT_16 = 0x2, | ||
| 6551 | IMG_DATA_FORMAT_8_8 = 0x3, | ||
| 6552 | IMG_DATA_FORMAT_32 = 0x4, | ||
| 6553 | IMG_DATA_FORMAT_16_16 = 0x5, | ||
| 6554 | IMG_DATA_FORMAT_10_11_11 = 0x6, | ||
| 6555 | IMG_DATA_FORMAT_11_11_10 = 0x7, | ||
| 6556 | IMG_DATA_FORMAT_10_10_10_2 = 0x8, | ||
| 6557 | IMG_DATA_FORMAT_2_10_10_10 = 0x9, | ||
| 6558 | IMG_DATA_FORMAT_8_8_8_8 = 0xa, | ||
| 6559 | IMG_DATA_FORMAT_32_32 = 0xb, | ||
| 6560 | IMG_DATA_FORMAT_16_16_16_16 = 0xc, | ||
| 6561 | IMG_DATA_FORMAT_32_32_32 = 0xd, | ||
| 6562 | IMG_DATA_FORMAT_32_32_32_32 = 0xe, | ||
| 6563 | IMG_DATA_FORMAT_16_AS_32_32 = 0xf, | ||
| 6564 | IMG_DATA_FORMAT_5_6_5 = 0x10, | ||
| 6565 | IMG_DATA_FORMAT_1_5_5_5 = 0x11, | ||
| 6566 | IMG_DATA_FORMAT_5_5_5_1 = 0x12, | ||
| 6567 | IMG_DATA_FORMAT_4_4_4_4 = 0x13, | ||
| 6568 | IMG_DATA_FORMAT_8_24 = 0x14, | ||
| 6569 | IMG_DATA_FORMAT_24_8 = 0x15, | ||
| 6570 | IMG_DATA_FORMAT_X24_8_32 = 0x16, | ||
| 6571 | IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x17, | ||
| 6572 | IMG_DATA_FORMAT_ETC2_RGB = 0x18, | ||
| 6573 | IMG_DATA_FORMAT_ETC2_RGBA = 0x19, | ||
| 6574 | IMG_DATA_FORMAT_ETC2_R = 0x1a, | ||
| 6575 | IMG_DATA_FORMAT_ETC2_RG = 0x1b, | ||
| 6576 | IMG_DATA_FORMAT_ETC2_RGBA1 = 0x1c, | ||
| 6577 | IMG_DATA_FORMAT_RESERVED_29 = 0x1d, | ||
| 6578 | IMG_DATA_FORMAT_RESERVED_30 = 0x1e, | ||
| 6579 | IMG_DATA_FORMAT_RESERVED_31 = 0x1f, | ||
| 6580 | IMG_DATA_FORMAT_GB_GR = 0x20, | ||
| 6581 | IMG_DATA_FORMAT_BG_RG = 0x21, | ||
| 6582 | IMG_DATA_FORMAT_5_9_9_9 = 0x22, | ||
| 6583 | IMG_DATA_FORMAT_BC1 = 0x23, | ||
| 6584 | IMG_DATA_FORMAT_BC2 = 0x24, | ||
| 6585 | IMG_DATA_FORMAT_BC3 = 0x25, | ||
| 6586 | IMG_DATA_FORMAT_BC4 = 0x26, | ||
| 6587 | IMG_DATA_FORMAT_BC5 = 0x27, | ||
| 6588 | IMG_DATA_FORMAT_BC6 = 0x28, | ||
| 6589 | IMG_DATA_FORMAT_BC7 = 0x29, | ||
| 6590 | IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x2a, | ||
| 6591 | IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x2b, | ||
| 6592 | IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, | ||
| 6593 | IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, | ||
| 6594 | IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, | ||
| 6595 | IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, | ||
| 6596 | IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, | ||
| 6597 | IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, | ||
| 6598 | IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, | ||
| 6599 | IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, | ||
| 6600 | IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, | ||
| 6601 | IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, | ||
| 6602 | IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, | ||
| 6603 | IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, | ||
| 6604 | IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, | ||
| 6605 | IMG_DATA_FORMAT_4_4 = 0x39, | ||
| 6606 | IMG_DATA_FORMAT_6_5_5 = 0x3a, | ||
| 6607 | IMG_DATA_FORMAT_1 = 0x3b, | ||
| 6608 | IMG_DATA_FORMAT_1_REVERSED = 0x3c, | ||
| 6609 | IMG_DATA_FORMAT_8_AS_32 = 0x3d, | ||
| 6610 | IMG_DATA_FORMAT_8_AS_32_32 = 0x3e, | ||
| 6611 | IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, | ||
| 6612 | } IMG_DATA_FORMAT; | ||
| 6613 | typedef enum BUF_NUM_FORMAT { | ||
| 6614 | BUF_NUM_FORMAT_UNORM = 0x0, | ||
| 6615 | BUF_NUM_FORMAT_SNORM = 0x1, | ||
| 6616 | BUF_NUM_FORMAT_USCALED = 0x2, | ||
| 6617 | BUF_NUM_FORMAT_SSCALED = 0x3, | ||
| 6618 | BUF_NUM_FORMAT_UINT = 0x4, | ||
| 6619 | BUF_NUM_FORMAT_SINT = 0x5, | ||
| 6620 | BUF_NUM_FORMAT_RESERVED_6 = 0x6, | ||
| 6621 | BUF_NUM_FORMAT_FLOAT = 0x7, | ||
| 6622 | } BUF_NUM_FORMAT; | ||
| 6623 | typedef enum IMG_NUM_FORMAT { | ||
| 6624 | IMG_NUM_FORMAT_UNORM = 0x0, | ||
| 6625 | IMG_NUM_FORMAT_SNORM = 0x1, | ||
| 6626 | IMG_NUM_FORMAT_USCALED = 0x2, | ||
| 6627 | IMG_NUM_FORMAT_SSCALED = 0x3, | ||
| 6628 | IMG_NUM_FORMAT_UINT = 0x4, | ||
| 6629 | IMG_NUM_FORMAT_SINT = 0x5, | ||
| 6630 | IMG_NUM_FORMAT_RESERVED_6 = 0x6, | ||
| 6631 | IMG_NUM_FORMAT_FLOAT = 0x7, | ||
| 6632 | IMG_NUM_FORMAT_RESERVED_8 = 0x8, | ||
| 6633 | IMG_NUM_FORMAT_SRGB = 0x9, | ||
| 6634 | IMG_NUM_FORMAT_RESERVED_10 = 0xa, | ||
| 6635 | IMG_NUM_FORMAT_RESERVED_11 = 0xb, | ||
| 6636 | IMG_NUM_FORMAT_RESERVED_12 = 0xc, | ||
| 6637 | IMG_NUM_FORMAT_RESERVED_13 = 0xd, | ||
| 6638 | IMG_NUM_FORMAT_RESERVED_14 = 0xe, | ||
| 6639 | IMG_NUM_FORMAT_RESERVED_15 = 0xf, | ||
| 6640 | } IMG_NUM_FORMAT; | ||
| 6641 | typedef enum TileType { | ||
| 6642 | ARRAY_COLOR_TILE = 0x0, | ||
| 6643 | ARRAY_DEPTH_TILE = 0x1, | ||
| 6644 | } TileType; | ||
| 6645 | typedef enum NonDispTilingOrder { | ||
| 6646 | ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, | ||
| 6647 | ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, | ||
| 6648 | } NonDispTilingOrder; | ||
| 6649 | typedef enum MicroTileMode { | ||
| 6650 | ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, | ||
| 6651 | ADDR_SURF_THIN_MICRO_TILING = 0x1, | ||
| 6652 | ADDR_SURF_DEPTH_MICRO_TILING = 0x2, | ||
| 6653 | ADDR_SURF_ROTATED_MICRO_TILING = 0x3, | ||
| 6654 | ADDR_SURF_THICK_MICRO_TILING = 0x4, | ||
| 6655 | } MicroTileMode; | ||
| 6656 | typedef enum TileSplit { | ||
| 6657 | ADDR_SURF_TILE_SPLIT_64B = 0x0, | ||
| 6658 | ADDR_SURF_TILE_SPLIT_128B = 0x1, | ||
| 6659 | ADDR_SURF_TILE_SPLIT_256B = 0x2, | ||
| 6660 | ADDR_SURF_TILE_SPLIT_512B = 0x3, | ||
| 6661 | ADDR_SURF_TILE_SPLIT_1KB = 0x4, | ||
| 6662 | ADDR_SURF_TILE_SPLIT_2KB = 0x5, | ||
| 6663 | ADDR_SURF_TILE_SPLIT_4KB = 0x6, | ||
| 6664 | } TileSplit; | ||
| 6665 | typedef enum SampleSplit { | ||
| 6666 | ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, | ||
| 6667 | ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, | ||
| 6668 | ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, | ||
| 6669 | ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, | ||
| 6670 | } SampleSplit; | ||
| 6671 | typedef enum PipeConfig { | ||
| 6672 | ADDR_SURF_P2 = 0x0, | ||
| 6673 | ADDR_SURF_P2_RESERVED0 = 0x1, | ||
| 6674 | ADDR_SURF_P2_RESERVED1 = 0x2, | ||
| 6675 | ADDR_SURF_P2_RESERVED2 = 0x3, | ||
| 6676 | ADDR_SURF_P4_8x16 = 0x4, | ||
| 6677 | ADDR_SURF_P4_16x16 = 0x5, | ||
| 6678 | ADDR_SURF_P4_16x32 = 0x6, | ||
| 6679 | ADDR_SURF_P4_32x32 = 0x7, | ||
| 6680 | ADDR_SURF_P8_16x16_8x16 = 0x8, | ||
| 6681 | ADDR_SURF_P8_16x32_8x16 = 0x9, | ||
| 6682 | ADDR_SURF_P8_32x32_8x16 = 0xa, | ||
| 6683 | ADDR_SURF_P8_16x32_16x16 = 0xb, | ||
| 6684 | ADDR_SURF_P8_32x32_16x16 = 0xc, | ||
| 6685 | ADDR_SURF_P8_32x32_16x32 = 0xd, | ||
| 6686 | ADDR_SURF_P8_32x64_32x32 = 0xe, | ||
| 6687 | ADDR_SURF_P8_RESERVED0 = 0xf, | ||
| 6688 | ADDR_SURF_P16_32x32_8x16 = 0x10, | ||
| 6689 | ADDR_SURF_P16_32x32_16x16 = 0x11, | ||
| 6690 | } PipeConfig; | ||
| 6691 | typedef enum NumBanks { | ||
| 6692 | ADDR_SURF_2_BANK = 0x0, | ||
| 6693 | ADDR_SURF_4_BANK = 0x1, | ||
| 6694 | ADDR_SURF_8_BANK = 0x2, | ||
| 6695 | ADDR_SURF_16_BANK = 0x3, | ||
| 6696 | } NumBanks; | ||
| 6697 | typedef enum BankWidth { | ||
| 6698 | ADDR_SURF_BANK_WIDTH_1 = 0x0, | ||
| 6699 | ADDR_SURF_BANK_WIDTH_2 = 0x1, | ||
| 6700 | ADDR_SURF_BANK_WIDTH_4 = 0x2, | ||
| 6701 | ADDR_SURF_BANK_WIDTH_8 = 0x3, | ||
| 6702 | } BankWidth; | ||
| 6703 | typedef enum BankHeight { | ||
| 6704 | ADDR_SURF_BANK_HEIGHT_1 = 0x0, | ||
| 6705 | ADDR_SURF_BANK_HEIGHT_2 = 0x1, | ||
| 6706 | ADDR_SURF_BANK_HEIGHT_4 = 0x2, | ||
| 6707 | ADDR_SURF_BANK_HEIGHT_8 = 0x3, | ||
| 6708 | } BankHeight; | ||
| 6709 | typedef enum BankWidthHeight { | ||
| 6710 | ADDR_SURF_BANK_WH_1 = 0x0, | ||
| 6711 | ADDR_SURF_BANK_WH_2 = 0x1, | ||
| 6712 | ADDR_SURF_BANK_WH_4 = 0x2, | ||
| 6713 | ADDR_SURF_BANK_WH_8 = 0x3, | ||
| 6714 | } BankWidthHeight; | ||
| 6715 | typedef enum MacroTileAspect { | ||
| 6716 | ADDR_SURF_MACRO_ASPECT_1 = 0x0, | ||
| 6717 | ADDR_SURF_MACRO_ASPECT_2 = 0x1, | ||
| 6718 | ADDR_SURF_MACRO_ASPECT_4 = 0x2, | ||
| 6719 | ADDR_SURF_MACRO_ASPECT_8 = 0x3, | ||
| 6720 | } MacroTileAspect; | ||
| 6721 | typedef enum GATCL1RequestType { | ||
| 6722 | GATCL1_TYPE_NORMAL = 0x0, | ||
| 6723 | GATCL1_TYPE_SHOOTDOWN = 0x1, | ||
| 6724 | GATCL1_TYPE_BYPASS = 0x2, | ||
| 6725 | } GATCL1RequestType; | ||
| 6726 | typedef enum TCC_CACHE_POLICIES { | ||
| 6727 | TCC_CACHE_POLICY_LRU = 0x0, | ||
| 6728 | TCC_CACHE_POLICY_STREAM = 0x1, | ||
| 6729 | } TCC_CACHE_POLICIES; | ||
| 6730 | typedef enum MTYPE { | ||
| 6731 | MTYPE_NC_NV = 0x0, | ||
| 6732 | MTYPE_NC = 0x1, | ||
| 6733 | MTYPE_CC = 0x2, | ||
| 6734 | MTYPE_UC = 0x3, | ||
| 6735 | } MTYPE; | ||
| 6736 | typedef enum PERFMON_COUNTER_MODE { | ||
| 6737 | PERFMON_COUNTER_MODE_ACCUM = 0x0, | ||
| 6738 | PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, | ||
| 6739 | PERFMON_COUNTER_MODE_MAX = 0x2, | ||
| 6740 | PERFMON_COUNTER_MODE_DIRTY = 0x3, | ||
| 6741 | PERFMON_COUNTER_MODE_SAMPLE = 0x4, | ||
| 6742 | PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, | ||
| 6743 | PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, | ||
| 6744 | PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, | ||
| 6745 | PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, | ||
| 6746 | PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, | ||
| 6747 | PERFMON_COUNTER_MODE_RESERVED = 0xf, | ||
| 6748 | } PERFMON_COUNTER_MODE; | ||
| 6749 | typedef enum PERFMON_SPM_MODE { | ||
| 6750 | PERFMON_SPM_MODE_OFF = 0x0, | ||
| 6751 | PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, | ||
| 6752 | PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, | ||
| 6753 | PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, | ||
| 6754 | PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, | ||
| 6755 | PERFMON_SPM_MODE_RESERVED_5 = 0x5, | ||
| 6756 | PERFMON_SPM_MODE_RESERVED_6 = 0x6, | ||
| 6757 | PERFMON_SPM_MODE_RESERVED_7 = 0x7, | ||
| 6758 | PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, | ||
| 6759 | PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, | ||
| 6760 | PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, | ||
| 6761 | } PERFMON_SPM_MODE; | ||
| 6762 | typedef enum SurfaceTiling { | ||
| 6763 | ARRAY_LINEAR = 0x0, | ||
| 6764 | ARRAY_TILED = 0x1, | ||
| 6765 | } SurfaceTiling; | ||
| 6766 | typedef enum SurfaceArray { | ||
| 6767 | ARRAY_1D = 0x0, | ||
| 6768 | ARRAY_2D = 0x1, | ||
| 6769 | ARRAY_3D = 0x2, | ||
| 6770 | ARRAY_3D_SLICE = 0x3, | ||
| 6771 | } SurfaceArray; | ||
| 6772 | typedef enum ColorArray { | ||
| 6773 | ARRAY_2D_ALT_COLOR = 0x0, | ||
| 6774 | ARRAY_2D_COLOR = 0x1, | ||
| 6775 | ARRAY_3D_SLICE_COLOR = 0x3, | ||
| 6776 | } ColorArray; | ||
| 6777 | typedef enum DepthArray { | ||
| 6778 | ARRAY_2D_ALT_DEPTH = 0x0, | ||
| 6779 | ARRAY_2D_DEPTH = 0x1, | ||
| 6780 | } DepthArray; | ||
| 6781 | typedef enum ENUM_NUM_SIMD_PER_CU { | ||
| 6782 | NUM_SIMD_PER_CU = 0x4, | ||
| 6783 | } ENUM_NUM_SIMD_PER_CU; | ||
| 6784 | typedef enum MEM_PWR_FORCE_CTRL { | ||
| 6785 | NO_FORCE_REQUEST = 0x0, | ||
| 6786 | FORCE_LIGHT_SLEEP_REQUEST = 0x1, | ||
| 6787 | FORCE_DEEP_SLEEP_REQUEST = 0x2, | ||
| 6788 | FORCE_SHUT_DOWN_REQUEST = 0x3, | ||
| 6789 | } MEM_PWR_FORCE_CTRL; | ||
| 6790 | typedef enum MEM_PWR_FORCE_CTRL2 { | ||
| 6791 | NO_FORCE_REQ = 0x0, | ||
| 6792 | FORCE_LIGHT_SLEEP_REQ = 0x1, | ||
| 6793 | } MEM_PWR_FORCE_CTRL2; | ||
| 6794 | typedef enum MEM_PWR_DIS_CTRL { | ||
| 6795 | ENABLE_MEM_PWR_CTRL = 0x0, | ||
| 6796 | DISABLE_MEM_PWR_CTRL = 0x1, | ||
| 6797 | } MEM_PWR_DIS_CTRL; | ||
| 6798 | typedef enum MEM_PWR_SEL_CTRL { | ||
| 6799 | DYNAMIC_SHUT_DOWN_ENABLE = 0x0, | ||
| 6800 | DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, | ||
| 6801 | DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, | ||
| 6802 | } MEM_PWR_SEL_CTRL; | ||
| 6803 | typedef enum MEM_PWR_SEL_CTRL2 { | ||
| 6804 | DYNAMIC_DEEP_SLEEP_EN = 0x0, | ||
| 6805 | DYNAMIC_LIGHT_SLEEP_EN = 0x1, | ||
| 6806 | } MEM_PWR_SEL_CTRL2; | ||
| 6807 | |||
| 6808 | #endif /* GFX_8_1_ENUM_H */ | ||
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h new file mode 100644 index 000000000000..397705a6b3a2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h | |||
| @@ -0,0 +1,21368 @@ | |||
| 1 | /* | ||
| 2 | * GFX_8_1 Register documentation | ||
| 3 | * | ||
| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included | ||
| 14 | * in all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN | ||
| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef GFX_8_1_SH_MASK_H | ||
| 25 | #define GFX_8_1_SH_MASK_H | ||
| 26 | |||
| 27 | #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff | ||
| 28 | #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 | ||
| 29 | #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff | ||
| 30 | #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 | ||
| 31 | #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff | ||
| 32 | #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 | ||
| 33 | #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff | ||
| 34 | #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 | ||
| 35 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 36 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 37 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2 | ||
| 38 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 | ||
| 39 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c | ||
| 40 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 | ||
| 41 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x1 | ||
| 42 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 | ||
| 43 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 | ||
| 44 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 | ||
| 45 | #define CB_COLOR_CONTROL__MODE_MASK 0x70 | ||
| 46 | #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 | ||
| 47 | #define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 | ||
| 48 | #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 | ||
| 49 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 50 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 51 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 52 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 53 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 54 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 55 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 56 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 57 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 58 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 59 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 60 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 61 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 62 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 63 | #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 | ||
| 64 | #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e | ||
| 65 | #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 66 | #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 67 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 68 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 69 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 70 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 71 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 72 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 73 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 74 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 75 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 76 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 77 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 78 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 79 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 80 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 81 | #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 | ||
| 82 | #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e | ||
| 83 | #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 84 | #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 85 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 86 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 87 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 88 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 89 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 90 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 91 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 92 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 93 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 94 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 95 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 96 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 97 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 98 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 99 | #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 | ||
| 100 | #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e | ||
| 101 | #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 102 | #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 103 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 104 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 105 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 106 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 107 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 108 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 109 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 110 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 111 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 112 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 113 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 114 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 115 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 116 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 117 | #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 | ||
| 118 | #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e | ||
| 119 | #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 120 | #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 121 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 122 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 123 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 124 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 125 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 126 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 127 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 128 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 129 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 130 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 131 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 132 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 133 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 134 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 135 | #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 | ||
| 136 | #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e | ||
| 137 | #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 138 | #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 139 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 140 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 141 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 142 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 143 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 144 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 145 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 146 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 147 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 148 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 149 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 150 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 151 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 152 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 153 | #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 | ||
| 154 | #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e | ||
| 155 | #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 156 | #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 157 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 158 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 159 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 160 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 161 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 162 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 163 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 164 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 165 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 166 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 167 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 168 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 169 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 170 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 171 | #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 | ||
| 172 | #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e | ||
| 173 | #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 174 | #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 175 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f | ||
| 176 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 | ||
| 177 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 | ||
| 178 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 | ||
| 179 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 | ||
| 180 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 | ||
| 181 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 | ||
| 182 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 | ||
| 183 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 | ||
| 184 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 | ||
| 185 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 | ||
| 186 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 | ||
| 187 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 | ||
| 188 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d | ||
| 189 | #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 | ||
| 190 | #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e | ||
| 191 | #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 | ||
| 192 | #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f | ||
| 193 | #define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff | ||
| 194 | #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 | ||
| 195 | #define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff | ||
| 196 | #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 | ||
| 197 | #define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff | ||
| 198 | #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 | ||
| 199 | #define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff | ||
| 200 | #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 | ||
| 201 | #define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff | ||
| 202 | #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 | ||
| 203 | #define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff | ||
| 204 | #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 | ||
| 205 | #define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff | ||
| 206 | #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 | ||
| 207 | #define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff | ||
| 208 | #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 | ||
| 209 | #define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff | ||
| 210 | #define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 211 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 212 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 213 | #define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff | ||
| 214 | #define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 215 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 216 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 217 | #define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff | ||
| 218 | #define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 219 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 220 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 221 | #define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff | ||
| 222 | #define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 223 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 224 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 225 | #define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff | ||
| 226 | #define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 227 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 228 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 229 | #define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff | ||
| 230 | #define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 231 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 232 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 233 | #define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff | ||
| 234 | #define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 235 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 236 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 237 | #define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff | ||
| 238 | #define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 | ||
| 239 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 | ||
| 240 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 | ||
| 241 | #define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 242 | #define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 243 | #define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 244 | #define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 245 | #define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 246 | #define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 247 | #define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 248 | #define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 249 | #define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 250 | #define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 251 | #define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 252 | #define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 253 | #define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 254 | #define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 255 | #define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 256 | #define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 257 | #define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff | ||
| 258 | #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 | ||
| 259 | #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 260 | #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 261 | #define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff | ||
| 262 | #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 | ||
| 263 | #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 264 | #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 265 | #define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff | ||
| 266 | #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 | ||
| 267 | #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 268 | #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 269 | #define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff | ||
| 270 | #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 | ||
| 271 | #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 272 | #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 273 | #define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff | ||
| 274 | #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 | ||
| 275 | #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 276 | #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 277 | #define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff | ||
| 278 | #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 | ||
| 279 | #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 280 | #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 281 | #define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff | ||
| 282 | #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 | ||
| 283 | #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 284 | #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 285 | #define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff | ||
| 286 | #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 | ||
| 287 | #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 288 | #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 289 | #define CB_COLOR0_INFO__ENDIAN_MASK 0x3 | ||
| 290 | #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 | ||
| 291 | #define CB_COLOR0_INFO__FORMAT_MASK 0x7c | ||
| 292 | #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 | ||
| 293 | #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 294 | #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 295 | #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 296 | #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 297 | #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 | ||
| 298 | #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb | ||
| 299 | #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 300 | #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 301 | #define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 | ||
| 302 | #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe | ||
| 303 | #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 304 | #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 305 | #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 306 | #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 307 | #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 308 | #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 309 | #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 | ||
| 310 | #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 311 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 312 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 313 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 314 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 315 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 316 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 317 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 318 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 319 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 320 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 321 | #define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 322 | #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 323 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 324 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 325 | #define CB_COLOR1_INFO__ENDIAN_MASK 0x3 | ||
| 326 | #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 | ||
| 327 | #define CB_COLOR1_INFO__FORMAT_MASK 0x7c | ||
| 328 | #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 | ||
| 329 | #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 330 | #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 331 | #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 332 | #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 333 | #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 | ||
| 334 | #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb | ||
| 335 | #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 336 | #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 337 | #define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 | ||
| 338 | #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe | ||
| 339 | #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 340 | #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 341 | #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 342 | #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 343 | #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 344 | #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 345 | #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 | ||
| 346 | #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 347 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 348 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 349 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 350 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 351 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 352 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 353 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 354 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 355 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 356 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 357 | #define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 358 | #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 359 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 360 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 361 | #define CB_COLOR2_INFO__ENDIAN_MASK 0x3 | ||
| 362 | #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 | ||
| 363 | #define CB_COLOR2_INFO__FORMAT_MASK 0x7c | ||
| 364 | #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 | ||
| 365 | #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 366 | #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 367 | #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 368 | #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 369 | #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 | ||
| 370 | #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb | ||
| 371 | #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 372 | #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 373 | #define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 | ||
| 374 | #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe | ||
| 375 | #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 376 | #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 377 | #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 378 | #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 379 | #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 380 | #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 381 | #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 | ||
| 382 | #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 383 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 384 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 385 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 386 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 387 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 388 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 389 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 390 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 391 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 392 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 393 | #define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 394 | #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 395 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 396 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 397 | #define CB_COLOR3_INFO__ENDIAN_MASK 0x3 | ||
| 398 | #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 | ||
| 399 | #define CB_COLOR3_INFO__FORMAT_MASK 0x7c | ||
| 400 | #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 | ||
| 401 | #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 402 | #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 403 | #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 404 | #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 405 | #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 | ||
| 406 | #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb | ||
| 407 | #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 408 | #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 409 | #define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 | ||
| 410 | #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe | ||
| 411 | #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 412 | #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 413 | #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 414 | #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 415 | #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 416 | #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 417 | #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 | ||
| 418 | #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 419 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 420 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 421 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 422 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 423 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 424 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 425 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 426 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 427 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 428 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 429 | #define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 430 | #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 431 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 432 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 433 | #define CB_COLOR4_INFO__ENDIAN_MASK 0x3 | ||
| 434 | #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 | ||
| 435 | #define CB_COLOR4_INFO__FORMAT_MASK 0x7c | ||
| 436 | #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 | ||
| 437 | #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 438 | #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 439 | #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 440 | #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 441 | #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 | ||
| 442 | #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb | ||
| 443 | #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 444 | #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 445 | #define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 | ||
| 446 | #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe | ||
| 447 | #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 448 | #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 449 | #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 450 | #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 451 | #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 452 | #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 453 | #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 | ||
| 454 | #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 455 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 456 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 457 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 458 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 459 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 460 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 461 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 462 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 463 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 464 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 465 | #define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 466 | #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 467 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 468 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 469 | #define CB_COLOR5_INFO__ENDIAN_MASK 0x3 | ||
| 470 | #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 | ||
| 471 | #define CB_COLOR5_INFO__FORMAT_MASK 0x7c | ||
| 472 | #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 | ||
| 473 | #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 474 | #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 475 | #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 476 | #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 477 | #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 | ||
| 478 | #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb | ||
| 479 | #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 480 | #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 481 | #define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 | ||
| 482 | #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe | ||
| 483 | #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 484 | #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 485 | #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 486 | #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 487 | #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 488 | #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 489 | #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 | ||
| 490 | #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 491 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 492 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 493 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 494 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 495 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 496 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 497 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 498 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 499 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 500 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 501 | #define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 502 | #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 503 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 504 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 505 | #define CB_COLOR6_INFO__ENDIAN_MASK 0x3 | ||
| 506 | #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 | ||
| 507 | #define CB_COLOR6_INFO__FORMAT_MASK 0x7c | ||
| 508 | #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 | ||
| 509 | #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 510 | #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 511 | #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 512 | #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 513 | #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 | ||
| 514 | #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb | ||
| 515 | #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 516 | #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 517 | #define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 | ||
| 518 | #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe | ||
| 519 | #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 520 | #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 521 | #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 522 | #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 523 | #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 524 | #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 525 | #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 | ||
| 526 | #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 527 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 528 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 529 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 530 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 531 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 532 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 533 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 534 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 535 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 536 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 537 | #define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 538 | #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 539 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 540 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 541 | #define CB_COLOR7_INFO__ENDIAN_MASK 0x3 | ||
| 542 | #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 | ||
| 543 | #define CB_COLOR7_INFO__FORMAT_MASK 0x7c | ||
| 544 | #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 | ||
| 545 | #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 | ||
| 546 | #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 | ||
| 547 | #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 | ||
| 548 | #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 | ||
| 549 | #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 | ||
| 550 | #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb | ||
| 551 | #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 | ||
| 552 | #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd | ||
| 553 | #define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 | ||
| 554 | #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe | ||
| 555 | #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 | ||
| 556 | #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf | ||
| 557 | #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 | ||
| 558 | #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 | ||
| 559 | #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 | ||
| 560 | #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 | ||
| 561 | #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 | ||
| 562 | #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 | ||
| 563 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 | ||
| 564 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 | ||
| 565 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 | ||
| 566 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 | ||
| 567 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 | ||
| 568 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 | ||
| 569 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 | ||
| 570 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a | ||
| 571 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 | ||
| 572 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b | ||
| 573 | #define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000 | ||
| 574 | #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c | ||
| 575 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 | ||
| 576 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d | ||
| 577 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 578 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 579 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 580 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 581 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 582 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 583 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 584 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 585 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 586 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 587 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 588 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 589 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 590 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 591 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 592 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 593 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 594 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 595 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 596 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 597 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 598 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 599 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 600 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 601 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 602 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 603 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 604 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 605 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 606 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 607 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 608 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 609 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 610 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 611 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 612 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 613 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 614 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 615 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 616 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 617 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 618 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 619 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 620 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 621 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 622 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 623 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 624 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 625 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 626 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 627 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 628 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 629 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 630 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 631 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 632 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 633 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 634 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 635 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 636 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 637 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 638 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 639 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 640 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 641 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 642 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 643 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 644 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 645 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 646 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 647 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 648 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 649 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 650 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 651 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 652 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 653 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 654 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 655 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 656 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 657 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 658 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 659 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 660 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 661 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f | ||
| 662 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 | ||
| 663 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 | ||
| 664 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 | ||
| 665 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 | ||
| 666 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa | ||
| 667 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 | ||
| 668 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc | ||
| 669 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 | ||
| 670 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf | ||
| 671 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 | ||
| 672 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 | ||
| 673 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 674 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 675 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 676 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 677 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 678 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 679 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 680 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 681 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 682 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 683 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 684 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 685 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 686 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 687 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 688 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 689 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 690 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 691 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 692 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 693 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 694 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 695 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 696 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 697 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 698 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 699 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 700 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 701 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 702 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 703 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 704 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 705 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 706 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 707 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 708 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 709 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 710 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 711 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 712 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 713 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 714 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 715 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 716 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 717 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 718 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 719 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 720 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 721 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 722 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 723 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 724 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 725 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 726 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 727 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 728 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 729 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 730 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 731 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 732 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 733 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 734 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 735 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 736 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 737 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 738 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 739 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 740 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 741 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 742 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 743 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 744 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 745 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 746 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 747 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 748 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 749 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 750 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 751 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 752 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 753 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 754 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 755 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 756 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 757 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 758 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 759 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 760 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 761 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 762 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 763 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 764 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 765 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 766 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 767 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 768 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 769 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 770 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 771 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 772 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 773 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 774 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 775 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 776 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 777 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 778 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 779 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 780 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 781 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 782 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 783 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 784 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 785 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 786 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 787 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 788 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 789 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 790 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 791 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 792 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 793 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 794 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 795 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 796 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 797 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 798 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 799 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 | ||
| 800 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 | ||
| 801 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 | ||
| 802 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 | ||
| 803 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc | ||
| 804 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 | ||
| 805 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 | ||
| 806 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 | ||
| 807 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 | ||
| 808 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 | ||
| 809 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 | ||
| 810 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 | ||
| 811 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 | ||
| 812 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 | ||
| 813 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 | ||
| 814 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa | ||
| 815 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 | ||
| 816 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe | ||
| 817 | #define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff | ||
| 818 | #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 | ||
| 819 | #define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff | ||
| 820 | #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 | ||
| 821 | #define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff | ||
| 822 | #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 | ||
| 823 | #define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff | ||
| 824 | #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 | ||
| 825 | #define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff | ||
| 826 | #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 | ||
| 827 | #define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff | ||
| 828 | #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 | ||
| 829 | #define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff | ||
| 830 | #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 | ||
| 831 | #define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff | ||
| 832 | #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 | ||
| 833 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 834 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 835 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 836 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 837 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 838 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 839 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 840 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 841 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 842 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 843 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 844 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 845 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 846 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 847 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff | ||
| 848 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 849 | #define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff | ||
| 850 | #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 | ||
| 851 | #define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff | ||
| 852 | #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 | ||
| 853 | #define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff | ||
| 854 | #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 | ||
| 855 | #define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff | ||
| 856 | #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 | ||
| 857 | #define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff | ||
| 858 | #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 | ||
| 859 | #define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff | ||
| 860 | #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 | ||
| 861 | #define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff | ||
| 862 | #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 | ||
| 863 | #define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff | ||
| 864 | #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 | ||
| 865 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 866 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 867 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 868 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 869 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 870 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 871 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 872 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 873 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 874 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 875 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 876 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 877 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 878 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 879 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff | ||
| 880 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 | ||
| 881 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 882 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 883 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 884 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 885 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 886 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 887 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 888 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 889 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 890 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 891 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 892 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 893 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 894 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 895 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff | ||
| 896 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 | ||
| 897 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 898 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 899 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 900 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 901 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 902 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 903 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 904 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 905 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 906 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 907 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 908 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 909 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 910 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 911 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff | ||
| 912 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 | ||
| 913 | #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 914 | #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 915 | #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 916 | #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 917 | #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 918 | #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 919 | #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 920 | #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 921 | #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 922 | #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 923 | #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 924 | #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 925 | #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 926 | #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 927 | #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff | ||
| 928 | #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 | ||
| 929 | #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf | ||
| 930 | #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 | ||
| 931 | #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 | ||
| 932 | #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 | ||
| 933 | #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 | ||
| 934 | #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 | ||
| 935 | #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 | ||
| 936 | #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc | ||
| 937 | #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 | ||
| 938 | #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 | ||
| 939 | #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 | ||
| 940 | #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 | ||
| 941 | #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 | ||
| 942 | #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 | ||
| 943 | #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 | ||
| 944 | #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c | ||
| 945 | #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf | ||
| 946 | #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 | ||
| 947 | #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 | ||
| 948 | #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 | ||
| 949 | #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 | ||
| 950 | #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 | ||
| 951 | #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 | ||
| 952 | #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc | ||
| 953 | #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 | ||
| 954 | #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 | ||
| 955 | #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 | ||
| 956 | #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 | ||
| 957 | #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 | ||
| 958 | #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 | ||
| 959 | #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 | ||
| 960 | #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c | ||
| 961 | #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf | ||
| 962 | #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 | ||
| 963 | #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 | ||
| 964 | #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 | ||
| 965 | #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 | ||
| 966 | #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc | ||
| 967 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 | ||
| 968 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 | ||
| 969 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 | ||
| 970 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 | ||
| 971 | #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 | ||
| 972 | #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 | ||
| 973 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 | ||
| 974 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 | ||
| 975 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 | ||
| 976 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 | ||
| 977 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 | ||
| 978 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 | ||
| 979 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 | ||
| 980 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 | ||
| 981 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 | ||
| 982 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 | ||
| 983 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 | ||
| 984 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 | ||
| 985 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 | ||
| 986 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a | ||
| 987 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 | ||
| 988 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b | ||
| 989 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 | ||
| 990 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c | ||
| 991 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 | ||
| 992 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d | ||
| 993 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 | ||
| 994 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e | ||
| 995 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 | ||
| 996 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f | ||
| 997 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f | ||
| 998 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 | ||
| 999 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 | ||
| 1000 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 | ||
| 1001 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 | ||
| 1002 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb | ||
| 1003 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 | ||
| 1004 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 | ||
| 1005 | #define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 | ||
| 1006 | #define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a | ||
| 1007 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff | ||
| 1008 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 | ||
| 1009 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 | ||
| 1010 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 | ||
| 1011 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 | ||
| 1012 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf | ||
| 1013 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000 | ||
| 1014 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 | ||
| 1015 | #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000 | ||
| 1016 | #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c | ||
| 1017 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 | ||
| 1018 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 | ||
| 1019 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2 | ||
| 1020 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 | ||
| 1021 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4 | ||
| 1022 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 | ||
| 1023 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8 | ||
| 1024 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 | ||
| 1025 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10 | ||
| 1026 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 | ||
| 1027 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20 | ||
| 1028 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 | ||
| 1029 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80 | ||
| 1030 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 | ||
| 1031 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100 | ||
| 1032 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 | ||
| 1033 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x200 | ||
| 1034 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 | ||
| 1035 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x400 | ||
| 1036 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa | ||
| 1037 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800 | ||
| 1038 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb | ||
| 1039 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x1000 | ||
| 1040 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc | ||
| 1041 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x2000 | ||
| 1042 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd | ||
| 1043 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f | ||
| 1044 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 | ||
| 1045 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20 | ||
| 1046 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 | ||
| 1047 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40 | ||
| 1048 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 | ||
| 1049 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00 | ||
| 1050 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 | ||
| 1051 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000 | ||
| 1052 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 | ||
| 1053 | #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000 | ||
| 1054 | #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 | ||
| 1055 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000 | ||
| 1056 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c | ||
| 1057 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 | ||
| 1058 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 | ||
| 1059 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe | ||
| 1060 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 | ||
| 1061 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 | ||
| 1062 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 | ||
| 1063 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 | ||
| 1064 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 | ||
| 1065 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 | ||
| 1066 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa | ||
| 1067 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 | ||
| 1068 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb | ||
| 1069 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 | ||
| 1070 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc | ||
| 1071 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 | ||
| 1072 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd | ||
| 1073 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 | ||
| 1074 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 | ||
| 1075 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 | ||
| 1076 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 | ||
| 1077 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 | ||
| 1078 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 | ||
| 1079 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 | ||
| 1080 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 | ||
| 1081 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff | ||
| 1082 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 1083 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 | ||
| 1084 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 1085 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 1086 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 1087 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 1088 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 1089 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 1090 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 1091 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff | ||
| 1092 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 1093 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 | ||
| 1094 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 1095 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 1096 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 1097 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 1098 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 1099 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff | ||
| 1100 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 1101 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 1102 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 1103 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff | ||
| 1104 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 1105 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 1106 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 1107 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff | ||
| 1108 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 1109 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 1110 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 1111 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 1112 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 1113 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 1114 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 1115 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 1116 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 1117 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 1118 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 1119 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 1120 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 1121 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 1122 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 1123 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 1124 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 1125 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 1126 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 1127 | #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf | ||
| 1128 | #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 1129 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 1130 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 1131 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 1132 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 1133 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 1134 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 1135 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 1136 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 1137 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 1138 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 1139 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 1140 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 1141 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 1142 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 1143 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 1144 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 1145 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 1146 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 1147 | #define CB_DEBUG_BUS_1__CB_BUSY_MASK 0x1 | ||
| 1148 | #define CB_DEBUG_BUS_1__CB_BUSY__SHIFT 0x0 | ||
| 1149 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY_MASK 0x2 | ||
| 1150 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY__SHIFT 0x1 | ||
| 1151 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB_MASK 0x4 | ||
| 1152 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB__SHIFT 0x2 | ||
| 1153 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY_MASK 0x8 | ||
| 1154 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY__SHIFT 0x3 | ||
| 1155 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB_MASK 0x10 | ||
| 1156 | #define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT 0x4 | ||
| 1157 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY_MASK 0x20 | ||
| 1158 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY__SHIFT 0x5 | ||
| 1159 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB_MASK 0x40 | ||
| 1160 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT 0x6 | ||
| 1161 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY_MASK 0x80 | ||
| 1162 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT 0x7 | ||
| 1163 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK 0x100 | ||
| 1164 | #define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT 0x8 | ||
| 1165 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY_MASK 0x200 | ||
| 1166 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT 0x9 | ||
| 1167 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB_MASK 0x400 | ||
| 1168 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT 0xa | ||
| 1169 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800 | ||
| 1170 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT 0xb | ||
| 1171 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK 0x1000 | ||
| 1172 | #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT 0xc | ||
| 1173 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY_MASK 0x2000 | ||
| 1174 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT 0xd | ||
| 1175 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB_MASK 0x4000 | ||
| 1176 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT 0xe | ||
| 1177 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK 0x8000 | ||
| 1178 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT 0xf | ||
| 1179 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK 0x10000 | ||
| 1180 | #define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT 0x10 | ||
| 1181 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY_MASK 0x20000 | ||
| 1182 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY__SHIFT 0x11 | ||
| 1183 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB_MASK 0x40000 | ||
| 1184 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB__SHIFT 0x12 | ||
| 1185 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY_MASK 0x80000 | ||
| 1186 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY__SHIFT 0x13 | ||
| 1187 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB_MASK 0x100000 | ||
| 1188 | #define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT 0x14 | ||
| 1189 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY_MASK 0x200000 | ||
| 1190 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT 0x15 | ||
| 1191 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK 0x400000 | ||
| 1192 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT 0x16 | ||
| 1193 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK 0x800000 | ||
| 1194 | #define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT 0x17 | ||
| 1195 | #define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK 0x1 | ||
| 1196 | #define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT 0x0 | ||
| 1197 | #define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL_MASK 0x2 | ||
| 1198 | #define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT 0x1 | ||
| 1199 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY_MASK 0x4 | ||
| 1200 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT 0x2 | ||
| 1201 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK 0x8 | ||
| 1202 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT 0x3 | ||
| 1203 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK 0x10 | ||
| 1204 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT 0x4 | ||
| 1205 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK 0x20 | ||
| 1206 | #define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT 0x5 | ||
| 1207 | #define CB_DEBUG_BUS_2__FOP_IN_VALID_READY_MASK 0x40 | ||
| 1208 | #define CB_DEBUG_BUS_2__FOP_IN_VALID_READY__SHIFT 0x6 | ||
| 1209 | #define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB_MASK 0x80 | ||
| 1210 | #define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB__SHIFT 0x7 | ||
| 1211 | #define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY_MASK 0x100 | ||
| 1212 | #define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY__SHIFT 0x8 | ||
| 1213 | #define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB_MASK 0x200 | ||
| 1214 | #define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB__SHIFT 0x9 | ||
| 1215 | #define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL_MASK 0x400 | ||
| 1216 | #define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL__SHIFT 0xa | ||
| 1217 | #define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800 | ||
| 1218 | #define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL__SHIFT 0xb | ||
| 1219 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY_MASK 0x1000 | ||
| 1220 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT 0xc | ||
| 1221 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK 0x2000 | ||
| 1222 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT 0xd | ||
| 1223 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK 0x4000 | ||
| 1224 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT 0xe | ||
| 1225 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK 0x8000 | ||
| 1226 | #define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT 0xf | ||
| 1227 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY_MASK 0x10000 | ||
| 1228 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT 0x10 | ||
| 1229 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK 0x20000 | ||
| 1230 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT 0x11 | ||
| 1231 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK 0x40000 | ||
| 1232 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT 0x12 | ||
| 1233 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK 0x80000 | ||
| 1234 | #define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT 0x13 | ||
| 1235 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK 0x100000 | ||
| 1236 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT 0x14 | ||
| 1237 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK 0x200000 | ||
| 1238 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT 0x15 | ||
| 1239 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK 0x400000 | ||
| 1240 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT 0x16 | ||
| 1241 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK 0x800000 | ||
| 1242 | #define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT 0x17 | ||
| 1243 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK 0x1 | ||
| 1244 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT 0x0 | ||
| 1245 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK 0x2 | ||
| 1246 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT 0x1 | ||
| 1247 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK 0x4 | ||
| 1248 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT 0x2 | ||
| 1249 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK 0x8 | ||
| 1250 | #define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT 0x3 | ||
| 1251 | #define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID_MASK 0x10 | ||
| 1252 | #define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID__SHIFT 0x4 | ||
| 1253 | #define CB_DEBUG_BUS_3__CC_SF_FULL_MASK 0x20 | ||
| 1254 | #define CB_DEBUG_BUS_3__CC_SF_FULL__SHIFT 0x5 | ||
| 1255 | #define CB_DEBUG_BUS_3__CC_RB_FULL_MASK 0x40 | ||
| 1256 | #define CB_DEBUG_BUS_3__CC_RB_FULL__SHIFT 0x6 | ||
| 1257 | #define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK 0x80 | ||
| 1258 | #define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x7 | ||
| 1259 | #define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK 0x100 | ||
| 1260 | #define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x8 | ||
| 1261 | #define CB_DEBUG_BUS_3__CM_TQ_FULL_MASK 0x200 | ||
| 1262 | #define CB_DEBUG_BUS_3__CM_TQ_FULL__SHIFT 0x9 | ||
| 1263 | #define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL_MASK 0x400 | ||
| 1264 | #define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL__SHIFT 0xa | ||
| 1265 | #define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800 | ||
| 1266 | #define CB_DEBUG_BUS_3__LQUAD_NO_TILE__SHIFT 0xb | ||
| 1267 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK 0x1000 | ||
| 1268 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT 0xc | ||
| 1269 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK 0x2000 | ||
| 1270 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT 0xd | ||
| 1271 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK 0x4000 | ||
| 1272 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT 0xe | ||
| 1273 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK 0x8000 | ||
| 1274 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT 0xf | ||
| 1275 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK 0x10000 | ||
| 1276 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT 0x10 | ||
| 1277 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK 0x20000 | ||
| 1278 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT 0x11 | ||
| 1279 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK 0x40000 | ||
| 1280 | #define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT 0x12 | ||
| 1281 | #define CB_DEBUG_BUS_3__CM_CACHE_HIT_MASK 0x80000 | ||
| 1282 | #define CB_DEBUG_BUS_3__CM_CACHE_HIT__SHIFT 0x13 | ||
| 1283 | #define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS_MASK 0x100000 | ||
| 1284 | #define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS__SHIFT 0x14 | ||
| 1285 | #define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS_MASK 0x200000 | ||
| 1286 | #define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS__SHIFT 0x15 | ||
| 1287 | #define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL_MASK 0x400000 | ||
| 1288 | #define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL__SHIFT 0x16 | ||
| 1289 | #define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x800000 | ||
| 1290 | #define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x17 | ||
| 1291 | #define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x1 | ||
| 1292 | #define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0 | ||
| 1293 | #define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x2 | ||
| 1294 | #define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x1 | ||
| 1295 | #define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK 0x4 | ||
| 1296 | #define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT 0x2 | ||
| 1297 | #define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK 0x8 | ||
| 1298 | #define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x3 | ||
| 1299 | #define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK 0x10 | ||
| 1300 | #define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT 0x4 | ||
| 1301 | #define CB_DEBUG_BUS_4__CM_CACHE_STALL_MASK 0x20 | ||
| 1302 | #define CB_DEBUG_BUS_4__CM_CACHE_STALL__SHIFT 0x5 | ||
| 1303 | #define CB_DEBUG_BUS_4__FC_CACHE_HIT_MASK 0x40 | ||
| 1304 | #define CB_DEBUG_BUS_4__FC_CACHE_HIT__SHIFT 0x6 | ||
| 1305 | #define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS_MASK 0x80 | ||
| 1306 | #define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS__SHIFT 0x7 | ||
| 1307 | #define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS_MASK 0x100 | ||
| 1308 | #define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS__SHIFT 0x8 | ||
| 1309 | #define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL_MASK 0x200 | ||
| 1310 | #define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL__SHIFT 0x9 | ||
| 1311 | #define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x400 | ||
| 1312 | #define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xa | ||
| 1313 | #define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800 | ||
| 1314 | #define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xb | ||
| 1315 | #define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x1000 | ||
| 1316 | #define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xc | ||
| 1317 | #define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK 0x2000 | ||
| 1318 | #define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT 0xd | ||
| 1319 | #define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK 0x4000 | ||
| 1320 | #define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0xe | ||
| 1321 | #define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK 0x8000 | ||
| 1322 | #define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT 0xf | ||
| 1323 | #define CB_DEBUG_BUS_4__FC_CACHE_STALL_MASK 0x10000 | ||
| 1324 | #define CB_DEBUG_BUS_4__FC_CACHE_STALL__SHIFT 0x10 | ||
| 1325 | #define CB_DEBUG_BUS_4__CC_CACHE_HIT_MASK 0x20000 | ||
| 1326 | #define CB_DEBUG_BUS_4__CC_CACHE_HIT__SHIFT 0x11 | ||
| 1327 | #define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS_MASK 0x40000 | ||
| 1328 | #define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS__SHIFT 0x12 | ||
| 1329 | #define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS_MASK 0x80000 | ||
| 1330 | #define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS__SHIFT 0x13 | ||
| 1331 | #define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL_MASK 0x100000 | ||
| 1332 | #define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL__SHIFT 0x14 | ||
| 1333 | #define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x200000 | ||
| 1334 | #define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x15 | ||
| 1335 | #define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x400000 | ||
| 1336 | #define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x16 | ||
| 1337 | #define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x800000 | ||
| 1338 | #define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x17 | ||
| 1339 | #define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK 0x1 | ||
| 1340 | #define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT 0x0 | ||
| 1341 | #define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK 0x2 | ||
| 1342 | #define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x1 | ||
| 1343 | #define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK 0x4 | ||
| 1344 | #define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x2 | ||
| 1345 | #define CB_DEBUG_BUS_5__CC_CACHE_STALL_MASK 0x8 | ||
| 1346 | #define CB_DEBUG_BUS_5__CC_CACHE_STALL__SHIFT 0x3 | ||
| 1347 | #define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK 0x10 | ||
| 1348 | #define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT 0x4 | ||
| 1349 | #define CB_DEBUG_BUS_5__CM_CACHE_FLUSH_MASK 0x20 | ||
| 1350 | #define CB_DEBUG_BUS_5__CM_CACHE_FLUSH__SHIFT 0x5 | ||
| 1351 | #define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED_MASK 0x40 | ||
| 1352 | #define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT 0x6 | ||
| 1353 | #define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED_MASK 0x80 | ||
| 1354 | #define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT 0x7 | ||
| 1355 | #define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x100 | ||
| 1356 | #define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x8 | ||
| 1357 | #define CB_DEBUG_BUS_5__FC_CACHE_FLUSH_MASK 0x200 | ||
| 1358 | #define CB_DEBUG_BUS_5__FC_CACHE_FLUSH__SHIFT 0x9 | ||
| 1359 | #define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED_MASK 0x400 | ||
| 1360 | #define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT 0xa | ||
| 1361 | #define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED_MASK 0x3800 | ||
| 1362 | #define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT 0xb | ||
| 1363 | #define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x1c000 | ||
| 1364 | #define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0xe | ||
| 1365 | #define CB_DEBUG_BUS_5__CC_CACHE_FLUSH_MASK 0x20000 | ||
| 1366 | #define CB_DEBUG_BUS_5__CC_CACHE_FLUSH__SHIFT 0x11 | ||
| 1367 | #define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED_MASK 0x40000 | ||
| 1368 | #define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT 0x12 | ||
| 1369 | #define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED_MASK 0x380000 | ||
| 1370 | #define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT 0x13 | ||
| 1371 | #define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x7 | ||
| 1372 | #define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x0 | ||
| 1373 | #define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST_MASK 0x8 | ||
| 1374 | #define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST__SHIFT 0x3 | ||
| 1375 | #define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST_MASK 0x10 | ||
| 1376 | #define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST__SHIFT 0x4 | ||
| 1377 | #define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST_MASK 0x20 | ||
| 1378 | #define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST__SHIFT 0x5 | ||
| 1379 | #define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST_MASK 0x40 | ||
| 1380 | #define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST__SHIFT 0x6 | ||
| 1381 | #define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST_MASK 0x80 | ||
| 1382 | #define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST__SHIFT 0x7 | ||
| 1383 | #define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST_MASK 0x100 | ||
| 1384 | #define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST__SHIFT 0x8 | ||
| 1385 | #define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1fe00 | ||
| 1386 | #define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x9 | ||
| 1387 | #define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x7ff | ||
| 1388 | #define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0 | ||
| 1389 | #define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1ff800 | ||
| 1390 | #define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb | ||
| 1391 | #define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0xff | ||
| 1392 | #define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 | ||
| 1393 | #define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff00 | ||
| 1394 | #define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x8 | ||
| 1395 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK 0x80000 | ||
| 1396 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT 0x13 | ||
| 1397 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK 0x100000 | ||
| 1398 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT 0x14 | ||
| 1399 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK 0x200000 | ||
| 1400 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT 0x15 | ||
| 1401 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR_MASK 0x400000 | ||
| 1402 | #define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR__SHIFT 0x16 | ||
| 1403 | #define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x3ff | ||
| 1404 | #define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 | ||
| 1405 | #define CB_DEBUG_BUS_9__CC_SURFACE_SYNC_MASK 0x400 | ||
| 1406 | #define CB_DEBUG_BUS_9__CC_SURFACE_SYNC__SHIFT 0xa | ||
| 1407 | #define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800 | ||
| 1408 | #define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT 0xb | ||
| 1409 | #define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK 0x1000 | ||
| 1410 | #define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT 0xc | ||
| 1411 | #define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK 0x2000 | ||
| 1412 | #define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT 0xd | ||
| 1413 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_MASK 0x4000 | ||
| 1414 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT 0xe | ||
| 1415 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK 0x78000 | ||
| 1416 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT 0xf | ||
| 1417 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK 0x80000 | ||
| 1418 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT 0x13 | ||
| 1419 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE_MASK 0x100000 | ||
| 1420 | #define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT 0x14 | ||
| 1421 | #define CB_DEBUG_BUS_9__EVENT_ALL_MASK 0x200000 | ||
| 1422 | #define CB_DEBUG_BUS_9__EVENT_ALL__SHIFT 0x15 | ||
| 1423 | #define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS_MASK 0x400000 | ||
| 1424 | #define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS__SHIFT 0x16 | ||
| 1425 | #define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE_MASK 0x800000 | ||
| 1426 | #define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE__SHIFT 0x17 | ||
| 1427 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_MASK 0x1 | ||
| 1428 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH__SHIFT 0x0 | ||
| 1429 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x2 | ||
| 1430 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x1 | ||
| 1431 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK 0x4 | ||
| 1432 | #define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x2 | ||
| 1433 | #define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK 0x8 | ||
| 1434 | #define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x3 | ||
| 1435 | #define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK 0x10 | ||
| 1436 | #define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT 0x4 | ||
| 1437 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC_MASK 0x20 | ||
| 1438 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC__SHIFT 0x5 | ||
| 1439 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD_MASK 0x40 | ||
| 1440 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD__SHIFT 0x6 | ||
| 1441 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE_MASK 0x80 | ||
| 1442 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE__SHIFT 0x7 | ||
| 1443 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF_MASK 0x100 | ||
| 1444 | #define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF__SHIFT 0x8 | ||
| 1445 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC_MASK 0x200 | ||
| 1446 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC__SHIFT 0x9 | ||
| 1447 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD_MASK 0x400 | ||
| 1448 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD__SHIFT 0xa | ||
| 1449 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800 | ||
| 1450 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE__SHIFT 0xb | ||
| 1451 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF_MASK 0x1000 | ||
| 1452 | #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF__SHIFT 0xc | ||
| 1453 | #define CB_DEBUG_BUS_10__CORE_SCLK_VLD_MASK 0x2000 | ||
| 1454 | #define CB_DEBUG_BUS_10__CORE_SCLK_VLD__SHIFT 0xd | ||
| 1455 | #define CB_DEBUG_BUS_10__REG_SCLK0_VLD_MASK 0x4000 | ||
| 1456 | #define CB_DEBUG_BUS_10__REG_SCLK0_VLD__SHIFT 0xe | ||
| 1457 | #define CB_DEBUG_BUS_10__REG_SCLK1_VLD_MASK 0x8000 | ||
| 1458 | #define CB_DEBUG_BUS_10__REG_SCLK1_VLD__SHIFT 0xf | ||
| 1459 | #define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY_MASK 0x10000 | ||
| 1460 | #define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT 0x10 | ||
| 1461 | #define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK 0x20000 | ||
| 1462 | #define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT 0x11 | ||
| 1463 | #define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK 0x40000 | ||
| 1464 | #define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT 0x12 | ||
| 1465 | #define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK 0x80000 | ||
| 1466 | #define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT 0x13 | ||
| 1467 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK 0x100000 | ||
| 1468 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT 0x14 | ||
| 1469 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK 0x200000 | ||
| 1470 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x15 | ||
| 1471 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK 0x400000 | ||
| 1472 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x16 | ||
| 1473 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK 0x800000 | ||
| 1474 | #define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x17 | ||
| 1475 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK 0x1 | ||
| 1476 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x0 | ||
| 1477 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK 0x2 | ||
| 1478 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x1 | ||
| 1479 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK 0x4 | ||
| 1480 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x2 | ||
| 1481 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK 0x8 | ||
| 1482 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x3 | ||
| 1483 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK 0x10 | ||
| 1484 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT 0x4 | ||
| 1485 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK 0x20 | ||
| 1486 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT 0x5 | ||
| 1487 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK 0x40 | ||
| 1488 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT 0x6 | ||
| 1489 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK 0x80 | ||
| 1490 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT 0x7 | ||
| 1491 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK 0x100 | ||
| 1492 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT 0x8 | ||
| 1493 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK 0x200 | ||
| 1494 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT 0x9 | ||
| 1495 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK 0x400 | ||
| 1496 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT 0xa | ||
| 1497 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800 | ||
| 1498 | #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT 0xb | ||
| 1499 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK 0x1000 | ||
| 1500 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT 0xc | ||
| 1501 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK 0x2000 | ||
| 1502 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT 0xd | ||
| 1503 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK 0x4000 | ||
| 1504 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT 0xe | ||
| 1505 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK 0x8000 | ||
| 1506 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT 0xf | ||
| 1507 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK 0x10000 | ||
| 1508 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT 0x10 | ||
| 1509 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK 0x20000 | ||
| 1510 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT 0x11 | ||
| 1511 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK 0x40000 | ||
| 1512 | #define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT 0x12 | ||
| 1513 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK 0x80000 | ||
| 1514 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT 0x13 | ||
| 1515 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK 0x100000 | ||
| 1516 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT 0x14 | ||
| 1517 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK 0x200000 | ||
| 1518 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT 0x15 | ||
| 1519 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK 0x400000 | ||
| 1520 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT 0x16 | ||
| 1521 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK 0x800000 | ||
| 1522 | #define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT 0x17 | ||
| 1523 | #define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK 0x1 | ||
| 1524 | #define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT 0x0 | ||
| 1525 | #define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK 0x2 | ||
| 1526 | #define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT 0x1 | ||
| 1527 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK 0x4 | ||
| 1528 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT 0x2 | ||
| 1529 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK 0x8 | ||
| 1530 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT 0x3 | ||
| 1531 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK 0x10 | ||
| 1532 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT 0x4 | ||
| 1533 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK 0x20 | ||
| 1534 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT 0x5 | ||
| 1535 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK 0x40 | ||
| 1536 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT 0x6 | ||
| 1537 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK 0x80 | ||
| 1538 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT 0x7 | ||
| 1539 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK 0x100 | ||
| 1540 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT 0x8 | ||
| 1541 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK 0x200 | ||
| 1542 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT 0x9 | ||
| 1543 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK 0x400 | ||
| 1544 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT 0xa | ||
| 1545 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800 | ||
| 1546 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT 0xb | ||
| 1547 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK 0x1000 | ||
| 1548 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT 0xc | ||
| 1549 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK 0x2000 | ||
| 1550 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT 0xd | ||
| 1551 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK 0x4000 | ||
| 1552 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT 0xe | ||
| 1553 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK 0x8000 | ||
| 1554 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT 0xf | ||
| 1555 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK 0x10000 | ||
| 1556 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT 0x10 | ||
| 1557 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK 0x20000 | ||
| 1558 | #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT 0x11 | ||
| 1559 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK 0x40000 | ||
| 1560 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT 0x12 | ||
| 1561 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK 0x80000 | ||
| 1562 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT 0x13 | ||
| 1563 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK 0x100000 | ||
| 1564 | #define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT 0x14 | ||
| 1565 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK 0x200000 | ||
| 1566 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT 0x15 | ||
| 1567 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK 0x400000 | ||
| 1568 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT 0x16 | ||
| 1569 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK 0x800000 | ||
| 1570 | #define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT 0x17 | ||
| 1571 | #define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK 0x1 | ||
| 1572 | #define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT 0x0 | ||
| 1573 | #define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS_MASK 0x2 | ||
| 1574 | #define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT 0x1 | ||
| 1575 | #define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT_MASK 0x4 | ||
| 1576 | #define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT 0x2 | ||
| 1577 | #define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS_MASK 0x8 | ||
| 1578 | #define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT 0x3 | ||
| 1579 | #define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT_MASK 0x10 | ||
| 1580 | #define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT 0x4 | ||
| 1581 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK 0x20 | ||
| 1582 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT 0x5 | ||
| 1583 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK 0x40 | ||
| 1584 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT 0x6 | ||
| 1585 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK 0x80 | ||
| 1586 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT 0x7 | ||
| 1587 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK 0x100 | ||
| 1588 | #define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT 0x8 | ||
| 1589 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT_MASK 0x200 | ||
| 1590 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT__SHIFT 0x9 | ||
| 1591 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK 0x400 | ||
| 1592 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT 0xa | ||
| 1593 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK 0x800 | ||
| 1594 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT 0xb | ||
| 1595 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK 0x1000 | ||
| 1596 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT 0xc | ||
| 1597 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x2000 | ||
| 1598 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xd | ||
| 1599 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x4000 | ||
| 1600 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xe | ||
| 1601 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x8000 | ||
| 1602 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xf | ||
| 1603 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK 0x10000 | ||
| 1604 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT 0x10 | ||
| 1605 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK 0x20000 | ||
| 1606 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x11 | ||
| 1607 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK 0x40000 | ||
| 1608 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x12 | ||
| 1609 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL_MASK 0x80000 | ||
| 1610 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL__SHIFT 0x13 | ||
| 1611 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH_MASK 0x100000 | ||
| 1612 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT 0x14 | ||
| 1613 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK 0x200000 | ||
| 1614 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT 0x15 | ||
| 1615 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x400000 | ||
| 1616 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x16 | ||
| 1617 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK 0x800000 | ||
| 1618 | #define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT 0x17 | ||
| 1619 | #define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff | ||
| 1620 | #define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 | ||
| 1621 | #define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK 0x3ff800 | ||
| 1622 | #define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb | ||
| 1623 | #define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK 0x400000 | ||
| 1624 | #define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT 0x16 | ||
| 1625 | #define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL_MASK 0x800000 | ||
| 1626 | #define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT 0x17 | ||
| 1627 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK 0x7 | ||
| 1628 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT 0x0 | ||
| 1629 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK 0x18 | ||
| 1630 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT 0x3 | ||
| 1631 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK 0x60 | ||
| 1632 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT 0x5 | ||
| 1633 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK 0x180 | ||
| 1634 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT 0x7 | ||
| 1635 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK 0x600 | ||
| 1636 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT 0x9 | ||
| 1637 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK 0x1800 | ||
| 1638 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT 0xb | ||
| 1639 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK 0x6000 | ||
| 1640 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT 0xd | ||
| 1641 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK 0x18000 | ||
| 1642 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT 0xf | ||
| 1643 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK 0x60000 | ||
| 1644 | #define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT 0x11 | ||
| 1645 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK 0x1 | ||
| 1646 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT 0x0 | ||
| 1647 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK 0x2 | ||
| 1648 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT 0x1 | ||
| 1649 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK 0x4 | ||
| 1650 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT 0x2 | ||
| 1651 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK 0x8 | ||
| 1652 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT 0x3 | ||
| 1653 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK 0x10 | ||
| 1654 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT 0x4 | ||
| 1655 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK 0x20 | ||
| 1656 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT 0x5 | ||
| 1657 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK 0x40 | ||
| 1658 | #define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT 0x6 | ||
| 1659 | #define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1 | ||
| 1660 | #define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0 | ||
| 1661 | #define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2 | ||
| 1662 | #define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1 | ||
| 1663 | #define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4 | ||
| 1664 | #define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2 | ||
| 1665 | #define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8 | ||
| 1666 | #define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3 | ||
| 1667 | #define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10 | ||
| 1668 | #define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4 | ||
| 1669 | #define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20 | ||
| 1670 | #define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5 | ||
| 1671 | #define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40 | ||
| 1672 | #define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6 | ||
| 1673 | #define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80 | ||
| 1674 | #define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7 | ||
| 1675 | #define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100 | ||
| 1676 | #define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8 | ||
| 1677 | #define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200 | ||
| 1678 | #define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9 | ||
| 1679 | #define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400 | ||
| 1680 | #define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa | ||
| 1681 | #define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800 | ||
| 1682 | #define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb | ||
| 1683 | #define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1 | ||
| 1684 | #define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0 | ||
| 1685 | #define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2 | ||
| 1686 | #define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1 | ||
| 1687 | #define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4 | ||
| 1688 | #define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2 | ||
| 1689 | #define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8 | ||
| 1690 | #define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3 | ||
| 1691 | #define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10 | ||
| 1692 | #define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4 | ||
| 1693 | #define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20 | ||
| 1694 | #define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5 | ||
| 1695 | #define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40 | ||
| 1696 | #define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6 | ||
| 1697 | #define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80 | ||
| 1698 | #define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7 | ||
| 1699 | #define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100 | ||
| 1700 | #define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8 | ||
| 1701 | #define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200 | ||
| 1702 | #define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9 | ||
| 1703 | #define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400 | ||
| 1704 | #define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa | ||
| 1705 | #define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800 | ||
| 1706 | #define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb | ||
| 1707 | #define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000 | ||
| 1708 | #define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc | ||
| 1709 | #define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000 | ||
| 1710 | #define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd | ||
| 1711 | #define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000 | ||
| 1712 | #define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe | ||
| 1713 | #define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000 | ||
| 1714 | #define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf | ||
| 1715 | #define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000 | ||
| 1716 | #define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10 | ||
| 1717 | #define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000 | ||
| 1718 | #define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11 | ||
| 1719 | #define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000 | ||
| 1720 | #define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12 | ||
| 1721 | #define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000 | ||
| 1722 | #define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13 | ||
| 1723 | #define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000 | ||
| 1724 | #define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14 | ||
| 1725 | #define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000 | ||
| 1726 | #define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15 | ||
| 1727 | #define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3 | ||
| 1728 | #define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0 | ||
| 1729 | #define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4 | ||
| 1730 | #define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2 | ||
| 1731 | #define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8 | ||
| 1732 | #define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3 | ||
| 1733 | #define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10 | ||
| 1734 | #define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4 | ||
| 1735 | #define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20 | ||
| 1736 | #define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5 | ||
| 1737 | #define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40 | ||
| 1738 | #define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6 | ||
| 1739 | #define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80 | ||
| 1740 | #define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7 | ||
| 1741 | #define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100 | ||
| 1742 | #define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8 | ||
| 1743 | #define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200 | ||
| 1744 | #define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9 | ||
| 1745 | #define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400 | ||
| 1746 | #define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa | ||
| 1747 | #define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800 | ||
| 1748 | #define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb | ||
| 1749 | #define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000 | ||
| 1750 | #define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc | ||
| 1751 | #define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000 | ||
| 1752 | #define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd | ||
| 1753 | #define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000 | ||
| 1754 | #define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe | ||
| 1755 | #define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000 | ||
| 1756 | #define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf | ||
| 1757 | #define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000 | ||
| 1758 | #define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10 | ||
| 1759 | #define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000 | ||
| 1760 | #define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11 | ||
| 1761 | #define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000 | ||
| 1762 | #define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12 | ||
| 1763 | #define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f | ||
| 1764 | #define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0 | ||
| 1765 | #define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0 | ||
| 1766 | #define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6 | ||
| 1767 | #define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000 | ||
| 1768 | #define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc | ||
| 1769 | #define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000 | ||
| 1770 | #define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd | ||
| 1771 | #define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000 | ||
| 1772 | #define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe | ||
| 1773 | #define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000 | ||
| 1774 | #define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10 | ||
| 1775 | #define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000 | ||
| 1776 | #define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11 | ||
| 1777 | #define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000 | ||
| 1778 | #define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12 | ||
| 1779 | #define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 | ||
| 1780 | #define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 | ||
| 1781 | #define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 | ||
| 1782 | #define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 | ||
| 1783 | #define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 | ||
| 1784 | #define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 | ||
| 1785 | #define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000 | ||
| 1786 | #define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17 | ||
| 1787 | #define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1 | ||
| 1788 | #define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0 | ||
| 1789 | #define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2 | ||
| 1790 | #define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1 | ||
| 1791 | #define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4 | ||
| 1792 | #define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2 | ||
| 1793 | #define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8 | ||
| 1794 | #define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3 | ||
| 1795 | #define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10 | ||
| 1796 | #define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4 | ||
| 1797 | #define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20 | ||
| 1798 | #define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5 | ||
| 1799 | #define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40 | ||
| 1800 | #define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6 | ||
| 1801 | #define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80 | ||
| 1802 | #define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7 | ||
| 1803 | #define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff | ||
| 1804 | #define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0 | ||
| 1805 | #define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000 | ||
| 1806 | #define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc | ||
| 1807 | #define CP_DFY_CNTL__POLICY_MASK 0x1 | ||
| 1808 | #define CP_DFY_CNTL__POLICY__SHIFT 0x0 | ||
| 1809 | #define CP_DFY_CNTL__MTYPE_MASK 0xc | ||
| 1810 | #define CP_DFY_CNTL__MTYPE__SHIFT 0x2 | ||
| 1811 | #define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000 | ||
| 1812 | #define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c | ||
| 1813 | #define CP_DFY_CNTL__MODE_MASK 0x60000000 | ||
| 1814 | #define CP_DFY_CNTL__MODE__SHIFT 0x1d | ||
| 1815 | #define CP_DFY_CNTL__ENABLE_MASK 0x80000000 | ||
| 1816 | #define CP_DFY_CNTL__ENABLE__SHIFT 0x1f | ||
| 1817 | #define CP_DFY_STAT__BURST_COUNT_MASK 0xffff | ||
| 1818 | #define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 | ||
| 1819 | #define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000 | ||
| 1820 | #define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 | ||
| 1821 | #define CP_DFY_STAT__BUSY_MASK 0x80000000 | ||
| 1822 | #define CP_DFY_STAT__BUSY__SHIFT 0x1f | ||
| 1823 | #define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff | ||
| 1824 | #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 1825 | #define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 | ||
| 1826 | #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 | ||
| 1827 | #define CP_DFY_DATA_0__DATA_MASK 0xffffffff | ||
| 1828 | #define CP_DFY_DATA_0__DATA__SHIFT 0x0 | ||
| 1829 | #define CP_DFY_DATA_1__DATA_MASK 0xffffffff | ||
| 1830 | #define CP_DFY_DATA_1__DATA__SHIFT 0x0 | ||
| 1831 | #define CP_DFY_DATA_2__DATA_MASK 0xffffffff | ||
| 1832 | #define CP_DFY_DATA_2__DATA__SHIFT 0x0 | ||
| 1833 | #define CP_DFY_DATA_3__DATA_MASK 0xffffffff | ||
| 1834 | #define CP_DFY_DATA_3__DATA__SHIFT 0x0 | ||
| 1835 | #define CP_DFY_DATA_4__DATA_MASK 0xffffffff | ||
| 1836 | #define CP_DFY_DATA_4__DATA__SHIFT 0x0 | ||
| 1837 | #define CP_DFY_DATA_5__DATA_MASK 0xffffffff | ||
| 1838 | #define CP_DFY_DATA_5__DATA__SHIFT 0x0 | ||
| 1839 | #define CP_DFY_DATA_6__DATA_MASK 0xffffffff | ||
| 1840 | #define CP_DFY_DATA_6__DATA__SHIFT 0x0 | ||
| 1841 | #define CP_DFY_DATA_7__DATA_MASK 0xffffffff | ||
| 1842 | #define CP_DFY_DATA_7__DATA__SHIFT 0x0 | ||
| 1843 | #define CP_DFY_DATA_8__DATA_MASK 0xffffffff | ||
| 1844 | #define CP_DFY_DATA_8__DATA__SHIFT 0x0 | ||
| 1845 | #define CP_DFY_DATA_9__DATA_MASK 0xffffffff | ||
| 1846 | #define CP_DFY_DATA_9__DATA__SHIFT 0x0 | ||
| 1847 | #define CP_DFY_DATA_10__DATA_MASK 0xffffffff | ||
| 1848 | #define CP_DFY_DATA_10__DATA__SHIFT 0x0 | ||
| 1849 | #define CP_DFY_DATA_11__DATA_MASK 0xffffffff | ||
| 1850 | #define CP_DFY_DATA_11__DATA__SHIFT 0x0 | ||
| 1851 | #define CP_DFY_DATA_12__DATA_MASK 0xffffffff | ||
| 1852 | #define CP_DFY_DATA_12__DATA__SHIFT 0x0 | ||
| 1853 | #define CP_DFY_DATA_13__DATA_MASK 0xffffffff | ||
| 1854 | #define CP_DFY_DATA_13__DATA__SHIFT 0x0 | ||
| 1855 | #define CP_DFY_DATA_14__DATA_MASK 0xffffffff | ||
| 1856 | #define CP_DFY_DATA_14__DATA__SHIFT 0x0 | ||
| 1857 | #define CP_DFY_DATA_15__DATA_MASK 0xffffffff | ||
| 1858 | #define CP_DFY_DATA_15__DATA__SHIFT 0x0 | ||
| 1859 | #define CP_DFY_CMD__OFFSET_MASK 0x1ff | ||
| 1860 | #define CP_DFY_CMD__OFFSET__SHIFT 0x0 | ||
| 1861 | #define CP_DFY_CMD__SIZE_MASK 0xffff0000 | ||
| 1862 | #define CP_DFY_CMD__SIZE__SHIFT 0x10 | ||
| 1863 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff | ||
| 1864 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 | ||
| 1865 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00 | ||
| 1866 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 | ||
| 1867 | #define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x3ff | ||
| 1868 | #define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 | ||
| 1869 | #define CP_RB0_BASE__RB_BASE_MASK 0xffffffff | ||
| 1870 | #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 | ||
| 1871 | #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff | ||
| 1872 | #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 | ||
| 1873 | #define CP_RB_BASE__RB_BASE_MASK 0xffffffff | ||
| 1874 | #define CP_RB_BASE__RB_BASE__SHIFT 0x0 | ||
| 1875 | #define CP_RB1_BASE__RB_BASE_MASK 0xffffffff | ||
| 1876 | #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 | ||
| 1877 | #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff | ||
| 1878 | #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 | ||
| 1879 | #define CP_RB2_BASE__RB_BASE_MASK 0xffffffff | ||
| 1880 | #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 | ||
| 1881 | #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f | ||
| 1882 | #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 | ||
| 1883 | #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 | ||
| 1884 | #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 | ||
| 1885 | #define CP_RB0_CNTL__MTYPE_MASK 0x18000 | ||
| 1886 | #define CP_RB0_CNTL__MTYPE__SHIFT 0xf | ||
| 1887 | #define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000 | ||
| 1888 | #define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 | ||
| 1889 | #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 | ||
| 1890 | #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 | ||
| 1891 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 | ||
| 1892 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 | ||
| 1893 | #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 | ||
| 1894 | #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 | ||
| 1895 | #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 | ||
| 1896 | #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b | ||
| 1897 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 | ||
| 1898 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f | ||
| 1899 | #define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f | ||
| 1900 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 | ||
| 1901 | #define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 | ||
| 1902 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 | ||
| 1903 | #define CP_RB_CNTL__MTYPE_MASK 0x18000 | ||
| 1904 | #define CP_RB_CNTL__MTYPE__SHIFT 0xf | ||
| 1905 | #define CP_RB_CNTL__BUF_SWAP_MASK 0x60000 | ||
| 1906 | #define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11 | ||
| 1907 | #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 | ||
| 1908 | #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 | ||
| 1909 | #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 | ||
| 1910 | #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 | ||
| 1911 | #define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000 | ||
| 1912 | #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 | ||
| 1913 | #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 | ||
| 1914 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b | ||
| 1915 | #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 | ||
| 1916 | #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f | ||
| 1917 | #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f | ||
| 1918 | #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 | ||
| 1919 | #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 | ||
| 1920 | #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 | ||
| 1921 | #define CP_RB1_CNTL__MTYPE_MASK 0x18000 | ||
| 1922 | #define CP_RB1_CNTL__MTYPE__SHIFT 0xf | ||
| 1923 | #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 | ||
| 1924 | #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 | ||
| 1925 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 | ||
| 1926 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 | ||
| 1927 | #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 | ||
| 1928 | #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 | ||
| 1929 | #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 | ||
| 1930 | #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b | ||
| 1931 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 | ||
| 1932 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f | ||
| 1933 | #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f | ||
| 1934 | #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 | ||
| 1935 | #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 | ||
| 1936 | #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 | ||
| 1937 | #define CP_RB2_CNTL__MTYPE_MASK 0x18000 | ||
| 1938 | #define CP_RB2_CNTL__MTYPE__SHIFT 0xf | ||
| 1939 | #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 | ||
| 1940 | #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 | ||
| 1941 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 | ||
| 1942 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 | ||
| 1943 | #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000 | ||
| 1944 | #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 | ||
| 1945 | #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 | ||
| 1946 | #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b | ||
| 1947 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 | ||
| 1948 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f | ||
| 1949 | #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff | ||
| 1950 | #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 | ||
| 1951 | #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 | ||
| 1952 | #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 | ||
| 1953 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc | ||
| 1954 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 | ||
| 1955 | #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 | ||
| 1956 | #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 | ||
| 1957 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc | ||
| 1958 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 | ||
| 1959 | #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 | ||
| 1960 | #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 | ||
| 1961 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc | ||
| 1962 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 | ||
| 1963 | #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 | ||
| 1964 | #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 | ||
| 1965 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc | ||
| 1966 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 | ||
| 1967 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff | ||
| 1968 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 | ||
| 1969 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff | ||
| 1970 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 | ||
| 1971 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff | ||
| 1972 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 | ||
| 1973 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff | ||
| 1974 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 | ||
| 1975 | #define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff | ||
| 1976 | #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 | ||
| 1977 | #define CP_RB_WPTR__RB_WPTR_MASK 0xfffff | ||
| 1978 | #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 | ||
| 1979 | #define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff | ||
| 1980 | #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 | ||
| 1981 | #define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff | ||
| 1982 | #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 | ||
| 1983 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc | ||
| 1984 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 | ||
| 1985 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff | ||
| 1986 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 | ||
| 1987 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 | ||
| 1988 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb | ||
| 1989 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 1990 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 1991 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 1992 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 1993 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000 | ||
| 1994 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 | ||
| 1995 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 | ||
| 1996 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 | ||
| 1997 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 | ||
| 1998 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 | ||
| 1999 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000 | ||
| 2000 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 | ||
| 2001 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 | ||
| 2002 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 | ||
| 2003 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2004 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2005 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2006 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2007 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2008 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2009 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2010 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2011 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2012 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2013 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2014 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2015 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2016 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2017 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 | ||
| 2018 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb | ||
| 2019 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2020 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2021 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2022 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2023 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000 | ||
| 2024 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 | ||
| 2025 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 | ||
| 2026 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 | ||
| 2027 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 | ||
| 2028 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 | ||
| 2029 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000 | ||
| 2030 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 | ||
| 2031 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 | ||
| 2032 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 | ||
| 2033 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2034 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2035 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2036 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2037 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2038 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2039 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2040 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2041 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2042 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2043 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2044 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2045 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2046 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2047 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 | ||
| 2048 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb | ||
| 2049 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2050 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2051 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2052 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2053 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000 | ||
| 2054 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 | ||
| 2055 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 | ||
| 2056 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 | ||
| 2057 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 | ||
| 2058 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 | ||
| 2059 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000 | ||
| 2060 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 | ||
| 2061 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 | ||
| 2062 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 | ||
| 2063 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2064 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2065 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2066 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2067 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2068 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2069 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2070 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2071 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2072 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2073 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2074 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2075 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2076 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2077 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 | ||
| 2078 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb | ||
| 2079 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2080 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2081 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2082 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2083 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000 | ||
| 2084 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 | ||
| 2085 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 | ||
| 2086 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 | ||
| 2087 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 | ||
| 2088 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 | ||
| 2089 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000 | ||
| 2090 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 | ||
| 2091 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 | ||
| 2092 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 | ||
| 2093 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2094 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2095 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2096 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2097 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2098 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2099 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2100 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2101 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2102 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2103 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2104 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2105 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2106 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2107 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 | ||
| 2108 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb | ||
| 2109 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 | ||
| 2110 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe | ||
| 2111 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 | ||
| 2112 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 | ||
| 2113 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000 | ||
| 2114 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 | ||
| 2115 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 | ||
| 2116 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 | ||
| 2117 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 | ||
| 2118 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 | ||
| 2119 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 | ||
| 2120 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 | ||
| 2121 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 | ||
| 2122 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 | ||
| 2123 | #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 | ||
| 2124 | #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 | ||
| 2125 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 | ||
| 2126 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 | ||
| 2127 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 | ||
| 2128 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a | ||
| 2129 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 | ||
| 2130 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b | ||
| 2131 | #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 | ||
| 2132 | #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d | ||
| 2133 | #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 | ||
| 2134 | #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e | ||
| 2135 | #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 | ||
| 2136 | #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f | ||
| 2137 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 | ||
| 2138 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb | ||
| 2139 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 | ||
| 2140 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe | ||
| 2141 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 | ||
| 2142 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 | ||
| 2143 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000 | ||
| 2144 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 | ||
| 2145 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000 | ||
| 2146 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 | ||
| 2147 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 | ||
| 2148 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 | ||
| 2149 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000 | ||
| 2150 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 | ||
| 2151 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 | ||
| 2152 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 | ||
| 2153 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 | ||
| 2154 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 | ||
| 2155 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 | ||
| 2156 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 | ||
| 2157 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 | ||
| 2158 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a | ||
| 2159 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 | ||
| 2160 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b | ||
| 2161 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 | ||
| 2162 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d | ||
| 2163 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 | ||
| 2164 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e | ||
| 2165 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 | ||
| 2166 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f | ||
| 2167 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 | ||
| 2168 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb | ||
| 2169 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 | ||
| 2170 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe | ||
| 2171 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 | ||
| 2172 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 | ||
| 2173 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000 | ||
| 2174 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 | ||
| 2175 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 | ||
| 2176 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 | ||
| 2177 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 | ||
| 2178 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 | ||
| 2179 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000 | ||
| 2180 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 | ||
| 2181 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 | ||
| 2182 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 | ||
| 2183 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 | ||
| 2184 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 | ||
| 2185 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 | ||
| 2186 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 | ||
| 2187 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 | ||
| 2188 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a | ||
| 2189 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 | ||
| 2190 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b | ||
| 2191 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 | ||
| 2192 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d | ||
| 2193 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 | ||
| 2194 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e | ||
| 2195 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 | ||
| 2196 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f | ||
| 2197 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 | ||
| 2198 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb | ||
| 2199 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 | ||
| 2200 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe | ||
| 2201 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 | ||
| 2202 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 | ||
| 2203 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000 | ||
| 2204 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 | ||
| 2205 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 | ||
| 2206 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 | ||
| 2207 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 | ||
| 2208 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 | ||
| 2209 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000 | ||
| 2210 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 | ||
| 2211 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 | ||
| 2212 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 | ||
| 2213 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 | ||
| 2214 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 | ||
| 2215 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 | ||
| 2216 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 | ||
| 2217 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 | ||
| 2218 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a | ||
| 2219 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 | ||
| 2220 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b | ||
| 2221 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 | ||
| 2222 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d | ||
| 2223 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 | ||
| 2224 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e | ||
| 2225 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 | ||
| 2226 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f | ||
| 2227 | #define CP_DEVICE_ID__DEVICE_ID_MASK 0xff | ||
| 2228 | #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 | ||
| 2229 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff | ||
| 2230 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 | ||
| 2231 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 | ||
| 2232 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 | ||
| 2233 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 | ||
| 2234 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 | ||
| 2235 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 | ||
| 2236 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 | ||
| 2237 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff | ||
| 2238 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 | ||
| 2239 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 | ||
| 2240 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 | ||
| 2241 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 | ||
| 2242 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 | ||
| 2243 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 | ||
| 2244 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 | ||
| 2245 | #define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2246 | #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2247 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2248 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2249 | #define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2250 | #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2251 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2252 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2253 | #define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2254 | #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2255 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2256 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2257 | #define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 | ||
| 2258 | #define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 | ||
| 2259 | #define CP_RB_VMID__RB0_VMID_MASK 0xf | ||
| 2260 | #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 | ||
| 2261 | #define CP_RB_VMID__RB1_VMID_MASK 0xf00 | ||
| 2262 | #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 | ||
| 2263 | #define CP_RB_VMID__RB2_VMID_MASK 0xf0000 | ||
| 2264 | #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 | ||
| 2265 | #define CP_ME0_PIPE0_VMID__VMID_MASK 0xf | ||
| 2266 | #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 | ||
| 2267 | #define CP_ME0_PIPE1_VMID__VMID_MASK 0xf | ||
| 2268 | #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 | ||
| 2269 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc | ||
| 2270 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 | ||
| 2271 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 | ||
| 2272 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e | ||
| 2273 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 | ||
| 2274 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f | ||
| 2275 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc | ||
| 2276 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 | ||
| 2277 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc | ||
| 2278 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 | ||
| 2279 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc | ||
| 2280 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 | ||
| 2281 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc | ||
| 2282 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 | ||
| 2283 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff | ||
| 2284 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 | ||
| 2285 | #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff | ||
| 2286 | #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 | ||
| 2287 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff | ||
| 2288 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 | ||
| 2289 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff | ||
| 2290 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 | ||
| 2291 | #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff | ||
| 2292 | #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 | ||
| 2293 | #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 2294 | #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 2295 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 2296 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 2297 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 | ||
| 2298 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d | ||
| 2299 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 | ||
| 2300 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e | ||
| 2301 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 | ||
| 2302 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f | ||
| 2303 | #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 2304 | #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 2305 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 2306 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 2307 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 | ||
| 2308 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d | ||
| 2309 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 | ||
| 2310 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e | ||
| 2311 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 | ||
| 2312 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f | ||
| 2313 | #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 2314 | #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 2315 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 2316 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 2317 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 | ||
| 2318 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d | ||
| 2319 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 | ||
| 2320 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e | ||
| 2321 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 | ||
| 2322 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f | ||
| 2323 | #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff | ||
| 2324 | #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 | ||
| 2325 | #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff | ||
| 2326 | #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 | ||
| 2327 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff | ||
| 2328 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 | ||
| 2329 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff | ||
| 2330 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 | ||
| 2331 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff | ||
| 2332 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 | ||
| 2333 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff | ||
| 2334 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 | ||
| 2335 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 | ||
| 2336 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 | ||
| 2337 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 | ||
| 2338 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 | ||
| 2339 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 | ||
| 2340 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 | ||
| 2341 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 | ||
| 2342 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 | ||
| 2343 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 | ||
| 2344 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 | ||
| 2345 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 | ||
| 2346 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 | ||
| 2347 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 | ||
| 2348 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 | ||
| 2349 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 | ||
| 2350 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 | ||
| 2351 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 | ||
| 2352 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 | ||
| 2353 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 | ||
| 2354 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 | ||
| 2355 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 | ||
| 2356 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 | ||
| 2357 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 | ||
| 2358 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 | ||
| 2359 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 | ||
| 2360 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 | ||
| 2361 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 | ||
| 2362 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 | ||
| 2363 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 | ||
| 2364 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 | ||
| 2365 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 | ||
| 2366 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 | ||
| 2367 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 | ||
| 2368 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 | ||
| 2369 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 | ||
| 2370 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 | ||
| 2371 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 | ||
| 2372 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 | ||
| 2373 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 | ||
| 2374 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 | ||
| 2375 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 | ||
| 2376 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 | ||
| 2377 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 | ||
| 2378 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 | ||
| 2379 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 | ||
| 2380 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 | ||
| 2381 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 | ||
| 2382 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 | ||
| 2383 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 | ||
| 2384 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 | ||
| 2385 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100 | ||
| 2386 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 | ||
| 2387 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200 | ||
| 2388 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 | ||
| 2389 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 | ||
| 2390 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa | ||
| 2391 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800 | ||
| 2392 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb | ||
| 2393 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 | ||
| 2394 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 | ||
| 2395 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000 | ||
| 2396 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 | ||
| 2397 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 | ||
| 2398 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 | ||
| 2399 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 | ||
| 2400 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 | ||
| 2401 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 | ||
| 2402 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 | ||
| 2403 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 | ||
| 2404 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 | ||
| 2405 | #define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c | ||
| 2406 | #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 | ||
| 2407 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80 | ||
| 2408 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 | ||
| 2409 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 | ||
| 2410 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 | ||
| 2411 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 | ||
| 2412 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 | ||
| 2413 | #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 | ||
| 2414 | #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 | ||
| 2415 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 | ||
| 2416 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 | ||
| 2417 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0 | ||
| 2418 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 | ||
| 2419 | #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300 | ||
| 2420 | #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 | ||
| 2421 | #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00 | ||
| 2422 | #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa | ||
| 2423 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000 | ||
| 2424 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc | ||
| 2425 | #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 | ||
| 2426 | #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 | ||
| 2427 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff | ||
| 2428 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 | ||
| 2429 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff | ||
| 2430 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 | ||
| 2431 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff | ||
| 2432 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 | ||
| 2433 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff | ||
| 2434 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 | ||
| 2435 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 | ||
| 2436 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e | ||
| 2437 | #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 | ||
| 2438 | #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f | ||
| 2439 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff | ||
| 2440 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 | ||
| 2441 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2442 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2443 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2444 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2445 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2446 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2447 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2448 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2449 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2450 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2451 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2452 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2453 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2454 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2455 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2456 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2457 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2458 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2459 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2460 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2461 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2462 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2463 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2464 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2465 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2466 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2467 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2468 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2469 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2470 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2471 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2472 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2473 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2474 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2475 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2476 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2477 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2478 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2479 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2480 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2481 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2482 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2483 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2484 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2485 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2486 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2487 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2488 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2489 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2490 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2491 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2492 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2493 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2494 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2495 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2496 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2497 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2498 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2499 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2500 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2501 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2502 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2503 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2504 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2505 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2506 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2507 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2508 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2509 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2510 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2511 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2512 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2513 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2514 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2515 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2516 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2517 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2518 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2519 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2520 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2521 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2522 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2523 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2524 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2525 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2526 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2527 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2528 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2529 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2530 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2531 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2532 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2533 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2534 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2535 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2536 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2537 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2538 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2539 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2540 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2541 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2542 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2543 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2544 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2545 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2546 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2547 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2548 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2549 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2550 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2551 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2552 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2553 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2554 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2555 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2556 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2557 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2558 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2559 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2560 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2561 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2562 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2563 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2564 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2565 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2566 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2567 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2568 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2569 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2570 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2571 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2572 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2573 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2574 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2575 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2576 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2577 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2578 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2579 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2580 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2581 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2582 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2583 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2584 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2585 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2586 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2587 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2588 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2589 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2590 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2591 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2592 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2593 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2594 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2595 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2596 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2597 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2598 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2599 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2600 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2601 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2602 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2603 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2604 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2605 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2606 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2607 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2608 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2609 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2610 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2611 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2612 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2613 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2614 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2615 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2616 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2617 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2618 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2619 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2620 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2621 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2622 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2623 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2624 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2625 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2626 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2627 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2628 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2629 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2630 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2631 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2632 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2633 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 | ||
| 2634 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc | ||
| 2635 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 | ||
| 2636 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd | ||
| 2637 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 | ||
| 2638 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe | ||
| 2639 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 | ||
| 2640 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf | ||
| 2641 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 | ||
| 2642 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 | ||
| 2643 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 | ||
| 2644 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 | ||
| 2645 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 | ||
| 2646 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 | ||
| 2647 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 | ||
| 2648 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a | ||
| 2649 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 | ||
| 2650 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b | ||
| 2651 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 | ||
| 2652 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d | ||
| 2653 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 | ||
| 2654 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e | ||
| 2655 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 | ||
| 2656 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f | ||
| 2657 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2658 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2659 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2660 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2661 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2662 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2663 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2664 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2665 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2666 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2667 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2668 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2669 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2670 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2671 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2672 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2673 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2674 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2675 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2676 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2677 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2678 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2679 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2680 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2681 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2682 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2683 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2684 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2685 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2686 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2687 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2688 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2689 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2690 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2691 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2692 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2693 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2694 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2695 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2696 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2697 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2698 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2699 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2700 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2701 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2702 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2703 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2704 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2705 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2706 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2707 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2708 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2709 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2710 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2711 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2712 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2713 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2714 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2715 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2716 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2717 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2718 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2719 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2720 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2721 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2722 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2723 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2724 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2725 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2726 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2727 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2728 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2729 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2730 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2731 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2732 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2733 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2734 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2735 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2736 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2737 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2738 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2739 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2740 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2741 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2742 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2743 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2744 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2745 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2746 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2747 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2748 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2749 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2750 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2751 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2752 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2753 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2754 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2755 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2756 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2757 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2758 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2759 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2760 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2761 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2762 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2763 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2764 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2765 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2766 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2767 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2768 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2769 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2770 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2771 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2772 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2773 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2774 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2775 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2776 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2777 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2778 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2779 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2780 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2781 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2782 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2783 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2784 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2785 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2786 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2787 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2788 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2789 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2790 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2791 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2792 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2793 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2794 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2795 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2796 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2797 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2798 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2799 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2800 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2801 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2802 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2803 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2804 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2805 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2806 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2807 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2808 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2809 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2810 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2811 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2812 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2813 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2814 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2815 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2816 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2817 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2818 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2819 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2820 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2821 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2822 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2823 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2824 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2825 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2826 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2827 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2828 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2829 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2830 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2831 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2832 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2833 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2834 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2835 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2836 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2837 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2838 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2839 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2840 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2841 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2842 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2843 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2844 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2845 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2846 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2847 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2848 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2849 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 | ||
| 2850 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc | ||
| 2851 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 | ||
| 2852 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd | ||
| 2853 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 | ||
| 2854 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe | ||
| 2855 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2856 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2857 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 | ||
| 2858 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 | ||
| 2859 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 | ||
| 2860 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 | ||
| 2861 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 | ||
| 2862 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 | ||
| 2863 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 | ||
| 2864 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a | ||
| 2865 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 | ||
| 2866 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b | ||
| 2867 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 | ||
| 2868 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d | ||
| 2869 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 | ||
| 2870 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e | ||
| 2871 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 | ||
| 2872 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f | ||
| 2873 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 | ||
| 2874 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc | ||
| 2875 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 | ||
| 2876 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd | ||
| 2877 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 | ||
| 2878 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe | ||
| 2879 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2880 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2881 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 | ||
| 2882 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 | ||
| 2883 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 | ||
| 2884 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 | ||
| 2885 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 | ||
| 2886 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 | ||
| 2887 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 | ||
| 2888 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a | ||
| 2889 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 | ||
| 2890 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b | ||
| 2891 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 | ||
| 2892 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d | ||
| 2893 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 | ||
| 2894 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e | ||
| 2895 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 | ||
| 2896 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f | ||
| 2897 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 | ||
| 2898 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc | ||
| 2899 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 | ||
| 2900 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd | ||
| 2901 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 | ||
| 2902 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe | ||
| 2903 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 | ||
| 2904 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf | ||
| 2905 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 | ||
| 2906 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 | ||
| 2907 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 | ||
| 2908 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 | ||
| 2909 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 | ||
| 2910 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 | ||
| 2911 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 | ||
| 2912 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a | ||
| 2913 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 | ||
| 2914 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b | ||
| 2915 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 | ||
| 2916 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d | ||
| 2917 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 | ||
| 2918 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e | ||
| 2919 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 | ||
| 2920 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f | ||
| 2921 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff | ||
| 2922 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 | ||
| 2923 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 | ||
| 2924 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 | ||
| 2925 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 | ||
| 2926 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 | ||
| 2927 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 | ||
| 2928 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 | ||
| 2929 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2930 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2931 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2932 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2933 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2934 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2935 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2936 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2937 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff | ||
| 2938 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 | ||
| 2939 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 | ||
| 2940 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 | ||
| 2941 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 | ||
| 2942 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 | ||
| 2943 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 | ||
| 2944 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 | ||
| 2945 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2946 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2947 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2948 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2949 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2950 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2951 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 | ||
| 2952 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 | ||
| 2953 | #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff | ||
| 2954 | #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 | ||
| 2955 | #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff | ||
| 2956 | #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 | ||
| 2957 | #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff | ||
| 2958 | #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 | ||
| 2959 | #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff | ||
| 2960 | #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 | ||
| 2961 | #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff | ||
| 2962 | #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 | ||
| 2963 | #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff | ||
| 2964 | #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 | ||
| 2965 | #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff | ||
| 2966 | #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 | ||
| 2967 | #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff | ||
| 2968 | #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 | ||
| 2969 | #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff | ||
| 2970 | #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 | ||
| 2971 | #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff | ||
| 2972 | #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 | ||
| 2973 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 | ||
| 2974 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 | ||
| 2975 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 | ||
| 2976 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 | ||
| 2977 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 | ||
| 2978 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 | ||
| 2979 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 | ||
| 2980 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 | ||
| 2981 | #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 | ||
| 2982 | #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 | ||
| 2983 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff | ||
| 2984 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 | ||
| 2985 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 | ||
| 2986 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 | ||
| 2987 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 | ||
| 2988 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 | ||
| 2989 | #define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 | ||
| 2990 | #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 | ||
| 2991 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff | ||
| 2992 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 | ||
| 2993 | #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 | ||
| 2994 | #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 | ||
| 2995 | #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 | ||
| 2996 | #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 | ||
| 2997 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 | ||
| 2998 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 | ||
| 2999 | #define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff | ||
| 3000 | #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 | ||
| 3001 | #define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 | ||
| 3002 | #define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 | ||
| 3003 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff | ||
| 3004 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 | ||
| 3005 | #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000 | ||
| 3006 | #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 | ||
| 3007 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff | ||
| 3008 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 | ||
| 3009 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000 | ||
| 3010 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 | ||
| 3011 | #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff | ||
| 3012 | #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 | ||
| 3013 | #define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000 | ||
| 3014 | #define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c | ||
| 3015 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 | ||
| 3016 | #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 | ||
| 3017 | #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 | ||
| 3018 | #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 | ||
| 3019 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000 | ||
| 3020 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc | ||
| 3021 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff | ||
| 3022 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 | ||
| 3023 | #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf | ||
| 3024 | #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 | ||
| 3025 | #define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000 | ||
| 3026 | #define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17 | ||
| 3027 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000 | ||
| 3028 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 | ||
| 3029 | #define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000 | ||
| 3030 | #define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b | ||
| 3031 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1 | ||
| 3032 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 | ||
| 3033 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10 | ||
| 3034 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 | ||
| 3035 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20 | ||
| 3036 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 | ||
| 3037 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 | ||
| 3038 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 | ||
| 3039 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 | ||
| 3040 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 | ||
| 3041 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 | ||
| 3042 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 | ||
| 3043 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 | ||
| 3044 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 | ||
| 3045 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 | ||
| 3046 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 | ||
| 3047 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 | ||
| 3048 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 | ||
| 3049 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 | ||
| 3050 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 | ||
| 3051 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 | ||
| 3052 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 | ||
| 3053 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 | ||
| 3054 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa | ||
| 3055 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 | ||
| 3056 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb | ||
| 3057 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 | ||
| 3058 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc | ||
| 3059 | #define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000 | ||
| 3060 | #define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd | ||
| 3061 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 | ||
| 3062 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d | ||
| 3063 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 | ||
| 3064 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e | ||
| 3065 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 | ||
| 3066 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f | ||
| 3067 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 | ||
| 3068 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 | ||
| 3069 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 | ||
| 3070 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 | ||
| 3071 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 | ||
| 3072 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 | ||
| 3073 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 | ||
| 3074 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 | ||
| 3075 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 | ||
| 3076 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 | ||
| 3077 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 | ||
| 3078 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 | ||
| 3079 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 | ||
| 3080 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 | ||
| 3081 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 | ||
| 3082 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 | ||
| 3083 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 | ||
| 3084 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 | ||
| 3085 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 | ||
| 3086 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 | ||
| 3087 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 | ||
| 3088 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa | ||
| 3089 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 | ||
| 3090 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb | ||
| 3091 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 | ||
| 3092 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc | ||
| 3093 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 | ||
| 3094 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd | ||
| 3095 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 | ||
| 3096 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 | ||
| 3097 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 | ||
| 3098 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 | ||
| 3099 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 | ||
| 3100 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 | ||
| 3101 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 | ||
| 3102 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 | ||
| 3103 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 | ||
| 3104 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 | ||
| 3105 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 | ||
| 3106 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 | ||
| 3107 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 | ||
| 3108 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 | ||
| 3109 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 | ||
| 3110 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 | ||
| 3111 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 | ||
| 3112 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 | ||
| 3113 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 | ||
| 3114 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 | ||
| 3115 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 | ||
| 3116 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a | ||
| 3117 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 | ||
| 3118 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b | ||
| 3119 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 | ||
| 3120 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c | ||
| 3121 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 | ||
| 3122 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d | ||
| 3123 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 | ||
| 3124 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 | ||
| 3125 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 | ||
| 3126 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 | ||
| 3127 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 | ||
| 3128 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 | ||
| 3129 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 | ||
| 3130 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 | ||
| 3131 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 | ||
| 3132 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 | ||
| 3133 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 | ||
| 3134 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa | ||
| 3135 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 | ||
| 3136 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd | ||
| 3137 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 | ||
| 3138 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 | ||
| 3139 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 | ||
| 3140 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 | ||
| 3141 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 | ||
| 3142 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 | ||
| 3143 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 | ||
| 3144 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 | ||
| 3145 | #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000 | ||
| 3146 | #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16 | ||
| 3147 | #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000 | ||
| 3148 | #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17 | ||
| 3149 | #define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000 | ||
| 3150 | #define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18 | ||
| 3151 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 | ||
| 3152 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 | ||
| 3153 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 | ||
| 3154 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 | ||
| 3155 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 | ||
| 3156 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 | ||
| 3157 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 | ||
| 3158 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 | ||
| 3159 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 | ||
| 3160 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 | ||
| 3161 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 | ||
| 3162 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 | ||
| 3163 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 | ||
| 3164 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 | ||
| 3165 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 | ||
| 3166 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 | ||
| 3167 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 | ||
| 3168 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa | ||
| 3169 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 | ||
| 3170 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb | ||
| 3171 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 | ||
| 3172 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc | ||
| 3173 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 | ||
| 3174 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd | ||
| 3175 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 | ||
| 3176 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe | ||
| 3177 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 | ||
| 3178 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf | ||
| 3179 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000 | ||
| 3180 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 | ||
| 3181 | #define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000 | ||
| 3182 | #define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11 | ||
| 3183 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000 | ||
| 3184 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a | ||
| 3185 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000 | ||
| 3186 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b | ||
| 3187 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000 | ||
| 3188 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c | ||
| 3189 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 | ||
| 3190 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e | ||
| 3191 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 | ||
| 3192 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f | ||
| 3193 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 | ||
| 3194 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 | ||
| 3195 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 | ||
| 3196 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 | ||
| 3197 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 | ||
| 3198 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 | ||
| 3199 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 | ||
| 3200 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 | ||
| 3201 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 | ||
| 3202 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 | ||
| 3203 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 | ||
| 3204 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 | ||
| 3205 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 | ||
| 3206 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 | ||
| 3207 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 | ||
| 3208 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 | ||
| 3209 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 | ||
| 3210 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 | ||
| 3211 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 | ||
| 3212 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 | ||
| 3213 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 | ||
| 3214 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb | ||
| 3215 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 | ||
| 3216 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc | ||
| 3217 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 | ||
| 3218 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd | ||
| 3219 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 | ||
| 3220 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe | ||
| 3221 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 | ||
| 3222 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf | ||
| 3223 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 | ||
| 3224 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 | ||
| 3225 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 | ||
| 3226 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 | ||
| 3227 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 | ||
| 3228 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 | ||
| 3229 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 | ||
| 3230 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 | ||
| 3231 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 | ||
| 3232 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 | ||
| 3233 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 | ||
| 3234 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 | ||
| 3235 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 | ||
| 3236 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 | ||
| 3237 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 | ||
| 3238 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 | ||
| 3239 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 | ||
| 3240 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 | ||
| 3241 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 | ||
| 3242 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 | ||
| 3243 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 | ||
| 3244 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a | ||
| 3245 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 | ||
| 3246 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b | ||
| 3247 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 | ||
| 3248 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c | ||
| 3249 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 | ||
| 3250 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d | ||
| 3251 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 | ||
| 3252 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e | ||
| 3253 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 | ||
| 3254 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f | ||
| 3255 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 | ||
| 3256 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 | ||
| 3257 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 | ||
| 3258 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 | ||
| 3259 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 | ||
| 3260 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 | ||
| 3261 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 | ||
| 3262 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 | ||
| 3263 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 | ||
| 3264 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 | ||
| 3265 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 | ||
| 3266 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 | ||
| 3267 | #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80 | ||
| 3268 | #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7 | ||
| 3269 | #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100 | ||
| 3270 | #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8 | ||
| 3271 | #define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200 | ||
| 3272 | #define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9 | ||
| 3273 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f | ||
| 3274 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 | ||
| 3275 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 | ||
| 3276 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 | ||
| 3277 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 | ||
| 3278 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 | ||
| 3279 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000 | ||
| 3280 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 | ||
| 3281 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000 | ||
| 3282 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 | ||
| 3283 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000 | ||
| 3284 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 | ||
| 3285 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 | ||
| 3286 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 | ||
| 3287 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000 | ||
| 3288 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 | ||
| 3289 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 | ||
| 3290 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c | ||
| 3291 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 | ||
| 3292 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d | ||
| 3293 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 | ||
| 3294 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e | ||
| 3295 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 | ||
| 3296 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f | ||
| 3297 | #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff | ||
| 3298 | #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 | ||
| 3299 | #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff | ||
| 3300 | #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 | ||
| 3301 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff | ||
| 3302 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 | ||
| 3303 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff | ||
| 3304 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 | ||
| 3305 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f | ||
| 3306 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3307 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3308 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3309 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3310 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3311 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f | ||
| 3312 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 3313 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 | ||
| 3314 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 3315 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f | ||
| 3316 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3317 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 | ||
| 3318 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 3319 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 3320 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 3321 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3322 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3323 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3324 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3325 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f | ||
| 3326 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3327 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3328 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3329 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3330 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3331 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f | ||
| 3332 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 3333 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 | ||
| 3334 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 3335 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f | ||
| 3336 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3337 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 | ||
| 3338 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 3339 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 3340 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 3341 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3342 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3343 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3344 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3345 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f | ||
| 3346 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3347 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3348 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3349 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3350 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3351 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f | ||
| 3352 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 3353 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 | ||
| 3354 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 3355 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f | ||
| 3356 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 3357 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 | ||
| 3358 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 3359 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 3360 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 3361 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 3362 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 3363 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 3364 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 3365 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf | ||
| 3366 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 | ||
| 3367 | #define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff | ||
| 3368 | #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 | ||
| 3369 | #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff | ||
| 3370 | #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 | ||
| 3371 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff | ||
| 3372 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 | ||
| 3373 | #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff | ||
| 3374 | #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 | ||
| 3375 | #define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff | ||
| 3376 | #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 | ||
| 3377 | #define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 | ||
| 3378 | #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 | ||
| 3379 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 | ||
| 3380 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 | ||
| 3381 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 | ||
| 3382 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 | ||
| 3383 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 | ||
| 3384 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 | ||
| 3385 | #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 | ||
| 3386 | #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 | ||
| 3387 | #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff | ||
| 3388 | #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 | ||
| 3389 | #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff | ||
| 3390 | #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 | ||
| 3391 | #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 | ||
| 3392 | #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 | ||
| 3393 | #define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc | ||
| 3394 | #define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 | ||
| 3395 | #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 | ||
| 3396 | #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa | ||
| 3397 | #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 | ||
| 3398 | #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 | ||
| 3399 | #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 | ||
| 3400 | #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 | ||
| 3401 | #define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 | ||
| 3402 | #define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 | ||
| 3403 | #define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000 | ||
| 3404 | #define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c | ||
| 3405 | #define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000 | ||
| 3406 | #define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e | ||
| 3407 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff | ||
| 3408 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 | ||
| 3409 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff | ||
| 3410 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 | ||
| 3411 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff | ||
| 3412 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 | ||
| 3413 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff | ||
| 3414 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 | ||
| 3415 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff | ||
| 3416 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 | ||
| 3417 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f | ||
| 3418 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 | ||
| 3419 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 | ||
| 3420 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc | ||
| 3421 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000 | ||
| 3422 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 | ||
| 3423 | #define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000 | ||
| 3424 | #define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b | ||
| 3425 | #define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff | ||
| 3426 | #define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 | ||
| 3427 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 | ||
| 3428 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 | ||
| 3429 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 | ||
| 3430 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 | ||
| 3431 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 | ||
| 3432 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d | ||
| 3433 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff | ||
| 3434 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 | ||
| 3435 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc | ||
| 3436 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 | ||
| 3437 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3438 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3439 | #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff | ||
| 3440 | #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 | ||
| 3441 | #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff | ||
| 3442 | #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 | ||
| 3443 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff | ||
| 3444 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 | ||
| 3445 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff | ||
| 3446 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 | ||
| 3447 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc | ||
| 3448 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 | ||
| 3449 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff | ||
| 3450 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 | ||
| 3451 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff | ||
| 3452 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 | ||
| 3453 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff | ||
| 3454 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 | ||
| 3455 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff | ||
| 3456 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 | ||
| 3457 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff | ||
| 3458 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 | ||
| 3459 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff | ||
| 3460 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 | ||
| 3461 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff | ||
| 3462 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 | ||
| 3463 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff | ||
| 3464 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 | ||
| 3465 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff | ||
| 3466 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 | ||
| 3467 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff | ||
| 3468 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 | ||
| 3469 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff | ||
| 3470 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 | ||
| 3471 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff | ||
| 3472 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 | ||
| 3473 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff | ||
| 3474 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 | ||
| 3475 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff | ||
| 3476 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 | ||
| 3477 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff | ||
| 3478 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 | ||
| 3479 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff | ||
| 3480 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 | ||
| 3481 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff | ||
| 3482 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 | ||
| 3483 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc | ||
| 3484 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 | ||
| 3485 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff | ||
| 3486 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 | ||
| 3487 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff | ||
| 3488 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 | ||
| 3489 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff | ||
| 3490 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 | ||
| 3491 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff | ||
| 3492 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 | ||
| 3493 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff | ||
| 3494 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 | ||
| 3495 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff | ||
| 3496 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 | ||
| 3497 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff | ||
| 3498 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 | ||
| 3499 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3500 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3501 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3502 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3503 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3504 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3505 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3506 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3507 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3508 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3509 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3510 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3511 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3512 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3513 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3514 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3515 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3516 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3517 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3518 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3519 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff | ||
| 3520 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 | ||
| 3521 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff | ||
| 3522 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 | ||
| 3523 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff | ||
| 3524 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 | ||
| 3525 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff | ||
| 3526 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 | ||
| 3527 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff | ||
| 3528 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 | ||
| 3529 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff | ||
| 3530 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 | ||
| 3531 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff | ||
| 3532 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 | ||
| 3533 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff | ||
| 3534 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 | ||
| 3535 | #define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000 | ||
| 3536 | #define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19 | ||
| 3537 | #define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000 | ||
| 3538 | #define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b | ||
| 3539 | #define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000 | ||
| 3540 | #define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19 | ||
| 3541 | #define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000 | ||
| 3542 | #define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b | ||
| 3543 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 | ||
| 3544 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 | ||
| 3545 | #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff | ||
| 3546 | #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 | ||
| 3547 | #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff | ||
| 3548 | #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 | ||
| 3549 | #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff | ||
| 3550 | #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 | ||
| 3551 | #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff | ||
| 3552 | #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 | ||
| 3553 | #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff | ||
| 3554 | #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 | ||
| 3555 | #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff | ||
| 3556 | #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 | ||
| 3557 | #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff | ||
| 3558 | #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 | ||
| 3559 | #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff | ||
| 3560 | #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 | ||
| 3561 | #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff | ||
| 3562 | #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 | ||
| 3563 | #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 | ||
| 3564 | #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 | ||
| 3565 | #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff | ||
| 3566 | #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 | ||
| 3567 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff | ||
| 3568 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 | ||
| 3569 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff | ||
| 3570 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 | ||
| 3571 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff | ||
| 3572 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 | ||
| 3573 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff | ||
| 3574 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 | ||
| 3575 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff | ||
| 3576 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 | ||
| 3577 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff | ||
| 3578 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 | ||
| 3579 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc | ||
| 3580 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 | ||
| 3581 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff | ||
| 3582 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 | ||
| 3583 | #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 | ||
| 3584 | #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 | ||
| 3585 | #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000 | ||
| 3586 | #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 | ||
| 3587 | #define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000 | ||
| 3588 | #define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b | ||
| 3589 | #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 | ||
| 3590 | #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d | ||
| 3591 | #define CP_APPEND_DATA__DATA_MASK 0xffffffff | ||
| 3592 | #define CP_APPEND_DATA__DATA__SHIFT 0x0 | ||
| 3593 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff | ||
| 3594 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 | ||
| 3595 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff | ||
| 3596 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 | ||
| 3597 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff | ||
| 3598 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 | ||
| 3599 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff | ||
| 3600 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 | ||
| 3601 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff | ||
| 3602 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 | ||
| 3603 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff | ||
| 3604 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 | ||
| 3605 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff | ||
| 3606 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 | ||
| 3607 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff | ||
| 3608 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 | ||
| 3609 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff | ||
| 3610 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 | ||
| 3611 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff | ||
| 3612 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 | ||
| 3613 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff | ||
| 3614 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 | ||
| 3615 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff | ||
| 3616 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 | ||
| 3617 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff | ||
| 3618 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 | ||
| 3619 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff | ||
| 3620 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 | ||
| 3621 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 | ||
| 3622 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 | ||
| 3623 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc | ||
| 3624 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 | ||
| 3625 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff | ||
| 3626 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 | ||
| 3627 | #define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000 | ||
| 3628 | #define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14 | ||
| 3629 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000 | ||
| 3630 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 | ||
| 3631 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff | ||
| 3632 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 | ||
| 3633 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff | ||
| 3634 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 | ||
| 3635 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 | ||
| 3636 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 | ||
| 3637 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc | ||
| 3638 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 | ||
| 3639 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff | ||
| 3640 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 | ||
| 3641 | #define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000 | ||
| 3642 | #define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14 | ||
| 3643 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000 | ||
| 3644 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 | ||
| 3645 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff | ||
| 3646 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 | ||
| 3647 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 | ||
| 3648 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 | ||
| 3649 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 | ||
| 3650 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 | ||
| 3651 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff | ||
| 3652 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 | ||
| 3653 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 | ||
| 3654 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 | ||
| 3655 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 | ||
| 3656 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 | ||
| 3657 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 | ||
| 3658 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 | ||
| 3659 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 | ||
| 3660 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d | ||
| 3661 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 | ||
| 3662 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 | ||
| 3663 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 | ||
| 3664 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 | ||
| 3665 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff | ||
| 3666 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 | ||
| 3667 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 | ||
| 3668 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 | ||
| 3669 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 | ||
| 3670 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 | ||
| 3671 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 | ||
| 3672 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 | ||
| 3673 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 | ||
| 3674 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d | ||
| 3675 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff | ||
| 3676 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 | ||
| 3677 | #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f | ||
| 3678 | #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 | ||
| 3679 | #define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 | ||
| 3680 | #define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 | ||
| 3681 | #define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 | ||
| 3682 | #define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 | ||
| 3683 | #define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4 | ||
| 3684 | #define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2 | ||
| 3685 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8 | ||
| 3686 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 | ||
| 3687 | #define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 | ||
| 3688 | #define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 | ||
| 3689 | #define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 | ||
| 3690 | #define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 | ||
| 3691 | #define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 | ||
| 3692 | #define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 | ||
| 3693 | #define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 | ||
| 3694 | #define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 | ||
| 3695 | #define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 | ||
| 3696 | #define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa | ||
| 3697 | #define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 | ||
| 3698 | #define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb | ||
| 3699 | #define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 | ||
| 3700 | #define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc | ||
| 3701 | #define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 | ||
| 3702 | #define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd | ||
| 3703 | #define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 | ||
| 3704 | #define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe | ||
| 3705 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 | ||
| 3706 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf | ||
| 3707 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 | ||
| 3708 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 | ||
| 3709 | #define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 | ||
| 3710 | #define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 | ||
| 3711 | #define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 | ||
| 3712 | #define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 | ||
| 3713 | #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 | ||
| 3714 | #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 | ||
| 3715 | #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 | ||
| 3716 | #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 | ||
| 3717 | #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 | ||
| 3718 | #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 | ||
| 3719 | #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 | ||
| 3720 | #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a | ||
| 3721 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 | ||
| 3722 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b | ||
| 3723 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 | ||
| 3724 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c | ||
| 3725 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 | ||
| 3726 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d | ||
| 3727 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000 | ||
| 3728 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e | ||
| 3729 | #define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000 | ||
| 3730 | #define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f | ||
| 3731 | #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff | ||
| 3732 | #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 | ||
| 3733 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff | ||
| 3734 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 | ||
| 3735 | #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff | ||
| 3736 | #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 | ||
| 3737 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff | ||
| 3738 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 | ||
| 3739 | #define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff | ||
| 3740 | #define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 | ||
| 3741 | #define CP_COHER_STATUS__MEID_MASK 0x3000000 | ||
| 3742 | #define CP_COHER_STATUS__MEID__SHIFT 0x18 | ||
| 3743 | #define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 | ||
| 3744 | #define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e | ||
| 3745 | #define CP_COHER_STATUS__STATUS_MASK 0x80000000 | ||
| 3746 | #define CP_COHER_STATUS__STATUS__SHIFT 0x1f | ||
| 3747 | #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff | ||
| 3748 | #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 | ||
| 3749 | #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff | ||
| 3750 | #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 | ||
| 3751 | #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff | ||
| 3752 | #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 | ||
| 3753 | #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff | ||
| 3754 | #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 | ||
| 3755 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff | ||
| 3756 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 | ||
| 3757 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff | ||
| 3758 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 | ||
| 3759 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff | ||
| 3760 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 | ||
| 3761 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff | ||
| 3762 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 | ||
| 3763 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff | ||
| 3764 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 | ||
| 3765 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff | ||
| 3766 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 | ||
| 3767 | #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff | ||
| 3768 | #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 | ||
| 3769 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff | ||
| 3770 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 | ||
| 3771 | #define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00 | ||
| 3772 | #define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa | ||
| 3773 | #define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 | ||
| 3774 | #define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc | ||
| 3775 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 | ||
| 3776 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd | ||
| 3777 | #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 | ||
| 3778 | #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 | ||
| 3779 | #define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000 | ||
| 3780 | #define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16 | ||
| 3781 | #define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 | ||
| 3782 | #define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 | ||
| 3783 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 | ||
| 3784 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 | ||
| 3785 | #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 | ||
| 3786 | #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d | ||
| 3787 | #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff | ||
| 3788 | #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 | ||
| 3789 | #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 | ||
| 3790 | #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 | ||
| 3791 | #define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 | ||
| 3792 | #define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 | ||
| 3793 | #define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 | ||
| 3794 | #define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 | ||
| 3795 | #define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 | ||
| 3796 | #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a | ||
| 3797 | #define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 | ||
| 3798 | #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b | ||
| 3799 | #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 | ||
| 3800 | #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c | ||
| 3801 | #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 | ||
| 3802 | #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d | ||
| 3803 | #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 | ||
| 3804 | #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e | ||
| 3805 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff | ||
| 3806 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 | ||
| 3807 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff | ||
| 3808 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 | ||
| 3809 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff | ||
| 3810 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 | ||
| 3811 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff | ||
| 3812 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 | ||
| 3813 | #define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00 | ||
| 3814 | #define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa | ||
| 3815 | #define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 | ||
| 3816 | #define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc | ||
| 3817 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 | ||
| 3818 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd | ||
| 3819 | #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 | ||
| 3820 | #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 | ||
| 3821 | #define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000 | ||
| 3822 | #define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16 | ||
| 3823 | #define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 | ||
| 3824 | #define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 | ||
| 3825 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 | ||
| 3826 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 | ||
| 3827 | #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 | ||
| 3828 | #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d | ||
| 3829 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff | ||
| 3830 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 | ||
| 3831 | #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 | ||
| 3832 | #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 | ||
| 3833 | #define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 | ||
| 3834 | #define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 | ||
| 3835 | #define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 | ||
| 3836 | #define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 | ||
| 3837 | #define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 | ||
| 3838 | #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a | ||
| 3839 | #define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 | ||
| 3840 | #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b | ||
| 3841 | #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 | ||
| 3842 | #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c | ||
| 3843 | #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 | ||
| 3844 | #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d | ||
| 3845 | #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 | ||
| 3846 | #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e | ||
| 3847 | #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 | ||
| 3848 | #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 | ||
| 3849 | #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 | ||
| 3850 | #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 | ||
| 3851 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 | ||
| 3852 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c | ||
| 3853 | #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 | ||
| 3854 | #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d | ||
| 3855 | #define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 | ||
| 3856 | #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e | ||
| 3857 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff | ||
| 3858 | #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 | ||
| 3859 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 | ||
| 3860 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c | ||
| 3861 | #define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff | ||
| 3862 | #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 | ||
| 3863 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 | ||
| 3864 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 | ||
| 3865 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 | ||
| 3866 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 | ||
| 3867 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 | ||
| 3868 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 | ||
| 3869 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 | ||
| 3870 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 | ||
| 3871 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff | ||
| 3872 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 | ||
| 3873 | #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff | ||
| 3874 | #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 | ||
| 3875 | #define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff | ||
| 3876 | #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 | ||
| 3877 | #define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff | ||
| 3878 | #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 | ||
| 3879 | #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff | ||
| 3880 | #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 | ||
| 3881 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff | ||
| 3882 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 | ||
| 3883 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff | ||
| 3884 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 | ||
| 3885 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff | ||
| 3886 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 | ||
| 3887 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff | ||
| 3888 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 | ||
| 3889 | #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff | ||
| 3890 | #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 | ||
| 3891 | #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff | ||
| 3892 | #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 | ||
| 3893 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff | ||
| 3894 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 | ||
| 3895 | #define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff | ||
| 3896 | #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 | ||
| 3897 | #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3 | ||
| 3898 | #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 | ||
| 3899 | #define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3 | ||
| 3900 | #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 | ||
| 3901 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1 | ||
| 3902 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 | ||
| 3903 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3904 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3905 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3906 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3907 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3908 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3909 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3910 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3911 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3912 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3913 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3914 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3915 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3916 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3917 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3918 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3919 | #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3920 | #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3921 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3922 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3923 | #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3 | ||
| 3924 | #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 | ||
| 3925 | #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff | ||
| 3926 | #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 | ||
| 3927 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 3928 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 3929 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1 | ||
| 3930 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 | ||
| 3931 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2 | ||
| 3932 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 | ||
| 3933 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4 | ||
| 3934 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 | ||
| 3935 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8 | ||
| 3936 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 | ||
| 3937 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10 | ||
| 3938 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 | ||
| 3939 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20 | ||
| 3940 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 | ||
| 3941 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40 | ||
| 3942 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 | ||
| 3943 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80 | ||
| 3944 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 | ||
| 3945 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 | ||
| 3946 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 | ||
| 3947 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 | ||
| 3948 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 | ||
| 3949 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 | ||
| 3950 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 | ||
| 3951 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 | ||
| 3952 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa | ||
| 3953 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 | ||
| 3954 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb | ||
| 3955 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 | ||
| 3956 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc | ||
| 3957 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 | ||
| 3958 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd | ||
| 3959 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000 | ||
| 3960 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe | ||
| 3961 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 | ||
| 3962 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf | ||
| 3963 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 | ||
| 3964 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 | ||
| 3965 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 | ||
| 3966 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 | ||
| 3967 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 | ||
| 3968 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 | ||
| 3969 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 | ||
| 3970 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a | ||
| 3971 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 | ||
| 3972 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b | ||
| 3973 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 | ||
| 3974 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c | ||
| 3975 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 | ||
| 3976 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d | ||
| 3977 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 | ||
| 3978 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 | ||
| 3979 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 | ||
| 3980 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 | ||
| 3981 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 | ||
| 3982 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 | ||
| 3983 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 | ||
| 3984 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 | ||
| 3985 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 | ||
| 3986 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 | ||
| 3987 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 | ||
| 3988 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 | ||
| 3989 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 | ||
| 3990 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 | ||
| 3991 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 | ||
| 3992 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa | ||
| 3993 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 | ||
| 3994 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb | ||
| 3995 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 | ||
| 3996 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc | ||
| 3997 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 | ||
| 3998 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd | ||
| 3999 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 | ||
| 4000 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe | ||
| 4001 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 | ||
| 4002 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf | ||
| 4003 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 | ||
| 4004 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 | ||
| 4005 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 | ||
| 4006 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 | ||
| 4007 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 | ||
| 4008 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 | ||
| 4009 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 | ||
| 4010 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 | ||
| 4011 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 | ||
| 4012 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 | ||
| 4013 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 | ||
| 4014 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 | ||
| 4015 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 | ||
| 4016 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 | ||
| 4017 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 | ||
| 4018 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 | ||
| 4019 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 | ||
| 4020 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 | ||
| 4021 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 | ||
| 4022 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 | ||
| 4023 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 | ||
| 4024 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a | ||
| 4025 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 | ||
| 4026 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b | ||
| 4027 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 | ||
| 4028 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c | ||
| 4029 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 | ||
| 4030 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d | ||
| 4031 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 | ||
| 4032 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e | ||
| 4033 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 | ||
| 4034 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f | ||
| 4035 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 | ||
| 4036 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 | ||
| 4037 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 | ||
| 4038 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 | ||
| 4039 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 | ||
| 4040 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 | ||
| 4041 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 | ||
| 4042 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 | ||
| 4043 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 | ||
| 4044 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 | ||
| 4045 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 | ||
| 4046 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 | ||
| 4047 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 | ||
| 4048 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 | ||
| 4049 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 | ||
| 4050 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 | ||
| 4051 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 | ||
| 4052 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa | ||
| 4053 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 | ||
| 4054 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb | ||
| 4055 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 | ||
| 4056 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc | ||
| 4057 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 | ||
| 4058 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd | ||
| 4059 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 | ||
| 4060 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe | ||
| 4061 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 | ||
| 4062 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf | ||
| 4063 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000 | ||
| 4064 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 | ||
| 4065 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000 | ||
| 4066 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 | ||
| 4067 | #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000 | ||
| 4068 | #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12 | ||
| 4069 | #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000 | ||
| 4070 | #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13 | ||
| 4071 | #define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000 | ||
| 4072 | #define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14 | ||
| 4073 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 | ||
| 4074 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 | ||
| 4075 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 | ||
| 4076 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 | ||
| 4077 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 | ||
| 4078 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 | ||
| 4079 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 | ||
| 4080 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 | ||
| 4081 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 | ||
| 4082 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 | ||
| 4083 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 | ||
| 4084 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa | ||
| 4085 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 | ||
| 4086 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc | ||
| 4087 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 | ||
| 4088 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd | ||
| 4089 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 | ||
| 4090 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe | ||
| 4091 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 | ||
| 4092 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf | ||
| 4093 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 | ||
| 4094 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 | ||
| 4095 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 | ||
| 4096 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 | ||
| 4097 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 | ||
| 4098 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 | ||
| 4099 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 | ||
| 4100 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 | ||
| 4101 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 | ||
| 4102 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 | ||
| 4103 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 | ||
| 4104 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 | ||
| 4105 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x200 | ||
| 4106 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 | ||
| 4107 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 | ||
| 4108 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa | ||
| 4109 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 | ||
| 4110 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb | ||
| 4111 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 | ||
| 4112 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc | ||
| 4113 | #define CP_STAT__DC_BUSY_MASK 0x2000 | ||
| 4114 | #define CP_STAT__DC_BUSY__SHIFT 0xd | ||
| 4115 | #define CP_STAT__ATCL2IU_BUSY_MASK 0x4000 | ||
| 4116 | #define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe | ||
| 4117 | #define CP_STAT__PFP_BUSY_MASK 0x8000 | ||
| 4118 | #define CP_STAT__PFP_BUSY__SHIFT 0xf | ||
| 4119 | #define CP_STAT__MEQ_BUSY_MASK 0x10000 | ||
| 4120 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 | ||
| 4121 | #define CP_STAT__ME_BUSY_MASK 0x20000 | ||
| 4122 | #define CP_STAT__ME_BUSY__SHIFT 0x11 | ||
| 4123 | #define CP_STAT__QUERY_BUSY_MASK 0x40000 | ||
| 4124 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 | ||
| 4125 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 | ||
| 4126 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 | ||
| 4127 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 | ||
| 4128 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 | ||
| 4129 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 | ||
| 4130 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 | ||
| 4131 | #define CP_STAT__DMA_BUSY_MASK 0x400000 | ||
| 4132 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 | ||
| 4133 | #define CP_STAT__RCIU_BUSY_MASK 0x800000 | ||
| 4134 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 | ||
| 4135 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 | ||
| 4136 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 | ||
| 4137 | #define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 | ||
| 4138 | #define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 | ||
| 4139 | #define CP_STAT__CE_BUSY_MASK 0x4000000 | ||
| 4140 | #define CP_STAT__CE_BUSY__SHIFT 0x1a | ||
| 4141 | #define CP_STAT__TCIU_BUSY_MASK 0x8000000 | ||
| 4142 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b | ||
| 4143 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 | ||
| 4144 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c | ||
| 4145 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 | ||
| 4146 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d | ||
| 4147 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 | ||
| 4148 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e | ||
| 4149 | #define CP_STAT__CP_BUSY_MASK 0x80000000 | ||
| 4150 | #define CP_STAT__CP_BUSY__SHIFT 0x1f | ||
| 4151 | #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff | ||
| 4152 | #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 | ||
| 4153 | #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff | ||
| 4154 | #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 | ||
| 4155 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f | ||
| 4156 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 | ||
| 4157 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 | ||
| 4158 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 | ||
| 4159 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 | ||
| 4160 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 | ||
| 4161 | #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff | ||
| 4162 | #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 | ||
| 4163 | #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf | ||
| 4164 | #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 | ||
| 4165 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00 | ||
| 4166 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 | ||
| 4167 | #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf | ||
| 4168 | #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 | ||
| 4169 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 | ||
| 4170 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 | ||
| 4171 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 | ||
| 4172 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 | ||
| 4173 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 | ||
| 4174 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 | ||
| 4175 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000 | ||
| 4176 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 | ||
| 4177 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000 | ||
| 4178 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 | ||
| 4179 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000 | ||
| 4180 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 | ||
| 4181 | #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 | ||
| 4182 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 | ||
| 4183 | #define CP_ME_CNTL__CE_STEP_MASK 0x2000000 | ||
| 4184 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 | ||
| 4185 | #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 | ||
| 4186 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a | ||
| 4187 | #define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 | ||
| 4188 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b | ||
| 4189 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 | ||
| 4190 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c | ||
| 4191 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000 | ||
| 4192 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d | ||
| 4193 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff | ||
| 4194 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 | ||
| 4195 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 | ||
| 4196 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 | ||
| 4197 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 | ||
| 4198 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 | ||
| 4199 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 | ||
| 4200 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c | ||
| 4201 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1 | ||
| 4202 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 | ||
| 4203 | #define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff | ||
| 4204 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 | ||
| 4205 | #define CP_RB_RPTR__RB_RPTR_MASK 0xfffff | ||
| 4206 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 | ||
| 4207 | #define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff | ||
| 4208 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 | ||
| 4209 | #define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff | ||
| 4210 | #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 | ||
| 4211 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff | ||
| 4212 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 | ||
| 4213 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 | ||
| 4214 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c | ||
| 4215 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff | ||
| 4216 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 | ||
| 4217 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 | ||
| 4218 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 | ||
| 4219 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 | ||
| 4220 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 | ||
| 4221 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff | ||
| 4222 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 | ||
| 4223 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff | ||
| 4224 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 | ||
| 4225 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc | ||
| 4226 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 | ||
| 4227 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff | ||
| 4228 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 | ||
| 4229 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff | ||
| 4230 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 | ||
| 4231 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc | ||
| 4232 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 | ||
| 4233 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff | ||
| 4234 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 | ||
| 4235 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff | ||
| 4236 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 | ||
| 4237 | #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc | ||
| 4238 | #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 | ||
| 4239 | #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff | ||
| 4240 | #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 | ||
| 4241 | #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff | ||
| 4242 | #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 | ||
| 4243 | #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc | ||
| 4244 | #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 | ||
| 4245 | #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff | ||
| 4246 | #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 | ||
| 4247 | #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff | ||
| 4248 | #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 | ||
| 4249 | #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc | ||
| 4250 | #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 | ||
| 4251 | #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff | ||
| 4252 | #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 | ||
| 4253 | #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff | ||
| 4254 | #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 | ||
| 4255 | #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff | ||
| 4256 | #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 | ||
| 4257 | #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 | ||
| 4258 | #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 | ||
| 4259 | #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff | ||
| 4260 | #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 | ||
| 4261 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff | ||
| 4262 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 | ||
| 4263 | #define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 | ||
| 4264 | #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 | ||
| 4265 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 | ||
| 4266 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 | ||
| 4267 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 | ||
| 4268 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 | ||
| 4269 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff | ||
| 4270 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 | ||
| 4271 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 | ||
| 4272 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 | ||
| 4273 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 | ||
| 4274 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 | ||
| 4275 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 | ||
| 4276 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 | ||
| 4277 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff | ||
| 4278 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 | ||
| 4279 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 | ||
| 4280 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 | ||
| 4281 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 | ||
| 4282 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 | ||
| 4283 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f | ||
| 4284 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 | ||
| 4285 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 | ||
| 4286 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 | ||
| 4287 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff | ||
| 4288 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 | ||
| 4289 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 | ||
| 4290 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 | ||
| 4291 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff | ||
| 4292 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 | ||
| 4293 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 | ||
| 4294 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 | ||
| 4295 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff | ||
| 4296 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 | ||
| 4297 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff | ||
| 4298 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 | ||
| 4299 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff | ||
| 4300 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 | ||
| 4301 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff | ||
| 4302 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 | ||
| 4303 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 | ||
| 4304 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc | ||
| 4305 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000 | ||
| 4306 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 | ||
| 4307 | #define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff | ||
| 4308 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 | ||
| 4309 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff | ||
| 4310 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 | ||
| 4311 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 | ||
| 4312 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 | ||
| 4313 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff | ||
| 4314 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 | ||
| 4315 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 | ||
| 4316 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 | ||
| 4317 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff | ||
| 4318 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 | ||
| 4319 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 | ||
| 4320 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 | ||
| 4321 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff | ||
| 4322 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 | ||
| 4323 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff | ||
| 4324 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 | ||
| 4325 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff | ||
| 4326 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 | ||
| 4327 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 | ||
| 4328 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 | ||
| 4329 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff | ||
| 4330 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 | ||
| 4331 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 | ||
| 4332 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 | ||
| 4333 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff | ||
| 4334 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 | ||
| 4335 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff | ||
| 4336 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 | ||
| 4337 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 | ||
| 4338 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 | ||
| 4339 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff | ||
| 4340 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 | ||
| 4341 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 | ||
| 4342 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 | ||
| 4343 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff | ||
| 4344 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 | ||
| 4345 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 | ||
| 4346 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 | ||
| 4347 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800 | ||
| 4348 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb | ||
| 4349 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 | ||
| 4350 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe | ||
| 4351 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 | ||
| 4352 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 | ||
| 4353 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000 | ||
| 4354 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 | ||
| 4355 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 | ||
| 4356 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 | ||
| 4357 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 | ||
| 4358 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 | ||
| 4359 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000 | ||
| 4360 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 | ||
| 4361 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 | ||
| 4362 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 | ||
| 4363 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 | ||
| 4364 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 | ||
| 4365 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 | ||
| 4366 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 | ||
| 4367 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 | ||
| 4368 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a | ||
| 4369 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 | ||
| 4370 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b | ||
| 4371 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 | ||
| 4372 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d | ||
| 4373 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 | ||
| 4374 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e | ||
| 4375 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 | ||
| 4376 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f | ||
| 4377 | #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf | ||
| 4378 | #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 | ||
| 4379 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 | ||
| 4380 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 | ||
| 4381 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 | ||
| 4382 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 | ||
| 4383 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 | ||
| 4384 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa | ||
| 4385 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 | ||
| 4386 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f | ||
| 4387 | #define CP_RINGID__RINGID_MASK 0x3 | ||
| 4388 | #define CP_RINGID__RINGID__SHIFT 0x0 | ||
| 4389 | #define CP_PIPEID__PIPE_ID_MASK 0x3 | ||
| 4390 | #define CP_PIPEID__PIPE_ID__SHIFT 0x0 | ||
| 4391 | #define CP_VMID__VMID_MASK 0xf | ||
| 4392 | #define CP_VMID__VMID__SHIFT 0x0 | ||
| 4393 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 | ||
| 4394 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 | ||
| 4395 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 | ||
| 4396 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 | ||
| 4397 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 | ||
| 4398 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 | ||
| 4399 | #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f | ||
| 4400 | #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 | ||
| 4401 | #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0 | ||
| 4402 | #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 | ||
| 4403 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00 | ||
| 4404 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 | ||
| 4405 | #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc | ||
| 4406 | #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 | ||
| 4407 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff | ||
| 4408 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 | ||
| 4409 | #define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 | ||
| 4410 | #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 | ||
| 4411 | #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2 | ||
| 4412 | #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 | ||
| 4413 | #define CP_HQD_VMID__VMID_MASK 0xf | ||
| 4414 | #define CP_HQD_VMID__VMID__SHIFT 0x0 | ||
| 4415 | #define CP_HQD_VMID__IB_VMID_MASK 0xf00 | ||
| 4416 | #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 | ||
| 4417 | #define CP_HQD_VMID__VQID_MASK 0x3ff0000 | ||
| 4418 | #define CP_HQD_VMID__VQID__SHIFT 0x10 | ||
| 4419 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 | ||
| 4420 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 | ||
| 4421 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 | ||
| 4422 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 | ||
| 4423 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000 | ||
| 4424 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c | ||
| 4425 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000 | ||
| 4426 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d | ||
| 4427 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000 | ||
| 4428 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e | ||
| 4429 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 | ||
| 4430 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f | ||
| 4431 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 | ||
| 4432 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 | ||
| 4433 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf | ||
| 4434 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 | ||
| 4435 | #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 | ||
| 4436 | #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 | ||
| 4437 | #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 | ||
| 4438 | #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 | ||
| 4439 | #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 | ||
| 4440 | #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 | ||
| 4441 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000 | ||
| 4442 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f | ||
| 4443 | #define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff | ||
| 4444 | #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 | ||
| 4445 | #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff | ||
| 4446 | #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 | ||
| 4447 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff | ||
| 4448 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 | ||
| 4449 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc | ||
| 4450 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 | ||
| 4451 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff | ||
| 4452 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 | ||
| 4453 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc | ||
| 4454 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 | ||
| 4455 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff | ||
| 4456 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 | ||
| 4457 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1 | ||
| 4458 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 | ||
| 4459 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2 | ||
| 4460 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 | ||
| 4461 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc | ||
| 4462 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 | ||
| 4463 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000 | ||
| 4464 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17 | ||
| 4465 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 | ||
| 4466 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c | ||
| 4467 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 | ||
| 4468 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d | ||
| 4469 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 | ||
| 4470 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e | ||
| 4471 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 | ||
| 4472 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f | ||
| 4473 | #define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff | ||
| 4474 | #define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 | ||
| 4475 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f | ||
| 4476 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 | ||
| 4477 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 | ||
| 4478 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 | ||
| 4479 | #define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000 | ||
| 4480 | #define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf | ||
| 4481 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000 | ||
| 4482 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 | ||
| 4483 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 | ||
| 4484 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 | ||
| 4485 | #define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 | ||
| 4486 | #define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 | ||
| 4487 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000 | ||
| 4488 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 | ||
| 4489 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 | ||
| 4490 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 | ||
| 4491 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 | ||
| 4492 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b | ||
| 4493 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 | ||
| 4494 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c | ||
| 4495 | #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 | ||
| 4496 | #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d | ||
| 4497 | #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 | ||
| 4498 | #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e | ||
| 4499 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 | ||
| 4500 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f | ||
| 4501 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc | ||
| 4502 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 | ||
| 4503 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff | ||
| 4504 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 | ||
| 4505 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff | ||
| 4506 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 | ||
| 4507 | #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff | ||
| 4508 | #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 | ||
| 4509 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 | ||
| 4510 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 | ||
| 4511 | #define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 | ||
| 4512 | #define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 | ||
| 4513 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000 | ||
| 4514 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 | ||
| 4515 | #define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000 | ||
| 4516 | #define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b | ||
| 4517 | #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 | ||
| 4518 | #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f | ||
| 4519 | #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff | ||
| 4520 | #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 | ||
| 4521 | #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 | ||
| 4522 | #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 | ||
| 4523 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800 | ||
| 4524 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb | ||
| 4525 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 | ||
| 4526 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc | ||
| 4527 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000 | ||
| 4528 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe | ||
| 4529 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 | ||
| 4530 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 | ||
| 4531 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 | ||
| 4532 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 | ||
| 4533 | #define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 | ||
| 4534 | #define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 | ||
| 4535 | #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000 | ||
| 4536 | #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 | ||
| 4537 | #define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000 | ||
| 4538 | #define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b | ||
| 4539 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 | ||
| 4540 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d | ||
| 4541 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 | ||
| 4542 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e | ||
| 4543 | #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 | ||
| 4544 | #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f | ||
| 4545 | #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f | ||
| 4546 | #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 | ||
| 4547 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7 | ||
| 4548 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 | ||
| 4549 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 | ||
| 4550 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 | ||
| 4551 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 | ||
| 4552 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 | ||
| 4553 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200 | ||
| 4554 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 | ||
| 4555 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400 | ||
| 4556 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa | ||
| 4557 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 | ||
| 4558 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 | ||
| 4559 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1 | ||
| 4560 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 | ||
| 4561 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2 | ||
| 4562 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 | ||
| 4563 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10 | ||
| 4564 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 | ||
| 4565 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20 | ||
| 4566 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 | ||
| 4567 | #define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 | ||
| 4568 | #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 | ||
| 4569 | #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 | ||
| 4570 | #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 | ||
| 4571 | #define CP_HQD_MSG_TYPE__ACTION_MASK 0x7 | ||
| 4572 | #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 | ||
| 4573 | #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70 | ||
| 4574 | #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 | ||
| 4575 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff | ||
| 4576 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 | ||
| 4577 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff | ||
| 4578 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 | ||
| 4579 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff | ||
| 4580 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 | ||
| 4581 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff | ||
| 4582 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 | ||
| 4583 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff | ||
| 4584 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 | ||
| 4585 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3 | ||
| 4586 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 | ||
| 4587 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc | ||
| 4588 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 | ||
| 4589 | #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70 | ||
| 4590 | #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 | ||
| 4591 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80 | ||
| 4592 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 | ||
| 4593 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100 | ||
| 4594 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 | ||
| 4595 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200 | ||
| 4596 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 | ||
| 4597 | #define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00 | ||
| 4598 | #define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa | ||
| 4599 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff | ||
| 4600 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 | ||
| 4601 | #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff | ||
| 4602 | #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 | ||
| 4603 | #define CP_MQD_CONTROL__VMID_MASK 0xf | ||
| 4604 | #define CP_MQD_CONTROL__VMID__SHIFT 0x0 | ||
| 4605 | #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000 | ||
| 4606 | #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc | ||
| 4607 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000 | ||
| 4608 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd | ||
| 4609 | #define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 | ||
| 4610 | #define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 | ||
| 4611 | #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000 | ||
| 4612 | #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 | ||
| 4613 | #define CP_MQD_CONTROL__MTYPE_MASK 0x18000000 | ||
| 4614 | #define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b | ||
| 4615 | #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff | ||
| 4616 | #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 | ||
| 4617 | #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff | ||
| 4618 | #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 | ||
| 4619 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff | ||
| 4620 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 | ||
| 4621 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff | ||
| 4622 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 | ||
| 4623 | #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f | ||
| 4624 | #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 | ||
| 4625 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 | ||
| 4626 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 | ||
| 4627 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 | ||
| 4628 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc | ||
| 4629 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 | ||
| 4630 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd | ||
| 4631 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 | ||
| 4632 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe | ||
| 4633 | #define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000 | ||
| 4634 | #define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf | ||
| 4635 | #define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000 | ||
| 4636 | #define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 | ||
| 4637 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000 | ||
| 4638 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 | ||
| 4639 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 | ||
| 4640 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d | ||
| 4641 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 | ||
| 4642 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f | ||
| 4643 | #define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff | ||
| 4644 | #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 | ||
| 4645 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 | ||
| 4646 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e | ||
| 4647 | #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000 | ||
| 4648 | #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f | ||
| 4649 | #define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff | ||
| 4650 | #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 | ||
| 4651 | #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000 | ||
| 4652 | #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 | ||
| 4653 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff | ||
| 4654 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 | ||
| 4655 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000 | ||
| 4656 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 | ||
| 4657 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000 | ||
| 4658 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc | ||
| 4659 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff | ||
| 4660 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 | ||
| 4661 | #define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1 | ||
| 4662 | #define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0 | ||
| 4663 | #define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6 | ||
| 4664 | #define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1 | ||
| 4665 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8 | ||
| 4666 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 | ||
| 4667 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc | ||
| 4668 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 | ||
| 4669 | #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000 | ||
| 4670 | #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc | ||
| 4671 | #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc | ||
| 4672 | #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 | ||
| 4673 | #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000 | ||
| 4674 | #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc | ||
| 4675 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1 | ||
| 4676 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 | ||
| 4677 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2 | ||
| 4678 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 | ||
| 4679 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0 | ||
| 4680 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 | ||
| 4681 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000 | ||
| 4682 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc | ||
| 4683 | #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf | ||
| 4684 | #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 | ||
| 4685 | #define CP_HQD_ERROR__SUA_ERROR_MASK 0x10 | ||
| 4686 | #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 | ||
| 4687 | #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff | ||
| 4688 | #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 | ||
| 4689 | #define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff | ||
| 4690 | #define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0 | ||
| 4691 | #define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff | ||
| 4692 | #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 | ||
| 4693 | #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff | ||
| 4694 | #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 | ||
| 4695 | #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff | ||
| 4696 | #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 | ||
| 4697 | #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff | ||
| 4698 | #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 | ||
| 4699 | #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf | ||
| 4700 | #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 | ||
| 4701 | #define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 | ||
| 4702 | #define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 | ||
| 4703 | #define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 | ||
| 4704 | #define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 | ||
| 4705 | #define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 | ||
| 4706 | #define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd | ||
| 4707 | #define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 | ||
| 4708 | #define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf | ||
| 4709 | #define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 | ||
| 4710 | #define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 | ||
| 4711 | #define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 | ||
| 4712 | #define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 | ||
| 4713 | #define DB_Z_INFO__FORMAT_MASK 0x3 | ||
| 4714 | #define DB_Z_INFO__FORMAT__SHIFT 0x0 | ||
| 4715 | #define DB_Z_INFO__NUM_SAMPLES_MASK 0xc | ||
| 4716 | #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 | ||
| 4717 | #define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 | ||
| 4718 | #define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd | ||
| 4719 | #define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 | ||
| 4720 | #define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 | ||
| 4721 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000 | ||
| 4722 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 | ||
| 4723 | #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 | ||
| 4724 | #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b | ||
| 4725 | #define DB_Z_INFO__READ_SIZE_MASK 0x10000000 | ||
| 4726 | #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c | ||
| 4727 | #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 | ||
| 4728 | #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d | ||
| 4729 | #define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000 | ||
| 4730 | #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e | ||
| 4731 | #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 | ||
| 4732 | #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f | ||
| 4733 | #define DB_STENCIL_INFO__FORMAT_MASK 0x1 | ||
| 4734 | #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 | ||
| 4735 | #define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 | ||
| 4736 | #define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd | ||
| 4737 | #define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 | ||
| 4738 | #define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 | ||
| 4739 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 | ||
| 4740 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b | ||
| 4741 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 | ||
| 4742 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d | ||
| 4743 | #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000 | ||
| 4744 | #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e | ||
| 4745 | #define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff | ||
| 4746 | #define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 | ||
| 4747 | #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 | ||
| 4748 | #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb | ||
| 4749 | #define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff | ||
| 4750 | #define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 | ||
| 4751 | #define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff | ||
| 4752 | #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 | ||
| 4753 | #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 | ||
| 4754 | #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd | ||
| 4755 | #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 | ||
| 4756 | #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 | ||
| 4757 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 | ||
| 4758 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 | ||
| 4759 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 | ||
| 4760 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 | ||
| 4761 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 | ||
| 4762 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 | ||
| 4763 | #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 | ||
| 4764 | #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 | ||
| 4765 | #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 | ||
| 4766 | #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 | ||
| 4767 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 | ||
| 4768 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 | ||
| 4769 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 | ||
| 4770 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 | ||
| 4771 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 | ||
| 4772 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 | ||
| 4773 | #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 | ||
| 4774 | #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 | ||
| 4775 | #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 | ||
| 4776 | #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 | ||
| 4777 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000 | ||
| 4778 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc | ||
| 4779 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 | ||
| 4780 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 | ||
| 4781 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 | ||
| 4782 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 | ||
| 4783 | #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 | ||
| 4784 | #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 | ||
| 4785 | #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 | ||
| 4786 | #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 | ||
| 4787 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 | ||
| 4788 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc | ||
| 4789 | #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 | ||
| 4790 | #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 | ||
| 4791 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 | ||
| 4792 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 | ||
| 4793 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 | ||
| 4794 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 | ||
| 4795 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 | ||
| 4796 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c | ||
| 4797 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 | ||
| 4798 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 | ||
| 4799 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc | ||
| 4800 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 | ||
| 4801 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 | ||
| 4802 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 | ||
| 4803 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 | ||
| 4804 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 | ||
| 4805 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 | ||
| 4806 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 | ||
| 4807 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 | ||
| 4808 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 | ||
| 4809 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 | ||
| 4810 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 | ||
| 4811 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 | ||
| 4812 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa | ||
| 4813 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 | ||
| 4814 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb | ||
| 4815 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 | ||
| 4816 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc | ||
| 4817 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 | ||
| 4818 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd | ||
| 4819 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 | ||
| 4820 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf | ||
| 4821 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 | ||
| 4822 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 | ||
| 4823 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 | ||
| 4824 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 | ||
| 4825 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 | ||
| 4826 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 | ||
| 4827 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 | ||
| 4828 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 | ||
| 4829 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 | ||
| 4830 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 | ||
| 4831 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 | ||
| 4832 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a | ||
| 4833 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 | ||
| 4834 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b | ||
| 4835 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 | ||
| 4836 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c | ||
| 4837 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 | ||
| 4838 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d | ||
| 4839 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 | ||
| 4840 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e | ||
| 4841 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 | ||
| 4842 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f | ||
| 4843 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 | ||
| 4844 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 | ||
| 4845 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c | ||
| 4846 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 | ||
| 4847 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 | ||
| 4848 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 | ||
| 4849 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 | ||
| 4850 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 | ||
| 4851 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 | ||
| 4852 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 | ||
| 4853 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 | ||
| 4854 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 | ||
| 4855 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 | ||
| 4856 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 | ||
| 4857 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 | ||
| 4858 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa | ||
| 4859 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 | ||
| 4860 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb | ||
| 4861 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 | ||
| 4862 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc | ||
| 4863 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 | ||
| 4864 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf | ||
| 4865 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 | ||
| 4866 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 | ||
| 4867 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 | ||
| 4868 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 | ||
| 4869 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 | ||
| 4870 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 | ||
| 4871 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 | ||
| 4872 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 | ||
| 4873 | #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 | ||
| 4874 | #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 | ||
| 4875 | #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 | ||
| 4876 | #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 | ||
| 4877 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 | ||
| 4878 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 | ||
| 4879 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 | ||
| 4880 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc | ||
| 4881 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 | ||
| 4882 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 | ||
| 4883 | #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 | ||
| 4884 | #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 | ||
| 4885 | #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 | ||
| 4886 | #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 | ||
| 4887 | #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 | ||
| 4888 | #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 | ||
| 4889 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 | ||
| 4890 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 | ||
| 4891 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 | ||
| 4892 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 | ||
| 4893 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 | ||
| 4894 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 | ||
| 4895 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 | ||
| 4896 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b | ||
| 4897 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 | ||
| 4898 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 | ||
| 4899 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 | ||
| 4900 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 | ||
| 4901 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 | ||
| 4902 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 | ||
| 4903 | #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 | ||
| 4904 | #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 | ||
| 4905 | #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 | ||
| 4906 | #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 | ||
| 4907 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 | ||
| 4908 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 | ||
| 4909 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 | ||
| 4910 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 | ||
| 4911 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 | ||
| 4912 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 | ||
| 4913 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 | ||
| 4914 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa | ||
| 4915 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 | ||
| 4916 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb | ||
| 4917 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 | ||
| 4918 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc | ||
| 4919 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 | ||
| 4920 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd | ||
| 4921 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x8000 | ||
| 4922 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf | ||
| 4923 | #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff | ||
| 4924 | #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 | ||
| 4925 | #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff | ||
| 4926 | #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 | ||
| 4927 | #define DB_STENCIL_CLEAR__CLEAR_MASK 0xff | ||
| 4928 | #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 | ||
| 4929 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff | ||
| 4930 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 | ||
| 4931 | #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff | ||
| 4932 | #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 | ||
| 4933 | #define DB_HTILE_SURFACE__LINEAR_MASK 0x1 | ||
| 4934 | #define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 | ||
| 4935 | #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 | ||
| 4936 | #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 | ||
| 4937 | #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 | ||
| 4938 | #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 | ||
| 4939 | #define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 | ||
| 4940 | #define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 | ||
| 4941 | #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 | ||
| 4942 | #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 | ||
| 4943 | #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 | ||
| 4944 | #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa | ||
| 4945 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 | ||
| 4946 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 | ||
| 4947 | #define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000 | ||
| 4948 | #define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11 | ||
| 4949 | #define DB_PRELOAD_CONTROL__START_X_MASK 0xff | ||
| 4950 | #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 | ||
| 4951 | #define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 | ||
| 4952 | #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 | ||
| 4953 | #define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 | ||
| 4954 | #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 | ||
| 4955 | #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 | ||
| 4956 | #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 | ||
| 4957 | #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff | ||
| 4958 | #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 | ||
| 4959 | #define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 | ||
| 4960 | #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 | ||
| 4961 | #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 | ||
| 4962 | #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 | ||
| 4963 | #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 | ||
| 4964 | #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 | ||
| 4965 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff | ||
| 4966 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 | ||
| 4967 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 | ||
| 4968 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 | ||
| 4969 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 | ||
| 4970 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 | ||
| 4971 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 | ||
| 4972 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 | ||
| 4973 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 | ||
| 4974 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 | ||
| 4975 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 | ||
| 4976 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 | ||
| 4977 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 | ||
| 4978 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc | ||
| 4979 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 | ||
| 4980 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 | ||
| 4981 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 | ||
| 4982 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 | ||
| 4983 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 | ||
| 4984 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 | ||
| 4985 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 | ||
| 4986 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc | ||
| 4987 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 | ||
| 4988 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 | ||
| 4989 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 | ||
| 4990 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 | ||
| 4991 | #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 | ||
| 4992 | #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 | ||
| 4993 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 | ||
| 4994 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 | ||
| 4995 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 | ||
| 4996 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 | ||
| 4997 | #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 | ||
| 4998 | #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 | ||
| 4999 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 | ||
| 5000 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 | ||
| 5001 | #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 | ||
| 5002 | #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 | ||
| 5003 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 | ||
| 5004 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 | ||
| 5005 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 | ||
| 5006 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e | ||
| 5007 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 | ||
| 5008 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f | ||
| 5009 | #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf | ||
| 5010 | #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 | ||
| 5011 | #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 | ||
| 5012 | #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 | ||
| 5013 | #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 | ||
| 5014 | #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 | ||
| 5015 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 | ||
| 5016 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc | ||
| 5017 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 | ||
| 5018 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 | ||
| 5019 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 | ||
| 5020 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 | ||
| 5021 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 | ||
| 5022 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 | ||
| 5023 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 | ||
| 5024 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 | ||
| 5025 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 | ||
| 5026 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa | ||
| 5027 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 | ||
| 5028 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc | ||
| 5029 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 | ||
| 5030 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe | ||
| 5031 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 | ||
| 5032 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 | ||
| 5033 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 5034 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 5035 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 5036 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 5037 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 5038 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 5039 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 5040 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 5041 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 5042 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 5043 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 5044 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 5045 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 5046 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 5047 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 5048 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 5049 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 5050 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 5051 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 5052 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 5053 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 5054 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 5055 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 5056 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 5057 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 5058 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 5059 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 5060 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 5061 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 5062 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 5063 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 5064 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 5065 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 5066 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 5067 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 5068 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 5069 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 5070 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 5071 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 5072 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 5073 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 5074 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 5075 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 5076 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 5077 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 5078 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 5079 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 5080 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 5081 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 5082 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 5083 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 5084 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 5085 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 5086 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 5087 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 5088 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 5089 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 5090 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 5091 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 5092 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 5093 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 5094 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 5095 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 5096 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 5097 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 5098 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 5099 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 5100 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 5101 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 5102 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 5103 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 5104 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 5105 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 | ||
| 5106 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 | ||
| 5107 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 | ||
| 5108 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 | ||
| 5109 | #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 | ||
| 5110 | #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 | ||
| 5111 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 | ||
| 5112 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 | ||
| 5113 | #define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 | ||
| 5114 | #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 | ||
| 5115 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 | ||
| 5116 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 | ||
| 5117 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 | ||
| 5118 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 | ||
| 5119 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 | ||
| 5120 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 | ||
| 5121 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 | ||
| 5122 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa | ||
| 5123 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 | ||
| 5124 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc | ||
| 5125 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 | ||
| 5126 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe | ||
| 5127 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 | ||
| 5128 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf | ||
| 5129 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 | ||
| 5130 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 | ||
| 5131 | #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 | ||
| 5132 | #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 | ||
| 5133 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 | ||
| 5134 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 | ||
| 5135 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 | ||
| 5136 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 | ||
| 5137 | #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 | ||
| 5138 | #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 | ||
| 5139 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 | ||
| 5140 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 | ||
| 5141 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 | ||
| 5142 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 | ||
| 5143 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 | ||
| 5144 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 | ||
| 5145 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 | ||
| 5146 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c | ||
| 5147 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 | ||
| 5148 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d | ||
| 5149 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 | ||
| 5150 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e | ||
| 5151 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 | ||
| 5152 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f | ||
| 5153 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 | ||
| 5154 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 | ||
| 5155 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 | ||
| 5156 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 | ||
| 5157 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 | ||
| 5158 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 | ||
| 5159 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 | ||
| 5160 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 | ||
| 5161 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 | ||
| 5162 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 | ||
| 5163 | #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 | ||
| 5164 | #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 | ||
| 5165 | #define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 | ||
| 5166 | #define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 | ||
| 5167 | #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 | ||
| 5168 | #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 | ||
| 5169 | #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 | ||
| 5170 | #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 | ||
| 5171 | #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 | ||
| 5172 | #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 | ||
| 5173 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 | ||
| 5174 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe | ||
| 5175 | #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 | ||
| 5176 | #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf | ||
| 5177 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 | ||
| 5178 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 | ||
| 5179 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 | ||
| 5180 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 | ||
| 5181 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 | ||
| 5182 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 | ||
| 5183 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 | ||
| 5184 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 | ||
| 5185 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 | ||
| 5186 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c | ||
| 5187 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 | ||
| 5188 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d | ||
| 5189 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 | ||
| 5190 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e | ||
| 5191 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 | ||
| 5192 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f | ||
| 5193 | #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 | ||
| 5194 | #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 | ||
| 5195 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 | ||
| 5196 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 | ||
| 5197 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 | ||
| 5198 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 | ||
| 5199 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 | ||
| 5200 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 | ||
| 5201 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 | ||
| 5202 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 | ||
| 5203 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 | ||
| 5204 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 | ||
| 5205 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 | ||
| 5206 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 | ||
| 5207 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 | ||
| 5208 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 | ||
| 5209 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 | ||
| 5210 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa | ||
| 5211 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 | ||
| 5212 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb | ||
| 5213 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 | ||
| 5214 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc | ||
| 5215 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 | ||
| 5216 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd | ||
| 5217 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 | ||
| 5218 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe | ||
| 5219 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 | ||
| 5220 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf | ||
| 5221 | #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 | ||
| 5222 | #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 | ||
| 5223 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 | ||
| 5224 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 | ||
| 5225 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 | ||
| 5226 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 | ||
| 5227 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 | ||
| 5228 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 | ||
| 5229 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 | ||
| 5230 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 | ||
| 5231 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 | ||
| 5232 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 | ||
| 5233 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 | ||
| 5234 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 | ||
| 5235 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 | ||
| 5236 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 | ||
| 5237 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 | ||
| 5238 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 | ||
| 5239 | #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 | ||
| 5240 | #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 | ||
| 5241 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 | ||
| 5242 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a | ||
| 5243 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 | ||
| 5244 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b | ||
| 5245 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 | ||
| 5246 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c | ||
| 5247 | #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 | ||
| 5248 | #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d | ||
| 5249 | #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000 | ||
| 5250 | #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e | ||
| 5251 | #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000 | ||
| 5252 | #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f | ||
| 5253 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 | ||
| 5254 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 | ||
| 5255 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 | ||
| 5256 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 | ||
| 5257 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 | ||
| 5258 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 | ||
| 5259 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 | ||
| 5260 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 | ||
| 5261 | #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x10 | ||
| 5262 | #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 | ||
| 5263 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x20 | ||
| 5264 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 | ||
| 5265 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x40 | ||
| 5266 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 | ||
| 5267 | #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffff80 | ||
| 5268 | #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x7 | ||
| 5269 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f | ||
| 5270 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 | ||
| 5271 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 | ||
| 5272 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 | ||
| 5273 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 | ||
| 5274 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa | ||
| 5275 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 | ||
| 5276 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 | ||
| 5277 | #define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f | ||
| 5278 | #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 | ||
| 5279 | #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 | ||
| 5280 | #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 | ||
| 5281 | #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 | ||
| 5282 | #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb | ||
| 5283 | #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 | ||
| 5284 | #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf | ||
| 5285 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 | ||
| 5286 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 | ||
| 5287 | #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 | ||
| 5288 | #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b | ||
| 5289 | #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 | ||
| 5290 | #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c | ||
| 5291 | #define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 | ||
| 5292 | #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d | ||
| 5293 | #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 | ||
| 5294 | #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e | ||
| 5295 | #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 | ||
| 5296 | #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f | ||
| 5297 | #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 | ||
| 5298 | #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 | ||
| 5299 | #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc | ||
| 5300 | #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 | ||
| 5301 | #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 | ||
| 5302 | #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 | ||
| 5303 | #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 | ||
| 5304 | #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 | ||
| 5305 | #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 | ||
| 5306 | #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 | ||
| 5307 | #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 | ||
| 5308 | #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa | ||
| 5309 | #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 | ||
| 5310 | #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc | ||
| 5311 | #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 | ||
| 5312 | #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe | ||
| 5313 | #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 | ||
| 5314 | #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 | ||
| 5315 | #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 | ||
| 5316 | #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 | ||
| 5317 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f | ||
| 5318 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 | ||
| 5319 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 | ||
| 5320 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 | ||
| 5321 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 | ||
| 5322 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe | ||
| 5323 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 | ||
| 5324 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 | ||
| 5325 | #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 | ||
| 5326 | #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 | ||
| 5327 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f | ||
| 5328 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 | ||
| 5329 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 | ||
| 5330 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 | ||
| 5331 | #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 | ||
| 5332 | #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa | ||
| 5333 | #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 | ||
| 5334 | #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 | ||
| 5335 | #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 | ||
| 5336 | #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 | ||
| 5337 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff | ||
| 5338 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 | ||
| 5339 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 | ||
| 5340 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 | ||
| 5341 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 | ||
| 5342 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf | ||
| 5343 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 | ||
| 5344 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 | ||
| 5345 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf | ||
| 5346 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 | ||
| 5347 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 | ||
| 5348 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 5349 | #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 | ||
| 5350 | #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc | ||
| 5351 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 5352 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 5353 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 5354 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 5355 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 5356 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 5357 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 5358 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 5359 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 5360 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 5361 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 5362 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 5363 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 5364 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 5365 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 5366 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 5367 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff | ||
| 5368 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 | ||
| 5369 | #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff | ||
| 5370 | #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 | ||
| 5371 | #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 | ||
| 5372 | #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 | ||
| 5373 | #define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff | ||
| 5374 | #define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 | ||
| 5375 | #define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff | ||
| 5376 | #define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 | ||
| 5377 | #define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff | ||
| 5378 | #define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 | ||
| 5379 | #define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff | ||
| 5380 | #define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 | ||
| 5381 | #define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff | ||
| 5382 | #define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 | ||
| 5383 | #define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff | ||
| 5384 | #define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 | ||
| 5385 | #define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff | ||
| 5386 | #define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 | ||
| 5387 | #define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff | ||
| 5388 | #define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 | ||
| 5389 | #define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff | ||
| 5390 | #define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 | ||
| 5391 | #define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff | ||
| 5392 | #define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 | ||
| 5393 | #define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff | ||
| 5394 | #define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 | ||
| 5395 | #define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff | ||
| 5396 | #define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 | ||
| 5397 | #define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff | ||
| 5398 | #define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 | ||
| 5399 | #define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff | ||
| 5400 | #define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 | ||
| 5401 | #define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff | ||
| 5402 | #define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 | ||
| 5403 | #define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff | ||
| 5404 | #define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 | ||
| 5405 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff | ||
| 5406 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 | ||
| 5407 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff | ||
| 5408 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 | ||
| 5409 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff | ||
| 5410 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 | ||
| 5411 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff | ||
| 5412 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 | ||
| 5413 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff | ||
| 5414 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 | ||
| 5415 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff | ||
| 5416 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 | ||
| 5417 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff | ||
| 5418 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 | ||
| 5419 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff | ||
| 5420 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 | ||
| 5421 | #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 | ||
| 5422 | #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 | ||
| 5423 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 | ||
| 5424 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc | ||
| 5425 | #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 | ||
| 5426 | #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 | ||
| 5427 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 | ||
| 5428 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 | ||
| 5429 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 | ||
| 5430 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 | ||
| 5431 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 | ||
| 5432 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 | ||
| 5433 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 | ||
| 5434 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc | ||
| 5435 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 | ||
| 5436 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 | ||
| 5437 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 | ||
| 5438 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 | ||
| 5439 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 | ||
| 5440 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 | ||
| 5441 | #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 | ||
| 5442 | #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 | ||
| 5443 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 | ||
| 5444 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 | ||
| 5445 | #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 | ||
| 5446 | #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 | ||
| 5447 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 | ||
| 5448 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc | ||
| 5449 | #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 | ||
| 5450 | #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 | ||
| 5451 | #define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 | ||
| 5452 | #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 | ||
| 5453 | #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 | ||
| 5454 | #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 | ||
| 5455 | #define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 | ||
| 5456 | #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c | ||
| 5457 | #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 | ||
| 5458 | #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e | ||
| 5459 | #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff | ||
| 5460 | #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 | ||
| 5461 | #define GB_GPU_ID__GPU_ID_MASK 0xf | ||
| 5462 | #define GB_GPU_ID__GPU_ID__SHIFT 0x0 | ||
| 5463 | #define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf | ||
| 5464 | #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 | ||
| 5465 | #define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 | ||
| 5466 | #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 | ||
| 5467 | #define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 | ||
| 5468 | #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 | ||
| 5469 | #define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 | ||
| 5470 | #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc | ||
| 5471 | #define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 | ||
| 5472 | #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 | ||
| 5473 | #define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 | ||
| 5474 | #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 | ||
| 5475 | #define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 | ||
| 5476 | #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 | ||
| 5477 | #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 | ||
| 5478 | #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c | ||
| 5479 | #define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c | ||
| 5480 | #define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 | ||
| 5481 | #define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 | ||
| 5482 | #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 | ||
| 5483 | #define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 | ||
| 5484 | #define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb | ||
| 5485 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5486 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5487 | #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5488 | #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5489 | #define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c | ||
| 5490 | #define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 | ||
| 5491 | #define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 | ||
| 5492 | #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 | ||
| 5493 | #define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 | ||
| 5494 | #define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb | ||
| 5495 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5496 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5497 | #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5498 | #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5499 | #define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c | ||
| 5500 | #define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 | ||
| 5501 | #define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 | ||
| 5502 | #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 | ||
| 5503 | #define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 | ||
| 5504 | #define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb | ||
| 5505 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5506 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5507 | #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5508 | #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5509 | #define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c | ||
| 5510 | #define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 | ||
| 5511 | #define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 | ||
| 5512 | #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 | ||
| 5513 | #define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 | ||
| 5514 | #define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb | ||
| 5515 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5516 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5517 | #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5518 | #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5519 | #define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c | ||
| 5520 | #define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 | ||
| 5521 | #define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 | ||
| 5522 | #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 | ||
| 5523 | #define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 | ||
| 5524 | #define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb | ||
| 5525 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5526 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5527 | #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5528 | #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5529 | #define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c | ||
| 5530 | #define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 | ||
| 5531 | #define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 | ||
| 5532 | #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 | ||
| 5533 | #define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 | ||
| 5534 | #define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb | ||
| 5535 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5536 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5537 | #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5538 | #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5539 | #define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c | ||
| 5540 | #define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 | ||
| 5541 | #define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 | ||
| 5542 | #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 | ||
| 5543 | #define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 | ||
| 5544 | #define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb | ||
| 5545 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5546 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5547 | #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5548 | #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5549 | #define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c | ||
| 5550 | #define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 | ||
| 5551 | #define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 | ||
| 5552 | #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 | ||
| 5553 | #define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 | ||
| 5554 | #define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb | ||
| 5555 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5556 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5557 | #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5558 | #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5559 | #define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c | ||
| 5560 | #define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 | ||
| 5561 | #define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 | ||
| 5562 | #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 | ||
| 5563 | #define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 | ||
| 5564 | #define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb | ||
| 5565 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5566 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5567 | #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5568 | #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5569 | #define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c | ||
| 5570 | #define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 | ||
| 5571 | #define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 | ||
| 5572 | #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 | ||
| 5573 | #define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 | ||
| 5574 | #define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb | ||
| 5575 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5576 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5577 | #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5578 | #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5579 | #define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c | ||
| 5580 | #define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 | ||
| 5581 | #define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 | ||
| 5582 | #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 | ||
| 5583 | #define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 | ||
| 5584 | #define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb | ||
| 5585 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5586 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5587 | #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5588 | #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5589 | #define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c | ||
| 5590 | #define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 | ||
| 5591 | #define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 | ||
| 5592 | #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 | ||
| 5593 | #define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 | ||
| 5594 | #define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb | ||
| 5595 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5596 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5597 | #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5598 | #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5599 | #define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c | ||
| 5600 | #define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 | ||
| 5601 | #define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 | ||
| 5602 | #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 | ||
| 5603 | #define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 | ||
| 5604 | #define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb | ||
| 5605 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5606 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5607 | #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5608 | #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5609 | #define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c | ||
| 5610 | #define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 | ||
| 5611 | #define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 | ||
| 5612 | #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 | ||
| 5613 | #define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 | ||
| 5614 | #define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb | ||
| 5615 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5616 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5617 | #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5618 | #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5619 | #define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c | ||
| 5620 | #define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 | ||
| 5621 | #define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 | ||
| 5622 | #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 | ||
| 5623 | #define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 | ||
| 5624 | #define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb | ||
| 5625 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5626 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5627 | #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5628 | #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5629 | #define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c | ||
| 5630 | #define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 | ||
| 5631 | #define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 | ||
| 5632 | #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 | ||
| 5633 | #define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 | ||
| 5634 | #define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb | ||
| 5635 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5636 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5637 | #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5638 | #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5639 | #define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c | ||
| 5640 | #define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 | ||
| 5641 | #define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 | ||
| 5642 | #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 | ||
| 5643 | #define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 | ||
| 5644 | #define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb | ||
| 5645 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5646 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5647 | #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5648 | #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5649 | #define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c | ||
| 5650 | #define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 | ||
| 5651 | #define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 | ||
| 5652 | #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 | ||
| 5653 | #define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 | ||
| 5654 | #define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb | ||
| 5655 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5656 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5657 | #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5658 | #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5659 | #define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c | ||
| 5660 | #define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 | ||
| 5661 | #define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 | ||
| 5662 | #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 | ||
| 5663 | #define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 | ||
| 5664 | #define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb | ||
| 5665 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5666 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5667 | #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5668 | #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5669 | #define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c | ||
| 5670 | #define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 | ||
| 5671 | #define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 | ||
| 5672 | #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 | ||
| 5673 | #define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 | ||
| 5674 | #define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb | ||
| 5675 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5676 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5677 | #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5678 | #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5679 | #define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c | ||
| 5680 | #define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 | ||
| 5681 | #define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 | ||
| 5682 | #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 | ||
| 5683 | #define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 | ||
| 5684 | #define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb | ||
| 5685 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5686 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5687 | #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5688 | #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5689 | #define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c | ||
| 5690 | #define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 | ||
| 5691 | #define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 | ||
| 5692 | #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 | ||
| 5693 | #define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 | ||
| 5694 | #define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb | ||
| 5695 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5696 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5697 | #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5698 | #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5699 | #define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c | ||
| 5700 | #define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 | ||
| 5701 | #define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 | ||
| 5702 | #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 | ||
| 5703 | #define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 | ||
| 5704 | #define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb | ||
| 5705 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5706 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5707 | #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5708 | #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5709 | #define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c | ||
| 5710 | #define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 | ||
| 5711 | #define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 | ||
| 5712 | #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 | ||
| 5713 | #define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 | ||
| 5714 | #define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb | ||
| 5715 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5716 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5717 | #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5718 | #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5719 | #define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c | ||
| 5720 | #define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 | ||
| 5721 | #define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 | ||
| 5722 | #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 | ||
| 5723 | #define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 | ||
| 5724 | #define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb | ||
| 5725 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5726 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5727 | #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5728 | #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5729 | #define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c | ||
| 5730 | #define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 | ||
| 5731 | #define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 | ||
| 5732 | #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 | ||
| 5733 | #define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 | ||
| 5734 | #define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb | ||
| 5735 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5736 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5737 | #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5738 | #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5739 | #define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c | ||
| 5740 | #define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 | ||
| 5741 | #define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 | ||
| 5742 | #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 | ||
| 5743 | #define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 | ||
| 5744 | #define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb | ||
| 5745 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5746 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5747 | #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5748 | #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5749 | #define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c | ||
| 5750 | #define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 | ||
| 5751 | #define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 | ||
| 5752 | #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 | ||
| 5753 | #define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 | ||
| 5754 | #define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb | ||
| 5755 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5756 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5757 | #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5758 | #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5759 | #define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c | ||
| 5760 | #define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 | ||
| 5761 | #define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 | ||
| 5762 | #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 | ||
| 5763 | #define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 | ||
| 5764 | #define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb | ||
| 5765 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5766 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5767 | #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5768 | #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5769 | #define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c | ||
| 5770 | #define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 | ||
| 5771 | #define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 | ||
| 5772 | #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 | ||
| 5773 | #define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 | ||
| 5774 | #define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb | ||
| 5775 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5776 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5777 | #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5778 | #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5779 | #define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c | ||
| 5780 | #define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 | ||
| 5781 | #define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 | ||
| 5782 | #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 | ||
| 5783 | #define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 | ||
| 5784 | #define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb | ||
| 5785 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5786 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5787 | #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5788 | #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5789 | #define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c | ||
| 5790 | #define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 | ||
| 5791 | #define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 | ||
| 5792 | #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 | ||
| 5793 | #define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 | ||
| 5794 | #define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb | ||
| 5795 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 | ||
| 5796 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 | ||
| 5797 | #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 | ||
| 5798 | #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 | ||
| 5799 | #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 | ||
| 5800 | #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 | ||
| 5801 | #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc | ||
| 5802 | #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 | ||
| 5803 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5804 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5805 | #define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 | ||
| 5806 | #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 | ||
| 5807 | #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 | ||
| 5808 | #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 | ||
| 5809 | #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc | ||
| 5810 | #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 | ||
| 5811 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5812 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5813 | #define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 | ||
| 5814 | #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 | ||
| 5815 | #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 | ||
| 5816 | #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 | ||
| 5817 | #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc | ||
| 5818 | #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 | ||
| 5819 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5820 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5821 | #define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 | ||
| 5822 | #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 | ||
| 5823 | #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 | ||
| 5824 | #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 | ||
| 5825 | #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc | ||
| 5826 | #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 | ||
| 5827 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5828 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5829 | #define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 | ||
| 5830 | #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 | ||
| 5831 | #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 | ||
| 5832 | #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 | ||
| 5833 | #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc | ||
| 5834 | #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 | ||
| 5835 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5836 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5837 | #define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 | ||
| 5838 | #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 | ||
| 5839 | #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 | ||
| 5840 | #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 | ||
| 5841 | #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc | ||
| 5842 | #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 | ||
| 5843 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5844 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5845 | #define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 | ||
| 5846 | #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 | ||
| 5847 | #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 | ||
| 5848 | #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 | ||
| 5849 | #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc | ||
| 5850 | #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 | ||
| 5851 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5852 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5853 | #define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 | ||
| 5854 | #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 | ||
| 5855 | #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 | ||
| 5856 | #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 | ||
| 5857 | #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc | ||
| 5858 | #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 | ||
| 5859 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5860 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5861 | #define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 | ||
| 5862 | #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 | ||
| 5863 | #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 | ||
| 5864 | #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 | ||
| 5865 | #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc | ||
| 5866 | #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 | ||
| 5867 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5868 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5869 | #define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 | ||
| 5870 | #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 | ||
| 5871 | #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 | ||
| 5872 | #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 | ||
| 5873 | #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc | ||
| 5874 | #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 | ||
| 5875 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5876 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5877 | #define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 | ||
| 5878 | #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 | ||
| 5879 | #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 | ||
| 5880 | #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 | ||
| 5881 | #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc | ||
| 5882 | #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 | ||
| 5883 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5884 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5885 | #define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 | ||
| 5886 | #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 | ||
| 5887 | #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 | ||
| 5888 | #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 | ||
| 5889 | #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc | ||
| 5890 | #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 | ||
| 5891 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5892 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5893 | #define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 | ||
| 5894 | #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 | ||
| 5895 | #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 | ||
| 5896 | #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 | ||
| 5897 | #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc | ||
| 5898 | #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 | ||
| 5899 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5900 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5901 | #define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 | ||
| 5902 | #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 | ||
| 5903 | #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 | ||
| 5904 | #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 | ||
| 5905 | #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc | ||
| 5906 | #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 | ||
| 5907 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5908 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5909 | #define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 | ||
| 5910 | #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 | ||
| 5911 | #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 | ||
| 5912 | #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 | ||
| 5913 | #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc | ||
| 5914 | #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 | ||
| 5915 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5916 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5917 | #define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 | ||
| 5918 | #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 | ||
| 5919 | #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 | ||
| 5920 | #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 | ||
| 5921 | #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc | ||
| 5922 | #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 | ||
| 5923 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 | ||
| 5924 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 | ||
| 5925 | #define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 | ||
| 5926 | #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 | ||
| 5927 | #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 | ||
| 5928 | #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 | ||
| 5929 | #define GB_EDC_MODE__DED_MODE_MASK 0x300000 | ||
| 5930 | #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 | ||
| 5931 | #define GB_EDC_MODE__PROP_FED_MASK 0x20000000 | ||
| 5932 | #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d | ||
| 5933 | #define GB_EDC_MODE__BYPASS_MASK 0x80000000 | ||
| 5934 | #define GB_EDC_MODE__BYPASS__SHIFT 0x1f | ||
| 5935 | #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 | ||
| 5936 | #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 | ||
| 5937 | #define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 | ||
| 5938 | #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 | ||
| 5939 | #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff | ||
| 5940 | #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 | ||
| 5941 | #define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5942 | #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5943 | #define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5944 | #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5945 | #define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff | ||
| 5946 | #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 | ||
| 5947 | #define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff | ||
| 5948 | #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 | ||
| 5949 | #define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5950 | #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5951 | #define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5952 | #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5953 | #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5954 | #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5955 | #define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5956 | #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5957 | #define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5958 | #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5959 | #define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff | ||
| 5960 | #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 | ||
| 5961 | #define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff | ||
| 5962 | #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 | ||
| 5963 | #define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff | ||
| 5964 | #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 | ||
| 5965 | #define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff | ||
| 5966 | #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 | ||
| 5967 | #define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff | ||
| 5968 | #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 | ||
| 5969 | #define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff | ||
| 5970 | #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 | ||
| 5971 | #define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5972 | #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5973 | #define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5974 | #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5975 | #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5976 | #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5977 | #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5978 | #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5979 | #define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5980 | #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5981 | #define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5982 | #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5983 | #define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5984 | #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5985 | #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff | ||
| 5986 | #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 | ||
| 5987 | #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5988 | #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5989 | #define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff | ||
| 5990 | #define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 | ||
| 5991 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7 | ||
| 5992 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 | ||
| 5993 | #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 | ||
| 5994 | #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 | ||
| 5995 | #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff | ||
| 5996 | #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 | ||
| 5997 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 | ||
| 5998 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 | ||
| 5999 | #define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff | ||
| 6000 | #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 | ||
| 6001 | #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 | ||
| 6002 | #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 | ||
| 6003 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0xff | ||
| 6004 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 | ||
| 6005 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000 | ||
| 6006 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f | ||
| 6007 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f | ||
| 6008 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 | ||
| 6009 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 | ||
| 6010 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 | ||
| 6011 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3 | ||
| 6012 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 | ||
| 6013 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc | ||
| 6014 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 | ||
| 6015 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30 | ||
| 6016 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 | ||
| 6017 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0 | ||
| 6018 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 | ||
| 6019 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000 | ||
| 6020 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe | ||
| 6021 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000 | ||
| 6022 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf | ||
| 6023 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf | ||
| 6024 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 | ||
| 6025 | #define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 | ||
| 6026 | #define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 | ||
| 6027 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 | ||
| 6028 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 | ||
| 6029 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 | ||
| 6030 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 | ||
| 6031 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 | ||
| 6032 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 | ||
| 6033 | #define GRBM_STATUS__DB_CLEAN_MASK 0x1000 | ||
| 6034 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc | ||
| 6035 | #define GRBM_STATUS__CB_CLEAN_MASK 0x2000 | ||
| 6036 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd | ||
| 6037 | #define GRBM_STATUS__TA_BUSY_MASK 0x4000 | ||
| 6038 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe | ||
| 6039 | #define GRBM_STATUS__GDS_BUSY_MASK 0x8000 | ||
| 6040 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf | ||
| 6041 | #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 | ||
| 6042 | #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 | ||
| 6043 | #define GRBM_STATUS__VGT_BUSY_MASK 0x20000 | ||
| 6044 | #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 | ||
| 6045 | #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 | ||
| 6046 | #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 | ||
| 6047 | #define GRBM_STATUS__IA_BUSY_MASK 0x80000 | ||
| 6048 | #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 | ||
| 6049 | #define GRBM_STATUS__SX_BUSY_MASK 0x100000 | ||
| 6050 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 | ||
| 6051 | #define GRBM_STATUS__WD_BUSY_MASK 0x200000 | ||
| 6052 | #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 | ||
| 6053 | #define GRBM_STATUS__SPI_BUSY_MASK 0x400000 | ||
| 6054 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 | ||
| 6055 | #define GRBM_STATUS__BCI_BUSY_MASK 0x800000 | ||
| 6056 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 | ||
| 6057 | #define GRBM_STATUS__SC_BUSY_MASK 0x1000000 | ||
| 6058 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 | ||
| 6059 | #define GRBM_STATUS__PA_BUSY_MASK 0x2000000 | ||
| 6060 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 | ||
| 6061 | #define GRBM_STATUS__DB_BUSY_MASK 0x4000000 | ||
| 6062 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a | ||
| 6063 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 | ||
| 6064 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c | ||
| 6065 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000 | ||
| 6066 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d | ||
| 6067 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000 | ||
| 6068 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e | ||
| 6069 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 | ||
| 6070 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f | ||
| 6071 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf | ||
| 6072 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 | ||
| 6073 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 | ||
| 6074 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 | ||
| 6075 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 | ||
| 6076 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 | ||
| 6077 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 | ||
| 6078 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 | ||
| 6079 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 | ||
| 6080 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 | ||
| 6081 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 | ||
| 6082 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 | ||
| 6083 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 | ||
| 6084 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 | ||
| 6085 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 | ||
| 6086 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa | ||
| 6087 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 | ||
| 6088 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb | ||
| 6089 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 | ||
| 6090 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc | ||
| 6091 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 | ||
| 6092 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd | ||
| 6093 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 | ||
| 6094 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe | ||
| 6095 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 | ||
| 6096 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 | ||
| 6097 | #define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 | ||
| 6098 | #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 | ||
| 6099 | #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000 | ||
| 6100 | #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a | ||
| 6101 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 | ||
| 6102 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c | ||
| 6103 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 | ||
| 6104 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d | ||
| 6105 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 | ||
| 6106 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e | ||
| 6107 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 | ||
| 6108 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 | ||
| 6109 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 | ||
| 6110 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 | ||
| 6111 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 | ||
| 6112 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 | ||
| 6113 | #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 | ||
| 6114 | #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 | ||
| 6115 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 | ||
| 6116 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 | ||
| 6117 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 | ||
| 6118 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 | ||
| 6119 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 | ||
| 6120 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a | ||
| 6121 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 | ||
| 6122 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b | ||
| 6123 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 | ||
| 6124 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d | ||
| 6125 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 | ||
| 6126 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e | ||
| 6127 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 | ||
| 6128 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f | ||
| 6129 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 | ||
| 6130 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 | ||
| 6131 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 | ||
| 6132 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 | ||
| 6133 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 | ||
| 6134 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 | ||
| 6135 | #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 | ||
| 6136 | #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 | ||
| 6137 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 | ||
| 6138 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 | ||
| 6139 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 | ||
| 6140 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 | ||
| 6141 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 | ||
| 6142 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a | ||
| 6143 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 | ||
| 6144 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b | ||
| 6145 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 | ||
| 6146 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d | ||
| 6147 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 | ||
| 6148 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e | ||
| 6149 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 | ||
| 6150 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f | ||
| 6151 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 | ||
| 6152 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 | ||
| 6153 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 | ||
| 6154 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 | ||
| 6155 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 | ||
| 6156 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 | ||
| 6157 | #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 | ||
| 6158 | #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 | ||
| 6159 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 | ||
| 6160 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 | ||
| 6161 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 | ||
| 6162 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 | ||
| 6163 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 | ||
| 6164 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a | ||
| 6165 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 | ||
| 6166 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b | ||
| 6167 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 | ||
| 6168 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d | ||
| 6169 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 | ||
| 6170 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e | ||
| 6171 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 | ||
| 6172 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f | ||
| 6173 | #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 | ||
| 6174 | #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 | ||
| 6175 | #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 | ||
| 6176 | #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 | ||
| 6177 | #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 | ||
| 6178 | #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 | ||
| 6179 | #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 | ||
| 6180 | #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 | ||
| 6181 | #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 | ||
| 6182 | #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 | ||
| 6183 | #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 | ||
| 6184 | #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 | ||
| 6185 | #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 | ||
| 6186 | #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a | ||
| 6187 | #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 | ||
| 6188 | #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b | ||
| 6189 | #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 | ||
| 6190 | #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d | ||
| 6191 | #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 | ||
| 6192 | #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e | ||
| 6193 | #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 | ||
| 6194 | #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f | ||
| 6195 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 | ||
| 6196 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 | ||
| 6197 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 | ||
| 6198 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 | ||
| 6199 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 | ||
| 6200 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 | ||
| 6201 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 | ||
| 6202 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 | ||
| 6203 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 | ||
| 6204 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 | ||
| 6205 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 | ||
| 6206 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 | ||
| 6207 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000 | ||
| 6208 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 | ||
| 6209 | #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f | ||
| 6210 | #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 | ||
| 6211 | #define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 6212 | #define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 6213 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0xf | ||
| 6214 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 | ||
| 6215 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 6216 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 6217 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000 | ||
| 6218 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e | ||
| 6219 | #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff | ||
| 6220 | #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 | ||
| 6221 | #define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 | ||
| 6222 | #define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 | ||
| 6223 | #define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 | ||
| 6224 | #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 | ||
| 6225 | #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 | ||
| 6226 | #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d | ||
| 6227 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 | ||
| 6228 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e | ||
| 6229 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 | ||
| 6230 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f | ||
| 6231 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf | ||
| 6232 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 | ||
| 6233 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 | ||
| 6234 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 | ||
| 6235 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff | ||
| 6236 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 | ||
| 6237 | #define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 | ||
| 6238 | #define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 | ||
| 6239 | #define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 | ||
| 6240 | #define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 | ||
| 6241 | #define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 | ||
| 6242 | #define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 | ||
| 6243 | #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 | ||
| 6244 | #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 | ||
| 6245 | #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 | ||
| 6246 | #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 | ||
| 6247 | #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 | ||
| 6248 | #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc | ||
| 6249 | #define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000 | ||
| 6250 | #define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd | ||
| 6251 | #define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000 | ||
| 6252 | #define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f | ||
| 6253 | #define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 | ||
| 6254 | #define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 | ||
| 6255 | #define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 | ||
| 6256 | #define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 | ||
| 6257 | #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 | ||
| 6258 | #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 | ||
| 6259 | #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 | ||
| 6260 | #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 | ||
| 6261 | #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 | ||
| 6262 | #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 | ||
| 6263 | #define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 | ||
| 6264 | #define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 | ||
| 6265 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 | ||
| 6266 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 | ||
| 6267 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 | ||
| 6268 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 | ||
| 6269 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 | ||
| 6270 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 | ||
| 6271 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 | ||
| 6272 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 | ||
| 6273 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 | ||
| 6274 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa | ||
| 6275 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 | ||
| 6276 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb | ||
| 6277 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 | ||
| 6278 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc | ||
| 6279 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 | ||
| 6280 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd | ||
| 6281 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 | ||
| 6282 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe | ||
| 6283 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 | ||
| 6284 | #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf | ||
| 6285 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 | ||
| 6286 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 | ||
| 6287 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 | ||
| 6288 | #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 | ||
| 6289 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 | ||
| 6290 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 | ||
| 6291 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 | ||
| 6292 | #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 | ||
| 6293 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 | ||
| 6294 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 | ||
| 6295 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 | ||
| 6296 | #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 | ||
| 6297 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc | ||
| 6298 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 | ||
| 6299 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 | ||
| 6300 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 | ||
| 6301 | #define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 | ||
| 6302 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 | ||
| 6303 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 | ||
| 6304 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f | ||
| 6305 | #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 | ||
| 6306 | #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 | ||
| 6307 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 | ||
| 6308 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 | ||
| 6309 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 | ||
| 6310 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 | ||
| 6311 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 | ||
| 6312 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 | ||
| 6313 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 | ||
| 6314 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 | ||
| 6315 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 | ||
| 6316 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 | ||
| 6317 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 | ||
| 6318 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 | ||
| 6319 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 | ||
| 6320 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 | ||
| 6321 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 | ||
| 6322 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 | ||
| 6323 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 | ||
| 6324 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a | ||
| 6325 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 | ||
| 6326 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b | ||
| 6327 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 | ||
| 6328 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c | ||
| 6329 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 | ||
| 6330 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d | ||
| 6331 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 | ||
| 6332 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e | ||
| 6333 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 | ||
| 6334 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f | ||
| 6335 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 | ||
| 6336 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 | ||
| 6337 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 | ||
| 6338 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 | ||
| 6339 | #define GRBM_TRAP_OP__RW_MASK 0x1 | ||
| 6340 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 | ||
| 6341 | #define GRBM_TRAP_ADDR__DATA_MASK 0xffff | ||
| 6342 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 | ||
| 6343 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff | ||
| 6344 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 | ||
| 6345 | #define GRBM_TRAP_WD__DATA_MASK 0xffffffff | ||
| 6346 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 | ||
| 6347 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff | ||
| 6348 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 | ||
| 6349 | #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3 | ||
| 6350 | #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 | ||
| 6351 | #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4 | ||
| 6352 | #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 | ||
| 6353 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1 | ||
| 6354 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 | ||
| 6355 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2 | ||
| 6356 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1 | ||
| 6357 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c | ||
| 6358 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 | ||
| 6359 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0 | ||
| 6360 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 | ||
| 6361 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000 | ||
| 6362 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc | ||
| 6363 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000 | ||
| 6364 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd | ||
| 6365 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000 | ||
| 6366 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 | ||
| 6367 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000 | ||
| 6368 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 | ||
| 6369 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000 | ||
| 6370 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f | ||
| 6371 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f | ||
| 6372 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6373 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6374 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6375 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6376 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6377 | #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6378 | #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6379 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6380 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6381 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 | ||
| 6382 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe | ||
| 6383 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6384 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6385 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6386 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6387 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6388 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6389 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6390 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6391 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6392 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6393 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6394 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6395 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 | ||
| 6396 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 | ||
| 6397 | #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 | ||
| 6398 | #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 | ||
| 6399 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 | ||
| 6400 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 | ||
| 6401 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 | ||
| 6402 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 | ||
| 6403 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 | ||
| 6404 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a | ||
| 6405 | #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 | ||
| 6406 | #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b | ||
| 6407 | #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 | ||
| 6408 | #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c | ||
| 6409 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f | ||
| 6410 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6411 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6412 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6413 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6414 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6415 | #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6416 | #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6417 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6418 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6419 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 | ||
| 6420 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe | ||
| 6421 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6422 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6423 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6424 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6425 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6426 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6427 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6428 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6429 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6430 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6431 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6432 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6433 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 | ||
| 6434 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 | ||
| 6435 | #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 | ||
| 6436 | #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 | ||
| 6437 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 | ||
| 6438 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 | ||
| 6439 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 | ||
| 6440 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 | ||
| 6441 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 | ||
| 6442 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a | ||
| 6443 | #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 | ||
| 6444 | #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b | ||
| 6445 | #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 | ||
| 6446 | #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c | ||
| 6447 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f | ||
| 6448 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6449 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6450 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6451 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6452 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6453 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6454 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6455 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6456 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6457 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 | ||
| 6458 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf | ||
| 6459 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6460 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6461 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6462 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6463 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6464 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6465 | #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6466 | #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6467 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6468 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6469 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6470 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6471 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f | ||
| 6472 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6473 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6474 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6475 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6476 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6477 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6478 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6479 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6480 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6481 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 | ||
| 6482 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf | ||
| 6483 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6484 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6485 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6486 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6487 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6488 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6489 | #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6490 | #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6491 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6492 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6493 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6494 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6495 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f | ||
| 6496 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6497 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6498 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6499 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6500 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6501 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6502 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6503 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6504 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6505 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 | ||
| 6506 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf | ||
| 6507 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6508 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6509 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6510 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6511 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6512 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6513 | #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6514 | #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6515 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6516 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6517 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6518 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6519 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f | ||
| 6520 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 6521 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 | ||
| 6522 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa | ||
| 6523 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 | ||
| 6524 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb | ||
| 6525 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 | ||
| 6526 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc | ||
| 6527 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 | ||
| 6528 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd | ||
| 6529 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 | ||
| 6530 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf | ||
| 6531 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 | ||
| 6532 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 | ||
| 6533 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 | ||
| 6534 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 | ||
| 6535 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 | ||
| 6536 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 | ||
| 6537 | #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 | ||
| 6538 | #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 | ||
| 6539 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 | ||
| 6540 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 | ||
| 6541 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 | ||
| 6542 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 | ||
| 6543 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6544 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6545 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6546 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6547 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6548 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6549 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6550 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6551 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6552 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6553 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6554 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6555 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6556 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6557 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6558 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6559 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6560 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6561 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6562 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6563 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 6564 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 6565 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 6566 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 6567 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff | ||
| 6568 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 | ||
| 6569 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff | ||
| 6570 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 | ||
| 6571 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff | ||
| 6572 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 | ||
| 6573 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff | ||
| 6574 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 | ||
| 6575 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff | ||
| 6576 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 | ||
| 6577 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff | ||
| 6578 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 | ||
| 6579 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff | ||
| 6580 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 | ||
| 6581 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff | ||
| 6582 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 | ||
| 6583 | #define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff | ||
| 6584 | #define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 | ||
| 6585 | #define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff | ||
| 6586 | #define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 | ||
| 6587 | #define GRBM_NOWHERE__DATA_MASK 0xffffffff | ||
| 6588 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 | ||
| 6589 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff | ||
| 6590 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 | ||
| 6591 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6592 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6593 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff | ||
| 6594 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 | ||
| 6595 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6596 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6597 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6598 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6599 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6600 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6601 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff | ||
| 6602 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 | ||
| 6603 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff | ||
| 6604 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 | ||
| 6605 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff | ||
| 6606 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 | ||
| 6607 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff | ||
| 6608 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 | ||
| 6609 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff | ||
| 6610 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 | ||
| 6611 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff | ||
| 6612 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 | ||
| 6613 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff | ||
| 6614 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 | ||
| 6615 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff | ||
| 6616 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 | ||
| 6617 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff | ||
| 6618 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 | ||
| 6619 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff | ||
| 6620 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 | ||
| 6621 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff | ||
| 6622 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 | ||
| 6623 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff | ||
| 6624 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 | ||
| 6625 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff | ||
| 6626 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 | ||
| 6627 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff | ||
| 6628 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 | ||
| 6629 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff | ||
| 6630 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 | ||
| 6631 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6632 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6633 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6634 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6635 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6636 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6637 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6638 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6639 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6640 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6641 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6642 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6643 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6644 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6645 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6646 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6647 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6648 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6649 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6650 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6651 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6652 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6653 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6654 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6655 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6656 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6657 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6658 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6659 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff | ||
| 6660 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 | ||
| 6661 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff | ||
| 6662 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 | ||
| 6663 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff | ||
| 6664 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 | ||
| 6665 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff | ||
| 6666 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 | ||
| 6667 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff | ||
| 6668 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 | ||
| 6669 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff | ||
| 6670 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 | ||
| 6671 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff | ||
| 6672 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 | ||
| 6673 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff | ||
| 6674 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 | ||
| 6675 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff | ||
| 6676 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 | ||
| 6677 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff | ||
| 6678 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 | ||
| 6679 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff | ||
| 6680 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 | ||
| 6681 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff | ||
| 6682 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 | ||
| 6683 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff | ||
| 6684 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 | ||
| 6685 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff | ||
| 6686 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 | ||
| 6687 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff | ||
| 6688 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 | ||
| 6689 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff | ||
| 6690 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 | ||
| 6691 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6692 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6693 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6694 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6695 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6696 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6697 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6698 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6699 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6700 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6701 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6702 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6703 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6704 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6705 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6706 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6707 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6708 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6709 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6710 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6711 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6712 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6713 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6714 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6715 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6716 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6717 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6718 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6719 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff | ||
| 6720 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 | ||
| 6721 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6722 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6723 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6724 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6725 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6726 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6727 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6728 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6729 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6730 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6731 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6732 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6733 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6734 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6735 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6736 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6737 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6738 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6739 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6740 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6741 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6742 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6743 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6744 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6745 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6746 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6747 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6748 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6749 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff | ||
| 6750 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 | ||
| 6751 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6752 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6753 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6754 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6755 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6756 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6757 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6758 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6759 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6760 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6761 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6762 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6763 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6764 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6765 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6766 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6767 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6768 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6769 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6770 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6771 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6772 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6773 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6774 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6775 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6776 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6777 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6778 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6779 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff | ||
| 6780 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 | ||
| 6781 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 | ||
| 6782 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 | ||
| 6783 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 | ||
| 6784 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 | ||
| 6785 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 | ||
| 6786 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 | ||
| 6787 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 | ||
| 6788 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 | ||
| 6789 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 | ||
| 6790 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 | ||
| 6791 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 | ||
| 6792 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 | ||
| 6793 | #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 | ||
| 6794 | #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 | ||
| 6795 | #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 | ||
| 6796 | #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 | ||
| 6797 | #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 | ||
| 6798 | #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa | ||
| 6799 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 | ||
| 6800 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb | ||
| 6801 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 | ||
| 6802 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 | ||
| 6803 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 | ||
| 6804 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 | ||
| 6805 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 | ||
| 6806 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 | ||
| 6807 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 | ||
| 6808 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 | ||
| 6809 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 | ||
| 6810 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 | ||
| 6811 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 | ||
| 6812 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 | ||
| 6813 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 | ||
| 6814 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 | ||
| 6815 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 | ||
| 6816 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 | ||
| 6817 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 | ||
| 6818 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 | ||
| 6819 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 | ||
| 6820 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 | ||
| 6821 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 | ||
| 6822 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa | ||
| 6823 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 | ||
| 6824 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb | ||
| 6825 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 | ||
| 6826 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc | ||
| 6827 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 | ||
| 6828 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd | ||
| 6829 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 | ||
| 6830 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe | ||
| 6831 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 | ||
| 6832 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf | ||
| 6833 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 | ||
| 6834 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 | ||
| 6835 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 | ||
| 6836 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 | ||
| 6837 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 | ||
| 6838 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 | ||
| 6839 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 | ||
| 6840 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 | ||
| 6841 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 | ||
| 6842 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 | ||
| 6843 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 | ||
| 6844 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 | ||
| 6845 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 | ||
| 6846 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 | ||
| 6847 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 | ||
| 6848 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 | ||
| 6849 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 | ||
| 6850 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 | ||
| 6851 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 | ||
| 6852 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 | ||
| 6853 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000 | ||
| 6854 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a | ||
| 6855 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 | ||
| 6856 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 | ||
| 6857 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 | ||
| 6858 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 | ||
| 6859 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 | ||
| 6860 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 | ||
| 6861 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 | ||
| 6862 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 | ||
| 6863 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 | ||
| 6864 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 | ||
| 6865 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 | ||
| 6866 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 | ||
| 6867 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 | ||
| 6868 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 | ||
| 6869 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 | ||
| 6870 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 | ||
| 6871 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 | ||
| 6872 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 | ||
| 6873 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 | ||
| 6874 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 | ||
| 6875 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 | ||
| 6876 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa | ||
| 6877 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 | ||
| 6878 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb | ||
| 6879 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 | ||
| 6880 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc | ||
| 6881 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 | ||
| 6882 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd | ||
| 6883 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 | ||
| 6884 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe | ||
| 6885 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 | ||
| 6886 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 | ||
| 6887 | #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 | ||
| 6888 | #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 | ||
| 6889 | #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 | ||
| 6890 | #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 | ||
| 6891 | #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 | ||
| 6892 | #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 | ||
| 6893 | #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 | ||
| 6894 | #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 | ||
| 6895 | #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 | ||
| 6896 | #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 | ||
| 6897 | #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 | ||
| 6898 | #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 | ||
| 6899 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 | ||
| 6900 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd | ||
| 6901 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 | ||
| 6902 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe | ||
| 6903 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 | ||
| 6904 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 | ||
| 6905 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 | ||
| 6906 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 | ||
| 6907 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 | ||
| 6908 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 | ||
| 6909 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 | ||
| 6910 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 | ||
| 6911 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 | ||
| 6912 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 | ||
| 6913 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 | ||
| 6914 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 | ||
| 6915 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 | ||
| 6916 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 | ||
| 6917 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 | ||
| 6918 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 | ||
| 6919 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 | ||
| 6920 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 | ||
| 6921 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 | ||
| 6922 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a | ||
| 6923 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 | ||
| 6924 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b | ||
| 6925 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff | ||
| 6926 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 | ||
| 6927 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff | ||
| 6928 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 | ||
| 6929 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff | ||
| 6930 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 | ||
| 6931 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff | ||
| 6932 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 | ||
| 6933 | #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6934 | #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6935 | #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6936 | #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6937 | #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6938 | #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6939 | #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6940 | #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6941 | #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6942 | #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6943 | #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6944 | #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6945 | #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6946 | #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6947 | #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6948 | #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6949 | #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6950 | #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6951 | #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6952 | #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6953 | #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6954 | #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6955 | #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6956 | #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6957 | #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6958 | #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6959 | #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6960 | #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6961 | #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6962 | #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6963 | #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6964 | #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6965 | #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6966 | #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6967 | #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6968 | #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6969 | #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6970 | #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6971 | #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6972 | #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6973 | #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff | ||
| 6974 | #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 | ||
| 6975 | #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff | ||
| 6976 | #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 | ||
| 6977 | #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff | ||
| 6978 | #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 | ||
| 6979 | #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff | ||
| 6980 | #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 | ||
| 6981 | #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff | ||
| 6982 | #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 | ||
| 6983 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff | ||
| 6984 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 | ||
| 6985 | #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff | ||
| 6986 | #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 | ||
| 6987 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff | ||
| 6988 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 | ||
| 6989 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 | ||
| 6990 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 | ||
| 6991 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 | ||
| 6992 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 | ||
| 6993 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 | ||
| 6994 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 | ||
| 6995 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 | ||
| 6996 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 | ||
| 6997 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 | ||
| 6998 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 | ||
| 6999 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 | ||
| 7000 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c | ||
| 7001 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 | ||
| 7002 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d | ||
| 7003 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 | ||
| 7004 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e | ||
| 7005 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 | ||
| 7006 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f | ||
| 7007 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 | ||
| 7008 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 | ||
| 7009 | #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 | ||
| 7010 | #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 | ||
| 7011 | #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 | ||
| 7012 | #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 | ||
| 7013 | #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 | ||
| 7014 | #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 | ||
| 7015 | #define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff | ||
| 7016 | #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 | ||
| 7017 | #define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 | ||
| 7018 | #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 | ||
| 7019 | #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff | ||
| 7020 | #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 | ||
| 7021 | #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 | ||
| 7022 | #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 | ||
| 7023 | #define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff | ||
| 7024 | #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 | ||
| 7025 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 | ||
| 7026 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 | ||
| 7027 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 | ||
| 7028 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 | ||
| 7029 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 | ||
| 7030 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 | ||
| 7031 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 | ||
| 7032 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 | ||
| 7033 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff | ||
| 7034 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 | ||
| 7035 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 | ||
| 7036 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 | ||
| 7037 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 | ||
| 7038 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 | ||
| 7039 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 | ||
| 7040 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 | ||
| 7041 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 | ||
| 7042 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 | ||
| 7043 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 | ||
| 7044 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 | ||
| 7045 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 | ||
| 7046 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 | ||
| 7047 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 | ||
| 7048 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 | ||
| 7049 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 | ||
| 7050 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 | ||
| 7051 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 | ||
| 7052 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 | ||
| 7053 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 | ||
| 7054 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e | ||
| 7055 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 | ||
| 7056 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f | ||
| 7057 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 | ||
| 7058 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 | ||
| 7059 | #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 | ||
| 7060 | #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 | ||
| 7061 | #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 | ||
| 7062 | #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 | ||
| 7063 | #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 | ||
| 7064 | #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 | ||
| 7065 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 | ||
| 7066 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 | ||
| 7067 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 | ||
| 7068 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 | ||
| 7069 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 | ||
| 7070 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb | ||
| 7071 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 | ||
| 7072 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc | ||
| 7073 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 | ||
| 7074 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd | ||
| 7075 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 | ||
| 7076 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 | ||
| 7077 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 | ||
| 7078 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 | ||
| 7079 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 | ||
| 7080 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 | ||
| 7081 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 | ||
| 7082 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 | ||
| 7083 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff | ||
| 7084 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 | ||
| 7085 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 | ||
| 7086 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 | ||
| 7087 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff | ||
| 7088 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 | ||
| 7089 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff | ||
| 7090 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 | ||
| 7091 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff | ||
| 7092 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 | ||
| 7093 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff | ||
| 7094 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 | ||
| 7095 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff | ||
| 7096 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 | ||
| 7097 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff | ||
| 7098 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 | ||
| 7099 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 | ||
| 7100 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 | ||
| 7101 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff | ||
| 7102 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 | ||
| 7103 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 7104 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 7105 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 7106 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 7107 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 7108 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 7109 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 7110 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 7111 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 7112 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 7113 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 7114 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 7115 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 7116 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 7117 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 7118 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 7119 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 7120 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 7121 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 7122 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 7123 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 7124 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 7125 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 7126 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 7127 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 7128 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 7129 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 7130 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 7131 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 7132 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 7133 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff | ||
| 7134 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 7135 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 7136 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 7137 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff | ||
| 7138 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 7139 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 7140 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 7141 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff | ||
| 7142 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 7143 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 7144 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 7145 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff | ||
| 7146 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 7147 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 | ||
| 7148 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 | ||
| 7149 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 | ||
| 7150 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 | ||
| 7151 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 | ||
| 7152 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd | ||
| 7153 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 | ||
| 7154 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 | ||
| 7155 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 | ||
| 7156 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 | ||
| 7157 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff | ||
| 7158 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 | ||
| 7159 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 | ||
| 7160 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 | ||
| 7161 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff | ||
| 7162 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 | ||
| 7163 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 | ||
| 7164 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 | ||
| 7165 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x3 | ||
| 7166 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 | ||
| 7167 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf | ||
| 7168 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 | ||
| 7169 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 | ||
| 7170 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 | ||
| 7171 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 | ||
| 7172 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 | ||
| 7173 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 | ||
| 7174 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc | ||
| 7175 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 | ||
| 7176 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 | ||
| 7177 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 | ||
| 7178 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 | ||
| 7179 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 | ||
| 7180 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 | ||
| 7181 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 | ||
| 7182 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c | ||
| 7183 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf | ||
| 7184 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 | ||
| 7185 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 | ||
| 7186 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 | ||
| 7187 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 | ||
| 7188 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 | ||
| 7189 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 | ||
| 7190 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc | ||
| 7191 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 | ||
| 7192 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 | ||
| 7193 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 | ||
| 7194 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 | ||
| 7195 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 | ||
| 7196 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 | ||
| 7197 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 | ||
| 7198 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c | ||
| 7199 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf | ||
| 7200 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 | ||
| 7201 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 | ||
| 7202 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 | ||
| 7203 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 | ||
| 7204 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 | ||
| 7205 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 | ||
| 7206 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc | ||
| 7207 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 | ||
| 7208 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 | ||
| 7209 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 | ||
| 7210 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 | ||
| 7211 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 | ||
| 7212 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 | ||
| 7213 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 | ||
| 7214 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c | ||
| 7215 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf | ||
| 7216 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 | ||
| 7217 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 | ||
| 7218 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 | ||
| 7219 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 | ||
| 7220 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 | ||
| 7221 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 | ||
| 7222 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc | ||
| 7223 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 | ||
| 7224 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 | ||
| 7225 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 | ||
| 7226 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 | ||
| 7227 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 | ||
| 7228 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 | ||
| 7229 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 | ||
| 7230 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c | ||
| 7231 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf | ||
| 7232 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 | ||
| 7233 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 | ||
| 7234 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 | ||
| 7235 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 | ||
| 7236 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 | ||
| 7237 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 | ||
| 7238 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc | ||
| 7239 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 | ||
| 7240 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 | ||
| 7241 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 | ||
| 7242 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 | ||
| 7243 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 | ||
| 7244 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 | ||
| 7245 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 | ||
| 7246 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c | ||
| 7247 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf | ||
| 7248 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 | ||
| 7249 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 | ||
| 7250 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 | ||
| 7251 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 | ||
| 7252 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 | ||
| 7253 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 | ||
| 7254 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc | ||
| 7255 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 | ||
| 7256 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 | ||
| 7257 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 | ||
| 7258 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 | ||
| 7259 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 | ||
| 7260 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 | ||
| 7261 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 | ||
| 7262 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c | ||
| 7263 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf | ||
| 7264 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 | ||
| 7265 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 | ||
| 7266 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 | ||
| 7267 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 | ||
| 7268 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 | ||
| 7269 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 | ||
| 7270 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc | ||
| 7271 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 | ||
| 7272 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 | ||
| 7273 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 | ||
| 7274 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 | ||
| 7275 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 | ||
| 7276 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 | ||
| 7277 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 | ||
| 7278 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c | ||
| 7279 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf | ||
| 7280 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 | ||
| 7281 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 | ||
| 7282 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 | ||
| 7283 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 | ||
| 7284 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 | ||
| 7285 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 | ||
| 7286 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc | ||
| 7287 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 | ||
| 7288 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 | ||
| 7289 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 | ||
| 7290 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 | ||
| 7291 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 | ||
| 7292 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 | ||
| 7293 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 | ||
| 7294 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c | ||
| 7295 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf | ||
| 7296 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 | ||
| 7297 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 | ||
| 7298 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 | ||
| 7299 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 | ||
| 7300 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 | ||
| 7301 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 | ||
| 7302 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc | ||
| 7303 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 | ||
| 7304 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 | ||
| 7305 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 | ||
| 7306 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 | ||
| 7307 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 | ||
| 7308 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 | ||
| 7309 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 | ||
| 7310 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c | ||
| 7311 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf | ||
| 7312 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 | ||
| 7313 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 | ||
| 7314 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 | ||
| 7315 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 | ||
| 7316 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 | ||
| 7317 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 | ||
| 7318 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc | ||
| 7319 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 | ||
| 7320 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 | ||
| 7321 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 | ||
| 7322 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 | ||
| 7323 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 | ||
| 7324 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 | ||
| 7325 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 | ||
| 7326 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c | ||
| 7327 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf | ||
| 7328 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 | ||
| 7329 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 | ||
| 7330 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 | ||
| 7331 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 | ||
| 7332 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 | ||
| 7333 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 | ||
| 7334 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc | ||
| 7335 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 | ||
| 7336 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 | ||
| 7337 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 | ||
| 7338 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 | ||
| 7339 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 | ||
| 7340 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 | ||
| 7341 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 | ||
| 7342 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c | ||
| 7343 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf | ||
| 7344 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 | ||
| 7345 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 | ||
| 7346 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 | ||
| 7347 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 | ||
| 7348 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 | ||
| 7349 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 | ||
| 7350 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc | ||
| 7351 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 | ||
| 7352 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 | ||
| 7353 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 | ||
| 7354 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 | ||
| 7355 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 | ||
| 7356 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 | ||
| 7357 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 | ||
| 7358 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c | ||
| 7359 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf | ||
| 7360 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 | ||
| 7361 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 | ||
| 7362 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 | ||
| 7363 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 | ||
| 7364 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 | ||
| 7365 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 | ||
| 7366 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc | ||
| 7367 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 | ||
| 7368 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 | ||
| 7369 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 | ||
| 7370 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 | ||
| 7371 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 | ||
| 7372 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 | ||
| 7373 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 | ||
| 7374 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c | ||
| 7375 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf | ||
| 7376 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 | ||
| 7377 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 | ||
| 7378 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 | ||
| 7379 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 | ||
| 7380 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 | ||
| 7381 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 | ||
| 7382 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc | ||
| 7383 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 | ||
| 7384 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 | ||
| 7385 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 | ||
| 7386 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 | ||
| 7387 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 | ||
| 7388 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 | ||
| 7389 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 | ||
| 7390 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c | ||
| 7391 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf | ||
| 7392 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 | ||
| 7393 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 | ||
| 7394 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 | ||
| 7395 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 | ||
| 7396 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 | ||
| 7397 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 | ||
| 7398 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc | ||
| 7399 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 | ||
| 7400 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 | ||
| 7401 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 | ||
| 7402 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 | ||
| 7403 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 | ||
| 7404 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 | ||
| 7405 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 | ||
| 7406 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c | ||
| 7407 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf | ||
| 7408 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 | ||
| 7409 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 | ||
| 7410 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 | ||
| 7411 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 | ||
| 7412 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 | ||
| 7413 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 | ||
| 7414 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc | ||
| 7415 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 | ||
| 7416 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 | ||
| 7417 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 | ||
| 7418 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 | ||
| 7419 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 | ||
| 7420 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 | ||
| 7421 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 | ||
| 7422 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c | ||
| 7423 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf | ||
| 7424 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 | ||
| 7425 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 | ||
| 7426 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 | ||
| 7427 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 | ||
| 7428 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 | ||
| 7429 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 | ||
| 7430 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc | ||
| 7431 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 | ||
| 7432 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 | ||
| 7433 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 | ||
| 7434 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 | ||
| 7435 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 | ||
| 7436 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 | ||
| 7437 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 | ||
| 7438 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c | ||
| 7439 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf | ||
| 7440 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 | ||
| 7441 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 | ||
| 7442 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 | ||
| 7443 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 | ||
| 7444 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 | ||
| 7445 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 | ||
| 7446 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc | ||
| 7447 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 | ||
| 7448 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 | ||
| 7449 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 | ||
| 7450 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 | ||
| 7451 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 | ||
| 7452 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 | ||
| 7453 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 | ||
| 7454 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c | ||
| 7455 | #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff | ||
| 7456 | #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 | ||
| 7457 | #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 | ||
| 7458 | #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 | ||
| 7459 | #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff | ||
| 7460 | #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 | ||
| 7461 | #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 | ||
| 7462 | #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 | ||
| 7463 | #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff | ||
| 7464 | #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 | ||
| 7465 | #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 | ||
| 7466 | #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 | ||
| 7467 | #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff | ||
| 7468 | #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 | ||
| 7469 | #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 | ||
| 7470 | #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 | ||
| 7471 | #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff | ||
| 7472 | #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 | ||
| 7473 | #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 | ||
| 7474 | #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 | ||
| 7475 | #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff | ||
| 7476 | #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 | ||
| 7477 | #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 | ||
| 7478 | #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 | ||
| 7479 | #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff | ||
| 7480 | #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 | ||
| 7481 | #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 | ||
| 7482 | #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 | ||
| 7483 | #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff | ||
| 7484 | #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 | ||
| 7485 | #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 | ||
| 7486 | #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 | ||
| 7487 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff | ||
| 7488 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 | ||
| 7489 | #define PA_SC_EDGERULE__ER_TRI_MASK 0xf | ||
| 7490 | #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 | ||
| 7491 | #define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 | ||
| 7492 | #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 | ||
| 7493 | #define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 | ||
| 7494 | #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 | ||
| 7495 | #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 | ||
| 7496 | #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc | ||
| 7497 | #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 | ||
| 7498 | #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 | ||
| 7499 | #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 | ||
| 7500 | #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 | ||
| 7501 | #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 | ||
| 7502 | #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c | ||
| 7503 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 | ||
| 7504 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 | ||
| 7505 | #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 | ||
| 7506 | #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa | ||
| 7507 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 | ||
| 7508 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb | ||
| 7509 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 | ||
| 7510 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc | ||
| 7511 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff | ||
| 7512 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 | ||
| 7513 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 | ||
| 7514 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 | ||
| 7515 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 | ||
| 7516 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c | ||
| 7517 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 | ||
| 7518 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d | ||
| 7519 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 | ||
| 7520 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 | ||
| 7521 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 | ||
| 7522 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 | ||
| 7523 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 | ||
| 7524 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 | ||
| 7525 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 | ||
| 7526 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 | ||
| 7527 | #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 | ||
| 7528 | #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 | ||
| 7529 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 | ||
| 7530 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 | ||
| 7531 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 | ||
| 7532 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 | ||
| 7533 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 | ||
| 7534 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 | ||
| 7535 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 | ||
| 7536 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 | ||
| 7537 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 | ||
| 7538 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 | ||
| 7539 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 | ||
| 7540 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 | ||
| 7541 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 | ||
| 7542 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 | ||
| 7543 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 | ||
| 7544 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa | ||
| 7545 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 | ||
| 7546 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb | ||
| 7547 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 | ||
| 7548 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc | ||
| 7549 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 | ||
| 7550 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd | ||
| 7551 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 | ||
| 7552 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe | ||
| 7553 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 | ||
| 7554 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf | ||
| 7555 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 | ||
| 7556 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 | ||
| 7557 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 | ||
| 7558 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 | ||
| 7559 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 | ||
| 7560 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 | ||
| 7561 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 | ||
| 7562 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 | ||
| 7563 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 | ||
| 7564 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 | ||
| 7565 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 | ||
| 7566 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 | ||
| 7567 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 | ||
| 7568 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 | ||
| 7569 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 | ||
| 7570 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a | ||
| 7571 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 | ||
| 7572 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b | ||
| 7573 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 | ||
| 7574 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c | ||
| 7575 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 | ||
| 7576 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 | ||
| 7577 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc | ||
| 7578 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 | ||
| 7579 | #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 | ||
| 7580 | #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 | ||
| 7581 | #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 | ||
| 7582 | #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 | ||
| 7583 | #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 | ||
| 7584 | #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 | ||
| 7585 | #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 | ||
| 7586 | #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 | ||
| 7587 | #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 | ||
| 7588 | #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa | ||
| 7589 | #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 | ||
| 7590 | #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc | ||
| 7591 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 | ||
| 7592 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe | ||
| 7593 | #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 | ||
| 7594 | #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 | ||
| 7595 | #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 | ||
| 7596 | #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 | ||
| 7597 | #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 | ||
| 7598 | #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 | ||
| 7599 | #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 | ||
| 7600 | #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 | ||
| 7601 | #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 | ||
| 7602 | #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a | ||
| 7603 | #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 | ||
| 7604 | #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c | ||
| 7605 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 | ||
| 7606 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 | ||
| 7607 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc | ||
| 7608 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 | ||
| 7609 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 | ||
| 7610 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 | ||
| 7611 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 | ||
| 7612 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 | ||
| 7613 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc | ||
| 7614 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 | ||
| 7615 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff | ||
| 7616 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 | ||
| 7617 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 | ||
| 7618 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 | ||
| 7619 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7620 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7621 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff | ||
| 7622 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 | ||
| 7623 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 | ||
| 7624 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 | ||
| 7625 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff | ||
| 7626 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 | ||
| 7627 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 | ||
| 7628 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 | ||
| 7629 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff | ||
| 7630 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 | ||
| 7631 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 | ||
| 7632 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 | ||
| 7633 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff | ||
| 7634 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 | ||
| 7635 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 | ||
| 7636 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 | ||
| 7637 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff | ||
| 7638 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 | ||
| 7639 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 | ||
| 7640 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 | ||
| 7641 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7642 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7643 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff | ||
| 7644 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 | ||
| 7645 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 | ||
| 7646 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 | ||
| 7647 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff | ||
| 7648 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 | ||
| 7649 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 | ||
| 7650 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 | ||
| 7651 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7652 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7653 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff | ||
| 7654 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 | ||
| 7655 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 | ||
| 7656 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 | ||
| 7657 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7658 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7659 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff | ||
| 7660 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 | ||
| 7661 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 | ||
| 7662 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 | ||
| 7663 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7664 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7665 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff | ||
| 7666 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 | ||
| 7667 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 | ||
| 7668 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 | ||
| 7669 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7670 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7671 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff | ||
| 7672 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 | ||
| 7673 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 | ||
| 7674 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 | ||
| 7675 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7676 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7677 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff | ||
| 7678 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 | ||
| 7679 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 | ||
| 7680 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 | ||
| 7681 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7682 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7683 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff | ||
| 7684 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 | ||
| 7685 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 | ||
| 7686 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 | ||
| 7687 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7688 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7689 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff | ||
| 7690 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 | ||
| 7691 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 | ||
| 7692 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 | ||
| 7693 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7694 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7695 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff | ||
| 7696 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 | ||
| 7697 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 | ||
| 7698 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 | ||
| 7699 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7700 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7701 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff | ||
| 7702 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 | ||
| 7703 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 | ||
| 7704 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 | ||
| 7705 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7706 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7707 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff | ||
| 7708 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 | ||
| 7709 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 | ||
| 7710 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 | ||
| 7711 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7712 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7713 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff | ||
| 7714 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 | ||
| 7715 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 | ||
| 7716 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 | ||
| 7717 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7718 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7719 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff | ||
| 7720 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 | ||
| 7721 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 | ||
| 7722 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 | ||
| 7723 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7724 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7725 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff | ||
| 7726 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 | ||
| 7727 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 | ||
| 7728 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 | ||
| 7729 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7730 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7731 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff | ||
| 7732 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 | ||
| 7733 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 | ||
| 7734 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 | ||
| 7735 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7736 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7737 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff | ||
| 7738 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 | ||
| 7739 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 | ||
| 7740 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 | ||
| 7741 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 | ||
| 7742 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f | ||
| 7743 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff | ||
| 7744 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 | ||
| 7745 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 | ||
| 7746 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 | ||
| 7747 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff | ||
| 7748 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 | ||
| 7749 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 | ||
| 7750 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 | ||
| 7751 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff | ||
| 7752 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 | ||
| 7753 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 | ||
| 7754 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 | ||
| 7755 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff | ||
| 7756 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 | ||
| 7757 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 | ||
| 7758 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 | ||
| 7759 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff | ||
| 7760 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 | ||
| 7761 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 | ||
| 7762 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 | ||
| 7763 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff | ||
| 7764 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 | ||
| 7765 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 | ||
| 7766 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 | ||
| 7767 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff | ||
| 7768 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 | ||
| 7769 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 | ||
| 7770 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 | ||
| 7771 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff | ||
| 7772 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 | ||
| 7773 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 | ||
| 7774 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 | ||
| 7775 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff | ||
| 7776 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 | ||
| 7777 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 | ||
| 7778 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 | ||
| 7779 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff | ||
| 7780 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 | ||
| 7781 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 | ||
| 7782 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 | ||
| 7783 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff | ||
| 7784 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 | ||
| 7785 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 | ||
| 7786 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 | ||
| 7787 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff | ||
| 7788 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 | ||
| 7789 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 | ||
| 7790 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 | ||
| 7791 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff | ||
| 7792 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 | ||
| 7793 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 | ||
| 7794 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 | ||
| 7795 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff | ||
| 7796 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 | ||
| 7797 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 | ||
| 7798 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 | ||
| 7799 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff | ||
| 7800 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 | ||
| 7801 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 | ||
| 7802 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 | ||
| 7803 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff | ||
| 7804 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 | ||
| 7805 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 | ||
| 7806 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 | ||
| 7807 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff | ||
| 7808 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 | ||
| 7809 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff | ||
| 7810 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 | ||
| 7811 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff | ||
| 7812 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 | ||
| 7813 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff | ||
| 7814 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 | ||
| 7815 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff | ||
| 7816 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 | ||
| 7817 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff | ||
| 7818 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 | ||
| 7819 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff | ||
| 7820 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 | ||
| 7821 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff | ||
| 7822 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 | ||
| 7823 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff | ||
| 7824 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 | ||
| 7825 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff | ||
| 7826 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 | ||
| 7827 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff | ||
| 7828 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 | ||
| 7829 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff | ||
| 7830 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 | ||
| 7831 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff | ||
| 7832 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 | ||
| 7833 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff | ||
| 7834 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 | ||
| 7835 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff | ||
| 7836 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 | ||
| 7837 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff | ||
| 7838 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 | ||
| 7839 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff | ||
| 7840 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 | ||
| 7841 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff | ||
| 7842 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 | ||
| 7843 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff | ||
| 7844 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 | ||
| 7845 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff | ||
| 7846 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 | ||
| 7847 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff | ||
| 7848 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 | ||
| 7849 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff | ||
| 7850 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 | ||
| 7851 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff | ||
| 7852 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 | ||
| 7853 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff | ||
| 7854 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 | ||
| 7855 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff | ||
| 7856 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 | ||
| 7857 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff | ||
| 7858 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 | ||
| 7859 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff | ||
| 7860 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 | ||
| 7861 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff | ||
| 7862 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 | ||
| 7863 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff | ||
| 7864 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 | ||
| 7865 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff | ||
| 7866 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 | ||
| 7867 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff | ||
| 7868 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 | ||
| 7869 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff | ||
| 7870 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 | ||
| 7871 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 | ||
| 7872 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 | ||
| 7873 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 | ||
| 7874 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 | ||
| 7875 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 | ||
| 7876 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 | ||
| 7877 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 | ||
| 7878 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 | ||
| 7879 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 | ||
| 7880 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 | ||
| 7881 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 | ||
| 7882 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 | ||
| 7883 | #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 | ||
| 7884 | #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 | ||
| 7885 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 | ||
| 7886 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 | ||
| 7887 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 | ||
| 7888 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 | ||
| 7889 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 | ||
| 7890 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa | ||
| 7891 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 | ||
| 7892 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb | ||
| 7893 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 | ||
| 7894 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc | ||
| 7895 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 | ||
| 7896 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd | ||
| 7897 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 | ||
| 7898 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe | ||
| 7899 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 | ||
| 7900 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf | ||
| 7901 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 | ||
| 7902 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 | ||
| 7903 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 | ||
| 7904 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 | ||
| 7905 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 | ||
| 7906 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 | ||
| 7907 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 | ||
| 7908 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 | ||
| 7909 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 | ||
| 7910 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 | ||
| 7911 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 | ||
| 7912 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 | ||
| 7913 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 | ||
| 7914 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 | ||
| 7915 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 | ||
| 7916 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 | ||
| 7917 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 | ||
| 7918 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 | ||
| 7919 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 | ||
| 7920 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 | ||
| 7921 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 | ||
| 7922 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a | ||
| 7923 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 | ||
| 7924 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b | ||
| 7925 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 | ||
| 7926 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c | ||
| 7927 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 | ||
| 7928 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d | ||
| 7929 | #define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 | ||
| 7930 | #define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e | ||
| 7931 | #define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 | ||
| 7932 | #define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f | ||
| 7933 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x1 | ||
| 7934 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 | ||
| 7935 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x6 | ||
| 7936 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 | ||
| 7937 | #define PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK 0x8 | ||
| 7938 | #define PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT 0x3 | ||
| 7939 | #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x10 | ||
| 7940 | #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x4 | ||
| 7941 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x20 | ||
| 7942 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x5 | ||
| 7943 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x40 | ||
| 7944 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x6 | ||
| 7945 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x80 | ||
| 7946 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x7 | ||
| 7947 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x1 | ||
| 7948 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 | ||
| 7949 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x2 | ||
| 7950 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 | ||
| 7951 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f | ||
| 7952 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 | ||
| 7953 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 | ||
| 7954 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 | ||
| 7955 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 | ||
| 7956 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf | ||
| 7957 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 | ||
| 7958 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 | ||
| 7959 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f | ||
| 7960 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 | ||
| 7961 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 | ||
| 7962 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 | ||
| 7963 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 | ||
| 7964 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc | ||
| 7965 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 | ||
| 7966 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 | ||
| 7967 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff | ||
| 7968 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 | ||
| 7969 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 | ||
| 7970 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 | ||
| 7971 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf | ||
| 7972 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 | ||
| 7973 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 | ||
| 7974 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 | ||
| 7975 | #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff | ||
| 7976 | #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 | ||
| 7977 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 | ||
| 7978 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 | ||
| 7979 | #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff | ||
| 7980 | #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 | ||
| 7981 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 | ||
| 7982 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 | ||
| 7983 | #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff | ||
| 7984 | #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 | ||
| 7985 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 | ||
| 7986 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 | ||
| 7987 | #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff | ||
| 7988 | #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 | ||
| 7989 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 | ||
| 7990 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 | ||
| 7991 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 7992 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 7993 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 7994 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 7995 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 7996 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 7997 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 7998 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 7999 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 8000 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 8001 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8002 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8003 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8004 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8005 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8006 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8007 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8008 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8009 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8010 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8011 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8012 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8013 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff | ||
| 8014 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 8015 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8016 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8017 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8018 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8019 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8020 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8021 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8022 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8023 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8024 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8025 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8026 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8027 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8028 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8029 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8030 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8031 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8032 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8033 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8034 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8035 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8036 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8037 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8038 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8039 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8040 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8041 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8042 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8043 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 8044 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 8045 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 8046 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 8047 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 | ||
| 8048 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 | ||
| 8049 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 | ||
| 8050 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 | ||
| 8051 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff | ||
| 8052 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 | ||
| 8053 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff | ||
| 8054 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 | ||
| 8055 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff | ||
| 8056 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 | ||
| 8057 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff | ||
| 8058 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 | ||
| 8059 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 | ||
| 8060 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 | ||
| 8061 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 | ||
| 8062 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 | ||
| 8063 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff | ||
| 8064 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 | ||
| 8065 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff | ||
| 8066 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 | ||
| 8067 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff | ||
| 8068 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 | ||
| 8069 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff | ||
| 8070 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 | ||
| 8071 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 | ||
| 8072 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 | ||
| 8073 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 | ||
| 8074 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 | ||
| 8075 | #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff | ||
| 8076 | #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 | ||
| 8077 | #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff | ||
| 8078 | #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 | ||
| 8079 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff | ||
| 8080 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 | ||
| 8081 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff | ||
| 8082 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 | ||
| 8083 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 | ||
| 8084 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 | ||
| 8085 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 | ||
| 8086 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 | ||
| 8087 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 | ||
| 8088 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 | ||
| 8089 | #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 | ||
| 8090 | #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f | ||
| 8091 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 | ||
| 8092 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f | ||
| 8093 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff | ||
| 8094 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 | ||
| 8095 | #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 8096 | #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 8097 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 8098 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 8099 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 8100 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 8101 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 8102 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 8103 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 8104 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 8105 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 8106 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 8107 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 8108 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 8109 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 | ||
| 8110 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d | ||
| 8111 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 | ||
| 8112 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e | ||
| 8113 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 | ||
| 8114 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f | ||
| 8115 | #define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 8116 | #define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 8117 | #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 8118 | #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 8119 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 8120 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 8121 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 8122 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 8123 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 8124 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 8125 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 8126 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 8127 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 8128 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 8129 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 8130 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 8131 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 8132 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 8133 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 8134 | #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 8135 | #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f | ||
| 8136 | #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 | ||
| 8137 | #define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 8138 | #define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 8139 | #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f | ||
| 8140 | #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 | ||
| 8141 | #define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 8142 | #define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 8143 | #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff | ||
| 8144 | #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 | ||
| 8145 | #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 | ||
| 8146 | #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 | ||
| 8147 | #define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 | ||
| 8148 | #define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 | ||
| 8149 | #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 | ||
| 8150 | #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb | ||
| 8151 | #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 | ||
| 8152 | #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc | ||
| 8153 | #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 | ||
| 8154 | #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd | ||
| 8155 | #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 | ||
| 8156 | #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe | ||
| 8157 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 | ||
| 8158 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf | ||
| 8159 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 | ||
| 8160 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 | ||
| 8161 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 | ||
| 8162 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 | ||
| 8163 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 | ||
| 8164 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 | ||
| 8165 | #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 | ||
| 8166 | #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 | ||
| 8167 | #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 | ||
| 8168 | #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 | ||
| 8169 | #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 | ||
| 8170 | #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 | ||
| 8171 | #define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 | ||
| 8172 | #define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 | ||
| 8173 | #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 | ||
| 8174 | #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 | ||
| 8175 | #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 | ||
| 8176 | #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 | ||
| 8177 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 | ||
| 8178 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 | ||
| 8179 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 | ||
| 8180 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a | ||
| 8181 | #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 | ||
| 8182 | #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b | ||
| 8183 | #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 | ||
| 8184 | #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c | ||
| 8185 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 | ||
| 8186 | #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d | ||
| 8187 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 | ||
| 8188 | #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e | ||
| 8189 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 | ||
| 8190 | #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f | ||
| 8191 | #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff | ||
| 8192 | #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 | ||
| 8193 | #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 | ||
| 8194 | #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 | ||
| 8195 | #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 | ||
| 8196 | #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb | ||
| 8197 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 | ||
| 8198 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe | ||
| 8199 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 | ||
| 8200 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 | ||
| 8201 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 | ||
| 8202 | #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 | ||
| 8203 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 | ||
| 8204 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 | ||
| 8205 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 | ||
| 8206 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 | ||
| 8207 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 | ||
| 8208 | #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 | ||
| 8209 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 | ||
| 8210 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 | ||
| 8211 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 | ||
| 8212 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 | ||
| 8213 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 | ||
| 8214 | #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a | ||
| 8215 | #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 | ||
| 8216 | #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c | ||
| 8217 | #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 | ||
| 8218 | #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d | ||
| 8219 | #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 | ||
| 8220 | #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e | ||
| 8221 | #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 | ||
| 8222 | #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f | ||
| 8223 | #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 | ||
| 8224 | #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 | ||
| 8225 | #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 | ||
| 8226 | #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 | ||
| 8227 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 | ||
| 8228 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 | ||
| 8229 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 | ||
| 8230 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 | ||
| 8231 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 | ||
| 8232 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc | ||
| 8233 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 | ||
| 8234 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 | ||
| 8235 | #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 | ||
| 8236 | #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 | ||
| 8237 | #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 | ||
| 8238 | #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 | ||
| 8239 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 | ||
| 8240 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 | ||
| 8241 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 | ||
| 8242 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 | ||
| 8243 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 | ||
| 8244 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 | ||
| 8245 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 | ||
| 8246 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 | ||
| 8247 | #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 | ||
| 8248 | #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a | ||
| 8249 | #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 | ||
| 8250 | #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b | ||
| 8251 | #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 | ||
| 8252 | #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c | ||
| 8253 | #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 | ||
| 8254 | #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d | ||
| 8255 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 | ||
| 8256 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e | ||
| 8257 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 | ||
| 8258 | #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f | ||
| 8259 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff | ||
| 8260 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 | ||
| 8261 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 | ||
| 8262 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe | ||
| 8263 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 | ||
| 8264 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 | ||
| 8265 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 | ||
| 8266 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 | ||
| 8267 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 | ||
| 8268 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 | ||
| 8269 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 | ||
| 8270 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b | ||
| 8271 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 | ||
| 8272 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c | ||
| 8273 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 | ||
| 8274 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d | ||
| 8275 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8276 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8277 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8278 | #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8279 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe | ||
| 8280 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 | ||
| 8281 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 | ||
| 8282 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb | ||
| 8283 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 | ||
| 8284 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 | ||
| 8285 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 | ||
| 8286 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 | ||
| 8287 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 | ||
| 8288 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d | ||
| 8289 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8290 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8291 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8292 | #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8293 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff | ||
| 8294 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 | ||
| 8295 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 | ||
| 8296 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe | ||
| 8297 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 | ||
| 8298 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 | ||
| 8299 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 | ||
| 8300 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 | ||
| 8301 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 | ||
| 8302 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 | ||
| 8303 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 | ||
| 8304 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b | ||
| 8305 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 | ||
| 8306 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c | ||
| 8307 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 | ||
| 8308 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d | ||
| 8309 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8310 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8311 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8312 | #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8313 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe | ||
| 8314 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 | ||
| 8315 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 | ||
| 8316 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb | ||
| 8317 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 | ||
| 8318 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 | ||
| 8319 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 | ||
| 8320 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 | ||
| 8321 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 | ||
| 8322 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d | ||
| 8323 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8324 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8325 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8326 | #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8327 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff | ||
| 8328 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 | ||
| 8329 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 | ||
| 8330 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe | ||
| 8331 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 | ||
| 8332 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 | ||
| 8333 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 | ||
| 8334 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 | ||
| 8335 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 | ||
| 8336 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 | ||
| 8337 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 | ||
| 8338 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b | ||
| 8339 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 | ||
| 8340 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c | ||
| 8341 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 | ||
| 8342 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d | ||
| 8343 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8344 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8345 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8346 | #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8347 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe | ||
| 8348 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 | ||
| 8349 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 | ||
| 8350 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb | ||
| 8351 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 | ||
| 8352 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 | ||
| 8353 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 | ||
| 8354 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 | ||
| 8355 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 | ||
| 8356 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d | ||
| 8357 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8358 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8359 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8360 | #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8361 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff | ||
| 8362 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 | ||
| 8363 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 | ||
| 8364 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe | ||
| 8365 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 | ||
| 8366 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 | ||
| 8367 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 | ||
| 8368 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 | ||
| 8369 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 | ||
| 8370 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 | ||
| 8371 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 | ||
| 8372 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b | ||
| 8373 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 | ||
| 8374 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c | ||
| 8375 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 | ||
| 8376 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d | ||
| 8377 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8378 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8379 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8380 | #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8381 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe | ||
| 8382 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 | ||
| 8383 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 | ||
| 8384 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb | ||
| 8385 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 | ||
| 8386 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 | ||
| 8387 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 | ||
| 8388 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 | ||
| 8389 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 | ||
| 8390 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d | ||
| 8391 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 | ||
| 8392 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e | ||
| 8393 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8394 | #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8395 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 | ||
| 8396 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 | ||
| 8397 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 | ||
| 8398 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 | ||
| 8399 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 | ||
| 8400 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 | ||
| 8401 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 | ||
| 8402 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 | ||
| 8403 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 | ||
| 8404 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 | ||
| 8405 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 | ||
| 8406 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 | ||
| 8407 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 | ||
| 8408 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 | ||
| 8409 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 | ||
| 8410 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 | ||
| 8411 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 | ||
| 8412 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 | ||
| 8413 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 | ||
| 8414 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc | ||
| 8415 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 | ||
| 8416 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 | ||
| 8417 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 | ||
| 8418 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 | ||
| 8419 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 | ||
| 8420 | #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 | ||
| 8421 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 | ||
| 8422 | #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 | ||
| 8423 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 | ||
| 8424 | #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a | ||
| 8425 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 | ||
| 8426 | #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b | ||
| 8427 | #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 | ||
| 8428 | #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c | ||
| 8429 | #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 | ||
| 8430 | #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d | ||
| 8431 | #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 | ||
| 8432 | #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e | ||
| 8433 | #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 | ||
| 8434 | #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f | ||
| 8435 | #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff | ||
| 8436 | #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 | ||
| 8437 | #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 | ||
| 8438 | #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 | ||
| 8439 | #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 | ||
| 8440 | #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd | ||
| 8441 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 | ||
| 8442 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 | ||
| 8443 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 | ||
| 8444 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 | ||
| 8445 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 | ||
| 8446 | #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 | ||
| 8447 | #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 | ||
| 8448 | #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 | ||
| 8449 | #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 | ||
| 8450 | #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 | ||
| 8451 | #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 | ||
| 8452 | #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a | ||
| 8453 | #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 | ||
| 8454 | #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b | ||
| 8455 | #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 | ||
| 8456 | #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c | ||
| 8457 | #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 | ||
| 8458 | #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d | ||
| 8459 | #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 | ||
| 8460 | #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e | ||
| 8461 | #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8462 | #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8463 | #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 | ||
| 8464 | #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 | ||
| 8465 | #define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 | ||
| 8466 | #define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 | ||
| 8467 | #define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 | ||
| 8468 | #define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 | ||
| 8469 | #define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 | ||
| 8470 | #define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 | ||
| 8471 | #define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 | ||
| 8472 | #define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 | ||
| 8473 | #define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 | ||
| 8474 | #define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 | ||
| 8475 | #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 | ||
| 8476 | #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 | ||
| 8477 | #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 | ||
| 8478 | #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc | ||
| 8479 | #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 | ||
| 8480 | #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe | ||
| 8481 | #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 | ||
| 8482 | #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf | ||
| 8483 | #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 | ||
| 8484 | #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 | ||
| 8485 | #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 | ||
| 8486 | #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 | ||
| 8487 | #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 | ||
| 8488 | #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 | ||
| 8489 | #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 | ||
| 8490 | #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 | ||
| 8491 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 | ||
| 8492 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 | ||
| 8493 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 | ||
| 8494 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d | ||
| 8495 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 | ||
| 8496 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e | ||
| 8497 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 | ||
| 8498 | #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f | ||
| 8499 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f | ||
| 8500 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 | ||
| 8501 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 | ||
| 8502 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 | ||
| 8503 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 | ||
| 8504 | #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc | ||
| 8505 | #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 | ||
| 8506 | #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 | ||
| 8507 | #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 | ||
| 8508 | #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 | ||
| 8509 | #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 | ||
| 8510 | #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 | ||
| 8511 | #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 | ||
| 8512 | #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 | ||
| 8513 | #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 | ||
| 8514 | #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 | ||
| 8515 | #define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 | ||
| 8516 | #define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e | ||
| 8517 | #define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 | ||
| 8518 | #define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f | ||
| 8519 | #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff | ||
| 8520 | #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 | ||
| 8521 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 | ||
| 8522 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 | ||
| 8523 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 | ||
| 8524 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 | ||
| 8525 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 | ||
| 8526 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a | ||
| 8527 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 | ||
| 8528 | #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f | ||
| 8529 | #define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f | ||
| 8530 | #define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 | ||
| 8531 | #define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 | ||
| 8532 | #define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 | ||
| 8533 | #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 | ||
| 8534 | #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 | ||
| 8535 | #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 | ||
| 8536 | #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd | ||
| 8537 | #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 | ||
| 8538 | #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 | ||
| 8539 | #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 | ||
| 8540 | #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 | ||
| 8541 | #define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 | ||
| 8542 | #define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 | ||
| 8543 | #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 | ||
| 8544 | #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b | ||
| 8545 | #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 | ||
| 8546 | #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c | ||
| 8547 | #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 | ||
| 8548 | #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d | ||
| 8549 | #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 | ||
| 8550 | #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e | ||
| 8551 | #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8552 | #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8553 | #define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f | ||
| 8554 | #define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 | ||
| 8555 | #define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 | ||
| 8556 | #define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 | ||
| 8557 | #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 | ||
| 8558 | #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 | ||
| 8559 | #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 | ||
| 8560 | #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd | ||
| 8561 | #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 | ||
| 8562 | #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 | ||
| 8563 | #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 | ||
| 8564 | #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 | ||
| 8565 | #define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 | ||
| 8566 | #define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 | ||
| 8567 | #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 | ||
| 8568 | #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b | ||
| 8569 | #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 | ||
| 8570 | #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c | ||
| 8571 | #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 | ||
| 8572 | #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d | ||
| 8573 | #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 | ||
| 8574 | #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e | ||
| 8575 | #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8576 | #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8577 | #define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f | ||
| 8578 | #define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 | ||
| 8579 | #define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 | ||
| 8580 | #define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 | ||
| 8581 | #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 | ||
| 8582 | #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 | ||
| 8583 | #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 | ||
| 8584 | #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd | ||
| 8585 | #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 | ||
| 8586 | #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 | ||
| 8587 | #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 | ||
| 8588 | #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 | ||
| 8589 | #define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 | ||
| 8590 | #define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 | ||
| 8591 | #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 | ||
| 8592 | #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b | ||
| 8593 | #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 | ||
| 8594 | #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c | ||
| 8595 | #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 | ||
| 8596 | #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d | ||
| 8597 | #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 | ||
| 8598 | #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e | ||
| 8599 | #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8600 | #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8601 | #define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f | ||
| 8602 | #define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 | ||
| 8603 | #define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 | ||
| 8604 | #define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 | ||
| 8605 | #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 | ||
| 8606 | #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 | ||
| 8607 | #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 | ||
| 8608 | #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd | ||
| 8609 | #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 | ||
| 8610 | #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 | ||
| 8611 | #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 | ||
| 8612 | #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 | ||
| 8613 | #define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 | ||
| 8614 | #define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 | ||
| 8615 | #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 | ||
| 8616 | #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b | ||
| 8617 | #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 | ||
| 8618 | #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c | ||
| 8619 | #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 | ||
| 8620 | #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d | ||
| 8621 | #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 | ||
| 8622 | #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e | ||
| 8623 | #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 | ||
| 8624 | #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f | ||
| 8625 | #define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f | ||
| 8626 | #define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 | ||
| 8627 | #define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 | ||
| 8628 | #define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 | ||
| 8629 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 | ||
| 8630 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 | ||
| 8631 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 | ||
| 8632 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc | ||
| 8633 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 | ||
| 8634 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 | ||
| 8635 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 | ||
| 8636 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a | ||
| 8637 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 | ||
| 8638 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c | ||
| 8639 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 | ||
| 8640 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e | ||
| 8641 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 | ||
| 8642 | #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f | ||
| 8643 | #define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f | ||
| 8644 | #define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 | ||
| 8645 | #define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 | ||
| 8646 | #define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 | ||
| 8647 | #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 | ||
| 8648 | #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa | ||
| 8649 | #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 | ||
| 8650 | #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf | ||
| 8651 | #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 | ||
| 8652 | #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 | ||
| 8653 | #define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 | ||
| 8654 | #define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 | ||
| 8655 | #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 | ||
| 8656 | #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 | ||
| 8657 | #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 | ||
| 8658 | #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 | ||
| 8659 | #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 | ||
| 8660 | #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 | ||
| 8661 | #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 | ||
| 8662 | #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c | ||
| 8663 | #define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f | ||
| 8664 | #define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 | ||
| 8665 | #define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 | ||
| 8666 | #define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 | ||
| 8667 | #define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 | ||
| 8668 | #define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 | ||
| 8669 | #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 | ||
| 8670 | #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf | ||
| 8671 | #define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 | ||
| 8672 | #define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 | ||
| 8673 | #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 | ||
| 8674 | #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 | ||
| 8675 | #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 | ||
| 8676 | #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a | ||
| 8677 | #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff | ||
| 8678 | #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 | ||
| 8679 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 | ||
| 8680 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 | ||
| 8681 | #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 | ||
| 8682 | #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc | ||
| 8683 | #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 | ||
| 8684 | #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd | ||
| 8685 | #define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 | ||
| 8686 | #define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe | ||
| 8687 | #define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 | ||
| 8688 | #define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 | ||
| 8689 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 | ||
| 8690 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 | ||
| 8691 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 | ||
| 8692 | #define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 | ||
| 8693 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 | ||
| 8694 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 | ||
| 8695 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 | ||
| 8696 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a | ||
| 8697 | #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 | ||
| 8698 | #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b | ||
| 8699 | #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 | ||
| 8700 | #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c | ||
| 8701 | #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 | ||
| 8702 | #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d | ||
| 8703 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 | ||
| 8704 | #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e | ||
| 8705 | #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 | ||
| 8706 | #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f | ||
| 8707 | #define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 | ||
| 8708 | #define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 | ||
| 8709 | #define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c | ||
| 8710 | #define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 | ||
| 8711 | #define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 | ||
| 8712 | #define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 | ||
| 8713 | #define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 | ||
| 8714 | #define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe | ||
| 8715 | #define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 | ||
| 8716 | #define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf | ||
| 8717 | #define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 | ||
| 8718 | #define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 | ||
| 8719 | #define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 | ||
| 8720 | #define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 | ||
| 8721 | #define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 | ||
| 8722 | #define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 | ||
| 8723 | #define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 | ||
| 8724 | #define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 | ||
| 8725 | #define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 | ||
| 8726 | #define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 | ||
| 8727 | #define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 | ||
| 8728 | #define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 | ||
| 8729 | #define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 | ||
| 8730 | #define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c | ||
| 8731 | #define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 | ||
| 8732 | #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d | ||
| 8733 | #define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 | ||
| 8734 | #define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e | ||
| 8735 | #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 | ||
| 8736 | #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f | ||
| 8737 | #define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff | ||
| 8738 | #define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 | ||
| 8739 | #define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 | ||
| 8740 | #define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 | ||
| 8741 | #define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff | ||
| 8742 | #define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 | ||
| 8743 | #define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 | ||
| 8744 | #define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 | ||
| 8745 | #define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff | ||
| 8746 | #define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 | ||
| 8747 | #define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 | ||
| 8748 | #define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 | ||
| 8749 | #define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff | ||
| 8750 | #define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 | ||
| 8751 | #define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 | ||
| 8752 | #define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe | ||
| 8753 | #define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 | ||
| 8754 | #define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf | ||
| 8755 | #define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 | ||
| 8756 | #define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 | ||
| 8757 | #define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 | ||
| 8758 | #define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 | ||
| 8759 | #define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 | ||
| 8760 | #define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 | ||
| 8761 | #define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 | ||
| 8762 | #define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 | ||
| 8763 | #define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 | ||
| 8764 | #define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 | ||
| 8765 | #define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 | ||
| 8766 | #define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a | ||
| 8767 | #define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 | ||
| 8768 | #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d | ||
| 8769 | #define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 | ||
| 8770 | #define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f | ||
| 8771 | #define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff | ||
| 8772 | #define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 | ||
| 8773 | #define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 | ||
| 8774 | #define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe | ||
| 8775 | #define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 | ||
| 8776 | #define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c | ||
| 8777 | #define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 | ||
| 8778 | #define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e | ||
| 8779 | #define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 | ||
| 8780 | #define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f | ||
| 8781 | #define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 | ||
| 8782 | #define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 | ||
| 8783 | #define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc | ||
| 8784 | #define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 | ||
| 8785 | #define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 | ||
| 8786 | #define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 | ||
| 8787 | #define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc | ||
| 8788 | #define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 | ||
| 8789 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 | ||
| 8790 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 | ||
| 8791 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 | ||
| 8792 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 | ||
| 8793 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 | ||
| 8794 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 | ||
| 8795 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 | ||
| 8796 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 | ||
| 8797 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 | ||
| 8798 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 | ||
| 8799 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 | ||
| 8800 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 | ||
| 8801 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 | ||
| 8802 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 | ||
| 8803 | #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 | ||
| 8804 | #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 | ||
| 8805 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 | ||
| 8806 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa | ||
| 8807 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 | ||
| 8808 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb | ||
| 8809 | #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 | ||
| 8810 | #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc | ||
| 8811 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 | ||
| 8812 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe | ||
| 8813 | #define COMPUTE_DIM_X__SIZE_MASK 0xffffffff | ||
| 8814 | #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 | ||
| 8815 | #define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff | ||
| 8816 | #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 | ||
| 8817 | #define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff | ||
| 8818 | #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 | ||
| 8819 | #define COMPUTE_START_X__START_MASK 0xffffffff | ||
| 8820 | #define COMPUTE_START_X__START__SHIFT 0x0 | ||
| 8821 | #define COMPUTE_START_Y__START_MASK 0xffffffff | ||
| 8822 | #define COMPUTE_START_Y__START__SHIFT 0x0 | ||
| 8823 | #define COMPUTE_START_Z__START_MASK 0xffffffff | ||
| 8824 | #define COMPUTE_START_Z__START__SHIFT 0x0 | ||
| 8825 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff | ||
| 8826 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 | ||
| 8827 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 | ||
| 8828 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 | ||
| 8829 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff | ||
| 8830 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 | ||
| 8831 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 | ||
| 8832 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 | ||
| 8833 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff | ||
| 8834 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 | ||
| 8835 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 | ||
| 8836 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 | ||
| 8837 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 | ||
| 8838 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 | ||
| 8839 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 | ||
| 8840 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 | ||
| 8841 | #define COMPUTE_PGM_LO__DATA_MASK 0xffffffff | ||
| 8842 | #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 | ||
| 8843 | #define COMPUTE_PGM_HI__DATA_MASK 0xff | ||
| 8844 | #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 | ||
| 8845 | #define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 | ||
| 8846 | #define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 | ||
| 8847 | #define COMPUTE_TBA_LO__DATA_MASK 0xffffffff | ||
| 8848 | #define COMPUTE_TBA_LO__DATA__SHIFT 0x0 | ||
| 8849 | #define COMPUTE_TBA_HI__DATA_MASK 0xff | ||
| 8850 | #define COMPUTE_TBA_HI__DATA__SHIFT 0x0 | ||
| 8851 | #define COMPUTE_TMA_LO__DATA_MASK 0xffffffff | ||
| 8852 | #define COMPUTE_TMA_LO__DATA__SHIFT 0x0 | ||
| 8853 | #define COMPUTE_TMA_HI__DATA_MASK 0xff | ||
| 8854 | #define COMPUTE_TMA_HI__DATA__SHIFT 0x0 | ||
| 8855 | #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f | ||
| 8856 | #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 | ||
| 8857 | #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 | ||
| 8858 | #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 | ||
| 8859 | #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 | ||
| 8860 | #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa | ||
| 8861 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 | ||
| 8862 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc | ||
| 8863 | #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 | ||
| 8864 | #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 | ||
| 8865 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 | ||
| 8866 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 | ||
| 8867 | #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 | ||
| 8868 | #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 | ||
| 8869 | #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 | ||
| 8870 | #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 | ||
| 8871 | #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 | ||
| 8872 | #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 | ||
| 8873 | #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 | ||
| 8874 | #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 | ||
| 8875 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 | ||
| 8876 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 | ||
| 8877 | #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e | ||
| 8878 | #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 | ||
| 8879 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 | ||
| 8880 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 | ||
| 8881 | #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 | ||
| 8882 | #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 | ||
| 8883 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 | ||
| 8884 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 | ||
| 8885 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 | ||
| 8886 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 | ||
| 8887 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 | ||
| 8888 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa | ||
| 8889 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 | ||
| 8890 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb | ||
| 8891 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 | ||
| 8892 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd | ||
| 8893 | #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 | ||
| 8894 | #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf | ||
| 8895 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 | ||
| 8896 | #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 | ||
| 8897 | #define COMPUTE_VMID__DATA_MASK 0xf | ||
| 8898 | #define COMPUTE_VMID__DATA__SHIFT 0x0 | ||
| 8899 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff | ||
| 8900 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 | ||
| 8901 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 | ||
| 8902 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc | ||
| 8903 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 | ||
| 8904 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 | ||
| 8905 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 | ||
| 8906 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 | ||
| 8907 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 | ||
| 8908 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 | ||
| 8909 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 | ||
| 8910 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 | ||
| 8911 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff | ||
| 8912 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 | ||
| 8913 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 | ||
| 8914 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 | ||
| 8915 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff | ||
| 8916 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 | ||
| 8917 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 | ||
| 8918 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 | ||
| 8919 | #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff | ||
| 8920 | #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 | ||
| 8921 | #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 | ||
| 8922 | #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc | ||
| 8923 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff | ||
| 8924 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 | ||
| 8925 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 | ||
| 8926 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 | ||
| 8927 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff | ||
| 8928 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 | ||
| 8929 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 | ||
| 8930 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 | ||
| 8931 | #define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff | ||
| 8932 | #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 | ||
| 8933 | #define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff | ||
| 8934 | #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 | ||
| 8935 | #define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff | ||
| 8936 | #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 | ||
| 8937 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 | ||
| 8938 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 | ||
| 8939 | #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 | ||
| 8940 | #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 | ||
| 8941 | #define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 | ||
| 8942 | #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 | ||
| 8943 | #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 | ||
| 8944 | #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 | ||
| 8945 | #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 | ||
| 8946 | #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 | ||
| 8947 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0 | ||
| 8948 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 | ||
| 8949 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff | ||
| 8950 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 | ||
| 8951 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff | ||
| 8952 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 | ||
| 8953 | #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff | ||
| 8954 | #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 | ||
| 8955 | #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000 | ||
| 8956 | #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e | ||
| 8957 | #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000 | ||
| 8958 | #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f | ||
| 8959 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff | ||
| 8960 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 | ||
| 8961 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff | ||
| 8962 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 | ||
| 8963 | #define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1 | ||
| 8964 | #define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0 | ||
| 8965 | #define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6 | ||
| 8966 | #define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1 | ||
| 8967 | #define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff | ||
| 8968 | #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 | ||
| 8969 | #define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff | ||
| 8970 | #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 | ||
| 8971 | #define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff | ||
| 8972 | #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 | ||
| 8973 | #define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff | ||
| 8974 | #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 | ||
| 8975 | #define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff | ||
| 8976 | #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 | ||
| 8977 | #define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff | ||
| 8978 | #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 | ||
| 8979 | #define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff | ||
| 8980 | #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 | ||
| 8981 | #define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff | ||
| 8982 | #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 | ||
| 8983 | #define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff | ||
| 8984 | #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 | ||
| 8985 | #define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff | ||
| 8986 | #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 | ||
| 8987 | #define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff | ||
| 8988 | #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 | ||
| 8989 | #define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff | ||
| 8990 | #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 | ||
| 8991 | #define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff | ||
| 8992 | #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 | ||
| 8993 | #define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff | ||
| 8994 | #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 | ||
| 8995 | #define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff | ||
| 8996 | #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 | ||
| 8997 | #define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff | ||
| 8998 | #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 | ||
| 8999 | #define COMPUTE_NOWHERE__DATA_MASK 0xffffffff | ||
| 9000 | #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 | ||
| 9001 | #define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff | ||
| 9002 | #define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 | ||
| 9003 | #define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 | ||
| 9004 | #define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 | ||
| 9005 | #define CSPRIV_CONNECT__VMID_MASK 0x3c000000 | ||
| 9006 | #define CSPRIV_CONNECT__VMID__SHIFT 0x1a | ||
| 9007 | #define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 | ||
| 9008 | #define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f | ||
| 9009 | #define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff | ||
| 9010 | #define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 | ||
| 9011 | #define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff | ||
| 9012 | #define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 | ||
| 9013 | #define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff | ||
| 9014 | #define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 | ||
| 9015 | #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff | ||
| 9016 | #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 | ||
| 9017 | #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 | ||
| 9018 | #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc | ||
| 9019 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 | ||
| 9020 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 | ||
| 9021 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 | ||
| 9022 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 | ||
| 9023 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 | ||
| 9024 | #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a | ||
| 9025 | #define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 | ||
| 9026 | #define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b | ||
| 9027 | #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 | ||
| 9028 | #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c | ||
| 9029 | #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f | ||
| 9030 | #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 | ||
| 9031 | #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 | ||
| 9032 | #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 | ||
| 9033 | #define RLC_CNTL__FORCE_RETRY_MASK 0x2 | ||
| 9034 | #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 | ||
| 9035 | #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 | ||
| 9036 | #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 | ||
| 9037 | #define RLC_CNTL__RLC_STEP_F32_MASK 0x8 | ||
| 9038 | #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 | ||
| 9039 | #define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 | ||
| 9040 | #define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 | ||
| 9041 | #define RLC_CNTL__RESERVED_MASK 0xffffff00 | ||
| 9042 | #define RLC_CNTL__RESERVED__SHIFT 0x8 | ||
| 9043 | #define RLC_DEBUG_SELECT__SELECT_MASK 0xff | ||
| 9044 | #define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 | ||
| 9045 | #define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 | ||
| 9046 | #define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 | ||
| 9047 | #define RLC_DEBUG__DATA_MASK 0xffffffff | ||
| 9048 | #define RLC_DEBUG__DATA__SHIFT 0x0 | ||
| 9049 | #define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 | ||
| 9050 | #define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 | ||
| 9051 | #define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 | ||
| 9052 | #define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 | ||
| 9053 | #define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 | ||
| 9054 | #define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 | ||
| 9055 | #define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 | ||
| 9056 | #define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 | ||
| 9057 | #define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 | ||
| 9058 | #define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 | ||
| 9059 | #define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 | ||
| 9060 | #define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 | ||
| 9061 | #define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 | ||
| 9062 | #define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd | ||
| 9063 | #define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 | ||
| 9064 | #define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 | ||
| 9065 | #define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 | ||
| 9066 | #define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 | ||
| 9067 | #define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 | ||
| 9068 | #define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a | ||
| 9069 | #define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 | ||
| 9070 | #define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b | ||
| 9071 | #define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 | ||
| 9072 | #define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c | ||
| 9073 | #define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 | ||
| 9074 | #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d | ||
| 9075 | #define RLC_STAT__RLC_BUSY_MASK 0x1 | ||
| 9076 | #define RLC_STAT__RLC_BUSY__SHIFT 0x0 | ||
| 9077 | #define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 | ||
| 9078 | #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 | ||
| 9079 | #define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 | ||
| 9080 | #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 | ||
| 9081 | #define RLC_STAT__RLC_SRM_BUSY_MASK 0x8 | ||
| 9082 | #define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 | ||
| 9083 | #define RLC_STAT__RESERVED_MASK 0xfffffff0 | ||
| 9084 | #define RLC_STAT__RESERVED__SHIFT 0x4 | ||
| 9085 | #define RLC_SAFE_MODE__CMD_MASK 0x1 | ||
| 9086 | #define RLC_SAFE_MODE__CMD__SHIFT 0x0 | ||
| 9087 | #define RLC_SAFE_MODE__MESSAGE_MASK 0x1e | ||
| 9088 | #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 | ||
| 9089 | #define RLC_SAFE_MODE__RESERVED1_MASK 0xe0 | ||
| 9090 | #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 | ||
| 9091 | #define RLC_SAFE_MODE__RESPONSE_MASK 0xf00 | ||
| 9092 | #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 | ||
| 9093 | #define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000 | ||
| 9094 | #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc | ||
| 9095 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 | ||
| 9096 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 | ||
| 9097 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 | ||
| 9098 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 | ||
| 9099 | #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c | ||
| 9100 | #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 | ||
| 9101 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80 | ||
| 9102 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 | ||
| 9103 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 | ||
| 9104 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 | ||
| 9105 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 | ||
| 9106 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 | ||
| 9107 | #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 | ||
| 9108 | #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 | ||
| 9109 | #define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff | ||
| 9110 | #define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 | ||
| 9111 | #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1 | ||
| 9112 | #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 | ||
| 9113 | #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e | ||
| 9114 | #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 | ||
| 9115 | #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0 | ||
| 9116 | #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 | ||
| 9117 | #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00 | ||
| 9118 | #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 | ||
| 9119 | #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000 | ||
| 9120 | #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc | ||
| 9121 | #define RLC_SMU_SAFE_MODE__CMD_MASK 0x1 | ||
| 9122 | #define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 | ||
| 9123 | #define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e | ||
| 9124 | #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 | ||
| 9125 | #define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0 | ||
| 9126 | #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 | ||
| 9127 | #define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00 | ||
| 9128 | #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 | ||
| 9129 | #define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000 | ||
| 9130 | #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc | ||
| 9131 | #define RLC_RLCV_COMMAND__CMD_MASK 0xf | ||
| 9132 | #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 | ||
| 9133 | #define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0 | ||
| 9134 | #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 | ||
| 9135 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x1 | ||
| 9136 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 | ||
| 9137 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x2 | ||
| 9138 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 | ||
| 9139 | #define RLC_CLK_CNTL__RESERVED_MASK 0xfffffffc | ||
| 9140 | #define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 | ||
| 9141 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1 | ||
| 9142 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 | ||
| 9143 | #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 | ||
| 9144 | #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 | ||
| 9145 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 | ||
| 9146 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa | ||
| 9147 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff | ||
| 9148 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 9149 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff | ||
| 9150 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 9151 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 9152 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 9153 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 9154 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 9155 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 9156 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 9157 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 9158 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 9159 | #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 9160 | #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 9161 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 9162 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 9163 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 | ||
| 9164 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e | ||
| 9165 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 | ||
| 9166 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f | ||
| 9167 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 | ||
| 9168 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 | ||
| 9169 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 | ||
| 9170 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 | ||
| 9171 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 | ||
| 9172 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 | ||
| 9173 | #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 | ||
| 9174 | #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 | ||
| 9175 | #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 | ||
| 9176 | #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 | ||
| 9177 | #define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 | ||
| 9178 | #define RLC_LB_CNTL__RESERVED__SHIFT 0xc | ||
| 9179 | #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff | ||
| 9180 | #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 | ||
| 9181 | #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff | ||
| 9182 | #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 | ||
| 9183 | #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff | ||
| 9184 | #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 | ||
| 9185 | #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff | ||
| 9186 | #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 | ||
| 9187 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff | ||
| 9188 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 | ||
| 9189 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 | ||
| 9190 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 | ||
| 9191 | #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 | ||
| 9192 | #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 | ||
| 9193 | #define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff | ||
| 9194 | #define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 | ||
| 9195 | #define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300 | ||
| 9196 | #define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8 | ||
| 9197 | #define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00 | ||
| 9198 | #define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa | ||
| 9199 | #define RLC_GPM_DEBUG__DATA_MASK 0xffffffff | ||
| 9200 | #define RLC_GPM_DEBUG__DATA__SHIFT 0x0 | ||
| 9201 | #define RLC_GPM_DEBUG_INST_A__INST_A_MASK 0xffffffff | ||
| 9202 | #define RLC_GPM_DEBUG_INST_A__INST_A__SHIFT 0x0 | ||
| 9203 | #define RLC_GPM_DEBUG_INST_B__INST_B_MASK 0xffffffff | ||
| 9204 | #define RLC_GPM_DEBUG_INST_B__INST_B__SHIFT 0x0 | ||
| 9205 | #define RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK 0xffff | ||
| 9206 | #define RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT 0x0 | ||
| 9207 | #define RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK 0xffff0000 | ||
| 9208 | #define RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT 0x10 | ||
| 9209 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff | ||
| 9210 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 | ||
| 9211 | #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 | ||
| 9212 | #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc | ||
| 9213 | #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff | ||
| 9214 | #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 | ||
| 9215 | #define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1 | ||
| 9216 | #define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0 | ||
| 9217 | #define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2 | ||
| 9218 | #define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1 | ||
| 9219 | #define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c | ||
| 9220 | #define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2 | ||
| 9221 | #define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80 | ||
| 9222 | #define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7 | ||
| 9223 | #define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000 | ||
| 9224 | #define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18 | ||
| 9225 | #define RLC_ROM_CNTL__USE_ROM_MASK 0x1 | ||
| 9226 | #define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0 | ||
| 9227 | #define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2 | ||
| 9228 | #define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1 | ||
| 9229 | #define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4 | ||
| 9230 | #define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2 | ||
| 9231 | #define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8 | ||
| 9232 | #define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3 | ||
| 9233 | #define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10 | ||
| 9234 | #define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4 | ||
| 9235 | #define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0 | ||
| 9236 | #define RLC_ROM_CNTL__RESERVED__SHIFT 0x5 | ||
| 9237 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff | ||
| 9238 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 | ||
| 9239 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff | ||
| 9240 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 | ||
| 9241 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 | ||
| 9242 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 | ||
| 9243 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe | ||
| 9244 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 | ||
| 9245 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff | ||
| 9246 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 | ||
| 9247 | #define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 | ||
| 9248 | #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 | ||
| 9249 | #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 | ||
| 9250 | #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 | ||
| 9251 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 | ||
| 9252 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 | ||
| 9253 | #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 | ||
| 9254 | #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 | ||
| 9255 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 | ||
| 9256 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 | ||
| 9257 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20 | ||
| 9258 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 | ||
| 9259 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40 | ||
| 9260 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 | ||
| 9261 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80 | ||
| 9262 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 | ||
| 9263 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100 | ||
| 9264 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 | ||
| 9265 | #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200 | ||
| 9266 | #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 | ||
| 9267 | #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400 | ||
| 9268 | #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa | ||
| 9269 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800 | ||
| 9270 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb | ||
| 9271 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000 | ||
| 9272 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc | ||
| 9273 | #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000 | ||
| 9274 | #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd | ||
| 9275 | #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000 | ||
| 9276 | #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe | ||
| 9277 | #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000 | ||
| 9278 | #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf | ||
| 9279 | #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000 | ||
| 9280 | #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 | ||
| 9281 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000 | ||
| 9282 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 | ||
| 9283 | #define RLC_GPM_STAT__RESERVED_MASK 0xfc0000 | ||
| 9284 | #define RLC_GPM_STAT__RESERVED__SHIFT 0x12 | ||
| 9285 | #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000 | ||
| 9286 | #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 | ||
| 9287 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f | ||
| 9288 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 | ||
| 9289 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 | ||
| 9290 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 | ||
| 9291 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff | ||
| 9292 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 | ||
| 9293 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 | ||
| 9294 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 | ||
| 9295 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 | ||
| 9296 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 | ||
| 9297 | #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 | ||
| 9298 | #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 | ||
| 9299 | #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 | ||
| 9300 | #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 | ||
| 9301 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10 | ||
| 9302 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 | ||
| 9303 | #define RLC_PG_CNTL__RESERVED_MASK 0x3fe0 | ||
| 9304 | #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 | ||
| 9305 | #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000 | ||
| 9306 | #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe | ||
| 9307 | #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000 | ||
| 9308 | #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf | ||
| 9309 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 | ||
| 9310 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 | ||
| 9311 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 | ||
| 9312 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 | ||
| 9313 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 | ||
| 9314 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 | ||
| 9315 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000 | ||
| 9316 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 | ||
| 9317 | #define RLC_PG_CNTL__RESERVED1_MASK 0xf00000 | ||
| 9318 | #define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 | ||
| 9319 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff | ||
| 9320 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 | ||
| 9321 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 | ||
| 9322 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 | ||
| 9323 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 | ||
| 9324 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 | ||
| 9325 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 | ||
| 9326 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 | ||
| 9327 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 | ||
| 9328 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 | ||
| 9329 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 | ||
| 9330 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 | ||
| 9331 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 | ||
| 9332 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 | ||
| 9333 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 | ||
| 9334 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 | ||
| 9335 | #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 | ||
| 9336 | #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 | ||
| 9337 | #define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf | ||
| 9338 | #define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 | ||
| 9339 | #define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0 | ||
| 9340 | #define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4 | ||
| 9341 | #define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700 | ||
| 9342 | #define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8 | ||
| 9343 | #define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800 | ||
| 9344 | #define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb | ||
| 9345 | #define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf | ||
| 9346 | #define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 | ||
| 9347 | #define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0 | ||
| 9348 | #define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4 | ||
| 9349 | #define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700 | ||
| 9350 | #define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8 | ||
| 9351 | #define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800 | ||
| 9352 | #define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb | ||
| 9353 | #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff | ||
| 9354 | #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 | ||
| 9355 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 | ||
| 9356 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 | ||
| 9357 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 | ||
| 9358 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 | ||
| 9359 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc | ||
| 9360 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 | ||
| 9361 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 | ||
| 9362 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 | ||
| 9363 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 | ||
| 9364 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b | ||
| 9365 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 | ||
| 9366 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c | ||
| 9367 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 | ||
| 9368 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d | ||
| 9369 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000 | ||
| 9370 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f | ||
| 9371 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf | ||
| 9372 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 | ||
| 9373 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 | ||
| 9374 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 | ||
| 9375 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 | ||
| 9376 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 | ||
| 9377 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 | ||
| 9378 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc | ||
| 9379 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 | ||
| 9380 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 | ||
| 9381 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 | ||
| 9382 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c | ||
| 9383 | #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff | ||
| 9384 | #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 | ||
| 9385 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff | ||
| 9386 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 | ||
| 9387 | #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff | ||
| 9388 | #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 | ||
| 9389 | #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 | ||
| 9390 | #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 | ||
| 9391 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 | ||
| 9392 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 | ||
| 9393 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 | ||
| 9394 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 | ||
| 9395 | #define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff | ||
| 9396 | #define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 | ||
| 9397 | #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff | ||
| 9398 | #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 | ||
| 9399 | #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff | ||
| 9400 | #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 | ||
| 9401 | #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 | ||
| 9402 | #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 | ||
| 9403 | #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe | ||
| 9404 | #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 | ||
| 9405 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 | ||
| 9406 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 | ||
| 9407 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 | ||
| 9408 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 | ||
| 9409 | #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff | ||
| 9410 | #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 | ||
| 9411 | #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 | ||
| 9412 | #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 | ||
| 9413 | #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 | ||
| 9414 | #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 | ||
| 9415 | #define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 | ||
| 9416 | #define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 | ||
| 9417 | #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff | ||
| 9418 | #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 | ||
| 9419 | #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff | ||
| 9420 | #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 | ||
| 9421 | #define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 | ||
| 9422 | #define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 | ||
| 9423 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 | ||
| 9424 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 | ||
| 9425 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 | ||
| 9426 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 | ||
| 9427 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 | ||
| 9428 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 | ||
| 9429 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 | ||
| 9430 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 | ||
| 9431 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 | ||
| 9432 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 | ||
| 9433 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 | ||
| 9434 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 | ||
| 9435 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe | ||
| 9436 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 | ||
| 9437 | #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf | ||
| 9438 | #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 | ||
| 9439 | #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 | ||
| 9440 | #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 | ||
| 9441 | #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 | ||
| 9442 | #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 | ||
| 9443 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 | ||
| 9444 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 | ||
| 9445 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 | ||
| 9446 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa | ||
| 9447 | #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800 | ||
| 9448 | #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb | ||
| 9449 | #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000 | ||
| 9450 | #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf | ||
| 9451 | #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000 | ||
| 9452 | #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11 | ||
| 9453 | #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff | ||
| 9454 | #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 | ||
| 9455 | #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff | ||
| 9456 | #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 | ||
| 9457 | #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff | ||
| 9458 | #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 | ||
| 9459 | #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff | ||
| 9460 | #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 | ||
| 9461 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff | ||
| 9462 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 | ||
| 9463 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 | ||
| 9464 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 | ||
| 9465 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000 | ||
| 9466 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 | ||
| 9467 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000 | ||
| 9468 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 | ||
| 9469 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000 | ||
| 9470 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 | ||
| 9471 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000 | ||
| 9472 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 | ||
| 9473 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000 | ||
| 9474 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 | ||
| 9475 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000 | ||
| 9476 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 | ||
| 9477 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000 | ||
| 9478 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 | ||
| 9479 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000 | ||
| 9480 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18 | ||
| 9481 | #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff | ||
| 9482 | #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 | ||
| 9483 | #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 | ||
| 9484 | #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 | ||
| 9485 | #define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 | ||
| 9486 | #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 | ||
| 9487 | #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 | ||
| 9488 | #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa | ||
| 9489 | #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 | ||
| 9490 | #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb | ||
| 9491 | #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 | ||
| 9492 | #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc | ||
| 9493 | #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 | ||
| 9494 | #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd | ||
| 9495 | #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000 | ||
| 9496 | #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe | ||
| 9497 | #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000 | ||
| 9498 | #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf | ||
| 9499 | #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000 | ||
| 9500 | #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 | ||
| 9501 | #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000 | ||
| 9502 | #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a | ||
| 9503 | #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000 | ||
| 9504 | #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b | ||
| 9505 | #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 | ||
| 9506 | #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c | ||
| 9507 | #define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff | ||
| 9508 | #define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 | ||
| 9509 | #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff | ||
| 9510 | #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 | ||
| 9511 | #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff | ||
| 9512 | #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 | ||
| 9513 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 | ||
| 9514 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 | ||
| 9515 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000 | ||
| 9516 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 | ||
| 9517 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000 | ||
| 9518 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 | ||
| 9519 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000 | ||
| 9520 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 | ||
| 9521 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000 | ||
| 9522 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 | ||
| 9523 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000 | ||
| 9524 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 | ||
| 9525 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000 | ||
| 9526 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 | ||
| 9527 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000 | ||
| 9528 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 | ||
| 9529 | #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000 | ||
| 9530 | #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18 | ||
| 9531 | #define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff | ||
| 9532 | #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 | ||
| 9533 | #define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff | ||
| 9534 | #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 | ||
| 9535 | #define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff | ||
| 9536 | #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 | ||
| 9537 | #define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff | ||
| 9538 | #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 | ||
| 9539 | #define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff | ||
| 9540 | #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 | ||
| 9541 | #define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff | ||
| 9542 | #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 | ||
| 9543 | #define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff | ||
| 9544 | #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 | ||
| 9545 | #define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff | ||
| 9546 | #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 | ||
| 9547 | #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff | ||
| 9548 | #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 | ||
| 9549 | #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 | ||
| 9550 | #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 | ||
| 9551 | #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff | ||
| 9552 | #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 | ||
| 9553 | #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff | ||
| 9554 | #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 | ||
| 9555 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf | ||
| 9556 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 | ||
| 9557 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 | ||
| 9558 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 | ||
| 9559 | #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 | ||
| 9560 | #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 | ||
| 9561 | #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 | ||
| 9562 | #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc | ||
| 9563 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 | ||
| 9564 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 | ||
| 9565 | #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 | ||
| 9566 | #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 | ||
| 9567 | #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 | ||
| 9568 | #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 | ||
| 9569 | #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 | ||
| 9570 | #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 | ||
| 9571 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf | ||
| 9572 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 | ||
| 9573 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 | ||
| 9574 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 | ||
| 9575 | #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 | ||
| 9576 | #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 | ||
| 9577 | #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 | ||
| 9578 | #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc | ||
| 9579 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 | ||
| 9580 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 | ||
| 9581 | #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 | ||
| 9582 | #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 | ||
| 9583 | #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 | ||
| 9584 | #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 | ||
| 9585 | #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 | ||
| 9586 | #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 | ||
| 9587 | #define RLC_GPR_REG1__DATA_MASK 0xffffffff | ||
| 9588 | #define RLC_GPR_REG1__DATA__SHIFT 0x0 | ||
| 9589 | #define RLC_GPR_REG2__DATA_MASK 0xffffffff | ||
| 9590 | #define RLC_GPR_REG2__DATA__SHIFT 0x0 | ||
| 9591 | #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1 | ||
| 9592 | #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 | ||
| 9593 | #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2 | ||
| 9594 | #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 | ||
| 9595 | #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4 | ||
| 9596 | #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 | ||
| 9597 | #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78 | ||
| 9598 | #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 | ||
| 9599 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80 | ||
| 9600 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 | ||
| 9601 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x8000 | ||
| 9602 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf | ||
| 9603 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x10000 | ||
| 9604 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 | ||
| 9605 | #define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000 | ||
| 9606 | #define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 | ||
| 9607 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1 | ||
| 9608 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 | ||
| 9609 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2 | ||
| 9610 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 | ||
| 9611 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4 | ||
| 9612 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 | ||
| 9613 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8 | ||
| 9614 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 | ||
| 9615 | #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0 | ||
| 9616 | #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 | ||
| 9617 | #define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf | ||
| 9618 | #define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 | ||
| 9619 | #define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 | ||
| 9620 | #define RLC_SPM_VMID__RESERVED__SHIFT 0x4 | ||
| 9621 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 | ||
| 9622 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 | ||
| 9623 | #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe | ||
| 9624 | #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 | ||
| 9625 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 | ||
| 9626 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 | ||
| 9627 | #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe | ||
| 9628 | #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 | ||
| 9629 | #define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff | ||
| 9630 | #define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 | ||
| 9631 | #define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 | ||
| 9632 | #define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 | ||
| 9633 | #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 | ||
| 9634 | #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf | ||
| 9635 | #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 | ||
| 9636 | #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 | ||
| 9637 | #define RLC_SPM_DEBUG__DATA_MASK 0xffffffff | ||
| 9638 | #define RLC_SPM_DEBUG__DATA__SHIFT 0x0 | ||
| 9639 | #define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff | ||
| 9640 | #define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 | ||
| 9641 | #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff | ||
| 9642 | #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 | ||
| 9643 | #define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff | ||
| 9644 | #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 | ||
| 9645 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff | ||
| 9646 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 | ||
| 9647 | #define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00 | ||
| 9648 | #define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 | ||
| 9649 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff | ||
| 9650 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 | ||
| 9651 | #define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff | ||
| 9652 | #define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 | ||
| 9653 | #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff | ||
| 9654 | #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 | ||
| 9655 | #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff | ||
| 9656 | #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 | ||
| 9657 | #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1 | ||
| 9658 | #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 | ||
| 9659 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2 | ||
| 9660 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 | ||
| 9661 | #define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc | ||
| 9662 | #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 | ||
| 9663 | #define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff | ||
| 9664 | #define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0 | ||
| 9665 | #define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 | ||
| 9666 | #define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8 | ||
| 9667 | #define RLC_SRM_DEBUG__DATA_MASK 0xffffffff | ||
| 9668 | #define RLC_SRM_DEBUG__DATA__SHIFT 0x0 | ||
| 9669 | #define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff | ||
| 9670 | #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 | ||
| 9671 | #define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00 | ||
| 9672 | #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa | ||
| 9673 | #define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff | ||
| 9674 | #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 | ||
| 9675 | #define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff | ||
| 9676 | #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 | ||
| 9677 | #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00 | ||
| 9678 | #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa | ||
| 9679 | #define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff | ||
| 9680 | #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 | ||
| 9681 | #define RLC_SRM_GPM_COMMAND__OP_MASK 0x1 | ||
| 9682 | #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 | ||
| 9683 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2 | ||
| 9684 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 | ||
| 9685 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c | ||
| 9686 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 | ||
| 9687 | #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0 | ||
| 9688 | #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 | ||
| 9689 | #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000 | ||
| 9690 | #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 | ||
| 9691 | #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000 | ||
| 9692 | #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d | ||
| 9693 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000 | ||
| 9694 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f | ||
| 9695 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 | ||
| 9696 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 | ||
| 9697 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2 | ||
| 9698 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 | ||
| 9699 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc | ||
| 9700 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 | ||
| 9701 | #define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1 | ||
| 9702 | #define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 | ||
| 9703 | #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe | ||
| 9704 | #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 | ||
| 9705 | #define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0 | ||
| 9706 | #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 | ||
| 9707 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000 | ||
| 9708 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 | ||
| 9709 | #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000 | ||
| 9710 | #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c | ||
| 9711 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000 | ||
| 9712 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f | ||
| 9713 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 | ||
| 9714 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 | ||
| 9715 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2 | ||
| 9716 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 | ||
| 9717 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc | ||
| 9718 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 | ||
| 9719 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff | ||
| 9720 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 | ||
| 9721 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000 | ||
| 9722 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 | ||
| 9723 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff | ||
| 9724 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 | ||
| 9725 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000 | ||
| 9726 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 | ||
| 9727 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff | ||
| 9728 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 | ||
| 9729 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000 | ||
| 9730 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 | ||
| 9731 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff | ||
| 9732 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 | ||
| 9733 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000 | ||
| 9734 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 | ||
| 9735 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff | ||
| 9736 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 | ||
| 9737 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000 | ||
| 9738 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 | ||
| 9739 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff | ||
| 9740 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 | ||
| 9741 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000 | ||
| 9742 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 | ||
| 9743 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff | ||
| 9744 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 | ||
| 9745 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000 | ||
| 9746 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 | ||
| 9747 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff | ||
| 9748 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 | ||
| 9749 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000 | ||
| 9750 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 | ||
| 9751 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff | ||
| 9752 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 | ||
| 9753 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff | ||
| 9754 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 | ||
| 9755 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff | ||
| 9756 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 | ||
| 9757 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff | ||
| 9758 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 | ||
| 9759 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff | ||
| 9760 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 | ||
| 9761 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff | ||
| 9762 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 | ||
| 9763 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff | ||
| 9764 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 | ||
| 9765 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff | ||
| 9766 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 | ||
| 9767 | #define RLC_SRM_STAT__SRM_STATUS_MASK 0x1 | ||
| 9768 | #define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0 | ||
| 9769 | #define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe | ||
| 9770 | #define RLC_SRM_STAT__RESERVED__SHIFT 0x1 | ||
| 9771 | #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1 | ||
| 9772 | #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 | ||
| 9773 | #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe | ||
| 9774 | #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 | ||
| 9775 | #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff | ||
| 9776 | #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 | ||
| 9777 | #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff | ||
| 9778 | #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 | ||
| 9779 | #define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff | ||
| 9780 | #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 | ||
| 9781 | #define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff | ||
| 9782 | #define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0 | ||
| 9783 | #define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff | ||
| 9784 | #define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0 | ||
| 9785 | #define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff | ||
| 9786 | #define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0 | ||
| 9787 | #define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff | ||
| 9788 | #define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0 | ||
| 9789 | #define RLC_SMU_COMMAND__CMD_MASK 0xffffffff | ||
| 9790 | #define RLC_SMU_COMMAND__CMD__SHIFT 0x0 | ||
| 9791 | #define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff | ||
| 9792 | #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 | ||
| 9793 | #define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00 | ||
| 9794 | #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 | ||
| 9795 | #define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000 | ||
| 9796 | #define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 | ||
| 9797 | #define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000 | ||
| 9798 | #define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 | ||
| 9799 | #define RLC_SMU_ARGUMENT_1__ARG_MASK 0xffffffff | ||
| 9800 | #define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 | ||
| 9801 | #define RLC_SMU_ARGUMENT_2__ARG_MASK 0xffffffff | ||
| 9802 | #define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 | ||
| 9803 | #define RLC_GPM_GENERAL_8__DATA_MASK 0xffffffff | ||
| 9804 | #define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 | ||
| 9805 | #define RLC_GPM_GENERAL_9__DATA_MASK 0xffffffff | ||
| 9806 | #define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 | ||
| 9807 | #define RLC_GPM_GENERAL_10__DATA_MASK 0xffffffff | ||
| 9808 | #define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 | ||
| 9809 | #define RLC_GPM_GENERAL_11__DATA_MASK 0xffffffff | ||
| 9810 | #define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 | ||
| 9811 | #define RLC_GPM_GENERAL_12__DATA_MASK 0xffffffff | ||
| 9812 | #define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 | ||
| 9813 | #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff | ||
| 9814 | #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 | ||
| 9815 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 | ||
| 9816 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc | ||
| 9817 | #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 | ||
| 9818 | #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe | ||
| 9819 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 | ||
| 9820 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 | ||
| 9821 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff | ||
| 9822 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 | ||
| 9823 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff | ||
| 9824 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 | ||
| 9825 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 | ||
| 9826 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 | ||
| 9827 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff | ||
| 9828 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 | ||
| 9829 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff | ||
| 9830 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 | ||
| 9831 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 | ||
| 9832 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 | ||
| 9833 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 | ||
| 9834 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb | ||
| 9835 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 | ||
| 9836 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 | ||
| 9837 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 | ||
| 9838 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 | ||
| 9839 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 | ||
| 9840 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a | ||
| 9841 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 | ||
| 9842 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f | ||
| 9843 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff | ||
| 9844 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 | ||
| 9845 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff | ||
| 9846 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 | ||
| 9847 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9848 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9849 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9850 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9851 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9852 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9853 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9854 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9855 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9856 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9857 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9858 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9859 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9860 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9861 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9862 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9863 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9864 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9865 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9866 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9867 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9868 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9869 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9870 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9871 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9872 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9873 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9874 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9875 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9876 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9877 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9878 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9879 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9880 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9881 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9882 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9883 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9884 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9885 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9886 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9887 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9888 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9889 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9890 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9891 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9892 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9893 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9894 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9895 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9896 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9897 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9898 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9899 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9900 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9901 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9902 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9903 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9904 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9905 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9906 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9907 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9908 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9909 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9910 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9911 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9912 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9913 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9914 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9915 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff | ||
| 9916 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 | ||
| 9917 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 | ||
| 9918 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 | ||
| 9919 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff | ||
| 9920 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 | ||
| 9921 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff | ||
| 9922 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 | ||
| 9923 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff | ||
| 9924 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 | ||
| 9925 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff | ||
| 9926 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 | ||
| 9927 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1 | ||
| 9928 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 | ||
| 9929 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe | ||
| 9930 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 | ||
| 9931 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000 | ||
| 9932 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 | ||
| 9933 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff | ||
| 9934 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 | ||
| 9935 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf | ||
| 9936 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 | ||
| 9937 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 | ||
| 9938 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 | ||
| 9939 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 | ||
| 9940 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f | ||
| 9941 | #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f | ||
| 9942 | #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 | ||
| 9943 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 | ||
| 9944 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 | ||
| 9945 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 | ||
| 9946 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa | ||
| 9947 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 | ||
| 9948 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd | ||
| 9949 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 | ||
| 9950 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 9951 | #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 | ||
| 9952 | #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 | ||
| 9953 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000 | ||
| 9954 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 9955 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 9956 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 9957 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 9958 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 9959 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 9960 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 9961 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000 | ||
| 9962 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 | ||
| 9963 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000 | ||
| 9964 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 | ||
| 9965 | #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f | ||
| 9966 | #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 | ||
| 9967 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 | ||
| 9968 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 | ||
| 9969 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 | ||
| 9970 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa | ||
| 9971 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 | ||
| 9972 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd | ||
| 9973 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 | ||
| 9974 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 9975 | #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 | ||
| 9976 | #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 | ||
| 9977 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000 | ||
| 9978 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 9979 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 9980 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 9981 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 9982 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 9983 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 9984 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 9985 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000 | ||
| 9986 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 | ||
| 9987 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000 | ||
| 9988 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 | ||
| 9989 | #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f | ||
| 9990 | #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 | ||
| 9991 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 | ||
| 9992 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 | ||
| 9993 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 | ||
| 9994 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa | ||
| 9995 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 | ||
| 9996 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd | ||
| 9997 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 | ||
| 9998 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 9999 | #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 | ||
| 10000 | #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 | ||
| 10001 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10002 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10003 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10004 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10005 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10006 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10007 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10008 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10009 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000 | ||
| 10010 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 | ||
| 10011 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000 | ||
| 10012 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 | ||
| 10013 | #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f | ||
| 10014 | #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 | ||
| 10015 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 | ||
| 10016 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 | ||
| 10017 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 | ||
| 10018 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa | ||
| 10019 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 | ||
| 10020 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd | ||
| 10021 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10022 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10023 | #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 | ||
| 10024 | #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 | ||
| 10025 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10026 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10027 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10028 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10029 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10030 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10031 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10032 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10033 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000 | ||
| 10034 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 | ||
| 10035 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000 | ||
| 10036 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 | ||
| 10037 | #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f | ||
| 10038 | #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 | ||
| 10039 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 | ||
| 10040 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 | ||
| 10041 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 | ||
| 10042 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa | ||
| 10043 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 | ||
| 10044 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd | ||
| 10045 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10046 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10047 | #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 | ||
| 10048 | #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 | ||
| 10049 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10050 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10051 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10052 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10053 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10054 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10055 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10056 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10057 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000 | ||
| 10058 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 | ||
| 10059 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000 | ||
| 10060 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 | ||
| 10061 | #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f | ||
| 10062 | #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 | ||
| 10063 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 | ||
| 10064 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 | ||
| 10065 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 | ||
| 10066 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa | ||
| 10067 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 | ||
| 10068 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd | ||
| 10069 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10070 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10071 | #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 | ||
| 10072 | #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 | ||
| 10073 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10074 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10075 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10076 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10077 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10078 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10079 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10080 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10081 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000 | ||
| 10082 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 | ||
| 10083 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000 | ||
| 10084 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 | ||
| 10085 | #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f | ||
| 10086 | #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 | ||
| 10087 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 | ||
| 10088 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 | ||
| 10089 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 | ||
| 10090 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa | ||
| 10091 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 | ||
| 10092 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd | ||
| 10093 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10094 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10095 | #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 | ||
| 10096 | #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 | ||
| 10097 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10098 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10099 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10100 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10101 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10102 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10103 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10104 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10105 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000 | ||
| 10106 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 | ||
| 10107 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000 | ||
| 10108 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 | ||
| 10109 | #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f | ||
| 10110 | #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 | ||
| 10111 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 | ||
| 10112 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 | ||
| 10113 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 | ||
| 10114 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa | ||
| 10115 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 | ||
| 10116 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd | ||
| 10117 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10118 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10119 | #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 | ||
| 10120 | #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 | ||
| 10121 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10122 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10123 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10124 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10125 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10126 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10127 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10128 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10129 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000 | ||
| 10130 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 | ||
| 10131 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000 | ||
| 10132 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 | ||
| 10133 | #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f | ||
| 10134 | #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 | ||
| 10135 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 | ||
| 10136 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 | ||
| 10137 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 | ||
| 10138 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa | ||
| 10139 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 | ||
| 10140 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd | ||
| 10141 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10142 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10143 | #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 | ||
| 10144 | #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 | ||
| 10145 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10146 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10147 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10148 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10149 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10150 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10151 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10152 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10153 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000 | ||
| 10154 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 | ||
| 10155 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000 | ||
| 10156 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 | ||
| 10157 | #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f | ||
| 10158 | #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 | ||
| 10159 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 | ||
| 10160 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 | ||
| 10161 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 | ||
| 10162 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa | ||
| 10163 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 | ||
| 10164 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd | ||
| 10165 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10166 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10167 | #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 | ||
| 10168 | #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 | ||
| 10169 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10170 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10171 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10172 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10173 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10174 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10175 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10176 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10177 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000 | ||
| 10178 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 | ||
| 10179 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000 | ||
| 10180 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 | ||
| 10181 | #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f | ||
| 10182 | #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 | ||
| 10183 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 | ||
| 10184 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 | ||
| 10185 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 | ||
| 10186 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa | ||
| 10187 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 | ||
| 10188 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd | ||
| 10189 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10190 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10191 | #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 | ||
| 10192 | #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 | ||
| 10193 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10194 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10195 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10196 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10197 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10198 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10199 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10200 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10201 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000 | ||
| 10202 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 | ||
| 10203 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000 | ||
| 10204 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 | ||
| 10205 | #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f | ||
| 10206 | #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 | ||
| 10207 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 | ||
| 10208 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 | ||
| 10209 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 | ||
| 10210 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa | ||
| 10211 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 | ||
| 10212 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd | ||
| 10213 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10214 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10215 | #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 | ||
| 10216 | #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 | ||
| 10217 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10218 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10219 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10220 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10221 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10222 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10223 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10224 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10225 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000 | ||
| 10226 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 | ||
| 10227 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000 | ||
| 10228 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 | ||
| 10229 | #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f | ||
| 10230 | #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 | ||
| 10231 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 | ||
| 10232 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 | ||
| 10233 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 | ||
| 10234 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa | ||
| 10235 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 | ||
| 10236 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd | ||
| 10237 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10238 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10239 | #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 | ||
| 10240 | #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 | ||
| 10241 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10242 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10243 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10244 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10245 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10246 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10247 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10248 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10249 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000 | ||
| 10250 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 | ||
| 10251 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000 | ||
| 10252 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 | ||
| 10253 | #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f | ||
| 10254 | #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 | ||
| 10255 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 | ||
| 10256 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 | ||
| 10257 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 | ||
| 10258 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa | ||
| 10259 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 | ||
| 10260 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd | ||
| 10261 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10262 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10263 | #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 | ||
| 10264 | #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 | ||
| 10265 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10266 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10267 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10268 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10269 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10270 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10271 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10272 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10273 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000 | ||
| 10274 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 | ||
| 10275 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000 | ||
| 10276 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 | ||
| 10277 | #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f | ||
| 10278 | #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 | ||
| 10279 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 | ||
| 10280 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 | ||
| 10281 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 | ||
| 10282 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa | ||
| 10283 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 | ||
| 10284 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd | ||
| 10285 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10286 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10287 | #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 | ||
| 10288 | #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 | ||
| 10289 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10290 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10291 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10292 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10293 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10294 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10295 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10296 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10297 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000 | ||
| 10298 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 | ||
| 10299 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000 | ||
| 10300 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 | ||
| 10301 | #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f | ||
| 10302 | #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 | ||
| 10303 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 | ||
| 10304 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 | ||
| 10305 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 | ||
| 10306 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa | ||
| 10307 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 | ||
| 10308 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd | ||
| 10309 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10310 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10311 | #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 | ||
| 10312 | #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 | ||
| 10313 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10314 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10315 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10316 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10317 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10318 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10319 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10320 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10321 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000 | ||
| 10322 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 | ||
| 10323 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000 | ||
| 10324 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 | ||
| 10325 | #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f | ||
| 10326 | #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 | ||
| 10327 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 | ||
| 10328 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 | ||
| 10329 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 | ||
| 10330 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa | ||
| 10331 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 | ||
| 10332 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd | ||
| 10333 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10334 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10335 | #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 | ||
| 10336 | #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 | ||
| 10337 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10338 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10339 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10340 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10341 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10342 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10343 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10344 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10345 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000 | ||
| 10346 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 | ||
| 10347 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000 | ||
| 10348 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 | ||
| 10349 | #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f | ||
| 10350 | #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 | ||
| 10351 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 | ||
| 10352 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 | ||
| 10353 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 | ||
| 10354 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa | ||
| 10355 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 | ||
| 10356 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd | ||
| 10357 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10358 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10359 | #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 | ||
| 10360 | #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 | ||
| 10361 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10362 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10363 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10364 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10365 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10366 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10367 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10368 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10369 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000 | ||
| 10370 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 | ||
| 10371 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000 | ||
| 10372 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 | ||
| 10373 | #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f | ||
| 10374 | #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 | ||
| 10375 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 | ||
| 10376 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 | ||
| 10377 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 | ||
| 10378 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa | ||
| 10379 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 | ||
| 10380 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd | ||
| 10381 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10382 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10383 | #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 | ||
| 10384 | #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 | ||
| 10385 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10386 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10387 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10388 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10389 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10390 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10391 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10392 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10393 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000 | ||
| 10394 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 | ||
| 10395 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000 | ||
| 10396 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 | ||
| 10397 | #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f | ||
| 10398 | #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 | ||
| 10399 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 | ||
| 10400 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 | ||
| 10401 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 | ||
| 10402 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa | ||
| 10403 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 | ||
| 10404 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd | ||
| 10405 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 | ||
| 10406 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 | ||
| 10407 | #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 | ||
| 10408 | #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 | ||
| 10409 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10410 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10411 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10412 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10413 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10414 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10415 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000 | ||
| 10416 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 | ||
| 10417 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000 | ||
| 10418 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 | ||
| 10419 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000 | ||
| 10420 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 | ||
| 10421 | #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f | ||
| 10422 | #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 | ||
| 10423 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 | ||
| 10424 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 | ||
| 10425 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 | ||
| 10426 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa | ||
| 10427 | #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 | ||
| 10428 | #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 | ||
| 10429 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10430 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10431 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10432 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10433 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10434 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10435 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000 | ||
| 10436 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 | ||
| 10437 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000 | ||
| 10438 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 | ||
| 10439 | #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f | ||
| 10440 | #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 | ||
| 10441 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 | ||
| 10442 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 | ||
| 10443 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 | ||
| 10444 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa | ||
| 10445 | #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 | ||
| 10446 | #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 | ||
| 10447 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10448 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10449 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10450 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10451 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10452 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10453 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000 | ||
| 10454 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 | ||
| 10455 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000 | ||
| 10456 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 | ||
| 10457 | #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f | ||
| 10458 | #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 | ||
| 10459 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 | ||
| 10460 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 | ||
| 10461 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 | ||
| 10462 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa | ||
| 10463 | #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 | ||
| 10464 | #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 | ||
| 10465 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10466 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10467 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10468 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10469 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10470 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10471 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000 | ||
| 10472 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 | ||
| 10473 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000 | ||
| 10474 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 | ||
| 10475 | #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f | ||
| 10476 | #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 | ||
| 10477 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 | ||
| 10478 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 | ||
| 10479 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 | ||
| 10480 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa | ||
| 10481 | #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 | ||
| 10482 | #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 | ||
| 10483 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10484 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10485 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10486 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10487 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10488 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10489 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000 | ||
| 10490 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 | ||
| 10491 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000 | ||
| 10492 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 | ||
| 10493 | #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f | ||
| 10494 | #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 | ||
| 10495 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 | ||
| 10496 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 | ||
| 10497 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 | ||
| 10498 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa | ||
| 10499 | #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 | ||
| 10500 | #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 | ||
| 10501 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10502 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10503 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10504 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10505 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10506 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10507 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000 | ||
| 10508 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 | ||
| 10509 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000 | ||
| 10510 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 | ||
| 10511 | #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f | ||
| 10512 | #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 | ||
| 10513 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 | ||
| 10514 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 | ||
| 10515 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 | ||
| 10516 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa | ||
| 10517 | #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 | ||
| 10518 | #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 | ||
| 10519 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10520 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10521 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10522 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10523 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10524 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10525 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000 | ||
| 10526 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 | ||
| 10527 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000 | ||
| 10528 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 | ||
| 10529 | #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f | ||
| 10530 | #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 | ||
| 10531 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 | ||
| 10532 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 | ||
| 10533 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 | ||
| 10534 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa | ||
| 10535 | #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 | ||
| 10536 | #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 | ||
| 10537 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10538 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10539 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10540 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10541 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10542 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10543 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000 | ||
| 10544 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 | ||
| 10545 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000 | ||
| 10546 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 | ||
| 10547 | #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f | ||
| 10548 | #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 | ||
| 10549 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 | ||
| 10550 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 | ||
| 10551 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 | ||
| 10552 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa | ||
| 10553 | #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 | ||
| 10554 | #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 | ||
| 10555 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10556 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10557 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10558 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10559 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10560 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10561 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000 | ||
| 10562 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 | ||
| 10563 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000 | ||
| 10564 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 | ||
| 10565 | #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f | ||
| 10566 | #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 | ||
| 10567 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 | ||
| 10568 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 | ||
| 10569 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 | ||
| 10570 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa | ||
| 10571 | #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 | ||
| 10572 | #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 | ||
| 10573 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10574 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10575 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10576 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10577 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10578 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10579 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000 | ||
| 10580 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 | ||
| 10581 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000 | ||
| 10582 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 | ||
| 10583 | #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f | ||
| 10584 | #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 | ||
| 10585 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 | ||
| 10586 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 | ||
| 10587 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 | ||
| 10588 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa | ||
| 10589 | #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 | ||
| 10590 | #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 | ||
| 10591 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10592 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10593 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10594 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10595 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10596 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10597 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000 | ||
| 10598 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 | ||
| 10599 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000 | ||
| 10600 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 | ||
| 10601 | #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f | ||
| 10602 | #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 | ||
| 10603 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 | ||
| 10604 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 | ||
| 10605 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 | ||
| 10606 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa | ||
| 10607 | #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 | ||
| 10608 | #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 | ||
| 10609 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10610 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10611 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10612 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10613 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10614 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10615 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000 | ||
| 10616 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 | ||
| 10617 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000 | ||
| 10618 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 | ||
| 10619 | #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f | ||
| 10620 | #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 | ||
| 10621 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 | ||
| 10622 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 | ||
| 10623 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 | ||
| 10624 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa | ||
| 10625 | #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 | ||
| 10626 | #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 | ||
| 10627 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000 | ||
| 10628 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 | ||
| 10629 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000 | ||
| 10630 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 | ||
| 10631 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000 | ||
| 10632 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 | ||
| 10633 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000 | ||
| 10634 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 | ||
| 10635 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000 | ||
| 10636 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 | ||
| 10637 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e | ||
| 10638 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 | ||
| 10639 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 | ||
| 10640 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 | ||
| 10641 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 | ||
| 10642 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 | ||
| 10643 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 | ||
| 10644 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 | ||
| 10645 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 | ||
| 10646 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 | ||
| 10647 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 | ||
| 10648 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 | ||
| 10649 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 | ||
| 10650 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 | ||
| 10651 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 | ||
| 10652 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 | ||
| 10653 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 | ||
| 10654 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 | ||
| 10655 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 | ||
| 10656 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 | ||
| 10657 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 | ||
| 10658 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 | ||
| 10659 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 | ||
| 10660 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 | ||
| 10661 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 | ||
| 10662 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa | ||
| 10663 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 | ||
| 10664 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb | ||
| 10665 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 | ||
| 10666 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc | ||
| 10667 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 | ||
| 10668 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd | ||
| 10669 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 | ||
| 10670 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe | ||
| 10671 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 | ||
| 10672 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf | ||
| 10673 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 | ||
| 10674 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 | ||
| 10675 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 | ||
| 10676 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 | ||
| 10677 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 | ||
| 10678 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 | ||
| 10679 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 | ||
| 10680 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 | ||
| 10681 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 | ||
| 10682 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 | ||
| 10683 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 | ||
| 10684 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 | ||
| 10685 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 | ||
| 10686 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 | ||
| 10687 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 | ||
| 10688 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 | ||
| 10689 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 | ||
| 10690 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 | ||
| 10691 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 | ||
| 10692 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 | ||
| 10693 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 | ||
| 10694 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa | ||
| 10695 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 | ||
| 10696 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb | ||
| 10697 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 | ||
| 10698 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc | ||
| 10699 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 | ||
| 10700 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd | ||
| 10701 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 | ||
| 10702 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe | ||
| 10703 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 | ||
| 10704 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf | ||
| 10705 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 | ||
| 10706 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 | ||
| 10707 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 | ||
| 10708 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 | ||
| 10709 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c | ||
| 10710 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 | ||
| 10711 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 | ||
| 10712 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 | ||
| 10713 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 | ||
| 10714 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 | ||
| 10715 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 | ||
| 10716 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb | ||
| 10717 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 | ||
| 10718 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe | ||
| 10719 | #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f | ||
| 10720 | #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 | ||
| 10721 | #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 | ||
| 10722 | #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 | ||
| 10723 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 | ||
| 10724 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe | ||
| 10725 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 | ||
| 10726 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 | ||
| 10727 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 | ||
| 10728 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 | ||
| 10729 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 | ||
| 10730 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 | ||
| 10731 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 | ||
| 10732 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc | ||
| 10733 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 | ||
| 10734 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 | ||
| 10735 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 | ||
| 10736 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 | ||
| 10737 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 | ||
| 10738 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 | ||
| 10739 | #define SPI_TMPRING_SIZE__WAVES_MASK 0xfff | ||
| 10740 | #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 | ||
| 10741 | #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 | ||
| 10742 | #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc | ||
| 10743 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf | ||
| 10744 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 | ||
| 10745 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 | ||
| 10746 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 | ||
| 10747 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 | ||
| 10748 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 | ||
| 10749 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 | ||
| 10750 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc | ||
| 10751 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf | ||
| 10752 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 | ||
| 10753 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf | ||
| 10754 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 | ||
| 10755 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 | ||
| 10756 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 | ||
| 10757 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 | ||
| 10758 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 | ||
| 10759 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 | ||
| 10760 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc | ||
| 10761 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 | ||
| 10762 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 | ||
| 10763 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 | ||
| 10764 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 | ||
| 10765 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 | ||
| 10766 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 | ||
| 10767 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 | ||
| 10768 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c | ||
| 10769 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 | ||
| 10770 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 | ||
| 10771 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 | ||
| 10772 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 | ||
| 10773 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 | ||
| 10774 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 | ||
| 10775 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 | ||
| 10776 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 | ||
| 10777 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 | ||
| 10778 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc | ||
| 10779 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 | ||
| 10780 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe | ||
| 10781 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 | ||
| 10782 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 | ||
| 10783 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 | ||
| 10784 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 | ||
| 10785 | #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff | ||
| 10786 | #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 | ||
| 10787 | #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 | ||
| 10788 | #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 | ||
| 10789 | #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff | ||
| 10790 | #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 | ||
| 10791 | #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 | ||
| 10792 | #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 | ||
| 10793 | #define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 | ||
| 10794 | #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 | ||
| 10795 | #define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 | ||
| 10796 | #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 | ||
| 10797 | #define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 | ||
| 10798 | #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 | ||
| 10799 | #define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 | ||
| 10800 | #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 | ||
| 10801 | #define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 | ||
| 10802 | #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 | ||
| 10803 | #define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 | ||
| 10804 | #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 | ||
| 10805 | #define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 | ||
| 10806 | #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 | ||
| 10807 | #define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 | ||
| 10808 | #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 | ||
| 10809 | #define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 | ||
| 10810 | #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 | ||
| 10811 | #define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 | ||
| 10812 | #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 | ||
| 10813 | #define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 | ||
| 10814 | #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 | ||
| 10815 | #define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 | ||
| 10816 | #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 | ||
| 10817 | #define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 | ||
| 10818 | #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 | ||
| 10819 | #define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff | ||
| 10820 | #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 | ||
| 10821 | #define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 | ||
| 10822 | #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 | ||
| 10823 | #define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 | ||
| 10824 | #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 | ||
| 10825 | #define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 | ||
| 10826 | #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 | ||
| 10827 | #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff | ||
| 10828 | #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 | ||
| 10829 | #define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 | ||
| 10830 | #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 | ||
| 10831 | #define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 | ||
| 10832 | #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 | ||
| 10833 | #define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 | ||
| 10834 | #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 | ||
| 10835 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f | ||
| 10836 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 | ||
| 10837 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80 | ||
| 10838 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 | ||
| 10839 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000 | ||
| 10840 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc | ||
| 10841 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000 | ||
| 10842 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 | ||
| 10843 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000 | ||
| 10844 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 | ||
| 10845 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f | ||
| 10846 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 | ||
| 10847 | #define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80 | ||
| 10848 | #define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7 | ||
| 10849 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000 | ||
| 10850 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc | ||
| 10851 | #define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000 | ||
| 10852 | #define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11 | ||
| 10853 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000 | ||
| 10854 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 | ||
| 10855 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f | ||
| 10856 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 | ||
| 10857 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f | ||
| 10858 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 | ||
| 10859 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f | ||
| 10860 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 | ||
| 10861 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f | ||
| 10862 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 | ||
| 10863 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f | ||
| 10864 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 | ||
| 10865 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f | ||
| 10866 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 | ||
| 10867 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f | ||
| 10868 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 | ||
| 10869 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f | ||
| 10870 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 | ||
| 10871 | #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 | ||
| 10872 | #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 | ||
| 10873 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe | ||
| 10874 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 | ||
| 10875 | #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 | ||
| 10876 | #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 | ||
| 10877 | #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc | ||
| 10878 | #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 | ||
| 10879 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 | ||
| 10880 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 | ||
| 10881 | #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 | ||
| 10882 | #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 | ||
| 10883 | #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 | ||
| 10884 | #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 | ||
| 10885 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 | ||
| 10886 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 | ||
| 10887 | #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 | ||
| 10888 | #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf | ||
| 10889 | #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 | ||
| 10890 | #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 | ||
| 10891 | #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff | ||
| 10892 | #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 | ||
| 10893 | #define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 | ||
| 10894 | #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 | ||
| 10895 | #define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff | ||
| 10896 | #define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 | ||
| 10897 | #define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff | ||
| 10898 | #define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 | ||
| 10899 | #define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff | ||
| 10900 | #define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 | ||
| 10901 | #define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff | ||
| 10902 | #define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 | ||
| 10903 | #define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff | ||
| 10904 | #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 | ||
| 10905 | #define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff | ||
| 10906 | #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 | ||
| 10907 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 | ||
| 10908 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 | ||
| 10909 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 | ||
| 10910 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 | ||
| 10911 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 | ||
| 10912 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 | ||
| 10913 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 | ||
| 10914 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 | ||
| 10915 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 | ||
| 10916 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 | ||
| 10917 | #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 | ||
| 10918 | #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 | ||
| 10919 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf | ||
| 10920 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 | ||
| 10921 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 | ||
| 10922 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 | ||
| 10923 | #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 | ||
| 10924 | #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 | ||
| 10925 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 | ||
| 10926 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc | ||
| 10927 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 | ||
| 10928 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf | ||
| 10929 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf | ||
| 10930 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 | ||
| 10931 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 | ||
| 10932 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 | ||
| 10933 | #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 | ||
| 10934 | #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 | ||
| 10935 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 | ||
| 10936 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc | ||
| 10937 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 | ||
| 10938 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf | ||
| 10939 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf | ||
| 10940 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 | ||
| 10941 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 | ||
| 10942 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 | ||
| 10943 | #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 | ||
| 10944 | #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 | ||
| 10945 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 | ||
| 10946 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc | ||
| 10947 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 | ||
| 10948 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf | ||
| 10949 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf | ||
| 10950 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 | ||
| 10951 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 | ||
| 10952 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 | ||
| 10953 | #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 | ||
| 10954 | #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 | ||
| 10955 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 | ||
| 10956 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc | ||
| 10957 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 | ||
| 10958 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf | ||
| 10959 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf | ||
| 10960 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 | ||
| 10961 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 | ||
| 10962 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 | ||
| 10963 | #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 | ||
| 10964 | #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 | ||
| 10965 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 | ||
| 10966 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc | ||
| 10967 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 | ||
| 10968 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf | ||
| 10969 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf | ||
| 10970 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 | ||
| 10971 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 | ||
| 10972 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 | ||
| 10973 | #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 | ||
| 10974 | #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 | ||
| 10975 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 | ||
| 10976 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc | ||
| 10977 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 | ||
| 10978 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf | ||
| 10979 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf | ||
| 10980 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 | ||
| 10981 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 | ||
| 10982 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 | ||
| 10983 | #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 | ||
| 10984 | #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 | ||
| 10985 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 | ||
| 10986 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc | ||
| 10987 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 | ||
| 10988 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf | ||
| 10989 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf | ||
| 10990 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 | ||
| 10991 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 | ||
| 10992 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 | ||
| 10993 | #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 | ||
| 10994 | #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 | ||
| 10995 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 | ||
| 10996 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc | ||
| 10997 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 | ||
| 10998 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf | ||
| 10999 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf | ||
| 11000 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 | ||
| 11001 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 | ||
| 11002 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 | ||
| 11003 | #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 | ||
| 11004 | #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 | ||
| 11005 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 | ||
| 11006 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc | ||
| 11007 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 | ||
| 11008 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf | ||
| 11009 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf | ||
| 11010 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 | ||
| 11011 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 | ||
| 11012 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 | ||
| 11013 | #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 | ||
| 11014 | #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 | ||
| 11015 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 | ||
| 11016 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc | ||
| 11017 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 | ||
| 11018 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf | ||
| 11019 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf | ||
| 11020 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 | ||
| 11021 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 | ||
| 11022 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 | ||
| 11023 | #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 | ||
| 11024 | #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 | ||
| 11025 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 | ||
| 11026 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc | ||
| 11027 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 | ||
| 11028 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf | ||
| 11029 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf | ||
| 11030 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 | ||
| 11031 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 | ||
| 11032 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 | ||
| 11033 | #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 | ||
| 11034 | #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 | ||
| 11035 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 | ||
| 11036 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc | ||
| 11037 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 | ||
| 11038 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf | ||
| 11039 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf | ||
| 11040 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 | ||
| 11041 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0 | ||
| 11042 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 | ||
| 11043 | #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00 | ||
| 11044 | #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 | ||
| 11045 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000 | ||
| 11046 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc | ||
| 11047 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000 | ||
| 11048 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf | ||
| 11049 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf | ||
| 11050 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 | ||
| 11051 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0 | ||
| 11052 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 | ||
| 11053 | #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00 | ||
| 11054 | #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 | ||
| 11055 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000 | ||
| 11056 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc | ||
| 11057 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000 | ||
| 11058 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf | ||
| 11059 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf | ||
| 11060 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 | ||
| 11061 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0 | ||
| 11062 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 | ||
| 11063 | #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00 | ||
| 11064 | #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 | ||
| 11065 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000 | ||
| 11066 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc | ||
| 11067 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000 | ||
| 11068 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf | ||
| 11069 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf | ||
| 11070 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 | ||
| 11071 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0 | ||
| 11072 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 | ||
| 11073 | #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00 | ||
| 11074 | #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 | ||
| 11075 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000 | ||
| 11076 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc | ||
| 11077 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000 | ||
| 11078 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf | ||
| 11079 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 | ||
| 11080 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 | ||
| 11081 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe | ||
| 11082 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 | ||
| 11083 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 | ||
| 11084 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 | ||
| 11085 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11086 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11087 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 | ||
| 11088 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 | ||
| 11089 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe | ||
| 11090 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 | ||
| 11091 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 | ||
| 11092 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 | ||
| 11093 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11094 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11095 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 | ||
| 11096 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 | ||
| 11097 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe | ||
| 11098 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 | ||
| 11099 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 | ||
| 11100 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 | ||
| 11101 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11102 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11103 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 | ||
| 11104 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 | ||
| 11105 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe | ||
| 11106 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 | ||
| 11107 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 | ||
| 11108 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 | ||
| 11109 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11110 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11111 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 | ||
| 11112 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 | ||
| 11113 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe | ||
| 11114 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 | ||
| 11115 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 | ||
| 11116 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 | ||
| 11117 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11118 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11119 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 | ||
| 11120 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 | ||
| 11121 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe | ||
| 11122 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 | ||
| 11123 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 | ||
| 11124 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 | ||
| 11125 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11126 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11127 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 | ||
| 11128 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 | ||
| 11129 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe | ||
| 11130 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 | ||
| 11131 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 | ||
| 11132 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 | ||
| 11133 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11134 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11135 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 | ||
| 11136 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 | ||
| 11137 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe | ||
| 11138 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 | ||
| 11139 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 | ||
| 11140 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 | ||
| 11141 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11142 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11143 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 | ||
| 11144 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 | ||
| 11145 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe | ||
| 11146 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 | ||
| 11147 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 | ||
| 11148 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 | ||
| 11149 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11150 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11151 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 | ||
| 11152 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 | ||
| 11153 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe | ||
| 11154 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 | ||
| 11155 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 | ||
| 11156 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 | ||
| 11157 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11158 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11159 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 | ||
| 11160 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 | ||
| 11161 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe | ||
| 11162 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 | ||
| 11163 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 | ||
| 11164 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 | ||
| 11165 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11166 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11167 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 | ||
| 11168 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 | ||
| 11169 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe | ||
| 11170 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 | ||
| 11171 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 | ||
| 11172 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 | ||
| 11173 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11174 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11175 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1 | ||
| 11176 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 | ||
| 11177 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe | ||
| 11178 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 | ||
| 11179 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000 | ||
| 11180 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 | ||
| 11181 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11182 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11183 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1 | ||
| 11184 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 | ||
| 11185 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe | ||
| 11186 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 | ||
| 11187 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000 | ||
| 11188 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 | ||
| 11189 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11190 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11191 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1 | ||
| 11192 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 | ||
| 11193 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe | ||
| 11194 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 | ||
| 11195 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000 | ||
| 11196 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 | ||
| 11197 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11198 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11199 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1 | ||
| 11200 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 | ||
| 11201 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe | ||
| 11202 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 | ||
| 11203 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000 | ||
| 11204 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 | ||
| 11205 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000 | ||
| 11206 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 | ||
| 11207 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1 | ||
| 11208 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 | ||
| 11209 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2 | ||
| 11210 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 | ||
| 11211 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4 | ||
| 11212 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 | ||
| 11213 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000 | ||
| 11214 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e | ||
| 11215 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000 | ||
| 11216 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f | ||
| 11217 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff | ||
| 11218 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 | ||
| 11219 | #define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3 | ||
| 11220 | #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 | ||
| 11221 | #define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc | ||
| 11222 | #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 | ||
| 11223 | #define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30 | ||
| 11224 | #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 | ||
| 11225 | #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 | ||
| 11226 | #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 | ||
| 11227 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff | ||
| 11228 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 | ||
| 11229 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 | ||
| 11230 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 | ||
| 11231 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 | ||
| 11232 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 | ||
| 11233 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 | ||
| 11234 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 | ||
| 11235 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 | ||
| 11236 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a | ||
| 11237 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 | ||
| 11238 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b | ||
| 11239 | #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 | ||
| 11240 | #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 | ||
| 11241 | #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe | ||
| 11242 | #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 | ||
| 11243 | #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 | ||
| 11244 | #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 | ||
| 11245 | #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 | ||
| 11246 | #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa | ||
| 11247 | #define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 | ||
| 11248 | #define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 | ||
| 11249 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 | ||
| 11250 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 | ||
| 11251 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 | ||
| 11252 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 | ||
| 11253 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 | ||
| 11254 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 | ||
| 11255 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 | ||
| 11256 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 | ||
| 11257 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 | ||
| 11258 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 | ||
| 11259 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 | ||
| 11260 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 | ||
| 11261 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 | ||
| 11262 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 | ||
| 11263 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 | ||
| 11264 | #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 | ||
| 11265 | #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 | ||
| 11266 | #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 | ||
| 11267 | #define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 | ||
| 11268 | #define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f | ||
| 11269 | #define SPI_DEBUG_READ__DATA_MASK 0xffffff | ||
| 11270 | #define SPI_DEBUG_READ__DATA__SHIFT 0x0 | ||
| 11271 | #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1 | ||
| 11272 | #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0 | ||
| 11273 | #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2 | ||
| 11274 | #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1 | ||
| 11275 | #define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4 | ||
| 11276 | #define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2 | ||
| 11277 | #define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8 | ||
| 11278 | #define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 | ||
| 11279 | #define SPI_EDC_CNT__SED_MASK 0xff | ||
| 11280 | #define SPI_EDC_CNT__SED__SHIFT 0x0 | ||
| 11281 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 11282 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11283 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 11284 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 11285 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 11286 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 11287 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 11288 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11289 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 11290 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 11291 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 11292 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 11293 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 11294 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11295 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 11296 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 11297 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 11298 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 11299 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 11300 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11301 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 11302 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 11303 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 11304 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 11305 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 11306 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 11307 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 11308 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 11309 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 11310 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 11311 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 11312 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 11313 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 11314 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 11315 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 11316 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 11317 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 11318 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 11319 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 11320 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 11321 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff | ||
| 11322 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11323 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff | ||
| 11324 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 11325 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf | ||
| 11326 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 | ||
| 11327 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 | ||
| 11328 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 | ||
| 11329 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 | ||
| 11330 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 | ||
| 11331 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 | ||
| 11332 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc | ||
| 11333 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 | ||
| 11334 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 | ||
| 11335 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 | ||
| 11336 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 | ||
| 11337 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 | ||
| 11338 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 | ||
| 11339 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 | ||
| 11340 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c | ||
| 11341 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11342 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11343 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11344 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11345 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11346 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11347 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11348 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11349 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11350 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11351 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11352 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11353 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11354 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11355 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11356 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11357 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11358 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11359 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11360 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11361 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 11362 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 11363 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 11364 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 11365 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf | ||
| 11366 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 | ||
| 11367 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 | ||
| 11368 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 | ||
| 11369 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 | ||
| 11370 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 | ||
| 11371 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 | ||
| 11372 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 | ||
| 11373 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 | ||
| 11374 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 | ||
| 11375 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 | ||
| 11376 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 | ||
| 11377 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 | ||
| 11378 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa | ||
| 11379 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 | ||
| 11380 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 | ||
| 11381 | #define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 | ||
| 11382 | #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 | ||
| 11383 | #define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 | ||
| 11384 | #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 | ||
| 11385 | #define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 | ||
| 11386 | #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 | ||
| 11387 | #define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 | ||
| 11388 | #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 | ||
| 11389 | #define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 | ||
| 11390 | #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 | ||
| 11391 | #define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 | ||
| 11392 | #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 | ||
| 11393 | #define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 | ||
| 11394 | #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 | ||
| 11395 | #define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 | ||
| 11396 | #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 | ||
| 11397 | #define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 | ||
| 11398 | #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 | ||
| 11399 | #define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 | ||
| 11400 | #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 | ||
| 11401 | #define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 | ||
| 11402 | #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa | ||
| 11403 | #define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 | ||
| 11404 | #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb | ||
| 11405 | #define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 | ||
| 11406 | #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc | ||
| 11407 | #define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 | ||
| 11408 | #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd | ||
| 11409 | #define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 | ||
| 11410 | #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe | ||
| 11411 | #define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 | ||
| 11412 | #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf | ||
| 11413 | #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 | ||
| 11414 | #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 | ||
| 11415 | #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 | ||
| 11416 | #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 | ||
| 11417 | #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 | ||
| 11418 | #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 | ||
| 11419 | #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 | ||
| 11420 | #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 | ||
| 11421 | #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 | ||
| 11422 | #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 | ||
| 11423 | #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 | ||
| 11424 | #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 | ||
| 11425 | #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 | ||
| 11426 | #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 | ||
| 11427 | #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 | ||
| 11428 | #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 | ||
| 11429 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf | ||
| 11430 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 | ||
| 11431 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0 | ||
| 11432 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 | ||
| 11433 | #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf | ||
| 11434 | #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 | ||
| 11435 | #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 | ||
| 11436 | #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 | ||
| 11437 | #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 | ||
| 11438 | #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc | ||
| 11439 | #define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 | ||
| 11440 | #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 | ||
| 11441 | #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 | ||
| 11442 | #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 | ||
| 11443 | #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 | ||
| 11444 | #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 | ||
| 11445 | #define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 | ||
| 11446 | #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 | ||
| 11447 | #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 | ||
| 11448 | #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 | ||
| 11449 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 | ||
| 11450 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 | ||
| 11451 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 | ||
| 11452 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 | ||
| 11453 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f | ||
| 11454 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 | ||
| 11455 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 | ||
| 11456 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 | ||
| 11457 | #define CGTS_RD_REG__READ_DATA_MASK 0x3fff | ||
| 11458 | #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 | ||
| 11459 | #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 | ||
| 11460 | #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 | ||
| 11461 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 | ||
| 11462 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 | ||
| 11463 | #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11464 | #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11465 | #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11466 | #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11467 | #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11468 | #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11469 | #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11470 | #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11471 | #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11472 | #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11473 | #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11474 | #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11475 | #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11476 | #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11477 | #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11478 | #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11479 | #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11480 | #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11481 | #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11482 | #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11483 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11484 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11485 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11486 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11487 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11488 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11489 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11490 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11491 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11492 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11493 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11494 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11495 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11496 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11497 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11498 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11499 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11500 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11501 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11502 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11503 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f | ||
| 11504 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 | ||
| 11505 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11506 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11507 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11508 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11509 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11510 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11511 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11512 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11513 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 | ||
| 11514 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 | ||
| 11515 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 | ||
| 11516 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 | ||
| 11517 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11518 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11519 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 | ||
| 11520 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a | ||
| 11521 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11522 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11523 | #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11524 | #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11525 | #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11526 | #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11527 | #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11528 | #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11529 | #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11530 | #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11531 | #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11532 | #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11533 | #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11534 | #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11535 | #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11536 | #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11537 | #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11538 | #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11539 | #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 11540 | #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 11541 | #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11542 | #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11543 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 11544 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 11545 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 11546 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 11547 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 11548 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11549 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 11550 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 11551 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11552 | #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11553 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 11554 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 11555 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 11556 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 11557 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11558 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11559 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 11560 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 11561 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11562 | #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11563 | #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11564 | #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11565 | #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11566 | #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11567 | #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11568 | #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11569 | #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11570 | #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11571 | #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11572 | #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11573 | #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11574 | #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11575 | #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11576 | #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11577 | #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11578 | #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11579 | #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11580 | #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11581 | #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11582 | #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11583 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11584 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11585 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11586 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11587 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11588 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11589 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11590 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11591 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11592 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11593 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11594 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11595 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11596 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11597 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11598 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11599 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11600 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11601 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11602 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11603 | #define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f | ||
| 11604 | #define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 11605 | #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11606 | #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11607 | #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11608 | #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11609 | #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11610 | #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11611 | #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11612 | #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11613 | #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11614 | #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11615 | #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11616 | #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11617 | #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11618 | #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11619 | #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11620 | #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11621 | #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11622 | #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11623 | #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11624 | #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11625 | #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11626 | #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11627 | #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11628 | #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11629 | #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 11630 | #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 11631 | #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11632 | #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11633 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 11634 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 11635 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 11636 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 11637 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 11638 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11639 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 11640 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 11641 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11642 | #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11643 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 11644 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 11645 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 11646 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 11647 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11648 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11649 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 11650 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 11651 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11652 | #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11653 | #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11654 | #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11655 | #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11656 | #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11657 | #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11658 | #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11659 | #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11660 | #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11661 | #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11662 | #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11663 | #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11664 | #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11665 | #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11666 | #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11667 | #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11668 | #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11669 | #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11670 | #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11671 | #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11672 | #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11673 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11674 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11675 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11676 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11677 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11678 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11679 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11680 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11681 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11682 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11683 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11684 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11685 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11686 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11687 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11688 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11689 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11690 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11691 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11692 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11693 | #define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f | ||
| 11694 | #define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 11695 | #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11696 | #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11697 | #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11698 | #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11699 | #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11700 | #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11701 | #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11702 | #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11703 | #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11704 | #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11705 | #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11706 | #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11707 | #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11708 | #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11709 | #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11710 | #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11711 | #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11712 | #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11713 | #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11714 | #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11715 | #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11716 | #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11717 | #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11718 | #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11719 | #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 11720 | #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 11721 | #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11722 | #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11723 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 11724 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 11725 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 11726 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 11727 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 11728 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11729 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 11730 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 11731 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11732 | #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11733 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 11734 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 11735 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 11736 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 11737 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11738 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11739 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 11740 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 11741 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11742 | #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11743 | #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11744 | #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11745 | #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11746 | #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11747 | #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11748 | #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11749 | #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11750 | #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11751 | #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11752 | #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11753 | #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11754 | #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11755 | #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11756 | #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11757 | #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11758 | #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11759 | #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11760 | #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11761 | #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11762 | #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11763 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11764 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11765 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11766 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11767 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11768 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11769 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11770 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11771 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11772 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11773 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11774 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11775 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11776 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11777 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11778 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11779 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11780 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11781 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11782 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11783 | #define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f | ||
| 11784 | #define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 11785 | #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11786 | #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11787 | #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11788 | #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11789 | #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11790 | #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11791 | #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11792 | #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11793 | #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11794 | #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11795 | #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11796 | #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11797 | #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11798 | #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11799 | #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11800 | #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11801 | #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11802 | #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11803 | #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11804 | #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11805 | #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11806 | #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11807 | #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11808 | #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11809 | #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 11810 | #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 11811 | #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11812 | #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11813 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 11814 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 11815 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 11816 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 11817 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 11818 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11819 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 11820 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 11821 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11822 | #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11823 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 11824 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 11825 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 11826 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 11827 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11828 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11829 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 11830 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 11831 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11832 | #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11833 | #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11834 | #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11835 | #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11836 | #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11837 | #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11838 | #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11839 | #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11840 | #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11841 | #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11842 | #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11843 | #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11844 | #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11845 | #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11846 | #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11847 | #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11848 | #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11849 | #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11850 | #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11851 | #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11852 | #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11853 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11854 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11855 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11856 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11857 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11858 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11859 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11860 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11861 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11862 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11863 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11864 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11865 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11866 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11867 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11868 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11869 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11870 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11871 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11872 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11873 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f | ||
| 11874 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 | ||
| 11875 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11876 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11877 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11878 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11879 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11880 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11881 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11882 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11883 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 | ||
| 11884 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 | ||
| 11885 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 | ||
| 11886 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 | ||
| 11887 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11888 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11889 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 | ||
| 11890 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a | ||
| 11891 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11892 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11893 | #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11894 | #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11895 | #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11896 | #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11897 | #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11898 | #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11899 | #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11900 | #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11901 | #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11902 | #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11903 | #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11904 | #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11905 | #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11906 | #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11907 | #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11908 | #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11909 | #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 11910 | #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 11911 | #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11912 | #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11913 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 11914 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 11915 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 11916 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 11917 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 11918 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11919 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 11920 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 11921 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11922 | #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11923 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 11924 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 11925 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 11926 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 11927 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11928 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11929 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 11930 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 11931 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11932 | #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11933 | #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 11934 | #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 11935 | #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 11936 | #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 11937 | #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 11938 | #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11939 | #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 11940 | #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 11941 | #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11942 | #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11943 | #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 11944 | #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 11945 | #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 11946 | #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 11947 | #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11948 | #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11949 | #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 11950 | #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 11951 | #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11952 | #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11953 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 11954 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 11955 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 11956 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 11957 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 11958 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11959 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 11960 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 11961 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11962 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11963 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 11964 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 11965 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 11966 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 11967 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11968 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11969 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 11970 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 11971 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 11972 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 11973 | #define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f | ||
| 11974 | #define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 11975 | #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 11976 | #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 11977 | #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 11978 | #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11979 | #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 11980 | #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 11981 | #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11982 | #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11983 | #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 11984 | #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 11985 | #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 11986 | #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 11987 | #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 11988 | #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 11989 | #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 11990 | #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 11991 | #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 11992 | #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 11993 | #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 11994 | #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 11995 | #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 11996 | #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 11997 | #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 11998 | #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 11999 | #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12000 | #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12001 | #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12002 | #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12003 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12004 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12005 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12006 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12007 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12008 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12009 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12010 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12011 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12012 | #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12013 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12014 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12015 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12016 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12017 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12018 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12019 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12020 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12021 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12022 | #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12023 | #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12024 | #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12025 | #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12026 | #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12027 | #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12028 | #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12029 | #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12030 | #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12031 | #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12032 | #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12033 | #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12034 | #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12035 | #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12036 | #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12037 | #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12038 | #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12039 | #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12040 | #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12041 | #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12042 | #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12043 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12044 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12045 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12046 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12047 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12048 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12049 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12050 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12051 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12052 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12053 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12054 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12055 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12056 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12057 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12058 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12059 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12060 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12061 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12062 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12063 | #define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12064 | #define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12065 | #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12066 | #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12067 | #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12068 | #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12069 | #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12070 | #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12071 | #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12072 | #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12073 | #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12074 | #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12075 | #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12076 | #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12077 | #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12078 | #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12079 | #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12080 | #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12081 | #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12082 | #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12083 | #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12084 | #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12085 | #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12086 | #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12087 | #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12088 | #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12089 | #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12090 | #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12091 | #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12092 | #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12093 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12094 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12095 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12096 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12097 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12098 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12099 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12100 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12101 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12102 | #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12103 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12104 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12105 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12106 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12107 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12108 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12109 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12110 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12111 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12112 | #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12113 | #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12114 | #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12115 | #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12116 | #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12117 | #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12118 | #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12119 | #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12120 | #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12121 | #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12122 | #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12123 | #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12124 | #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12125 | #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12126 | #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12127 | #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12128 | #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12129 | #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12130 | #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12131 | #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12132 | #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12133 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12134 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12135 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12136 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12137 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12138 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12139 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12140 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12141 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12142 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12143 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12144 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12145 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12146 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12147 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12148 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12149 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12150 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12151 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12152 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12153 | #define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12154 | #define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12155 | #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12156 | #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12157 | #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12158 | #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12159 | #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12160 | #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12161 | #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12162 | #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12163 | #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12164 | #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12165 | #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12166 | #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12167 | #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12168 | #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12169 | #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12170 | #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12171 | #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12172 | #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12173 | #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12174 | #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12175 | #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12176 | #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12177 | #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12178 | #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12179 | #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12180 | #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12181 | #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12182 | #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12183 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12184 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12185 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12186 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12187 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12188 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12189 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12190 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12191 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12192 | #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12193 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12194 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12195 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12196 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12197 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12198 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12199 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12200 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12201 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12202 | #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12203 | #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12204 | #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12205 | #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12206 | #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12207 | #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12208 | #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12209 | #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12210 | #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12211 | #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12212 | #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12213 | #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12214 | #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12215 | #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12216 | #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12217 | #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12218 | #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12219 | #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12220 | #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12221 | #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12222 | #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12223 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12224 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12225 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12226 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12227 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12228 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12229 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12230 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12231 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12232 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12233 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12234 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12235 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12236 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12237 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12238 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12239 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12240 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12241 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12242 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12243 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f | ||
| 12244 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 | ||
| 12245 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12246 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12247 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12248 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12249 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12250 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12251 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12252 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12253 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 | ||
| 12254 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 | ||
| 12255 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 | ||
| 12256 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 | ||
| 12257 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12258 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12259 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 | ||
| 12260 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a | ||
| 12261 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12262 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12263 | #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12264 | #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12265 | #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12266 | #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12267 | #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12268 | #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12269 | #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12270 | #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12271 | #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12272 | #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12273 | #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12274 | #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12275 | #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12276 | #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12277 | #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12278 | #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12279 | #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12280 | #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12281 | #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12282 | #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12283 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12284 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12285 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12286 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12287 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12288 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12289 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12290 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12291 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12292 | #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12293 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12294 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12295 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12296 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12297 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12298 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12299 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12300 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12301 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12302 | #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12303 | #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12304 | #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12305 | #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12306 | #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12307 | #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12308 | #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12309 | #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12310 | #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12311 | #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12312 | #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12313 | #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12314 | #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12315 | #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12316 | #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12317 | #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12318 | #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12319 | #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12320 | #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12321 | #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12322 | #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12323 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12324 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12325 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12326 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12327 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12328 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12329 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12330 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12331 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12332 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12333 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12334 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12335 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12336 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12337 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12338 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12339 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12340 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12341 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12342 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12343 | #define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12344 | #define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12345 | #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12346 | #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12347 | #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12348 | #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12349 | #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12350 | #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12351 | #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12352 | #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12353 | #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12354 | #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12355 | #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12356 | #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12357 | #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12358 | #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12359 | #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12360 | #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12361 | #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12362 | #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12363 | #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12364 | #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12365 | #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12366 | #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12367 | #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12368 | #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12369 | #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12370 | #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12371 | #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12372 | #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12373 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12374 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12375 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12376 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12377 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12378 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12379 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12380 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12381 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12382 | #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12383 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12384 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12385 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12386 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12387 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12388 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12389 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12390 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12391 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12392 | #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12393 | #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12394 | #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12395 | #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12396 | #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12397 | #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12398 | #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12399 | #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12400 | #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12401 | #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12402 | #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12403 | #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12404 | #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12405 | #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12406 | #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12407 | #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12408 | #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12409 | #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12410 | #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12411 | #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12412 | #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12413 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12414 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12415 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12416 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12417 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12418 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12419 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12420 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12421 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12422 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12423 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12424 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12425 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12426 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12427 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12428 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12429 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12430 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12431 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12432 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12433 | #define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12434 | #define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12435 | #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12436 | #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12437 | #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12438 | #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12439 | #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12440 | #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12441 | #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12442 | #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12443 | #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12444 | #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12445 | #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12446 | #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12447 | #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12448 | #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12449 | #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12450 | #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12451 | #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12452 | #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12453 | #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12454 | #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12455 | #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12456 | #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12457 | #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12458 | #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12459 | #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12460 | #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12461 | #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12462 | #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12463 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12464 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12465 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12466 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12467 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12468 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12469 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12470 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12471 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12472 | #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12473 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12474 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12475 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12476 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12477 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12478 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12479 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12480 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12481 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12482 | #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12483 | #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12484 | #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12485 | #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12486 | #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12487 | #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12488 | #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12489 | #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12490 | #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12491 | #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12492 | #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12493 | #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12494 | #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12495 | #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12496 | #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12497 | #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12498 | #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12499 | #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12500 | #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12501 | #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12502 | #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12503 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12504 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12505 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12506 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12507 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12508 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12509 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12510 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12511 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12512 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12513 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12514 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12515 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12516 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12517 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12518 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12519 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12520 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12521 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12522 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12523 | #define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12524 | #define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12525 | #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12526 | #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12527 | #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12528 | #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12529 | #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12530 | #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12531 | #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12532 | #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12533 | #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12534 | #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12535 | #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12536 | #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12537 | #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12538 | #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12539 | #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12540 | #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12541 | #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12542 | #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12543 | #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12544 | #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12545 | #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12546 | #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12547 | #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12548 | #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12549 | #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12550 | #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12551 | #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12552 | #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12553 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12554 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12555 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12556 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12557 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12558 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12559 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12560 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12561 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12562 | #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12563 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12564 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12565 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12566 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12567 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12568 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12569 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12570 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12571 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12572 | #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12573 | #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12574 | #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12575 | #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12576 | #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12577 | #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12578 | #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12579 | #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12580 | #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12581 | #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12582 | #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12583 | #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12584 | #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12585 | #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12586 | #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12587 | #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12588 | #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12589 | #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12590 | #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12591 | #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12592 | #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12593 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12594 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12595 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12596 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12597 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12598 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12599 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12600 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12601 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12602 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12603 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12604 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12605 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12606 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12607 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12608 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12609 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12610 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12611 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12612 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12613 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f | ||
| 12614 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 | ||
| 12615 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12616 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12617 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12618 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12619 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12620 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12621 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12622 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12623 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 | ||
| 12624 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 | ||
| 12625 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 | ||
| 12626 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 | ||
| 12627 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12628 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12629 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 | ||
| 12630 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a | ||
| 12631 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12632 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12633 | #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12634 | #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12635 | #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12636 | #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12637 | #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12638 | #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12639 | #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12640 | #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12641 | #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12642 | #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12643 | #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12644 | #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12645 | #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12646 | #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12647 | #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12648 | #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12649 | #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12650 | #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12651 | #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12652 | #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12653 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12654 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12655 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12656 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12657 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12658 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12659 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12660 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12661 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12662 | #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12663 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12664 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12665 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12666 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12667 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12668 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12669 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12670 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12671 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12672 | #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12673 | #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12674 | #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12675 | #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12676 | #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12677 | #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12678 | #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12679 | #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12680 | #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12681 | #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12682 | #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12683 | #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12684 | #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12685 | #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12686 | #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12687 | #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12688 | #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12689 | #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12690 | #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12691 | #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12692 | #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12693 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12694 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12695 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12696 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12697 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12698 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12699 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12700 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12701 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12702 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12703 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12704 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12705 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12706 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12707 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12708 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12709 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12710 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12711 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12712 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12713 | #define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12714 | #define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12715 | #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12716 | #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12717 | #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12718 | #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12719 | #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12720 | #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12721 | #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12722 | #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12723 | #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12724 | #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12725 | #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12726 | #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12727 | #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12728 | #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12729 | #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12730 | #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12731 | #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12732 | #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12733 | #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12734 | #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12735 | #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12736 | #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12737 | #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12738 | #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12739 | #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12740 | #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12741 | #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12742 | #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12743 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12744 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12745 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12746 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12747 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12748 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12749 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12750 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12751 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12752 | #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12753 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12754 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12755 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12756 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12757 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12758 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12759 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12760 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12761 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12762 | #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12763 | #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12764 | #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12765 | #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12766 | #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12767 | #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12768 | #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12769 | #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12770 | #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12771 | #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12772 | #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12773 | #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12774 | #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12775 | #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12776 | #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12777 | #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12778 | #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12779 | #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12780 | #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12781 | #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12782 | #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12783 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12784 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12785 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12786 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12787 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12788 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12789 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12790 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12791 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12792 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12793 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12794 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12795 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12796 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12797 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12798 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12799 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12800 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12801 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12802 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12803 | #define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12804 | #define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12805 | #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12806 | #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12807 | #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12808 | #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12809 | #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12810 | #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12811 | #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12812 | #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12813 | #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12814 | #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12815 | #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12816 | #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12817 | #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12818 | #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12819 | #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12820 | #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12821 | #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12822 | #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12823 | #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12824 | #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12825 | #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12826 | #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12827 | #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12828 | #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12829 | #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12830 | #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12831 | #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12832 | #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12833 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12834 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12835 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12836 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12837 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12838 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12839 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12840 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12841 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12842 | #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12843 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12844 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12845 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12846 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12847 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12848 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12849 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12850 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12851 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12852 | #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12853 | #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f | ||
| 12854 | #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 | ||
| 12855 | #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 | ||
| 12856 | #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 | ||
| 12857 | #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 | ||
| 12858 | #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12859 | #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 | ||
| 12860 | #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa | ||
| 12861 | #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12862 | #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12863 | #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 | ||
| 12864 | #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 | ||
| 12865 | #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 | ||
| 12866 | #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 | ||
| 12867 | #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12868 | #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12869 | #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 | ||
| 12870 | #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a | ||
| 12871 | #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12872 | #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12873 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f | ||
| 12874 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 | ||
| 12875 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 | ||
| 12876 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 | ||
| 12877 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 | ||
| 12878 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12879 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 | ||
| 12880 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa | ||
| 12881 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12882 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12883 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 | ||
| 12884 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 | ||
| 12885 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 | ||
| 12886 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 | ||
| 12887 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12888 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12889 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 | ||
| 12890 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a | ||
| 12891 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12892 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12893 | #define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f | ||
| 12894 | #define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 | ||
| 12895 | #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 | ||
| 12896 | #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 | ||
| 12897 | #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 | ||
| 12898 | #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12899 | #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 | ||
| 12900 | #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa | ||
| 12901 | #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12902 | #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12903 | #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f | ||
| 12904 | #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 | ||
| 12905 | #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 | ||
| 12906 | #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 | ||
| 12907 | #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 | ||
| 12908 | #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12909 | #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 | ||
| 12910 | #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa | ||
| 12911 | #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12912 | #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12913 | #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 | ||
| 12914 | #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 | ||
| 12915 | #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 | ||
| 12916 | #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 | ||
| 12917 | #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12918 | #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12919 | #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 | ||
| 12920 | #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a | ||
| 12921 | #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12922 | #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12923 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f | ||
| 12924 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 | ||
| 12925 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 | ||
| 12926 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 | ||
| 12927 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 | ||
| 12928 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 | ||
| 12929 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 | ||
| 12930 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa | ||
| 12931 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 | ||
| 12932 | #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb | ||
| 12933 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 | ||
| 12934 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 | ||
| 12935 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 | ||
| 12936 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 | ||
| 12937 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 | ||
| 12938 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 | ||
| 12939 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 | ||
| 12940 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a | ||
| 12941 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 | ||
| 12942 | #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b | ||
| 12943 | #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 12944 | #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 12945 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 12946 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 12947 | #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 | ||
| 12948 | #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 | ||
| 12949 | #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 | ||
| 12950 | #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 | ||
| 12951 | #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 | ||
| 12952 | #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a | ||
| 12953 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 | ||
| 12954 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b | ||
| 12955 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 | ||
| 12956 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c | ||
| 12957 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 | ||
| 12958 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d | ||
| 12959 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 | ||
| 12960 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e | ||
| 12961 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 12962 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 12963 | #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 12964 | #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 12965 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 12966 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 12967 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 | ||
| 12968 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 | ||
| 12969 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 | ||
| 12970 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 | ||
| 12971 | #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 | ||
| 12972 | #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 | ||
| 12973 | #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 | ||
| 12974 | #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a | ||
| 12975 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 | ||
| 12976 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b | ||
| 12977 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 | ||
| 12978 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c | ||
| 12979 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 | ||
| 12980 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d | ||
| 12981 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 | ||
| 12982 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e | ||
| 12983 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 12984 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 12985 | #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 12986 | #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 12987 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 12988 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 12989 | #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 | ||
| 12990 | #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc | ||
| 12991 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 | ||
| 12992 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 | ||
| 12993 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 | ||
| 12994 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 | ||
| 12995 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 | ||
| 12996 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a | ||
| 12997 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 | ||
| 12998 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b | ||
| 12999 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 | ||
| 13000 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c | ||
| 13001 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 | ||
| 13002 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d | ||
| 13003 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 | ||
| 13004 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e | ||
| 13005 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 13006 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 13007 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf | ||
| 13008 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 | ||
| 13009 | #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 | ||
| 13010 | #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 | ||
| 13011 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff | ||
| 13012 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 | ||
| 13013 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 | ||
| 13014 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f | ||
| 13015 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff | ||
| 13016 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 | ||
| 13017 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 | ||
| 13018 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f | ||
| 13019 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff | ||
| 13020 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 | ||
| 13021 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 | ||
| 13022 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f | ||
| 13023 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff | ||
| 13024 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 | ||
| 13025 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 | ||
| 13026 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f | ||
| 13027 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff | ||
| 13028 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 | ||
| 13029 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 | ||
| 13030 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f | ||
| 13031 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff | ||
| 13032 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 | ||
| 13033 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 | ||
| 13034 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f | ||
| 13035 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff | ||
| 13036 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 | ||
| 13037 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 | ||
| 13038 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f | ||
| 13039 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff | ||
| 13040 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 | ||
| 13041 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 | ||
| 13042 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f | ||
| 13043 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff | ||
| 13044 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 | ||
| 13045 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 | ||
| 13046 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f | ||
| 13047 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff | ||
| 13048 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 | ||
| 13049 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 | ||
| 13050 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f | ||
| 13051 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff | ||
| 13052 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 | ||
| 13053 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 | ||
| 13054 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f | ||
| 13055 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff | ||
| 13056 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 | ||
| 13057 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 | ||
| 13058 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f | ||
| 13059 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff | ||
| 13060 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 | ||
| 13061 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 | ||
| 13062 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f | ||
| 13063 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff | ||
| 13064 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 | ||
| 13065 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 | ||
| 13066 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f | ||
| 13067 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff | ||
| 13068 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 | ||
| 13069 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 | ||
| 13070 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f | ||
| 13071 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff | ||
| 13072 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 | ||
| 13073 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 | ||
| 13074 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f | ||
| 13075 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff | ||
| 13076 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 | ||
| 13077 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 | ||
| 13078 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f | ||
| 13079 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff | ||
| 13080 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 | ||
| 13081 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 | ||
| 13082 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f | ||
| 13083 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff | ||
| 13084 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 | ||
| 13085 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 | ||
| 13086 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f | ||
| 13087 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff | ||
| 13088 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 | ||
| 13089 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 | ||
| 13090 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f | ||
| 13091 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff | ||
| 13092 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 | ||
| 13093 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 | ||
| 13094 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f | ||
| 13095 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff | ||
| 13096 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 | ||
| 13097 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 | ||
| 13098 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f | ||
| 13099 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff | ||
| 13100 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 | ||
| 13101 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 | ||
| 13102 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f | ||
| 13103 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff | ||
| 13104 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 | ||
| 13105 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 | ||
| 13106 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f | ||
| 13107 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff | ||
| 13108 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 | ||
| 13109 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 | ||
| 13110 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f | ||
| 13111 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff | ||
| 13112 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 | ||
| 13113 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 | ||
| 13114 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f | ||
| 13115 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff | ||
| 13116 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 | ||
| 13117 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 | ||
| 13118 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f | ||
| 13119 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff | ||
| 13120 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 | ||
| 13121 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 | ||
| 13122 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f | ||
| 13123 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff | ||
| 13124 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 | ||
| 13125 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 | ||
| 13126 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f | ||
| 13127 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff | ||
| 13128 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 | ||
| 13129 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 | ||
| 13130 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f | ||
| 13131 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff | ||
| 13132 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 | ||
| 13133 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 | ||
| 13134 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f | ||
| 13135 | #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff | ||
| 13136 | #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 | ||
| 13137 | #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 | ||
| 13138 | #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f | ||
| 13139 | #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 | ||
| 13140 | #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 | ||
| 13141 | #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 | ||
| 13142 | #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 | ||
| 13143 | #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 | ||
| 13144 | #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 | ||
| 13145 | #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 | ||
| 13146 | #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 | ||
| 13147 | #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 | ||
| 13148 | #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 | ||
| 13149 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 | ||
| 13150 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 | ||
| 13151 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 | ||
| 13152 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 | ||
| 13153 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 | ||
| 13154 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 | ||
| 13155 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 | ||
| 13156 | #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 | ||
| 13157 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 | ||
| 13158 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 | ||
| 13159 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 | ||
| 13160 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa | ||
| 13161 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 | ||
| 13162 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb | ||
| 13163 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 | ||
| 13164 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc | ||
| 13165 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 | ||
| 13166 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd | ||
| 13167 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 | ||
| 13168 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe | ||
| 13169 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 | ||
| 13170 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf | ||
| 13171 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 | ||
| 13172 | #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 | ||
| 13173 | #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 | ||
| 13174 | #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 | ||
| 13175 | #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 | ||
| 13176 | #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 | ||
| 13177 | #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 | ||
| 13178 | #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 | ||
| 13179 | #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 | ||
| 13180 | #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 | ||
| 13181 | #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 | ||
| 13182 | #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 | ||
| 13183 | #define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000 | ||
| 13184 | #define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16 | ||
| 13185 | #define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 | ||
| 13186 | #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 | ||
| 13187 | #define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff | ||
| 13188 | #define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 | ||
| 13189 | #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff | ||
| 13190 | #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 | ||
| 13191 | #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff | ||
| 13192 | #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 | ||
| 13193 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff | ||
| 13194 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 | ||
| 13195 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 | ||
| 13196 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 | ||
| 13197 | #define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 | ||
| 13198 | #define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 | ||
| 13199 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff | ||
| 13200 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 | ||
| 13201 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 | ||
| 13202 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 | ||
| 13203 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff | ||
| 13204 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 | ||
| 13205 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 | ||
| 13206 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 | ||
| 13207 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff | ||
| 13208 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 | ||
| 13209 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff | ||
| 13210 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 | ||
| 13211 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff | ||
| 13212 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 | ||
| 13213 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff | ||
| 13214 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 | ||
| 13215 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff | ||
| 13216 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 | ||
| 13217 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff | ||
| 13218 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 | ||
| 13219 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff | ||
| 13220 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 | ||
| 13221 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff | ||
| 13222 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 | ||
| 13223 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff | ||
| 13224 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 | ||
| 13225 | #define BCI_DEBUG_READ__DATA_MASK 0xffffff | ||
| 13226 | #define BCI_DEBUG_READ__DATA__SHIFT 0x0 | ||
| 13227 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff | ||
| 13228 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 | ||
| 13229 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff | ||
| 13230 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 | ||
| 13231 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff | ||
| 13232 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 | ||
| 13233 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff | ||
| 13234 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 | ||
| 13235 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f | ||
| 13236 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 | ||
| 13237 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 | ||
| 13238 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 | ||
| 13239 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff | ||
| 13240 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 | ||
| 13241 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff | ||
| 13242 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 | ||
| 13243 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff | ||
| 13244 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 | ||
| 13245 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff | ||
| 13246 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 | ||
| 13247 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f | ||
| 13248 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 | ||
| 13249 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 | ||
| 13250 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 | ||
| 13251 | #define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff | ||
| 13252 | #define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 | ||
| 13253 | #define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff | ||
| 13254 | #define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 | ||
| 13255 | #define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff | ||
| 13256 | #define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 | ||
| 13257 | #define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff | ||
| 13258 | #define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 | ||
| 13259 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff | ||
| 13260 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 | ||
| 13261 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff | ||
| 13262 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 | ||
| 13263 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f | ||
| 13264 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 | ||
| 13265 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 | ||
| 13266 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 | ||
| 13267 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 | ||
| 13268 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa | ||
| 13269 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 | ||
| 13270 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc | ||
| 13271 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 | ||
| 13272 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 | ||
| 13273 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 | ||
| 13274 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 | ||
| 13275 | #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 | ||
| 13276 | #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 | ||
| 13277 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 | ||
| 13278 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 | ||
| 13279 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 | ||
| 13280 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 | ||
| 13281 | #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 | ||
| 13282 | #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 | ||
| 13283 | #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 | ||
| 13284 | #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c | ||
| 13285 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 | ||
| 13286 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 | ||
| 13287 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e | ||
| 13288 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 | ||
| 13289 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 | ||
| 13290 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13291 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 | ||
| 13292 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 | ||
| 13293 | #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 | ||
| 13294 | #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 | ||
| 13295 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 | ||
| 13296 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 | ||
| 13297 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff | ||
| 13298 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 | ||
| 13299 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 | ||
| 13300 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 | ||
| 13301 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 | ||
| 13302 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 | ||
| 13303 | #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff | ||
| 13304 | #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 | ||
| 13305 | #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff | ||
| 13306 | #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 | ||
| 13307 | #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff | ||
| 13308 | #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 | ||
| 13309 | #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff | ||
| 13310 | #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 | ||
| 13311 | #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff | ||
| 13312 | #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 | ||
| 13313 | #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff | ||
| 13314 | #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 | ||
| 13315 | #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff | ||
| 13316 | #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 | ||
| 13317 | #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff | ||
| 13318 | #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 | ||
| 13319 | #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff | ||
| 13320 | #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 | ||
| 13321 | #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff | ||
| 13322 | #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 | ||
| 13323 | #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff | ||
| 13324 | #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 | ||
| 13325 | #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff | ||
| 13326 | #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 | ||
| 13327 | #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff | ||
| 13328 | #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 | ||
| 13329 | #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff | ||
| 13330 | #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 | ||
| 13331 | #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff | ||
| 13332 | #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 | ||
| 13333 | #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff | ||
| 13334 | #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 | ||
| 13335 | #define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff | ||
| 13336 | #define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 | ||
| 13337 | #define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff | ||
| 13338 | #define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 | ||
| 13339 | #define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff | ||
| 13340 | #define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 | ||
| 13341 | #define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff | ||
| 13342 | #define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 | ||
| 13343 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff | ||
| 13344 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 | ||
| 13345 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff | ||
| 13346 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 | ||
| 13347 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f | ||
| 13348 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 | ||
| 13349 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 | ||
| 13350 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 | ||
| 13351 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 | ||
| 13352 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa | ||
| 13353 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 | ||
| 13354 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc | ||
| 13355 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 | ||
| 13356 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 | ||
| 13357 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 | ||
| 13358 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 | ||
| 13359 | #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 | ||
| 13360 | #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 | ||
| 13361 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 | ||
| 13362 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 | ||
| 13363 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 | ||
| 13364 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 | ||
| 13365 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 | ||
| 13366 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a | ||
| 13367 | #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 | ||
| 13368 | #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b | ||
| 13369 | #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 | ||
| 13370 | #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e | ||
| 13371 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 | ||
| 13372 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 | ||
| 13373 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e | ||
| 13374 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 | ||
| 13375 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 | ||
| 13376 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13377 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 | ||
| 13378 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 | ||
| 13379 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 | ||
| 13380 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 | ||
| 13381 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 | ||
| 13382 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 | ||
| 13383 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 | ||
| 13384 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa | ||
| 13385 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 | ||
| 13386 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb | ||
| 13387 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 | ||
| 13388 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc | ||
| 13389 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 | ||
| 13390 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd | ||
| 13391 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000 | ||
| 13392 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 | ||
| 13393 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff | ||
| 13394 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 | ||
| 13395 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 | ||
| 13396 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 | ||
| 13397 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 | ||
| 13398 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 | ||
| 13399 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f | ||
| 13400 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 | ||
| 13401 | #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff | ||
| 13402 | #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 | ||
| 13403 | #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff | ||
| 13404 | #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 | ||
| 13405 | #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff | ||
| 13406 | #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 | ||
| 13407 | #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff | ||
| 13408 | #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 | ||
| 13409 | #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff | ||
| 13410 | #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 | ||
| 13411 | #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff | ||
| 13412 | #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 | ||
| 13413 | #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff | ||
| 13414 | #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 | ||
| 13415 | #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff | ||
| 13416 | #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 | ||
| 13417 | #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff | ||
| 13418 | #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 | ||
| 13419 | #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff | ||
| 13420 | #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 | ||
| 13421 | #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff | ||
| 13422 | #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 | ||
| 13423 | #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff | ||
| 13424 | #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 | ||
| 13425 | #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff | ||
| 13426 | #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 | ||
| 13427 | #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff | ||
| 13428 | #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 | ||
| 13429 | #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff | ||
| 13430 | #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 | ||
| 13431 | #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff | ||
| 13432 | #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 | ||
| 13433 | #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 | ||
| 13434 | #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 | ||
| 13435 | #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e | ||
| 13436 | #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 | ||
| 13437 | #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 | ||
| 13438 | #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13439 | #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 | ||
| 13440 | #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 | ||
| 13441 | #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 | ||
| 13442 | #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 | ||
| 13443 | #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 | ||
| 13444 | #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 | ||
| 13445 | #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 | ||
| 13446 | #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 | ||
| 13447 | #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e | ||
| 13448 | #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 | ||
| 13449 | #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 | ||
| 13450 | #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13451 | #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 | ||
| 13452 | #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 | ||
| 13453 | #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 | ||
| 13454 | #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 | ||
| 13455 | #define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff | ||
| 13456 | #define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 | ||
| 13457 | #define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff | ||
| 13458 | #define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 | ||
| 13459 | #define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff | ||
| 13460 | #define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 | ||
| 13461 | #define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff | ||
| 13462 | #define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 | ||
| 13463 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff | ||
| 13464 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 | ||
| 13465 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff | ||
| 13466 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 | ||
| 13467 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f | ||
| 13468 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 | ||
| 13469 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 | ||
| 13470 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 | ||
| 13471 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 | ||
| 13472 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa | ||
| 13473 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 | ||
| 13474 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc | ||
| 13475 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 | ||
| 13476 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 | ||
| 13477 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 | ||
| 13478 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 | ||
| 13479 | #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 | ||
| 13480 | #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 | ||
| 13481 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 | ||
| 13482 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 | ||
| 13483 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 | ||
| 13484 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 | ||
| 13485 | #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 | ||
| 13486 | #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 | ||
| 13487 | #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 | ||
| 13488 | #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c | ||
| 13489 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 | ||
| 13490 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 | ||
| 13491 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e | ||
| 13492 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 | ||
| 13493 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 | ||
| 13494 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13495 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 | ||
| 13496 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 | ||
| 13497 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff | ||
| 13498 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 | ||
| 13499 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 | ||
| 13500 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 | ||
| 13501 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 | ||
| 13502 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 | ||
| 13503 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000 | ||
| 13504 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a | ||
| 13505 | #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff | ||
| 13506 | #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 | ||
| 13507 | #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff | ||
| 13508 | #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 | ||
| 13509 | #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff | ||
| 13510 | #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 | ||
| 13511 | #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff | ||
| 13512 | #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 | ||
| 13513 | #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff | ||
| 13514 | #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 | ||
| 13515 | #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff | ||
| 13516 | #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 | ||
| 13517 | #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff | ||
| 13518 | #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 | ||
| 13519 | #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff | ||
| 13520 | #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 | ||
| 13521 | #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff | ||
| 13522 | #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 | ||
| 13523 | #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff | ||
| 13524 | #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 | ||
| 13525 | #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff | ||
| 13526 | #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 | ||
| 13527 | #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff | ||
| 13528 | #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 | ||
| 13529 | #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff | ||
| 13530 | #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 | ||
| 13531 | #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff | ||
| 13532 | #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 | ||
| 13533 | #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff | ||
| 13534 | #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 | ||
| 13535 | #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff | ||
| 13536 | #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 | ||
| 13537 | #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 | ||
| 13538 | #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 | ||
| 13539 | #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e | ||
| 13540 | #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 | ||
| 13541 | #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 | ||
| 13542 | #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13543 | #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 | ||
| 13544 | #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 | ||
| 13545 | #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 | ||
| 13546 | #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 | ||
| 13547 | #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 | ||
| 13548 | #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 | ||
| 13549 | #define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff | ||
| 13550 | #define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 | ||
| 13551 | #define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff | ||
| 13552 | #define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 | ||
| 13553 | #define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff | ||
| 13554 | #define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 | ||
| 13555 | #define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff | ||
| 13556 | #define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 | ||
| 13557 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff | ||
| 13558 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 | ||
| 13559 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff | ||
| 13560 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 | ||
| 13561 | #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f | ||
| 13562 | #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 | ||
| 13563 | #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 | ||
| 13564 | #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 | ||
| 13565 | #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 | ||
| 13566 | #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa | ||
| 13567 | #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 | ||
| 13568 | #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc | ||
| 13569 | #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 | ||
| 13570 | #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 | ||
| 13571 | #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 | ||
| 13572 | #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 | ||
| 13573 | #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 | ||
| 13574 | #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 | ||
| 13575 | #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 | ||
| 13576 | #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 | ||
| 13577 | #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 | ||
| 13578 | #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 | ||
| 13579 | #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 | ||
| 13580 | #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a | ||
| 13581 | #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 | ||
| 13582 | #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b | ||
| 13583 | #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 | ||
| 13584 | #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e | ||
| 13585 | #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 | ||
| 13586 | #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 | ||
| 13587 | #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e | ||
| 13588 | #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 | ||
| 13589 | #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 | ||
| 13590 | #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 | ||
| 13591 | #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 | ||
| 13592 | #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 | ||
| 13593 | #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 | ||
| 13594 | #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 | ||
| 13595 | #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 | ||
| 13596 | #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 | ||
| 13597 | #define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff | ||
| 13598 | #define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 | ||
| 13599 | #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 | ||
| 13600 | #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 | ||
| 13601 | #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 | ||
| 13602 | #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 | ||
| 13603 | #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000 | ||
| 13604 | #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a | ||
| 13605 | #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff | ||
| 13606 | #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 | ||
| 13607 | #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff | ||
| 13608 | #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 | ||
| 13609 | #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff | ||
| 13610 | #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 | ||
| 13611 | #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff | ||
| 13612 | #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 | ||
| 13613 | #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff | ||
| 13614 | #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 | ||
| 13615 | #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff | ||
| 13616 | #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 | ||
| 13617 | #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff | ||
| 13618 | #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 | ||
| 13619 | #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff | ||
| 13620 | #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 | ||
| 13621 | #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff | ||
| 13622 | #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 | ||
| 13623 | #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff | ||
| 13624 | #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 | ||
| 13625 | #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff | ||
| 13626 | #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 | ||
| 13627 | #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff | ||
| 13628 | #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 | ||
| 13629 | #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff | ||
| 13630 | #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 | ||
| 13631 | #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff | ||
| 13632 | #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 | ||
| 13633 | #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff | ||
| 13634 | #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 | ||
| 13635 | #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff | ||
| 13636 | #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 | ||
| 13637 | #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 | ||
| 13638 | #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 | ||
| 13639 | #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e | ||
| 13640 | #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 | ||
| 13641 | #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 | ||
| 13642 | #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 | ||
| 13643 | #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 | ||
| 13644 | #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 | ||
| 13645 | #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 | ||
| 13646 | #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 | ||
| 13647 | #define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff | ||
| 13648 | #define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 | ||
| 13649 | #define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff | ||
| 13650 | #define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 | ||
| 13651 | #define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff | ||
| 13652 | #define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 | ||
| 13653 | #define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff | ||
| 13654 | #define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 | ||
| 13655 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff | ||
| 13656 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 | ||
| 13657 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff | ||
| 13658 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 | ||
| 13659 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f | ||
| 13660 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 | ||
| 13661 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 | ||
| 13662 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 | ||
| 13663 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 | ||
| 13664 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa | ||
| 13665 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 | ||
| 13666 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc | ||
| 13667 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 | ||
| 13668 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 | ||
| 13669 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 | ||
| 13670 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 | ||
| 13671 | #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 | ||
| 13672 | #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 | ||
| 13673 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 | ||
| 13674 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 | ||
| 13675 | #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 | ||
| 13676 | #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 | ||
| 13677 | #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 | ||
| 13678 | #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b | ||
| 13679 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 | ||
| 13680 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 | ||
| 13681 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e | ||
| 13682 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 | ||
| 13683 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 | ||
| 13684 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13685 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 | ||
| 13686 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 | ||
| 13687 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 | ||
| 13688 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 | ||
| 13689 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 | ||
| 13690 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 | ||
| 13691 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f | ||
| 13692 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 | ||
| 13693 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 | ||
| 13694 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 | ||
| 13695 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00 | ||
| 13696 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa | ||
| 13697 | #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff | ||
| 13698 | #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 | ||
| 13699 | #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff | ||
| 13700 | #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 | ||
| 13701 | #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff | ||
| 13702 | #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 | ||
| 13703 | #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff | ||
| 13704 | #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 | ||
| 13705 | #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff | ||
| 13706 | #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 | ||
| 13707 | #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff | ||
| 13708 | #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 | ||
| 13709 | #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff | ||
| 13710 | #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 | ||
| 13711 | #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff | ||
| 13712 | #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 | ||
| 13713 | #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff | ||
| 13714 | #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 | ||
| 13715 | #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff | ||
| 13716 | #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 | ||
| 13717 | #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff | ||
| 13718 | #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 | ||
| 13719 | #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff | ||
| 13720 | #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 | ||
| 13721 | #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff | ||
| 13722 | #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 | ||
| 13723 | #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff | ||
| 13724 | #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 | ||
| 13725 | #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff | ||
| 13726 | #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 | ||
| 13727 | #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff | ||
| 13728 | #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 | ||
| 13729 | #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 | ||
| 13730 | #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 | ||
| 13731 | #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e | ||
| 13732 | #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 | ||
| 13733 | #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 | ||
| 13734 | #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13735 | #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 | ||
| 13736 | #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 | ||
| 13737 | #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 | ||
| 13738 | #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 | ||
| 13739 | #define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff | ||
| 13740 | #define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 | ||
| 13741 | #define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff | ||
| 13742 | #define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 | ||
| 13743 | #define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff | ||
| 13744 | #define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 | ||
| 13745 | #define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff | ||
| 13746 | #define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 | ||
| 13747 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff | ||
| 13748 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 | ||
| 13749 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff | ||
| 13750 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 | ||
| 13751 | #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f | ||
| 13752 | #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 | ||
| 13753 | #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 | ||
| 13754 | #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 | ||
| 13755 | #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 | ||
| 13756 | #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa | ||
| 13757 | #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 | ||
| 13758 | #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc | ||
| 13759 | #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 | ||
| 13760 | #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 | ||
| 13761 | #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 | ||
| 13762 | #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 | ||
| 13763 | #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 | ||
| 13764 | #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 | ||
| 13765 | #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 | ||
| 13766 | #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 | ||
| 13767 | #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 | ||
| 13768 | #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 | ||
| 13769 | #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 | ||
| 13770 | #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a | ||
| 13771 | #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 | ||
| 13772 | #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d | ||
| 13773 | #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 | ||
| 13774 | #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 | ||
| 13775 | #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e | ||
| 13776 | #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 | ||
| 13777 | #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 | ||
| 13778 | #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 | ||
| 13779 | #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 | ||
| 13780 | #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 | ||
| 13781 | #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 | ||
| 13782 | #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 | ||
| 13783 | #define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff | ||
| 13784 | #define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 | ||
| 13785 | #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 | ||
| 13786 | #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 | ||
| 13787 | #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 | ||
| 13788 | #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 | ||
| 13789 | #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000 | ||
| 13790 | #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a | ||
| 13791 | #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff | ||
| 13792 | #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 | ||
| 13793 | #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff | ||
| 13794 | #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 | ||
| 13795 | #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff | ||
| 13796 | #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 | ||
| 13797 | #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff | ||
| 13798 | #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 | ||
| 13799 | #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff | ||
| 13800 | #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 | ||
| 13801 | #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff | ||
| 13802 | #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 | ||
| 13803 | #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff | ||
| 13804 | #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 | ||
| 13805 | #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff | ||
| 13806 | #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 | ||
| 13807 | #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff | ||
| 13808 | #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 | ||
| 13809 | #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff | ||
| 13810 | #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 | ||
| 13811 | #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff | ||
| 13812 | #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 | ||
| 13813 | #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff | ||
| 13814 | #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 | ||
| 13815 | #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff | ||
| 13816 | #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 | ||
| 13817 | #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff | ||
| 13818 | #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 | ||
| 13819 | #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff | ||
| 13820 | #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 | ||
| 13821 | #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff | ||
| 13822 | #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 | ||
| 13823 | #define SQ_CONFIG__UNUSED_MASK 0xff | ||
| 13824 | #define SQ_CONFIG__UNUSED__SHIFT 0x0 | ||
| 13825 | #define SQ_CONFIG__DEBUG_EN_MASK 0x100 | ||
| 13826 | #define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 | ||
| 13827 | #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200 | ||
| 13828 | #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 | ||
| 13829 | #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400 | ||
| 13830 | #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa | ||
| 13831 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 | ||
| 13832 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc | ||
| 13833 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 | ||
| 13834 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd | ||
| 13835 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 | ||
| 13836 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe | ||
| 13837 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 | ||
| 13838 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf | ||
| 13839 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000 | ||
| 13840 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 | ||
| 13841 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000 | ||
| 13842 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 | ||
| 13843 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000 | ||
| 13844 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 | ||
| 13845 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000 | ||
| 13846 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 | ||
| 13847 | #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000 | ||
| 13848 | #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 | ||
| 13849 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 | ||
| 13850 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 | ||
| 13851 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc | ||
| 13852 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 | ||
| 13853 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 | ||
| 13854 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 | ||
| 13855 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 | ||
| 13856 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 | ||
| 13857 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 | ||
| 13858 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 | ||
| 13859 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 | ||
| 13860 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 | ||
| 13861 | #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 | ||
| 13862 | #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 | ||
| 13863 | #define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 | ||
| 13864 | #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa | ||
| 13865 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 | ||
| 13866 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb | ||
| 13867 | #define SQC_CONFIG__EVICT_LRU_MASK 0x3000 | ||
| 13868 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc | ||
| 13869 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000 | ||
| 13870 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe | ||
| 13871 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000 | ||
| 13872 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf | ||
| 13873 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000 | ||
| 13874 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 | ||
| 13875 | #define SQC_CACHES__TARGET_INST_MASK 0x1 | ||
| 13876 | #define SQC_CACHES__TARGET_INST__SHIFT 0x0 | ||
| 13877 | #define SQC_CACHES__TARGET_DATA_MASK 0x2 | ||
| 13878 | #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 | ||
| 13879 | #define SQC_CACHES__INVALIDATE_MASK 0x4 | ||
| 13880 | #define SQC_CACHES__INVALIDATE__SHIFT 0x2 | ||
| 13881 | #define SQC_CACHES__WRITEBACK_MASK 0x8 | ||
| 13882 | #define SQC_CACHES__WRITEBACK__SHIFT 0x3 | ||
| 13883 | #define SQC_CACHES__VOL_MASK 0x10 | ||
| 13884 | #define SQC_CACHES__VOL__SHIFT 0x4 | ||
| 13885 | #define SQC_CACHES__COMPLETE_MASK 0x10000 | ||
| 13886 | #define SQC_CACHES__COMPLETE__SHIFT 0x10 | ||
| 13887 | #define SQC_WRITEBACK__DWB_MASK 0x1 | ||
| 13888 | #define SQC_WRITEBACK__DWB__SHIFT 0x0 | ||
| 13889 | #define SQC_WRITEBACK__DIRTY_MASK 0x2 | ||
| 13890 | #define SQC_WRITEBACK__DIRTY__SHIFT 0x1 | ||
| 13891 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3 | ||
| 13892 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0 | ||
| 13893 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4 | ||
| 13894 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2 | ||
| 13895 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18 | ||
| 13896 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3 | ||
| 13897 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20 | ||
| 13898 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5 | ||
| 13899 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0 | ||
| 13900 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6 | ||
| 13901 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100 | ||
| 13902 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8 | ||
| 13903 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600 | ||
| 13904 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9 | ||
| 13905 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800 | ||
| 13906 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb | ||
| 13907 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000 | ||
| 13908 | #define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc | ||
| 13909 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000 | ||
| 13910 | #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe | ||
| 13911 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000 | ||
| 13912 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf | ||
| 13913 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000 | ||
| 13914 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11 | ||
| 13915 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000 | ||
| 13916 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12 | ||
| 13917 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000 | ||
| 13918 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14 | ||
| 13919 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000 | ||
| 13920 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15 | ||
| 13921 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000 | ||
| 13922 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17 | ||
| 13923 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000 | ||
| 13924 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18 | ||
| 13925 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000 | ||
| 13926 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a | ||
| 13927 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000 | ||
| 13928 | #define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b | ||
| 13929 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000 | ||
| 13930 | #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d | ||
| 13931 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f | ||
| 13932 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 | ||
| 13933 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 | ||
| 13934 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 | ||
| 13935 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 | ||
| 13936 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa | ||
| 13937 | #define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f | ||
| 13938 | #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 | ||
| 13939 | #define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 | ||
| 13940 | #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 | ||
| 13941 | #define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 | ||
| 13942 | #define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c | ||
| 13943 | #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 | ||
| 13944 | #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d | ||
| 13945 | #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 | ||
| 13946 | #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e | ||
| 13947 | #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 | ||
| 13948 | #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f | ||
| 13949 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf | ||
| 13950 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 | ||
| 13951 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 | ||
| 13952 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 | ||
| 13953 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 | ||
| 13954 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 | ||
| 13955 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 | ||
| 13956 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 | ||
| 13957 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 | ||
| 13958 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 | ||
| 13959 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2 | ||
| 13960 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 | ||
| 13961 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4 | ||
| 13962 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 | ||
| 13963 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8 | ||
| 13964 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 | ||
| 13965 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100 | ||
| 13966 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 | ||
| 13967 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200 | ||
| 13968 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 | ||
| 13969 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400 | ||
| 13970 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa | ||
| 13971 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000 | ||
| 13972 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 | ||
| 13973 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000 | ||
| 13974 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 | ||
| 13975 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000 | ||
| 13976 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 | ||
| 13977 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000 | ||
| 13978 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 | ||
| 13979 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000 | ||
| 13980 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 | ||
| 13981 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000 | ||
| 13982 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 | ||
| 13983 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000 | ||
| 13984 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 | ||
| 13985 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000 | ||
| 13986 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 | ||
| 13987 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000 | ||
| 13988 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a | ||
| 13989 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 | ||
| 13990 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 | ||
| 13991 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 | ||
| 13992 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 | ||
| 13993 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 | ||
| 13994 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 | ||
| 13995 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 | ||
| 13996 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 | ||
| 13997 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 | ||
| 13998 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 | ||
| 13999 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 | ||
| 14000 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 | ||
| 14001 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff | ||
| 14002 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 | ||
| 14003 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 | ||
| 14004 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 | ||
| 14005 | #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 | ||
| 14006 | #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 | ||
| 14007 | #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 | ||
| 14008 | #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 | ||
| 14009 | #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 | ||
| 14010 | #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 | ||
| 14011 | #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 | ||
| 14012 | #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 | ||
| 14013 | #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 | ||
| 14014 | #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 | ||
| 14015 | #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 | ||
| 14016 | #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 | ||
| 14017 | #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 | ||
| 14018 | #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 | ||
| 14019 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 | ||
| 14020 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 | ||
| 14021 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 | ||
| 14022 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd | ||
| 14023 | #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff | ||
| 14024 | #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 | ||
| 14025 | #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 | ||
| 14026 | #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 | ||
| 14027 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 | ||
| 14028 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 | ||
| 14029 | #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 | ||
| 14030 | #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 | ||
| 14031 | #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 | ||
| 14032 | #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 | ||
| 14033 | #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 | ||
| 14034 | #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 | ||
| 14035 | #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 | ||
| 14036 | #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c | ||
| 14037 | #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 | ||
| 14038 | #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 | ||
| 14039 | #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 | ||
| 14040 | #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 | ||
| 14041 | #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 | ||
| 14042 | #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 | ||
| 14043 | #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 | ||
| 14044 | #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c | ||
| 14045 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14046 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14047 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14048 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14049 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14050 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14051 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14052 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14053 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14054 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14055 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14056 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14057 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14058 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14059 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14060 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14061 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14062 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14063 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14064 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14065 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14066 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14067 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14068 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14069 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14070 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14071 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14072 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14073 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14074 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14075 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 14076 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 14077 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14078 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14079 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14080 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14081 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14082 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14083 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14084 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14085 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14086 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14087 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14088 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14089 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14090 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14091 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14092 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14093 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14094 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14095 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14096 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14097 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14098 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14099 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14100 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14101 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14102 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14103 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14104 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14105 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14106 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14107 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 14108 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 14109 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14110 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14111 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14112 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14113 | #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14114 | #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14115 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14116 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14117 | #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14118 | #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14119 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14120 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14121 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14122 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14123 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14124 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14125 | #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14126 | #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14127 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14128 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14129 | #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14130 | #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14131 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14132 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14133 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14134 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14135 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14136 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14137 | #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14138 | #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14139 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14140 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14141 | #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14142 | #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14143 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14144 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14145 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14146 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14147 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14148 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14149 | #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14150 | #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14151 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14152 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14153 | #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14154 | #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14155 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14156 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14157 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14158 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14159 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14160 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14161 | #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14162 | #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14163 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14164 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14165 | #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14166 | #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14167 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14168 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14169 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14170 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14171 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14172 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14173 | #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14174 | #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14175 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14176 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14177 | #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14178 | #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14179 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14180 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14181 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14182 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14183 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14184 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14185 | #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14186 | #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14187 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14188 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14189 | #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14190 | #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14191 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14192 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14193 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14194 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14195 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14196 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14197 | #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14198 | #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14199 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14200 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14201 | #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14202 | #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14203 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14204 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14205 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14206 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14207 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14208 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14209 | #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14210 | #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14211 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14212 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14213 | #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14214 | #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14215 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14216 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14217 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14218 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14219 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14220 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14221 | #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14222 | #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14223 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14224 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14225 | #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14226 | #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14227 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14228 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14229 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14230 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14231 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14232 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14233 | #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14234 | #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14235 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14236 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14237 | #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14238 | #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14239 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14240 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14241 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14242 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14243 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14244 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14245 | #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14246 | #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14247 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14248 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14249 | #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14250 | #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14251 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14252 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14253 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14254 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14255 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14256 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14257 | #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14258 | #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14259 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14260 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14261 | #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14262 | #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14263 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14264 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14265 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14266 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14267 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14268 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14269 | #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14270 | #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14271 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14272 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14273 | #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14274 | #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14275 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14276 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14277 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14278 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14279 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14280 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14281 | #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14282 | #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14283 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14284 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14285 | #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14286 | #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14287 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14288 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14289 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff | ||
| 14290 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 14291 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 | ||
| 14292 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc | ||
| 14293 | #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 | ||
| 14294 | #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 | ||
| 14295 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 | ||
| 14296 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 | ||
| 14297 | #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 | ||
| 14298 | #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 | ||
| 14299 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 14300 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 14301 | #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 14302 | #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 14303 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 14304 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 14305 | #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 | ||
| 14306 | #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d | ||
| 14307 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 | ||
| 14308 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e | ||
| 14309 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 14310 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 14311 | #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 14312 | #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 14313 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 14314 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 14315 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000 | ||
| 14316 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c | ||
| 14317 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 | ||
| 14318 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d | ||
| 14319 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 | ||
| 14320 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e | ||
| 14321 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 14322 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 14323 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff | ||
| 14324 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 | ||
| 14325 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 | ||
| 14326 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 | ||
| 14327 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff | ||
| 14328 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 | ||
| 14329 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 | ||
| 14330 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 | ||
| 14331 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff | ||
| 14332 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 | ||
| 14333 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 | ||
| 14334 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 | ||
| 14335 | #define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff | ||
| 14336 | #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 | ||
| 14337 | #define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 | ||
| 14338 | #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 | ||
| 14339 | #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 | ||
| 14340 | #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e | ||
| 14341 | #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 14342 | #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 14343 | #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 14344 | #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 14345 | #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 14346 | #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 14347 | #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 | ||
| 14348 | #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f | ||
| 14349 | #define SQ_TIME_HI__TIME_MASK 0xffffffff | ||
| 14350 | #define SQ_TIME_HI__TIME__SHIFT 0x0 | ||
| 14351 | #define SQ_TIME_LO__TIME_MASK 0xffffffff | ||
| 14352 | #define SQ_TIME_LO__TIME__SHIFT 0x0 | ||
| 14353 | #define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff | ||
| 14354 | #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 | ||
| 14355 | #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf | ||
| 14356 | #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 | ||
| 14357 | #define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff | ||
| 14358 | #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 | ||
| 14359 | #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f | ||
| 14360 | #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 | ||
| 14361 | #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 | ||
| 14362 | #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 | ||
| 14363 | #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 | ||
| 14364 | #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 | ||
| 14365 | #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 | ||
| 14366 | #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 | ||
| 14367 | #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 | ||
| 14368 | #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc | ||
| 14369 | #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 | ||
| 14370 | #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe | ||
| 14371 | #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 | ||
| 14372 | #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf | ||
| 14373 | #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff | ||
| 14374 | #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 | ||
| 14375 | #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff | ||
| 14376 | #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 | ||
| 14377 | #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff | ||
| 14378 | #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 | ||
| 14379 | #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff | ||
| 14380 | #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 | ||
| 14381 | #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 | ||
| 14382 | #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 | ||
| 14383 | #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 | ||
| 14384 | #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 | ||
| 14385 | #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 | ||
| 14386 | #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 | ||
| 14387 | #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 | ||
| 14388 | #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 | ||
| 14389 | #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 | ||
| 14390 | #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc | ||
| 14391 | #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 | ||
| 14392 | #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf | ||
| 14393 | #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 | ||
| 14394 | #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 | ||
| 14395 | #define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 | ||
| 14396 | #define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 | ||
| 14397 | #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 | ||
| 14398 | #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 | ||
| 14399 | #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 | ||
| 14400 | #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 | ||
| 14401 | #define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 | ||
| 14402 | #define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a | ||
| 14403 | #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 | ||
| 14404 | #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b | ||
| 14405 | #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 | ||
| 14406 | #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d | ||
| 14407 | #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 | ||
| 14408 | #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e | ||
| 14409 | #define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 | ||
| 14410 | #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f | ||
| 14411 | #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 | ||
| 14412 | #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f | ||
| 14413 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff | ||
| 14414 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 | ||
| 14415 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 | ||
| 14416 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 | ||
| 14417 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 | ||
| 14418 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 | ||
| 14419 | #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff | ||
| 14420 | #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 | ||
| 14421 | #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff | ||
| 14422 | #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 | ||
| 14423 | #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 | ||
| 14424 | #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 | ||
| 14425 | #define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff | ||
| 14426 | #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 | ||
| 14427 | #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 | ||
| 14428 | #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e | ||
| 14429 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff | ||
| 14430 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 | ||
| 14431 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 | ||
| 14432 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 | ||
| 14433 | #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 | ||
| 14434 | #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d | ||
| 14435 | #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 | ||
| 14436 | #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e | ||
| 14437 | #define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 | ||
| 14438 | #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f | ||
| 14439 | #define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff | ||
| 14440 | #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 | ||
| 14441 | #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 | ||
| 14442 | #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 | ||
| 14443 | #define SQ_LB_CTR_CTRL__START_MASK 0x1 | ||
| 14444 | #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 | ||
| 14445 | #define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 | ||
| 14446 | #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 | ||
| 14447 | #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 | ||
| 14448 | #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 | ||
| 14449 | #define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff | ||
| 14450 | #define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 | ||
| 14451 | #define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff | ||
| 14452 | #define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 | ||
| 14453 | #define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff | ||
| 14454 | #define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 | ||
| 14455 | #define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff | ||
| 14456 | #define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 | ||
| 14457 | #define SQC_EDC_CNT__INST_SEC_MASK 0xff | ||
| 14458 | #define SQC_EDC_CNT__INST_SEC__SHIFT 0x0 | ||
| 14459 | #define SQC_EDC_CNT__INST_DED_MASK 0xff00 | ||
| 14460 | #define SQC_EDC_CNT__INST_DED__SHIFT 0x8 | ||
| 14461 | #define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000 | ||
| 14462 | #define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10 | ||
| 14463 | #define SQC_EDC_CNT__DATA_DED_MASK 0xff000000 | ||
| 14464 | #define SQC_EDC_CNT__DATA_DED__SHIFT 0x18 | ||
| 14465 | #define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff | ||
| 14466 | #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 | ||
| 14467 | #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00 | ||
| 14468 | #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 | ||
| 14469 | #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 | ||
| 14470 | #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 | ||
| 14471 | #define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff | ||
| 14472 | #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 | ||
| 14473 | #define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00 | ||
| 14474 | #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 | ||
| 14475 | #define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000 | ||
| 14476 | #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 | ||
| 14477 | #define SQ_EDC_INFO__WAVE_ID_MASK 0xf | ||
| 14478 | #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 | ||
| 14479 | #define SQ_EDC_INFO__SIMD_ID_MASK 0x30 | ||
| 14480 | #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 | ||
| 14481 | #define SQ_EDC_INFO__SOURCE_MASK 0x1c0 | ||
| 14482 | #define SQ_EDC_INFO__SOURCE__SHIFT 0x6 | ||
| 14483 | #define SQ_EDC_INFO__VM_ID_MASK 0x1e00 | ||
| 14484 | #define SQ_EDC_INFO__VM_ID__SHIFT 0x9 | ||
| 14485 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff | ||
| 14486 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 | ||
| 14487 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff | ||
| 14488 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 | ||
| 14489 | #define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 | ||
| 14490 | #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 | ||
| 14491 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 | ||
| 14492 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e | ||
| 14493 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 | ||
| 14494 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f | ||
| 14495 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff | ||
| 14496 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 | ||
| 14497 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 | ||
| 14498 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 | ||
| 14499 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 | ||
| 14500 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 | ||
| 14501 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 | ||
| 14502 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 | ||
| 14503 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 | ||
| 14504 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 | ||
| 14505 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 | ||
| 14506 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc | ||
| 14507 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 | ||
| 14508 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf | ||
| 14509 | #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 | ||
| 14510 | #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 | ||
| 14511 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 | ||
| 14512 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 | ||
| 14513 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 | ||
| 14514 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 | ||
| 14515 | #define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 | ||
| 14516 | #define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 | ||
| 14517 | #define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 | ||
| 14518 | #define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 | ||
| 14519 | #define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 | ||
| 14520 | #define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a | ||
| 14521 | #define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 | ||
| 14522 | #define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b | ||
| 14523 | #define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 | ||
| 14524 | #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e | ||
| 14525 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff | ||
| 14526 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 | ||
| 14527 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff | ||
| 14528 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 | ||
| 14529 | #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 | ||
| 14530 | #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 | ||
| 14531 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 | ||
| 14532 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 | ||
| 14533 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 | ||
| 14534 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a | ||
| 14535 | #define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 | ||
| 14536 | #define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e | ||
| 14537 | #define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff | ||
| 14538 | #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 | ||
| 14539 | #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 | ||
| 14540 | #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe | ||
| 14541 | #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 | ||
| 14542 | #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c | ||
| 14543 | #define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 | ||
| 14544 | #define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f | ||
| 14545 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 | ||
| 14546 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 | ||
| 14547 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 | ||
| 14548 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 | ||
| 14549 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 | ||
| 14550 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 | ||
| 14551 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 | ||
| 14552 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 | ||
| 14553 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 | ||
| 14554 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc | ||
| 14555 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 | ||
| 14556 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 | ||
| 14557 | #define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 | ||
| 14558 | #define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 | ||
| 14559 | #define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 | ||
| 14560 | #define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 | ||
| 14561 | #define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 | ||
| 14562 | #define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a | ||
| 14563 | #define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 | ||
| 14564 | #define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b | ||
| 14565 | #define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 | ||
| 14566 | #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c | ||
| 14567 | #define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff | ||
| 14568 | #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 | ||
| 14569 | #define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 | ||
| 14570 | #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd | ||
| 14571 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff | ||
| 14572 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 | ||
| 14573 | #define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 | ||
| 14574 | #define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd | ||
| 14575 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff | ||
| 14576 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 | ||
| 14577 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 | ||
| 14578 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc | ||
| 14579 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 | ||
| 14580 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 | ||
| 14581 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000 | ||
| 14582 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 | ||
| 14583 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000 | ||
| 14584 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 | ||
| 14585 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000 | ||
| 14586 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 | ||
| 14587 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000 | ||
| 14588 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 | ||
| 14589 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000 | ||
| 14590 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c | ||
| 14591 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff | ||
| 14592 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 | ||
| 14593 | #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 | ||
| 14594 | #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 | ||
| 14595 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 | ||
| 14596 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 | ||
| 14597 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 | ||
| 14598 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 | ||
| 14599 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 | ||
| 14600 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 | ||
| 14601 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 | ||
| 14602 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc | ||
| 14603 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 | ||
| 14604 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf | ||
| 14605 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 | ||
| 14606 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 | ||
| 14607 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 | ||
| 14608 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 | ||
| 14609 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 | ||
| 14610 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 | ||
| 14611 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 | ||
| 14612 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 | ||
| 14613 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 | ||
| 14614 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b | ||
| 14615 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 | ||
| 14616 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c | ||
| 14617 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 | ||
| 14618 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d | ||
| 14619 | #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000 | ||
| 14620 | #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f | ||
| 14621 | #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff | ||
| 14622 | #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 | ||
| 14623 | #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 | ||
| 14624 | #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc | ||
| 14625 | #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 | ||
| 14626 | #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 | ||
| 14627 | #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 | ||
| 14628 | #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c | ||
| 14629 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff | ||
| 14630 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 | ||
| 14631 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 | ||
| 14632 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe | ||
| 14633 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 | ||
| 14634 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 | ||
| 14635 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 | ||
| 14636 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 | ||
| 14637 | #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 | ||
| 14638 | #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 | ||
| 14639 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 | ||
| 14640 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a | ||
| 14641 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 | ||
| 14642 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c | ||
| 14643 | #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 | ||
| 14644 | #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d | ||
| 14645 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 | ||
| 14646 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e | ||
| 14647 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000 | ||
| 14648 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f | ||
| 14649 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff | ||
| 14650 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 | ||
| 14651 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 | ||
| 14652 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e | ||
| 14653 | #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff | ||
| 14654 | #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 | ||
| 14655 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff | ||
| 14656 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 | ||
| 14657 | #define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff | ||
| 14658 | #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 | ||
| 14659 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000 | ||
| 14660 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc | ||
| 14661 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000 | ||
| 14662 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd | ||
| 14663 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000 | ||
| 14664 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe | ||
| 14665 | #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000 | ||
| 14666 | #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf | ||
| 14667 | #define SQ_IND_INDEX__WAVE_ID_MASK 0xf | ||
| 14668 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 | ||
| 14669 | #define SQ_IND_INDEX__SIMD_ID_MASK 0x30 | ||
| 14670 | #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 | ||
| 14671 | #define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 | ||
| 14672 | #define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 | ||
| 14673 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 | ||
| 14674 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc | ||
| 14675 | #define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 | ||
| 14676 | #define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd | ||
| 14677 | #define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 | ||
| 14678 | #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe | ||
| 14679 | #define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 | ||
| 14680 | #define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf | ||
| 14681 | #define SQ_IND_INDEX__INDEX_MASK 0xffff0000 | ||
| 14682 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 | ||
| 14683 | #define SQ_CMD__CMD_MASK 0x7 | ||
| 14684 | #define SQ_CMD__CMD__SHIFT 0x0 | ||
| 14685 | #define SQ_CMD__MODE_MASK 0x70 | ||
| 14686 | #define SQ_CMD__MODE__SHIFT 0x4 | ||
| 14687 | #define SQ_CMD__CHECK_VMID_MASK 0x80 | ||
| 14688 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 | ||
| 14689 | #define SQ_CMD__DATA_MASK 0x700 | ||
| 14690 | #define SQ_CMD__DATA__SHIFT 0x8 | ||
| 14691 | #define SQ_CMD__WAVE_ID_MASK 0xf0000 | ||
| 14692 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 | ||
| 14693 | #define SQ_CMD__SIMD_ID_MASK 0x300000 | ||
| 14694 | #define SQ_CMD__SIMD_ID__SHIFT 0x14 | ||
| 14695 | #define SQ_CMD__QUEUE_ID_MASK 0x7000000 | ||
| 14696 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 | ||
| 14697 | #define SQ_CMD__VM_ID_MASK 0xf0000000 | ||
| 14698 | #define SQ_CMD__VM_ID__SHIFT 0x1c | ||
| 14699 | #define SQ_IND_DATA__DATA_MASK 0xffffffff | ||
| 14700 | #define SQ_IND_DATA__DATA__SHIFT 0x0 | ||
| 14701 | #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff | ||
| 14702 | #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 | ||
| 14703 | #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff | ||
| 14704 | #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 | ||
| 14705 | #define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf | ||
| 14706 | #define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 | ||
| 14707 | #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 | ||
| 14708 | #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 | ||
| 14709 | #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff | ||
| 14710 | #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 | ||
| 14711 | #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff | ||
| 14712 | #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 | ||
| 14713 | #define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff | ||
| 14714 | #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 | ||
| 14715 | #define SQ_WAVE_PC_HI__PC_HI_MASK 0xffff | ||
| 14716 | #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 | ||
| 14717 | #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 | ||
| 14718 | #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 | ||
| 14719 | #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 | ||
| 14720 | #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 | ||
| 14721 | #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 | ||
| 14722 | #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 | ||
| 14723 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 | ||
| 14724 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 | ||
| 14725 | #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 | ||
| 14726 | #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 | ||
| 14727 | #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 | ||
| 14728 | #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa | ||
| 14729 | #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000 | ||
| 14730 | #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 | ||
| 14731 | #define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000 | ||
| 14732 | #define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14 | ||
| 14733 | #define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000 | ||
| 14734 | #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 | ||
| 14735 | #define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000 | ||
| 14736 | #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a | ||
| 14737 | #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000 | ||
| 14738 | #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b | ||
| 14739 | #define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000 | ||
| 14740 | #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d | ||
| 14741 | #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000 | ||
| 14742 | #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e | ||
| 14743 | #define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1 | ||
| 14744 | #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 | ||
| 14745 | #define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2 | ||
| 14746 | #define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 | ||
| 14747 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4 | ||
| 14748 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 | ||
| 14749 | #define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0 | ||
| 14750 | #define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 | ||
| 14751 | #define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00 | ||
| 14752 | #define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8 | ||
| 14753 | #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff | ||
| 14754 | #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 | ||
| 14755 | #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff | ||
| 14756 | #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 | ||
| 14757 | #define SQ_WAVE_STATUS__SCC_MASK 0x1 | ||
| 14758 | #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 | ||
| 14759 | #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 | ||
| 14760 | #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 | ||
| 14761 | #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18 | ||
| 14762 | #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 | ||
| 14763 | #define SQ_WAVE_STATUS__PRIV_MASK 0x20 | ||
| 14764 | #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 | ||
| 14765 | #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 | ||
| 14766 | #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 | ||
| 14767 | #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 | ||
| 14768 | #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 | ||
| 14769 | #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 | ||
| 14770 | #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 | ||
| 14771 | #define SQ_WAVE_STATUS__EXECZ_MASK 0x200 | ||
| 14772 | #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 | ||
| 14773 | #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 | ||
| 14774 | #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa | ||
| 14775 | #define SQ_WAVE_STATUS__IN_TG_MASK 0x800 | ||
| 14776 | #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb | ||
| 14777 | #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 | ||
| 14778 | #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc | ||
| 14779 | #define SQ_WAVE_STATUS__HALT_MASK 0x2000 | ||
| 14780 | #define SQ_WAVE_STATUS__HALT__SHIFT 0xd | ||
| 14781 | #define SQ_WAVE_STATUS__TRAP_MASK 0x4000 | ||
| 14782 | #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe | ||
| 14783 | #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 | ||
| 14784 | #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf | ||
| 14785 | #define SQ_WAVE_STATUS__VALID_MASK 0x10000 | ||
| 14786 | #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 | ||
| 14787 | #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 | ||
| 14788 | #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 | ||
| 14789 | #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 | ||
| 14790 | #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 | ||
| 14791 | #define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 | ||
| 14792 | #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 | ||
| 14793 | #define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 | ||
| 14794 | #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 | ||
| 14795 | #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 | ||
| 14796 | #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 | ||
| 14797 | #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000 | ||
| 14798 | #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 | ||
| 14799 | #define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 | ||
| 14800 | #define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 | ||
| 14801 | #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 | ||
| 14802 | #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b | ||
| 14803 | #define SQ_WAVE_MODE__FP_ROUND_MASK 0xf | ||
| 14804 | #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 | ||
| 14805 | #define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 | ||
| 14806 | #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 | ||
| 14807 | #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 | ||
| 14808 | #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 | ||
| 14809 | #define SQ_WAVE_MODE__IEEE_MASK 0x200 | ||
| 14810 | #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 | ||
| 14811 | #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 | ||
| 14812 | #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa | ||
| 14813 | #define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 | ||
| 14814 | #define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb | ||
| 14815 | #define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 | ||
| 14816 | #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc | ||
| 14817 | #define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000 | ||
| 14818 | #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b | ||
| 14819 | #define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 | ||
| 14820 | #define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c | ||
| 14821 | #define SQ_WAVE_MODE__CSP_MASK 0xe0000000 | ||
| 14822 | #define SQ_WAVE_MODE__CSP__SHIFT 0x1d | ||
| 14823 | #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff | ||
| 14824 | #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 | ||
| 14825 | #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400 | ||
| 14826 | #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa | ||
| 14827 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 | ||
| 14828 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 | ||
| 14829 | #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 | ||
| 14830 | #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d | ||
| 14831 | #define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf | ||
| 14832 | #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 | ||
| 14833 | #define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 | ||
| 14834 | #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 | ||
| 14835 | #define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 | ||
| 14836 | #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 | ||
| 14837 | #define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 | ||
| 14838 | #define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 | ||
| 14839 | #define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 | ||
| 14840 | #define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc | ||
| 14841 | #define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 | ||
| 14842 | #define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd | ||
| 14843 | #define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 | ||
| 14844 | #define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 | ||
| 14845 | #define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 | ||
| 14846 | #define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 | ||
| 14847 | #define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 | ||
| 14848 | #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 | ||
| 14849 | #define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 | ||
| 14850 | #define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b | ||
| 14851 | #define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 | ||
| 14852 | #define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e | ||
| 14853 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f | ||
| 14854 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 | ||
| 14855 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 | ||
| 14856 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 | ||
| 14857 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 | ||
| 14858 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 | ||
| 14859 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 | ||
| 14860 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 | ||
| 14861 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff | ||
| 14862 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 | ||
| 14863 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 | ||
| 14864 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc | ||
| 14865 | #define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf | ||
| 14866 | #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 | ||
| 14867 | #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 | ||
| 14868 | #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 | ||
| 14869 | #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 | ||
| 14870 | #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 | ||
| 14871 | #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 | ||
| 14872 | #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc | ||
| 14873 | #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000 | ||
| 14874 | #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf | ||
| 14875 | #define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000 | ||
| 14876 | #define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 | ||
| 14877 | #define SQ_WAVE_M0__M0_MASK 0xffffffff | ||
| 14878 | #define SQ_WAVE_M0__M0__SHIFT 0x0 | ||
| 14879 | #define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff | ||
| 14880 | #define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 | ||
| 14881 | #define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff | ||
| 14882 | #define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 | ||
| 14883 | #define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff | ||
| 14884 | #define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 | ||
| 14885 | #define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff | ||
| 14886 | #define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 | ||
| 14887 | #define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff | ||
| 14888 | #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 | ||
| 14889 | #define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff | ||
| 14890 | #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 | ||
| 14891 | #define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff | ||
| 14892 | #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 | ||
| 14893 | #define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff | ||
| 14894 | #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 | ||
| 14895 | #define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff | ||
| 14896 | #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 | ||
| 14897 | #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff | ||
| 14898 | #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 | ||
| 14899 | #define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff | ||
| 14900 | #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 | ||
| 14901 | #define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff | ||
| 14902 | #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 | ||
| 14903 | #define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff | ||
| 14904 | #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 | ||
| 14905 | #define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff | ||
| 14906 | #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 | ||
| 14907 | #define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff | ||
| 14908 | #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 | ||
| 14909 | #define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff | ||
| 14910 | #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 | ||
| 14911 | #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 | ||
| 14912 | #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 | ||
| 14913 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 | ||
| 14914 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 | ||
| 14915 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 | ||
| 14916 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 | ||
| 14917 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 | ||
| 14918 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 | ||
| 14919 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff | ||
| 14920 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 | ||
| 14921 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 | ||
| 14922 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 | ||
| 14923 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 | ||
| 14924 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 | ||
| 14925 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 | ||
| 14926 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 | ||
| 14927 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf | ||
| 14928 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 | ||
| 14929 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0 | ||
| 14930 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 | ||
| 14931 | #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 | ||
| 14932 | #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 | ||
| 14933 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 | ||
| 14934 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 | ||
| 14935 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff | ||
| 14936 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 | ||
| 14937 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff | ||
| 14938 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 | ||
| 14939 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 | ||
| 14940 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 | ||
| 14941 | #define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff | ||
| 14942 | #define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 | ||
| 14943 | #define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff | ||
| 14944 | #define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 | ||
| 14945 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3 | ||
| 14946 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 | ||
| 14947 | #define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4 | ||
| 14948 | #define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2 | ||
| 14949 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18 | ||
| 14950 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 | ||
| 14951 | #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0 | ||
| 14952 | #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5 | ||
| 14953 | #define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700 | ||
| 14954 | #define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8 | ||
| 14955 | #define SH_MEM_CONFIG__APE1_ATC_MASK 0x800 | ||
| 14956 | #define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb | ||
| 14957 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf | ||
| 14958 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 | ||
| 14959 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 | ||
| 14960 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 | ||
| 14961 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf | ||
| 14962 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 | ||
| 14963 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 | ||
| 14964 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 | ||
| 14965 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 | ||
| 14966 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 | ||
| 14967 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 | ||
| 14968 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 | ||
| 14969 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800 | ||
| 14970 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb | ||
| 14971 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 14972 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 14973 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 | ||
| 14974 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 | ||
| 14975 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 | ||
| 14976 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 | ||
| 14977 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 | ||
| 14978 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 | ||
| 14979 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 | ||
| 14980 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 | ||
| 14981 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff | ||
| 14982 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 | ||
| 14983 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 14984 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 14985 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 | ||
| 14986 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 | ||
| 14987 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 | ||
| 14988 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 | ||
| 14989 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 | ||
| 14990 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 | ||
| 14991 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 | ||
| 14992 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa | ||
| 14993 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 | ||
| 14994 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe | ||
| 14995 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 | ||
| 14996 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 | ||
| 14997 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff | ||
| 14998 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 | ||
| 14999 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 15000 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 15001 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 | ||
| 15002 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 | ||
| 15003 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff | ||
| 15004 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 | ||
| 15005 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf | ||
| 15006 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 | ||
| 15007 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 | ||
| 15008 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 | ||
| 15009 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 | ||
| 15010 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 | ||
| 15011 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 | ||
| 15012 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 | ||
| 15013 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 | ||
| 15014 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa | ||
| 15015 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 | ||
| 15016 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe | ||
| 15017 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf | ||
| 15018 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 | ||
| 15019 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 | ||
| 15020 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 | ||
| 15021 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 | ||
| 15022 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc | ||
| 15023 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 | ||
| 15024 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd | ||
| 15025 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf | ||
| 15026 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 | ||
| 15027 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 | ||
| 15028 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 | ||
| 15029 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 | ||
| 15030 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 | ||
| 15031 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 | ||
| 15032 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 | ||
| 15033 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 | ||
| 15034 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa | ||
| 15035 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 | ||
| 15036 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe | ||
| 15037 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 | ||
| 15038 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 | ||
| 15039 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 | ||
| 15040 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 | ||
| 15041 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 | ||
| 15042 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 | ||
| 15043 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 | ||
| 15044 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d | ||
| 15045 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 15046 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 15047 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 | ||
| 15048 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 | ||
| 15049 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 | ||
| 15050 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 | ||
| 15051 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 | ||
| 15052 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 | ||
| 15053 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 | ||
| 15054 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 | ||
| 15055 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 | ||
| 15056 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa | ||
| 15057 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 | ||
| 15058 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe | ||
| 15059 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 | ||
| 15060 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf | ||
| 15061 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 | ||
| 15062 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 | ||
| 15063 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff | ||
| 15064 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 | ||
| 15065 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 15066 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 15067 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 | ||
| 15068 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 | ||
| 15069 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 | ||
| 15070 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 | ||
| 15071 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 | ||
| 15072 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 | ||
| 15073 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 | ||
| 15074 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 | ||
| 15075 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 | ||
| 15076 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 | ||
| 15077 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff | ||
| 15078 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 | ||
| 15079 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf | ||
| 15080 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 | ||
| 15081 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 | ||
| 15082 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 | ||
| 15083 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 | ||
| 15084 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 | ||
| 15085 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 | ||
| 15086 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 | ||
| 15087 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 | ||
| 15088 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa | ||
| 15089 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf | ||
| 15090 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 | ||
| 15091 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 | ||
| 15092 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 | ||
| 15093 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 | ||
| 15094 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 | ||
| 15095 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 | ||
| 15096 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 | ||
| 15097 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 | ||
| 15098 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa | ||
| 15099 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 | ||
| 15100 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc | ||
| 15101 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 | ||
| 15102 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe | ||
| 15103 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 | ||
| 15104 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 | ||
| 15105 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 | ||
| 15106 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 | ||
| 15107 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 | ||
| 15108 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 | ||
| 15109 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 | ||
| 15110 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 | ||
| 15111 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 | ||
| 15112 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 | ||
| 15113 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 | ||
| 15114 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a | ||
| 15115 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf | ||
| 15116 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 | ||
| 15117 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 | ||
| 15118 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 | ||
| 15119 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 | ||
| 15120 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 | ||
| 15121 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 | ||
| 15122 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 | ||
| 15123 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 | ||
| 15124 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa | ||
| 15125 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 | ||
| 15126 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc | ||
| 15127 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 | ||
| 15128 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 | ||
| 15129 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f | ||
| 15130 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 | ||
| 15131 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 | ||
| 15132 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 | ||
| 15133 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 | ||
| 15134 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 | ||
| 15135 | #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff | ||
| 15136 | #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 | ||
| 15137 | #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff | ||
| 15138 | #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 | ||
| 15139 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000 | ||
| 15140 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a | ||
| 15141 | #define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000 | ||
| 15142 | #define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b | ||
| 15143 | #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000 | ||
| 15144 | #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c | ||
| 15145 | #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000 | ||
| 15146 | #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f | ||
| 15147 | #define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff | ||
| 15148 | #define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0 | ||
| 15149 | #define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000 | ||
| 15150 | #define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12 | ||
| 15151 | #define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000 | ||
| 15152 | #define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13 | ||
| 15153 | #define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000 | ||
| 15154 | #define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14 | ||
| 15155 | #define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000 | ||
| 15156 | #define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15 | ||
| 15157 | #define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000 | ||
| 15158 | #define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17 | ||
| 15159 | #define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000 | ||
| 15160 | #define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19 | ||
| 15161 | #define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000 | ||
| 15162 | #define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a | ||
| 15163 | #define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000 | ||
| 15164 | #define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b | ||
| 15165 | #define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 | ||
| 15166 | #define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c | ||
| 15167 | #define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 | ||
| 15168 | #define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e | ||
| 15169 | #define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff | ||
| 15170 | #define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0 | ||
| 15171 | #define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000 | ||
| 15172 | #define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10 | ||
| 15173 | #define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 | ||
| 15174 | #define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 | ||
| 15175 | #define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 | ||
| 15176 | #define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a | ||
| 15177 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 | ||
| 15178 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 | ||
| 15179 | #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 | ||
| 15180 | #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 | ||
| 15181 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 | ||
| 15182 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 | ||
| 15183 | #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 | ||
| 15184 | #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 | ||
| 15185 | #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 | ||
| 15186 | #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 | ||
| 15187 | #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 | ||
| 15188 | #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 | ||
| 15189 | #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 | ||
| 15190 | #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 | ||
| 15191 | #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 | ||
| 15192 | #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 | ||
| 15193 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 | ||
| 15194 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 | ||
| 15195 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 | ||
| 15196 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a | ||
| 15197 | #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff | ||
| 15198 | #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 | ||
| 15199 | #define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 | ||
| 15200 | #define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 | ||
| 15201 | #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 | ||
| 15202 | #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 | ||
| 15203 | #define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 | ||
| 15204 | #define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa | ||
| 15205 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 | ||
| 15206 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe | ||
| 15207 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 | ||
| 15208 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 | ||
| 15209 | #define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 | ||
| 15210 | #define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 | ||
| 15211 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 | ||
| 15212 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 | ||
| 15213 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 | ||
| 15214 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a | ||
| 15215 | #define SQ_SOP2__SSRC0_MASK 0xff | ||
| 15216 | #define SQ_SOP2__SSRC0__SHIFT 0x0 | ||
| 15217 | #define SQ_SOP2__SSRC1_MASK 0xff00 | ||
| 15218 | #define SQ_SOP2__SSRC1__SHIFT 0x8 | ||
| 15219 | #define SQ_SOP2__SDST_MASK 0x7f0000 | ||
| 15220 | #define SQ_SOP2__SDST__SHIFT 0x10 | ||
| 15221 | #define SQ_SOP2__OP_MASK 0x3f800000 | ||
| 15222 | #define SQ_SOP2__OP__SHIFT 0x17 | ||
| 15223 | #define SQ_SOP2__ENCODING_MASK 0xc0000000 | ||
| 15224 | #define SQ_SOP2__ENCODING__SHIFT 0x1e | ||
| 15225 | #define SQ_VOP1__SRC0_MASK 0x1ff | ||
| 15226 | #define SQ_VOP1__SRC0__SHIFT 0x0 | ||
| 15227 | #define SQ_VOP1__OP_MASK 0x1fe00 | ||
| 15228 | #define SQ_VOP1__OP__SHIFT 0x9 | ||
| 15229 | #define SQ_VOP1__VDST_MASK 0x1fe0000 | ||
| 15230 | #define SQ_VOP1__VDST__SHIFT 0x11 | ||
| 15231 | #define SQ_VOP1__ENCODING_MASK 0xfe000000 | ||
| 15232 | #define SQ_VOP1__ENCODING__SHIFT 0x19 | ||
| 15233 | #define SQ_MTBUF_1__VADDR_MASK 0xff | ||
| 15234 | #define SQ_MTBUF_1__VADDR__SHIFT 0x0 | ||
| 15235 | #define SQ_MTBUF_1__VDATA_MASK 0xff00 | ||
| 15236 | #define SQ_MTBUF_1__VDATA__SHIFT 0x8 | ||
| 15237 | #define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 | ||
| 15238 | #define SQ_MTBUF_1__SRSRC__SHIFT 0x10 | ||
| 15239 | #define SQ_MTBUF_1__SLC_MASK 0x400000 | ||
| 15240 | #define SQ_MTBUF_1__SLC__SHIFT 0x16 | ||
| 15241 | #define SQ_MTBUF_1__TFE_MASK 0x800000 | ||
| 15242 | #define SQ_MTBUF_1__TFE__SHIFT 0x17 | ||
| 15243 | #define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 | ||
| 15244 | #define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 | ||
| 15245 | #define SQ_EXP_1__VSRC0_MASK 0xff | ||
| 15246 | #define SQ_EXP_1__VSRC0__SHIFT 0x0 | ||
| 15247 | #define SQ_EXP_1__VSRC1_MASK 0xff00 | ||
| 15248 | #define SQ_EXP_1__VSRC1__SHIFT 0x8 | ||
| 15249 | #define SQ_EXP_1__VSRC2_MASK 0xff0000 | ||
| 15250 | #define SQ_EXP_1__VSRC2__SHIFT 0x10 | ||
| 15251 | #define SQ_EXP_1__VSRC3_MASK 0xff000000 | ||
| 15252 | #define SQ_EXP_1__VSRC3__SHIFT 0x18 | ||
| 15253 | #define SQ_MUBUF_1__VADDR_MASK 0xff | ||
| 15254 | #define SQ_MUBUF_1__VADDR__SHIFT 0x0 | ||
| 15255 | #define SQ_MUBUF_1__VDATA_MASK 0xff00 | ||
| 15256 | #define SQ_MUBUF_1__VDATA__SHIFT 0x8 | ||
| 15257 | #define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 | ||
| 15258 | #define SQ_MUBUF_1__SRSRC__SHIFT 0x10 | ||
| 15259 | #define SQ_MUBUF_1__TFE_MASK 0x800000 | ||
| 15260 | #define SQ_MUBUF_1__TFE__SHIFT 0x17 | ||
| 15261 | #define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 | ||
| 15262 | #define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 | ||
| 15263 | #define SQ_SMEM_1__OFFSET_MASK 0xfffff | ||
| 15264 | #define SQ_SMEM_1__OFFSET__SHIFT 0x0 | ||
| 15265 | #define SQ_INST__ENCODING_MASK 0xffffffff | ||
| 15266 | #define SQ_INST__ENCODING__SHIFT 0x0 | ||
| 15267 | #define SQ_EXP_0__EN_MASK 0xf | ||
| 15268 | #define SQ_EXP_0__EN__SHIFT 0x0 | ||
| 15269 | #define SQ_EXP_0__TGT_MASK 0x3f0 | ||
| 15270 | #define SQ_EXP_0__TGT__SHIFT 0x4 | ||
| 15271 | #define SQ_EXP_0__COMPR_MASK 0x400 | ||
| 15272 | #define SQ_EXP_0__COMPR__SHIFT 0xa | ||
| 15273 | #define SQ_EXP_0__DONE_MASK 0x800 | ||
| 15274 | #define SQ_EXP_0__DONE__SHIFT 0xb | ||
| 15275 | #define SQ_EXP_0__VM_MASK 0x1000 | ||
| 15276 | #define SQ_EXP_0__VM__SHIFT 0xc | ||
| 15277 | #define SQ_EXP_0__ENCODING_MASK 0xfc000000 | ||
| 15278 | #define SQ_EXP_0__ENCODING__SHIFT 0x1a | ||
| 15279 | #define SQ_MUBUF_0__OFFSET_MASK 0xfff | ||
| 15280 | #define SQ_MUBUF_0__OFFSET__SHIFT 0x0 | ||
| 15281 | #define SQ_MUBUF_0__OFFEN_MASK 0x1000 | ||
| 15282 | #define SQ_MUBUF_0__OFFEN__SHIFT 0xc | ||
| 15283 | #define SQ_MUBUF_0__IDXEN_MASK 0x2000 | ||
| 15284 | #define SQ_MUBUF_0__IDXEN__SHIFT 0xd | ||
| 15285 | #define SQ_MUBUF_0__GLC_MASK 0x4000 | ||
| 15286 | #define SQ_MUBUF_0__GLC__SHIFT 0xe | ||
| 15287 | #define SQ_MUBUF_0__LDS_MASK 0x10000 | ||
| 15288 | #define SQ_MUBUF_0__LDS__SHIFT 0x10 | ||
| 15289 | #define SQ_MUBUF_0__SLC_MASK 0x20000 | ||
| 15290 | #define SQ_MUBUF_0__SLC__SHIFT 0x11 | ||
| 15291 | #define SQ_MUBUF_0__OP_MASK 0x1fc0000 | ||
| 15292 | #define SQ_MUBUF_0__OP__SHIFT 0x12 | ||
| 15293 | #define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 | ||
| 15294 | #define SQ_MUBUF_0__ENCODING__SHIFT 0x1a | ||
| 15295 | #define SQ_VOP_SDWA__SRC0_MASK 0xff | ||
| 15296 | #define SQ_VOP_SDWA__SRC0__SHIFT 0x0 | ||
| 15297 | #define SQ_VOP_SDWA__DST_SEL_MASK 0x700 | ||
| 15298 | #define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 | ||
| 15299 | #define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800 | ||
| 15300 | #define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb | ||
| 15301 | #define SQ_VOP_SDWA__CLAMP_MASK 0x2000 | ||
| 15302 | #define SQ_VOP_SDWA__CLAMP__SHIFT 0xd | ||
| 15303 | #define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000 | ||
| 15304 | #define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 | ||
| 15305 | #define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000 | ||
| 15306 | #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 | ||
| 15307 | #define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000 | ||
| 15308 | #define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 | ||
| 15309 | #define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000 | ||
| 15310 | #define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 | ||
| 15311 | #define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000 | ||
| 15312 | #define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 | ||
| 15313 | #define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000 | ||
| 15314 | #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b | ||
| 15315 | #define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000 | ||
| 15316 | #define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c | ||
| 15317 | #define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000 | ||
| 15318 | #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d | ||
| 15319 | #define SQ_VOP3_0__VDST_MASK 0xff | ||
| 15320 | #define SQ_VOP3_0__VDST__SHIFT 0x0 | ||
| 15321 | #define SQ_VOP3_0__ABS_MASK 0x700 | ||
| 15322 | #define SQ_VOP3_0__ABS__SHIFT 0x8 | ||
| 15323 | #define SQ_VOP3_0__CLAMP_MASK 0x8000 | ||
| 15324 | #define SQ_VOP3_0__CLAMP__SHIFT 0xf | ||
| 15325 | #define SQ_VOP3_0__OP_MASK 0x3ff0000 | ||
| 15326 | #define SQ_VOP3_0__OP__SHIFT 0x10 | ||
| 15327 | #define SQ_VOP3_0__ENCODING_MASK 0xfc000000 | ||
| 15328 | #define SQ_VOP3_0__ENCODING__SHIFT 0x1a | ||
| 15329 | #define SQ_VOP2__SRC0_MASK 0x1ff | ||
| 15330 | #define SQ_VOP2__SRC0__SHIFT 0x0 | ||
| 15331 | #define SQ_VOP2__VSRC1_MASK 0x1fe00 | ||
| 15332 | #define SQ_VOP2__VSRC1__SHIFT 0x9 | ||
| 15333 | #define SQ_VOP2__VDST_MASK 0x1fe0000 | ||
| 15334 | #define SQ_VOP2__VDST__SHIFT 0x11 | ||
| 15335 | #define SQ_VOP2__OP_MASK 0x7e000000 | ||
| 15336 | #define SQ_VOP2__OP__SHIFT 0x19 | ||
| 15337 | #define SQ_VOP2__ENCODING_MASK 0x80000000 | ||
| 15338 | #define SQ_VOP2__ENCODING__SHIFT 0x1f | ||
| 15339 | #define SQ_MTBUF_0__OFFSET_MASK 0xfff | ||
| 15340 | #define SQ_MTBUF_0__OFFSET__SHIFT 0x0 | ||
| 15341 | #define SQ_MTBUF_0__OFFEN_MASK 0x1000 | ||
| 15342 | #define SQ_MTBUF_0__OFFEN__SHIFT 0xc | ||
| 15343 | #define SQ_MTBUF_0__IDXEN_MASK 0x2000 | ||
| 15344 | #define SQ_MTBUF_0__IDXEN__SHIFT 0xd | ||
| 15345 | #define SQ_MTBUF_0__GLC_MASK 0x4000 | ||
| 15346 | #define SQ_MTBUF_0__GLC__SHIFT 0xe | ||
| 15347 | #define SQ_MTBUF_0__OP_MASK 0x78000 | ||
| 15348 | #define SQ_MTBUF_0__OP__SHIFT 0xf | ||
| 15349 | #define SQ_MTBUF_0__DFMT_MASK 0x780000 | ||
| 15350 | #define SQ_MTBUF_0__DFMT__SHIFT 0x13 | ||
| 15351 | #define SQ_MTBUF_0__NFMT_MASK 0x3800000 | ||
| 15352 | #define SQ_MTBUF_0__NFMT__SHIFT 0x17 | ||
| 15353 | #define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 | ||
| 15354 | #define SQ_MTBUF_0__ENCODING__SHIFT 0x1a | ||
| 15355 | #define SQ_SOPP__SIMM16_MASK 0xffff | ||
| 15356 | #define SQ_SOPP__SIMM16__SHIFT 0x0 | ||
| 15357 | #define SQ_SOPP__OP_MASK 0x7f0000 | ||
| 15358 | #define SQ_SOPP__OP__SHIFT 0x10 | ||
| 15359 | #define SQ_SOPP__ENCODING_MASK 0xff800000 | ||
| 15360 | #define SQ_SOPP__ENCODING__SHIFT 0x17 | ||
| 15361 | #define SQ_FLAT_0__GLC_MASK 0x10000 | ||
| 15362 | #define SQ_FLAT_0__GLC__SHIFT 0x10 | ||
| 15363 | #define SQ_FLAT_0__SLC_MASK 0x20000 | ||
| 15364 | #define SQ_FLAT_0__SLC__SHIFT 0x11 | ||
| 15365 | #define SQ_FLAT_0__OP_MASK 0x1fc0000 | ||
| 15366 | #define SQ_FLAT_0__OP__SHIFT 0x12 | ||
| 15367 | #define SQ_FLAT_0__ENCODING_MASK 0xfc000000 | ||
| 15368 | #define SQ_FLAT_0__ENCODING__SHIFT 0x1a | ||
| 15369 | #define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff | ||
| 15370 | #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 | ||
| 15371 | #define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 | ||
| 15372 | #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 | ||
| 15373 | #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000 | ||
| 15374 | #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf | ||
| 15375 | #define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000 | ||
| 15376 | #define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 | ||
| 15377 | #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 | ||
| 15378 | #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a | ||
| 15379 | #define SQ_MIMG_1__VADDR_MASK 0xff | ||
| 15380 | #define SQ_MIMG_1__VADDR__SHIFT 0x0 | ||
| 15381 | #define SQ_MIMG_1__VDATA_MASK 0xff00 | ||
| 15382 | #define SQ_MIMG_1__VDATA__SHIFT 0x8 | ||
| 15383 | #define SQ_MIMG_1__SRSRC_MASK 0x1f0000 | ||
| 15384 | #define SQ_MIMG_1__SRSRC__SHIFT 0x10 | ||
| 15385 | #define SQ_MIMG_1__SSAMP_MASK 0x3e00000 | ||
| 15386 | #define SQ_MIMG_1__SSAMP__SHIFT 0x15 | ||
| 15387 | #define SQ_MIMG_1__D16_MASK 0x80000000 | ||
| 15388 | #define SQ_MIMG_1__D16__SHIFT 0x1f | ||
| 15389 | #define SQ_SOP1__SSRC0_MASK 0xff | ||
| 15390 | #define SQ_SOP1__SSRC0__SHIFT 0x0 | ||
| 15391 | #define SQ_SOP1__OP_MASK 0xff00 | ||
| 15392 | #define SQ_SOP1__OP__SHIFT 0x8 | ||
| 15393 | #define SQ_SOP1__SDST_MASK 0x7f0000 | ||
| 15394 | #define SQ_SOP1__SDST__SHIFT 0x10 | ||
| 15395 | #define SQ_SOP1__ENCODING_MASK 0xff800000 | ||
| 15396 | #define SQ_SOP1__ENCODING__SHIFT 0x17 | ||
| 15397 | #define SQ_SOPC__SSRC0_MASK 0xff | ||
| 15398 | #define SQ_SOPC__SSRC0__SHIFT 0x0 | ||
| 15399 | #define SQ_SOPC__SSRC1_MASK 0xff00 | ||
| 15400 | #define SQ_SOPC__SSRC1__SHIFT 0x8 | ||
| 15401 | #define SQ_SOPC__OP_MASK 0x7f0000 | ||
| 15402 | #define SQ_SOPC__OP__SHIFT 0x10 | ||
| 15403 | #define SQ_SOPC__ENCODING_MASK 0xff800000 | ||
| 15404 | #define SQ_SOPC__ENCODING__SHIFT 0x17 | ||
| 15405 | #define SQ_FLAT_1__ADDR_MASK 0xff | ||
| 15406 | #define SQ_FLAT_1__ADDR__SHIFT 0x0 | ||
| 15407 | #define SQ_FLAT_1__DATA_MASK 0xff00 | ||
| 15408 | #define SQ_FLAT_1__DATA__SHIFT 0x8 | ||
| 15409 | #define SQ_FLAT_1__TFE_MASK 0x800000 | ||
| 15410 | #define SQ_FLAT_1__TFE__SHIFT 0x17 | ||
| 15411 | #define SQ_FLAT_1__VDST_MASK 0xff000000 | ||
| 15412 | #define SQ_FLAT_1__VDST__SHIFT 0x18 | ||
| 15413 | #define SQ_DS_1__ADDR_MASK 0xff | ||
| 15414 | #define SQ_DS_1__ADDR__SHIFT 0x0 | ||
| 15415 | #define SQ_DS_1__DATA0_MASK 0xff00 | ||
| 15416 | #define SQ_DS_1__DATA0__SHIFT 0x8 | ||
| 15417 | #define SQ_DS_1__DATA1_MASK 0xff0000 | ||
| 15418 | #define SQ_DS_1__DATA1__SHIFT 0x10 | ||
| 15419 | #define SQ_DS_1__VDST_MASK 0xff000000 | ||
| 15420 | #define SQ_DS_1__VDST__SHIFT 0x18 | ||
| 15421 | #define SQ_VOP3_1__SRC0_MASK 0x1ff | ||
| 15422 | #define SQ_VOP3_1__SRC0__SHIFT 0x0 | ||
| 15423 | #define SQ_VOP3_1__SRC1_MASK 0x3fe00 | ||
| 15424 | #define SQ_VOP3_1__SRC1__SHIFT 0x9 | ||
| 15425 | #define SQ_VOP3_1__SRC2_MASK 0x7fc0000 | ||
| 15426 | #define SQ_VOP3_1__SRC2__SHIFT 0x12 | ||
| 15427 | #define SQ_VOP3_1__OMOD_MASK 0x18000000 | ||
| 15428 | #define SQ_VOP3_1__OMOD__SHIFT 0x1b | ||
| 15429 | #define SQ_VOP3_1__NEG_MASK 0xe0000000 | ||
| 15430 | #define SQ_VOP3_1__NEG__SHIFT 0x1d | ||
| 15431 | #define SQ_SMEM_0__SBASE_MASK 0x3f | ||
| 15432 | #define SQ_SMEM_0__SBASE__SHIFT 0x0 | ||
| 15433 | #define SQ_SMEM_0__SDATA_MASK 0x1fc0 | ||
| 15434 | #define SQ_SMEM_0__SDATA__SHIFT 0x6 | ||
| 15435 | #define SQ_SMEM_0__GLC_MASK 0x10000 | ||
| 15436 | #define SQ_SMEM_0__GLC__SHIFT 0x10 | ||
| 15437 | #define SQ_SMEM_0__IMM_MASK 0x20000 | ||
| 15438 | #define SQ_SMEM_0__IMM__SHIFT 0x11 | ||
| 15439 | #define SQ_SMEM_0__OP_MASK 0x3fc0000 | ||
| 15440 | #define SQ_SMEM_0__OP__SHIFT 0x12 | ||
| 15441 | #define SQ_SMEM_0__ENCODING_MASK 0xfc000000 | ||
| 15442 | #define SQ_SMEM_0__ENCODING__SHIFT 0x1a | ||
| 15443 | #define SQ_MIMG_0__DMASK_MASK 0xf00 | ||
| 15444 | #define SQ_MIMG_0__DMASK__SHIFT 0x8 | ||
| 15445 | #define SQ_MIMG_0__UNORM_MASK 0x1000 | ||
| 15446 | #define SQ_MIMG_0__UNORM__SHIFT 0xc | ||
| 15447 | #define SQ_MIMG_0__GLC_MASK 0x2000 | ||
| 15448 | #define SQ_MIMG_0__GLC__SHIFT 0xd | ||
| 15449 | #define SQ_MIMG_0__DA_MASK 0x4000 | ||
| 15450 | #define SQ_MIMG_0__DA__SHIFT 0xe | ||
| 15451 | #define SQ_MIMG_0__R128_MASK 0x8000 | ||
| 15452 | #define SQ_MIMG_0__R128__SHIFT 0xf | ||
| 15453 | #define SQ_MIMG_0__TFE_MASK 0x10000 | ||
| 15454 | #define SQ_MIMG_0__TFE__SHIFT 0x10 | ||
| 15455 | #define SQ_MIMG_0__LWE_MASK 0x20000 | ||
| 15456 | #define SQ_MIMG_0__LWE__SHIFT 0x11 | ||
| 15457 | #define SQ_MIMG_0__OP_MASK 0x1fc0000 | ||
| 15458 | #define SQ_MIMG_0__OP__SHIFT 0x12 | ||
| 15459 | #define SQ_MIMG_0__SLC_MASK 0x2000000 | ||
| 15460 | #define SQ_MIMG_0__SLC__SHIFT 0x19 | ||
| 15461 | #define SQ_MIMG_0__ENCODING_MASK 0xfc000000 | ||
| 15462 | #define SQ_MIMG_0__ENCODING__SHIFT 0x1a | ||
| 15463 | #define SQ_SOPK__SIMM16_MASK 0xffff | ||
| 15464 | #define SQ_SOPK__SIMM16__SHIFT 0x0 | ||
| 15465 | #define SQ_SOPK__SDST_MASK 0x7f0000 | ||
| 15466 | #define SQ_SOPK__SDST__SHIFT 0x10 | ||
| 15467 | #define SQ_SOPK__OP_MASK 0xf800000 | ||
| 15468 | #define SQ_SOPK__OP__SHIFT 0x17 | ||
| 15469 | #define SQ_SOPK__ENCODING_MASK 0xf0000000 | ||
| 15470 | #define SQ_SOPK__ENCODING__SHIFT 0x1c | ||
| 15471 | #define SQ_DS_0__OFFSET0_MASK 0xff | ||
| 15472 | #define SQ_DS_0__OFFSET0__SHIFT 0x0 | ||
| 15473 | #define SQ_DS_0__OFFSET1_MASK 0xff00 | ||
| 15474 | #define SQ_DS_0__OFFSET1__SHIFT 0x8 | ||
| 15475 | #define SQ_DS_0__GDS_MASK 0x10000 | ||
| 15476 | #define SQ_DS_0__GDS__SHIFT 0x10 | ||
| 15477 | #define SQ_DS_0__OP_MASK 0x1fe0000 | ||
| 15478 | #define SQ_DS_0__OP__SHIFT 0x11 | ||
| 15479 | #define SQ_DS_0__ENCODING_MASK 0xfc000000 | ||
| 15480 | #define SQ_DS_0__ENCODING__SHIFT 0x1a | ||
| 15481 | #define SQ_VOP_DPP__SRC0_MASK 0xff | ||
| 15482 | #define SQ_VOP_DPP__SRC0__SHIFT 0x0 | ||
| 15483 | #define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00 | ||
| 15484 | #define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 | ||
| 15485 | #define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000 | ||
| 15486 | #define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 | ||
| 15487 | #define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000 | ||
| 15488 | #define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 | ||
| 15489 | #define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000 | ||
| 15490 | #define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 | ||
| 15491 | #define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000 | ||
| 15492 | #define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 | ||
| 15493 | #define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000 | ||
| 15494 | #define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 | ||
| 15495 | #define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000 | ||
| 15496 | #define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 | ||
| 15497 | #define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000 | ||
| 15498 | #define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c | ||
| 15499 | #define SQ_VOPC__SRC0_MASK 0x1ff | ||
| 15500 | #define SQ_VOPC__SRC0__SHIFT 0x0 | ||
| 15501 | #define SQ_VOPC__VSRC1_MASK 0x1fe00 | ||
| 15502 | #define SQ_VOPC__VSRC1__SHIFT 0x9 | ||
| 15503 | #define SQ_VOPC__OP_MASK 0x1fe0000 | ||
| 15504 | #define SQ_VOPC__OP__SHIFT 0x11 | ||
| 15505 | #define SQ_VOPC__ENCODING_MASK 0xfe000000 | ||
| 15506 | #define SQ_VOPC__ENCODING__SHIFT 0x19 | ||
| 15507 | #define SQ_VINTRP__VSRC_MASK 0xff | ||
| 15508 | #define SQ_VINTRP__VSRC__SHIFT 0x0 | ||
| 15509 | #define SQ_VINTRP__ATTRCHAN_MASK 0x300 | ||
| 15510 | #define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 | ||
| 15511 | #define SQ_VINTRP__ATTR_MASK 0xfc00 | ||
| 15512 | #define SQ_VINTRP__ATTR__SHIFT 0xa | ||
| 15513 | #define SQ_VINTRP__OP_MASK 0x30000 | ||
| 15514 | #define SQ_VINTRP__OP__SHIFT 0x10 | ||
| 15515 | #define SQ_VINTRP__VDST_MASK 0x3fc0000 | ||
| 15516 | #define SQ_VINTRP__VDST__SHIFT 0x12 | ||
| 15517 | #define SQ_VINTRP__ENCODING_MASK 0xfc000000 | ||
| 15518 | #define SQ_VINTRP__ENCODING__SHIFT 0x1a | ||
| 15519 | #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf | ||
| 15520 | #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 | ||
| 15521 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 | ||
| 15522 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 15523 | #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 | ||
| 15524 | #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc | ||
| 15525 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 15526 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 15527 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 15528 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 15529 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 15530 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 15531 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 15532 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 15533 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 15534 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 15535 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 15536 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 15537 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 15538 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 15539 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 15540 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 15541 | #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf | ||
| 15542 | #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 | ||
| 15543 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 | ||
| 15544 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 15545 | #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 | ||
| 15546 | #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc | ||
| 15547 | #define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x1000000 | ||
| 15548 | #define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18 | ||
| 15549 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 15550 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 15551 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 15552 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 15553 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 15554 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 15555 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 15556 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 15557 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 15558 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 15559 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 15560 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 15561 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 15562 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 15563 | #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf | ||
| 15564 | #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 | ||
| 15565 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 | ||
| 15566 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 15567 | #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 | ||
| 15568 | #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc | ||
| 15569 | #define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x1000000 | ||
| 15570 | #define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18 | ||
| 15571 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 15572 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 15573 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 15574 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 15575 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 15576 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 15577 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 15578 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 15579 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 15580 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 15581 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 15582 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 15583 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 15584 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 15585 | #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf | ||
| 15586 | #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 | ||
| 15587 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 | ||
| 15588 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 15589 | #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 | ||
| 15590 | #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc | ||
| 15591 | #define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x1000000 | ||
| 15592 | #define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18 | ||
| 15593 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 15594 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 15595 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 15596 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 15597 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 15598 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 15599 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 15600 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 15601 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 15602 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 15603 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 15604 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 15605 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 15606 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 15607 | #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf | ||
| 15608 | #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 | ||
| 15609 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 | ||
| 15610 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 15611 | #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 | ||
| 15612 | #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc | ||
| 15613 | #define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x1000000 | ||
| 15614 | #define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18 | ||
| 15615 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 15616 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 15617 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 15618 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 15619 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 15620 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 15621 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 15622 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 15623 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 15624 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 15625 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 15626 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 15627 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 15628 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 15629 | #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 | ||
| 15630 | #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 | ||
| 15631 | #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 | ||
| 15632 | #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 | ||
| 15633 | #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 | ||
| 15634 | #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 | ||
| 15635 | #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 | ||
| 15636 | #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 | ||
| 15637 | #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 | ||
| 15638 | #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 | ||
| 15639 | #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 | ||
| 15640 | #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 | ||
| 15641 | #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 | ||
| 15642 | #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 | ||
| 15643 | #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 | ||
| 15644 | #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 | ||
| 15645 | #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 | ||
| 15646 | #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 | ||
| 15647 | #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 | ||
| 15648 | #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 | ||
| 15649 | #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 | ||
| 15650 | #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa | ||
| 15651 | #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 | ||
| 15652 | #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb | ||
| 15653 | #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 | ||
| 15654 | #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc | ||
| 15655 | #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 | ||
| 15656 | #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd | ||
| 15657 | #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 | ||
| 15658 | #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe | ||
| 15659 | #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 | ||
| 15660 | #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf | ||
| 15661 | #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 | ||
| 15662 | #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 | ||
| 15663 | #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 | ||
| 15664 | #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 | ||
| 15665 | #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 | ||
| 15666 | #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 | ||
| 15667 | #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 | ||
| 15668 | #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 | ||
| 15669 | #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 | ||
| 15670 | #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 | ||
| 15671 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 | ||
| 15672 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 | ||
| 15673 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 | ||
| 15674 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 | ||
| 15675 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 | ||
| 15676 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 | ||
| 15677 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 | ||
| 15678 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 | ||
| 15679 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 | ||
| 15680 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 | ||
| 15681 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 | ||
| 15682 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a | ||
| 15683 | #define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 | ||
| 15684 | #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b | ||
| 15685 | #define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 | ||
| 15686 | #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c | ||
| 15687 | #define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 | ||
| 15688 | #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d | ||
| 15689 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 | ||
| 15690 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e | ||
| 15691 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 | ||
| 15692 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f | ||
| 15693 | #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 | ||
| 15694 | #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 | ||
| 15695 | #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 | ||
| 15696 | #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 | ||
| 15697 | #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 | ||
| 15698 | #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 | ||
| 15699 | #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 | ||
| 15700 | #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 | ||
| 15701 | #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 | ||
| 15702 | #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 | ||
| 15703 | #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 | ||
| 15704 | #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 | ||
| 15705 | #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 | ||
| 15706 | #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 | ||
| 15707 | #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 | ||
| 15708 | #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 | ||
| 15709 | #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 | ||
| 15710 | #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 | ||
| 15711 | #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 | ||
| 15712 | #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 | ||
| 15713 | #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 | ||
| 15714 | #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa | ||
| 15715 | #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 | ||
| 15716 | #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb | ||
| 15717 | #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 | ||
| 15718 | #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc | ||
| 15719 | #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 | ||
| 15720 | #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd | ||
| 15721 | #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 | ||
| 15722 | #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe | ||
| 15723 | #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 | ||
| 15724 | #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf | ||
| 15725 | #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 | ||
| 15726 | #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 | ||
| 15727 | #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 | ||
| 15728 | #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 | ||
| 15729 | #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 | ||
| 15730 | #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 | ||
| 15731 | #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 | ||
| 15732 | #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 | ||
| 15733 | #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 | ||
| 15734 | #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 | ||
| 15735 | #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 | ||
| 15736 | #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 | ||
| 15737 | #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 | ||
| 15738 | #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 | ||
| 15739 | #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 | ||
| 15740 | #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 | ||
| 15741 | #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 | ||
| 15742 | #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 | ||
| 15743 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 | ||
| 15744 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 | ||
| 15745 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 | ||
| 15746 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a | ||
| 15747 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 | ||
| 15748 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b | ||
| 15749 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 | ||
| 15750 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c | ||
| 15751 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 | ||
| 15752 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d | ||
| 15753 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 | ||
| 15754 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e | ||
| 15755 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 | ||
| 15756 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f | ||
| 15757 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 | ||
| 15758 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 | ||
| 15759 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 | ||
| 15760 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 | ||
| 15761 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 | ||
| 15762 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 | ||
| 15763 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 | ||
| 15764 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 | ||
| 15765 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 | ||
| 15766 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 | ||
| 15767 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 | ||
| 15768 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 | ||
| 15769 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 | ||
| 15770 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 | ||
| 15771 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 | ||
| 15772 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 | ||
| 15773 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 | ||
| 15774 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 | ||
| 15775 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 | ||
| 15776 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 | ||
| 15777 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 | ||
| 15778 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa | ||
| 15779 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 | ||
| 15780 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb | ||
| 15781 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 | ||
| 15782 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc | ||
| 15783 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 | ||
| 15784 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd | ||
| 15785 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 | ||
| 15786 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe | ||
| 15787 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 | ||
| 15788 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf | ||
| 15789 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 | ||
| 15790 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 | ||
| 15791 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 | ||
| 15792 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 | ||
| 15793 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 | ||
| 15794 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 | ||
| 15795 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 | ||
| 15796 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 | ||
| 15797 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 | ||
| 15798 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 | ||
| 15799 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 | ||
| 15800 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 | ||
| 15801 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 | ||
| 15802 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 | ||
| 15803 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 | ||
| 15804 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 | ||
| 15805 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 | ||
| 15806 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 | ||
| 15807 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 | ||
| 15808 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 | ||
| 15809 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 | ||
| 15810 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a | ||
| 15811 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 | ||
| 15812 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b | ||
| 15813 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 | ||
| 15814 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c | ||
| 15815 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 | ||
| 15816 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d | ||
| 15817 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 | ||
| 15818 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e | ||
| 15819 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 | ||
| 15820 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f | ||
| 15821 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 | ||
| 15822 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 | ||
| 15823 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 | ||
| 15824 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 | ||
| 15825 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 | ||
| 15826 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 | ||
| 15827 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 | ||
| 15828 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 | ||
| 15829 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 | ||
| 15830 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 | ||
| 15831 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 | ||
| 15832 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 | ||
| 15833 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 | ||
| 15834 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 | ||
| 15835 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 | ||
| 15836 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 | ||
| 15837 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 | ||
| 15838 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 | ||
| 15839 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 | ||
| 15840 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 | ||
| 15841 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 | ||
| 15842 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa | ||
| 15843 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 | ||
| 15844 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb | ||
| 15845 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 | ||
| 15846 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc | ||
| 15847 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 | ||
| 15848 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd | ||
| 15849 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 | ||
| 15850 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe | ||
| 15851 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 | ||
| 15852 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf | ||
| 15853 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 | ||
| 15854 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 | ||
| 15855 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 | ||
| 15856 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 | ||
| 15857 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 | ||
| 15858 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 | ||
| 15859 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 | ||
| 15860 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 | ||
| 15861 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 | ||
| 15862 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 | ||
| 15863 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 | ||
| 15864 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 | ||
| 15865 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 | ||
| 15866 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 | ||
| 15867 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 | ||
| 15868 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 | ||
| 15869 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 | ||
| 15870 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 | ||
| 15871 | #define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 | ||
| 15872 | #define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 | ||
| 15873 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f | ||
| 15874 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 | ||
| 15875 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x100 | ||
| 15876 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 | ||
| 15877 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x200 | ||
| 15878 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 | ||
| 15879 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x400 | ||
| 15880 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa | ||
| 15881 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x800 | ||
| 15882 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb | ||
| 15883 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x1000 | ||
| 15884 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc | ||
| 15885 | #define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffe000 | ||
| 15886 | #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xd | ||
| 15887 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 15888 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 15889 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 15890 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 15891 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 15892 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 15893 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 15894 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 15895 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 15896 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 15897 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 15898 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 15899 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 15900 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 15901 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 15902 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 15903 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 15904 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 15905 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 15906 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 15907 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 15908 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 15909 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 15910 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 15911 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff | ||
| 15912 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 | ||
| 15913 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 | ||
| 15914 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa | ||
| 15915 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff | ||
| 15916 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 | ||
| 15917 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 | ||
| 15918 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa | ||
| 15919 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 15920 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 15921 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 15922 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 15923 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 15924 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 15925 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 15926 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 15927 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 15928 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 15929 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 15930 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 15931 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 15932 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 15933 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 15934 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 15935 | #define SX_PS_DOWNCONVERT__MRT0_MASK 0xf | ||
| 15936 | #define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 | ||
| 15937 | #define SX_PS_DOWNCONVERT__MRT1_MASK 0xf0 | ||
| 15938 | #define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 | ||
| 15939 | #define SX_PS_DOWNCONVERT__MRT2_MASK 0xf00 | ||
| 15940 | #define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 | ||
| 15941 | #define SX_PS_DOWNCONVERT__MRT3_MASK 0xf000 | ||
| 15942 | #define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc | ||
| 15943 | #define SX_PS_DOWNCONVERT__MRT4_MASK 0xf0000 | ||
| 15944 | #define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 | ||
| 15945 | #define SX_PS_DOWNCONVERT__MRT5_MASK 0xf00000 | ||
| 15946 | #define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 | ||
| 15947 | #define SX_PS_DOWNCONVERT__MRT6_MASK 0xf000000 | ||
| 15948 | #define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 | ||
| 15949 | #define SX_PS_DOWNCONVERT__MRT7_MASK 0xf0000000 | ||
| 15950 | #define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c | ||
| 15951 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0xf | ||
| 15952 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 | ||
| 15953 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0xf0 | ||
| 15954 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 | ||
| 15955 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0xf00 | ||
| 15956 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 | ||
| 15957 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0xf000 | ||
| 15958 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc | ||
| 15959 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0xf0000 | ||
| 15960 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 | ||
| 15961 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0xf00000 | ||
| 15962 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 | ||
| 15963 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0xf000000 | ||
| 15964 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 | ||
| 15965 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xf0000000 | ||
| 15966 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c | ||
| 15967 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x1 | ||
| 15968 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 | ||
| 15969 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x2 | ||
| 15970 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 | ||
| 15971 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x10 | ||
| 15972 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 | ||
| 15973 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x20 | ||
| 15974 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 | ||
| 15975 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x100 | ||
| 15976 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 | ||
| 15977 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x200 | ||
| 15978 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 | ||
| 15979 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x1000 | ||
| 15980 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc | ||
| 15981 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x2000 | ||
| 15982 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd | ||
| 15983 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x10000 | ||
| 15984 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 | ||
| 15985 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x20000 | ||
| 15986 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 | ||
| 15987 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x100000 | ||
| 15988 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 | ||
| 15989 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x200000 | ||
| 15990 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 | ||
| 15991 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x1000000 | ||
| 15992 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 | ||
| 15993 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x2000000 | ||
| 15994 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 | ||
| 15995 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000 | ||
| 15996 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c | ||
| 15997 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000 | ||
| 15998 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d | ||
| 15999 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000 | ||
| 16000 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f | ||
| 16001 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16002 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16003 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16004 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16005 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16006 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16007 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16008 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16009 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16010 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16011 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16012 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16013 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16014 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16015 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16016 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16017 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16018 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16019 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16020 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16021 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16022 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16023 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16024 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16025 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16026 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16027 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16028 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16029 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16030 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16031 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16032 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16033 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16034 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16035 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16036 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16037 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16038 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16039 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16040 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16041 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16042 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16043 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16044 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16045 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16046 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16047 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16048 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16049 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16050 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16051 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16052 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16053 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16054 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16055 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16056 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16057 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16058 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16059 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16060 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16061 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16062 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16063 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16064 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16065 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16066 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16067 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16068 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16069 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16070 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16071 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16072 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16073 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16074 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16075 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16076 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16077 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16078 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16079 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16080 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16081 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16082 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16083 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16084 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16085 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 | ||
| 16086 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 | ||
| 16087 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 | ||
| 16088 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 | ||
| 16089 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 | ||
| 16090 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 | ||
| 16091 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 | ||
| 16092 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 | ||
| 16093 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 | ||
| 16094 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 | ||
| 16095 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 | ||
| 16096 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 | ||
| 16097 | #define TCC_CTRL__CACHE_SIZE_MASK 0x3 | ||
| 16098 | #define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 | ||
| 16099 | #define TCC_CTRL__RATE_MASK 0xc | ||
| 16100 | #define TCC_CTRL__RATE__SHIFT 0x2 | ||
| 16101 | #define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 | ||
| 16102 | #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 | ||
| 16103 | #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 | ||
| 16104 | #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 | ||
| 16105 | #define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 | ||
| 16106 | #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc | ||
| 16107 | #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 | ||
| 16108 | #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 | ||
| 16109 | #define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 | ||
| 16110 | #define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 | ||
| 16111 | #define TCC_CTRL__MDC_SIZE_MASK 0x3000000 | ||
| 16112 | #define TCC_CTRL__MDC_SIZE__SHIFT 0x18 | ||
| 16113 | #define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000 | ||
| 16114 | #define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a | ||
| 16115 | #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000 | ||
| 16116 | #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c | ||
| 16117 | #define TCC_EDC_CNT__SEC_COUNT_MASK 0xff | ||
| 16118 | #define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0 | ||
| 16119 | #define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000 | ||
| 16120 | #define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10 | ||
| 16121 | #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 | ||
| 16122 | #define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 | ||
| 16123 | #define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 | ||
| 16124 | #define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 | ||
| 16125 | #define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2 | ||
| 16126 | #define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 | ||
| 16127 | #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 | ||
| 16128 | #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 | ||
| 16129 | #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 | ||
| 16130 | #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 | ||
| 16131 | #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf | ||
| 16132 | #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 16133 | #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 16134 | #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 16135 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 16136 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 16137 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 16138 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 16139 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 16140 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 16141 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 16142 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 16143 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 16144 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 16145 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 16146 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 16147 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 16148 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 16149 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 16150 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 16151 | #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf | ||
| 16152 | #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 16153 | #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 16154 | #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 16155 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 16156 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 16157 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 16158 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 16159 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 16160 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 16161 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 16162 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 16163 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 16164 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 16165 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 16166 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 16167 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 16168 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 16169 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 16170 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 16171 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16172 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16173 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16174 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16175 | #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16176 | #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16177 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16178 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16179 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16180 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16181 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16182 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16183 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16184 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16185 | #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16186 | #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16187 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16188 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16189 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16190 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16191 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16192 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16193 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16194 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16195 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 | ||
| 16196 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 | ||
| 16197 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 | ||
| 16198 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c | ||
| 16199 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16200 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16201 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16202 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16203 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 | ||
| 16204 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 | ||
| 16205 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 | ||
| 16206 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c | ||
| 16207 | #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16208 | #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16209 | #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16210 | #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16211 | #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16212 | #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16213 | #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16214 | #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16215 | #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16216 | #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16217 | #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16218 | #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16219 | #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16220 | #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16221 | #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16222 | #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16223 | #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16224 | #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16225 | #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16226 | #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16227 | #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16228 | #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16229 | #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16230 | #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16231 | #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16232 | #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16233 | #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16234 | #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16235 | #define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf | ||
| 16236 | #define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 | ||
| 16237 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16238 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16239 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16240 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16241 | #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16242 | #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16243 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16244 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16245 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16246 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16247 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16248 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16249 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16250 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16251 | #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16252 | #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16253 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16254 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16255 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16256 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16257 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16258 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16259 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16260 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16261 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 | ||
| 16262 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 | ||
| 16263 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 | ||
| 16264 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c | ||
| 16265 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16266 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16267 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16268 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16269 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 | ||
| 16270 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 | ||
| 16271 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 | ||
| 16272 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c | ||
| 16273 | #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16274 | #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16275 | #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16276 | #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16277 | #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16278 | #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16279 | #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16280 | #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16281 | #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16282 | #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16283 | #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16284 | #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16285 | #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16286 | #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16287 | #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16288 | #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16289 | #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16290 | #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16291 | #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16292 | #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16293 | #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16294 | #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16295 | #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16296 | #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16297 | #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16298 | #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16299 | #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16300 | #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16301 | #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff | ||
| 16302 | #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 | ||
| 16303 | #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff | ||
| 16304 | #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 | ||
| 16305 | #define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 | ||
| 16306 | #define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 | ||
| 16307 | #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 | ||
| 16308 | #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 | ||
| 16309 | #define TD_CNTL__PAD_STALL_EN_MASK 0x100 | ||
| 16310 | #define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 | ||
| 16311 | #define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 | ||
| 16312 | #define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 | ||
| 16313 | #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 | ||
| 16314 | #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb | ||
| 16315 | #define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 | ||
| 16316 | #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf | ||
| 16317 | #define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 | ||
| 16318 | #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 | ||
| 16319 | #define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 | ||
| 16320 | #define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 | ||
| 16321 | #define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 | ||
| 16322 | #define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 | ||
| 16323 | #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 | ||
| 16324 | #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 | ||
| 16325 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000 | ||
| 16326 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 | ||
| 16327 | #define TD_CNTL__DISABLE_D16_PACKING_MASK 0x400000 | ||
| 16328 | #define TD_CNTL__DISABLE_D16_PACKING__SHIFT 0x16 | ||
| 16329 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x800000 | ||
| 16330 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 | ||
| 16331 | #define TD_STATUS__BUSY_MASK 0x80000000 | ||
| 16332 | #define TD_STATUS__BUSY__SHIFT 0x1f | ||
| 16333 | #define TD_DEBUG_INDEX__INDEX_MASK 0x1f | ||
| 16334 | #define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 | ||
| 16335 | #define TD_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 16336 | #define TD_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 16337 | #define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1 | ||
| 16338 | #define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0 | ||
| 16339 | #define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2 | ||
| 16340 | #define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1 | ||
| 16341 | #define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4 | ||
| 16342 | #define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2 | ||
| 16343 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff | ||
| 16344 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16345 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 | ||
| 16346 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16347 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16348 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16349 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16350 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16351 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16352 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16353 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff | ||
| 16354 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16355 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 | ||
| 16356 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16357 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16358 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16359 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16360 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16361 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16362 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16363 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff | ||
| 16364 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16365 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 | ||
| 16366 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16367 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 16368 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 16369 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 16370 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 16371 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16372 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16373 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16374 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16375 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16376 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16377 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16378 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16379 | #define TD_SCRATCH__SCRATCH_MASK 0xffffffff | ||
| 16380 | #define TD_SCRATCH__SCRATCH__SHIFT 0x0 | ||
| 16381 | #define TA_CNTL__FX_XNACK_CREDIT_MASK 0x7f | ||
| 16382 | #define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 | ||
| 16383 | #define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x1e00 | ||
| 16384 | #define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 | ||
| 16385 | #define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 | ||
| 16386 | #define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd | ||
| 16387 | #define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 | ||
| 16388 | #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 | ||
| 16389 | #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 | ||
| 16390 | #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 | ||
| 16391 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 | ||
| 16392 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 | ||
| 16393 | #define TA_CNTL_AUX__RESERVED_MASK 0xe | ||
| 16394 | #define TA_CNTL_AUX__RESERVED__SHIFT 0x1 | ||
| 16395 | #define TA_CNTL_AUX__D16_PACK_DISABLE_MASK 0x10 | ||
| 16396 | #define TA_CNTL_AUX__D16_PACK_DISABLE__SHIFT 0x4 | ||
| 16397 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 | ||
| 16398 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 | ||
| 16399 | #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000 | ||
| 16400 | #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 | ||
| 16401 | #define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000 | ||
| 16402 | #define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 | ||
| 16403 | #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000 | ||
| 16404 | #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 | ||
| 16405 | #define TA_RESERVED_010C__Unused_MASK 0xffffffff | ||
| 16406 | #define TA_RESERVED_010C__Unused__SHIFT 0x0 | ||
| 16407 | #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff | ||
| 16408 | #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 | ||
| 16409 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff | ||
| 16410 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 | ||
| 16411 | #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 | ||
| 16412 | #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc | ||
| 16413 | #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 | ||
| 16414 | #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd | ||
| 16415 | #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 | ||
| 16416 | #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe | ||
| 16417 | #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 | ||
| 16418 | #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 | ||
| 16419 | #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 | ||
| 16420 | #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 | ||
| 16421 | #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 | ||
| 16422 | #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 | ||
| 16423 | #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 | ||
| 16424 | #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 | ||
| 16425 | #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 | ||
| 16426 | #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 | ||
| 16427 | #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 | ||
| 16428 | #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 | ||
| 16429 | #define TA_STATUS__IN_BUSY_MASK 0x1000000 | ||
| 16430 | #define TA_STATUS__IN_BUSY__SHIFT 0x18 | ||
| 16431 | #define TA_STATUS__FG_BUSY_MASK 0x2000000 | ||
| 16432 | #define TA_STATUS__FG_BUSY__SHIFT 0x19 | ||
| 16433 | #define TA_STATUS__LA_BUSY_MASK 0x4000000 | ||
| 16434 | #define TA_STATUS__LA_BUSY__SHIFT 0x1a | ||
| 16435 | #define TA_STATUS__FL_BUSY_MASK 0x8000000 | ||
| 16436 | #define TA_STATUS__FL_BUSY__SHIFT 0x1b | ||
| 16437 | #define TA_STATUS__TA_BUSY_MASK 0x10000000 | ||
| 16438 | #define TA_STATUS__TA_BUSY__SHIFT 0x1c | ||
| 16439 | #define TA_STATUS__FA_BUSY_MASK 0x20000000 | ||
| 16440 | #define TA_STATUS__FA_BUSY__SHIFT 0x1d | ||
| 16441 | #define TA_STATUS__AL_BUSY_MASK 0x40000000 | ||
| 16442 | #define TA_STATUS__AL_BUSY__SHIFT 0x1e | ||
| 16443 | #define TA_STATUS__BUSY_MASK 0x80000000 | ||
| 16444 | #define TA_STATUS__BUSY__SHIFT 0x1f | ||
| 16445 | #define TA_DEBUG_INDEX__INDEX_MASK 0x1f | ||
| 16446 | #define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 | ||
| 16447 | #define TA_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 16448 | #define TA_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 16449 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff | ||
| 16450 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16451 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 | ||
| 16452 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16453 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16454 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16455 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16456 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16457 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16458 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16459 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff | ||
| 16460 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16461 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 | ||
| 16462 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16463 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16464 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16465 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16466 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16467 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16468 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16469 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff | ||
| 16470 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16471 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 | ||
| 16472 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16473 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 16474 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 16475 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 16476 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 16477 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16478 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16479 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16480 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16481 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16482 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16483 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16484 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16485 | #define TA_SCRATCH__SCRATCH_MASK 0xffffffff | ||
| 16486 | #define TA_SCRATCH__SCRATCH__SHIFT 0x0 | ||
| 16487 | #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff | ||
| 16488 | #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 | ||
| 16489 | #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 | ||
| 16490 | #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 | ||
| 16491 | #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 | ||
| 16492 | #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 | ||
| 16493 | #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 | ||
| 16494 | #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 | ||
| 16495 | #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 | ||
| 16496 | #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 | ||
| 16497 | #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 | ||
| 16498 | #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 | ||
| 16499 | #define TCP_INVALIDATE__START_MASK 0x1 | ||
| 16500 | #define TCP_INVALIDATE__START__SHIFT 0x0 | ||
| 16501 | #define TCP_STATUS__TCP_BUSY_MASK 0x1 | ||
| 16502 | #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 | ||
| 16503 | #define TCP_STATUS__INPUT_BUSY_MASK 0x2 | ||
| 16504 | #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 | ||
| 16505 | #define TCP_STATUS__ADRS_BUSY_MASK 0x4 | ||
| 16506 | #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 | ||
| 16507 | #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8 | ||
| 16508 | #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 | ||
| 16509 | #define TCP_STATUS__CNTRL_BUSY_MASK 0x10 | ||
| 16510 | #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 | ||
| 16511 | #define TCP_STATUS__LFIFO_BUSY_MASK 0x20 | ||
| 16512 | #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 | ||
| 16513 | #define TCP_STATUS__READ_BUSY_MASK 0x40 | ||
| 16514 | #define TCP_STATUS__READ_BUSY__SHIFT 0x6 | ||
| 16515 | #define TCP_STATUS__FORMAT_BUSY_MASK 0x80 | ||
| 16516 | #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 | ||
| 16517 | #define TCP_CNTL__FORCE_HIT_MASK 0x1 | ||
| 16518 | #define TCP_CNTL__FORCE_HIT__SHIFT 0x0 | ||
| 16519 | #define TCP_CNTL__FORCE_MISS_MASK 0x2 | ||
| 16520 | #define TCP_CNTL__FORCE_MISS__SHIFT 0x1 | ||
| 16521 | #define TCP_CNTL__L1_SIZE_MASK 0xc | ||
| 16522 | #define TCP_CNTL__L1_SIZE__SHIFT 0x2 | ||
| 16523 | #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 | ||
| 16524 | #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 | ||
| 16525 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 | ||
| 16526 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 | ||
| 16527 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 | ||
| 16528 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf | ||
| 16529 | #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 | ||
| 16530 | #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 | ||
| 16531 | #define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 | ||
| 16532 | #define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c | ||
| 16533 | #define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 | ||
| 16534 | #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d | ||
| 16535 | #define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf | ||
| 16536 | #define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 | ||
| 16537 | #define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 | ||
| 16538 | #define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 | ||
| 16539 | #define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 | ||
| 16540 | #define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 | ||
| 16541 | #define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 | ||
| 16542 | #define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc | ||
| 16543 | #define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 | ||
| 16544 | #define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 | ||
| 16545 | #define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 | ||
| 16546 | #define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 | ||
| 16547 | #define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 | ||
| 16548 | #define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 | ||
| 16549 | #define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 | ||
| 16550 | #define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c | ||
| 16551 | #define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf | ||
| 16552 | #define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 | ||
| 16553 | #define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 | ||
| 16554 | #define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 | ||
| 16555 | #define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 | ||
| 16556 | #define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 | ||
| 16557 | #define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 | ||
| 16558 | #define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc | ||
| 16559 | #define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 | ||
| 16560 | #define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 | ||
| 16561 | #define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 | ||
| 16562 | #define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 | ||
| 16563 | #define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 | ||
| 16564 | #define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 | ||
| 16565 | #define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 | ||
| 16566 | #define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c | ||
| 16567 | #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf | ||
| 16568 | #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 | ||
| 16569 | #define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 | ||
| 16570 | #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 | ||
| 16571 | #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 | ||
| 16572 | #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 | ||
| 16573 | #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 | ||
| 16574 | #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 | ||
| 16575 | #define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff | ||
| 16576 | #define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 | ||
| 16577 | #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 | ||
| 16578 | #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 | ||
| 16579 | #define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 | ||
| 16580 | #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d | ||
| 16581 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16582 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16583 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16584 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16585 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16586 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16587 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16588 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16589 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16590 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16591 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16592 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16593 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 16594 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 16595 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16596 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16597 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 16598 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 16599 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16600 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16601 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16602 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16603 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16604 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16605 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 16606 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 16607 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 16608 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 16609 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 16610 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 16611 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 16612 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 16613 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 16614 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 16615 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 16616 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 16617 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16618 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16619 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16620 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16621 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16622 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16623 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff | ||
| 16624 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 16625 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 16626 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 16627 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 16628 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 16629 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16630 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16631 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16632 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16633 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16634 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16635 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 16636 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 16637 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16638 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16639 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16640 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16641 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16642 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16643 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 16644 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 16645 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 | ||
| 16646 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 | ||
| 16647 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 | ||
| 16648 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 | ||
| 16649 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 | ||
| 16650 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 | ||
| 16651 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 | ||
| 16652 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 | ||
| 16653 | #define TCP_EDC_CNT__SEC_COUNT_MASK 0xff | ||
| 16654 | #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 | ||
| 16655 | #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00 | ||
| 16656 | #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 | ||
| 16657 | #define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000 | ||
| 16658 | #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 | ||
| 16659 | #define TCP_EDC_CNT__UNUSED_MASK 0xff000000 | ||
| 16660 | #define TCP_EDC_CNT__UNUSED__SHIFT 0x18 | ||
| 16661 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 | ||
| 16662 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 | ||
| 16663 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc | ||
| 16664 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 | ||
| 16665 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 | ||
| 16666 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 | ||
| 16667 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 | ||
| 16668 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 | ||
| 16669 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 | ||
| 16670 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 | ||
| 16671 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 | ||
| 16672 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa | ||
| 16673 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 | ||
| 16674 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc | ||
| 16675 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 | ||
| 16676 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe | ||
| 16677 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 | ||
| 16678 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 | ||
| 16679 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 | ||
| 16680 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 | ||
| 16681 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 | ||
| 16682 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 | ||
| 16683 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 | ||
| 16684 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 | ||
| 16685 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 | ||
| 16686 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 | ||
| 16687 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 | ||
| 16688 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a | ||
| 16689 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 | ||
| 16690 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c | ||
| 16691 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 | ||
| 16692 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e | ||
| 16693 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 | ||
| 16694 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 | ||
| 16695 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc | ||
| 16696 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 | ||
| 16697 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 | ||
| 16698 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 | ||
| 16699 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 | ||
| 16700 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 | ||
| 16701 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 | ||
| 16702 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 | ||
| 16703 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 | ||
| 16704 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa | ||
| 16705 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 | ||
| 16706 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc | ||
| 16707 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 | ||
| 16708 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe | ||
| 16709 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 | ||
| 16710 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 | ||
| 16711 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 | ||
| 16712 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 | ||
| 16713 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 | ||
| 16714 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 | ||
| 16715 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 | ||
| 16716 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 | ||
| 16717 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 | ||
| 16718 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 | ||
| 16719 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 | ||
| 16720 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a | ||
| 16721 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 | ||
| 16722 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c | ||
| 16723 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 | ||
| 16724 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e | ||
| 16725 | #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 | ||
| 16726 | #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 | ||
| 16727 | #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 | ||
| 16728 | #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 | ||
| 16729 | #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 | ||
| 16730 | #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 | ||
| 16731 | #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 | ||
| 16732 | #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 | ||
| 16733 | #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 | ||
| 16734 | #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 | ||
| 16735 | #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 | ||
| 16736 | #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 | ||
| 16737 | #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 | ||
| 16738 | #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 | ||
| 16739 | #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 | ||
| 16740 | #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 | ||
| 16741 | #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 | ||
| 16742 | #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 | ||
| 16743 | #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 | ||
| 16744 | #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 | ||
| 16745 | #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 | ||
| 16746 | #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa | ||
| 16747 | #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 | ||
| 16748 | #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb | ||
| 16749 | #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 | ||
| 16750 | #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc | ||
| 16751 | #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 | ||
| 16752 | #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd | ||
| 16753 | #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 | ||
| 16754 | #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe | ||
| 16755 | #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 | ||
| 16756 | #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf | ||
| 16757 | #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 | ||
| 16758 | #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 | ||
| 16759 | #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 | ||
| 16760 | #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 | ||
| 16761 | #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 | ||
| 16762 | #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 | ||
| 16763 | #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 | ||
| 16764 | #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 | ||
| 16765 | #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 | ||
| 16766 | #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 | ||
| 16767 | #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 | ||
| 16768 | #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 | ||
| 16769 | #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 | ||
| 16770 | #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 | ||
| 16771 | #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 | ||
| 16772 | #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 | ||
| 16773 | #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 | ||
| 16774 | #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 | ||
| 16775 | #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 | ||
| 16776 | #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 | ||
| 16777 | #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 | ||
| 16778 | #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a | ||
| 16779 | #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 | ||
| 16780 | #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b | ||
| 16781 | #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 | ||
| 16782 | #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c | ||
| 16783 | #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 | ||
| 16784 | #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d | ||
| 16785 | #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 | ||
| 16786 | #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e | ||
| 16787 | #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 | ||
| 16788 | #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f | ||
| 16789 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 | ||
| 16790 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 | ||
| 16791 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc | ||
| 16792 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 | ||
| 16793 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 | ||
| 16794 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 | ||
| 16795 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 | ||
| 16796 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 | ||
| 16797 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 | ||
| 16798 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 | ||
| 16799 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 | ||
| 16800 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa | ||
| 16801 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 | ||
| 16802 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc | ||
| 16803 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 | ||
| 16804 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe | ||
| 16805 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 | ||
| 16806 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 | ||
| 16807 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 | ||
| 16808 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 | ||
| 16809 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 | ||
| 16810 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 | ||
| 16811 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 | ||
| 16812 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 | ||
| 16813 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 | ||
| 16814 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 | ||
| 16815 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 | ||
| 16816 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a | ||
| 16817 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 | ||
| 16818 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c | ||
| 16819 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 | ||
| 16820 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e | ||
| 16821 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 | ||
| 16822 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 | ||
| 16823 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc | ||
| 16824 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 | ||
| 16825 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 | ||
| 16826 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 | ||
| 16827 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 | ||
| 16828 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 | ||
| 16829 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 | ||
| 16830 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 | ||
| 16831 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 | ||
| 16832 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa | ||
| 16833 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 | ||
| 16834 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc | ||
| 16835 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 | ||
| 16836 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe | ||
| 16837 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 | ||
| 16838 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 | ||
| 16839 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 | ||
| 16840 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 | ||
| 16841 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 | ||
| 16842 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 | ||
| 16843 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 | ||
| 16844 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 | ||
| 16845 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 | ||
| 16846 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 | ||
| 16847 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 | ||
| 16848 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a | ||
| 16849 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 | ||
| 16850 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c | ||
| 16851 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 | ||
| 16852 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e | ||
| 16853 | #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 | ||
| 16854 | #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 | ||
| 16855 | #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc | ||
| 16856 | #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 | ||
| 16857 | #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 | ||
| 16858 | #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 | ||
| 16859 | #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 | ||
| 16860 | #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 | ||
| 16861 | #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 | ||
| 16862 | #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 | ||
| 16863 | #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 | ||
| 16864 | #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa | ||
| 16865 | #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 | ||
| 16866 | #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc | ||
| 16867 | #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 | ||
| 16868 | #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe | ||
| 16869 | #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 | ||
| 16870 | #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 | ||
| 16871 | #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 | ||
| 16872 | #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 | ||
| 16873 | #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 | ||
| 16874 | #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 | ||
| 16875 | #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 | ||
| 16876 | #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 | ||
| 16877 | #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 | ||
| 16878 | #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 | ||
| 16879 | #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 | ||
| 16880 | #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a | ||
| 16881 | #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 | ||
| 16882 | #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c | ||
| 16883 | #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 | ||
| 16884 | #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e | ||
| 16885 | #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 | ||
| 16886 | #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 | ||
| 16887 | #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc | ||
| 16888 | #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 | ||
| 16889 | #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 | ||
| 16890 | #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 | ||
| 16891 | #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 | ||
| 16892 | #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 | ||
| 16893 | #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 | ||
| 16894 | #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 | ||
| 16895 | #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 | ||
| 16896 | #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa | ||
| 16897 | #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 | ||
| 16898 | #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc | ||
| 16899 | #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 | ||
| 16900 | #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe | ||
| 16901 | #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 | ||
| 16902 | #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 | ||
| 16903 | #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 | ||
| 16904 | #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 | ||
| 16905 | #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 | ||
| 16906 | #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 | ||
| 16907 | #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 | ||
| 16908 | #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 | ||
| 16909 | #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 | ||
| 16910 | #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 | ||
| 16911 | #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 | ||
| 16912 | #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a | ||
| 16913 | #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 | ||
| 16914 | #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c | ||
| 16915 | #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 | ||
| 16916 | #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e | ||
| 16917 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 | ||
| 16918 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 | ||
| 16919 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc | ||
| 16920 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 | ||
| 16921 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 | ||
| 16922 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 | ||
| 16923 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 | ||
| 16924 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 | ||
| 16925 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 | ||
| 16926 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 | ||
| 16927 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 | ||
| 16928 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa | ||
| 16929 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 | ||
| 16930 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc | ||
| 16931 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 | ||
| 16932 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe | ||
| 16933 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 | ||
| 16934 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 | ||
| 16935 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 | ||
| 16936 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 | ||
| 16937 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 | ||
| 16938 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 | ||
| 16939 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 | ||
| 16940 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 | ||
| 16941 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 | ||
| 16942 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 | ||
| 16943 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 | ||
| 16944 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a | ||
| 16945 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 | ||
| 16946 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c | ||
| 16947 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 | ||
| 16948 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e | ||
| 16949 | #define TC_CFG_L1_VOLATILE__VOL_MASK 0xf | ||
| 16950 | #define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 | ||
| 16951 | #define TC_CFG_L2_VOLATILE__VOL_MASK 0xf | ||
| 16952 | #define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 | ||
| 16953 | #define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff | ||
| 16954 | #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 | ||
| 16955 | #define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff | ||
| 16956 | #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 | ||
| 16957 | #define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff | ||
| 16958 | #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 | ||
| 16959 | #define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff | ||
| 16960 | #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 | ||
| 16961 | #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 | ||
| 16962 | #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 | ||
| 16963 | #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 | ||
| 16964 | #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 | ||
| 16965 | #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 | ||
| 16966 | #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 | ||
| 16967 | #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 | ||
| 16968 | #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 | ||
| 16969 | #define TCP_WATCH0_CNTL__MASK_MASK 0xffffff | ||
| 16970 | #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 | ||
| 16971 | #define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 | ||
| 16972 | #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 | ||
| 16973 | #define TCP_WATCH0_CNTL__ATC_MASK 0x10000000 | ||
| 16974 | #define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c | ||
| 16975 | #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 | ||
| 16976 | #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d | ||
| 16977 | #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 | ||
| 16978 | #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f | ||
| 16979 | #define TCP_WATCH1_CNTL__MASK_MASK 0xffffff | ||
| 16980 | #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 | ||
| 16981 | #define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 | ||
| 16982 | #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 | ||
| 16983 | #define TCP_WATCH1_CNTL__ATC_MASK 0x10000000 | ||
| 16984 | #define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c | ||
| 16985 | #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 | ||
| 16986 | #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d | ||
| 16987 | #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 | ||
| 16988 | #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f | ||
| 16989 | #define TCP_WATCH2_CNTL__MASK_MASK 0xffffff | ||
| 16990 | #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 | ||
| 16991 | #define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 | ||
| 16992 | #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 | ||
| 16993 | #define TCP_WATCH2_CNTL__ATC_MASK 0x10000000 | ||
| 16994 | #define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c | ||
| 16995 | #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 | ||
| 16996 | #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d | ||
| 16997 | #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 | ||
| 16998 | #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f | ||
| 16999 | #define TCP_WATCH3_CNTL__MASK_MASK 0xffffff | ||
| 17000 | #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 | ||
| 17001 | #define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 | ||
| 17002 | #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 | ||
| 17003 | #define TCP_WATCH3_CNTL__ATC_MASK 0x10000000 | ||
| 17004 | #define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c | ||
| 17005 | #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 | ||
| 17006 | #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d | ||
| 17007 | #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 | ||
| 17008 | #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f | ||
| 17009 | #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000 | ||
| 17010 | #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 | ||
| 17011 | #define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000 | ||
| 17012 | #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a | ||
| 17013 | #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000 | ||
| 17014 | #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b | ||
| 17015 | #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 | ||
| 17016 | #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c | ||
| 17017 | #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 | ||
| 17018 | #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e | ||
| 17019 | #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff | ||
| 17020 | #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 | ||
| 17021 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1 | ||
| 17022 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 | ||
| 17023 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2 | ||
| 17024 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 | ||
| 17025 | #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4 | ||
| 17026 | #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 | ||
| 17027 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 | ||
| 17028 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 | ||
| 17029 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 | ||
| 17030 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 | ||
| 17031 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18 | ||
| 17032 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 | ||
| 17033 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20 | ||
| 17034 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 | ||
| 17035 | #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff | ||
| 17036 | #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 | ||
| 17037 | #define TD_CGTT_CTRL__ON_DELAY_MASK 0xf | ||
| 17038 | #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 17039 | #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 17040 | #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 17041 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 17042 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 17043 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 17044 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 17045 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 17046 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 17047 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 17048 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 17049 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 17050 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 17051 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 17052 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 17053 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 17054 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 17055 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 17056 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 17057 | #define TA_CGTT_CTRL__ON_DELAY_MASK 0xf | ||
| 17058 | #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 17059 | #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 17060 | #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 17061 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 17062 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 17063 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 17064 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 17065 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 17066 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 17067 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 17068 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 17069 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 17070 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 17071 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 17072 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 17073 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 17074 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 17075 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 17076 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 17077 | #define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 17078 | #define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 17079 | #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 17080 | #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 17081 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 17082 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 17083 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 17084 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 17085 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 17086 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 17087 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 17088 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 17089 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 17090 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 17091 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 17092 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 17093 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 17094 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 17095 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 17096 | #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 17097 | #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 17098 | #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 17099 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 17100 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 17101 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 17102 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 17103 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 17104 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 17105 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 17106 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 17107 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 17108 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 17109 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 17110 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 17111 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 17112 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 17113 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 17114 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 17115 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 17116 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 17117 | #define TCI_STATUS__TCI_BUSY_MASK 0x1 | ||
| 17118 | #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 | ||
| 17119 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff | ||
| 17120 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 | ||
| 17121 | #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 | ||
| 17122 | #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 | ||
| 17123 | #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 | ||
| 17124 | #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 | ||
| 17125 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 | ||
| 17126 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 | ||
| 17127 | #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe | ||
| 17128 | #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 | ||
| 17129 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 | ||
| 17130 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 | ||
| 17131 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 | ||
| 17132 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 | ||
| 17133 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 | ||
| 17134 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 | ||
| 17135 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 | ||
| 17136 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 | ||
| 17137 | #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 | ||
| 17138 | #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 | ||
| 17139 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 | ||
| 17140 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 | ||
| 17141 | #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 | ||
| 17142 | #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 | ||
| 17143 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 | ||
| 17144 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 | ||
| 17145 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 | ||
| 17146 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 | ||
| 17147 | #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 | ||
| 17148 | #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 | ||
| 17149 | #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 | ||
| 17150 | #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 | ||
| 17151 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80 | ||
| 17152 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 | ||
| 17153 | #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100 | ||
| 17154 | #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 | ||
| 17155 | #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200 | ||
| 17156 | #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 | ||
| 17157 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400 | ||
| 17158 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa | ||
| 17159 | #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800 | ||
| 17160 | #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb | ||
| 17161 | #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000 | ||
| 17162 | #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc | ||
| 17163 | #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000 | ||
| 17164 | #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd | ||
| 17165 | #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000 | ||
| 17166 | #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe | ||
| 17167 | #define GDS_ENHANCE2__MISC_MASK 0xffff | ||
| 17168 | #define GDS_ENHANCE2__MISC__SHIFT 0x0 | ||
| 17169 | #define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 | ||
| 17170 | #define GDS_ENHANCE2__UNUSED__SHIFT 0x10 | ||
| 17171 | #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 | ||
| 17172 | #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 | ||
| 17173 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 | ||
| 17174 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 | ||
| 17175 | #define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 | ||
| 17176 | #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 | ||
| 17177 | #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 | ||
| 17178 | #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 | ||
| 17179 | #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 | ||
| 17180 | #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 | ||
| 17181 | #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 | ||
| 17182 | #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa | ||
| 17183 | #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 | ||
| 17184 | #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc | ||
| 17185 | #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 | ||
| 17186 | #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 | ||
| 17187 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 | ||
| 17188 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 | ||
| 17189 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 | ||
| 17190 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 | ||
| 17191 | #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 | ||
| 17192 | #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 | ||
| 17193 | #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 | ||
| 17194 | #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 | ||
| 17195 | #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 | ||
| 17196 | #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 | ||
| 17197 | #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 | ||
| 17198 | #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 | ||
| 17199 | #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 | ||
| 17200 | #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 | ||
| 17201 | #define GDS_EDC_CNT__DED_MASK 0xff | ||
| 17202 | #define GDS_EDC_CNT__DED__SHIFT 0x0 | ||
| 17203 | #define GDS_EDC_CNT__SED_MASK 0xff00 | ||
| 17204 | #define GDS_EDC_CNT__SED__SHIFT 0x8 | ||
| 17205 | #define GDS_EDC_CNT__SEC_MASK 0xff0000 | ||
| 17206 | #define GDS_EDC_CNT__SEC__SHIFT 0x10 | ||
| 17207 | #define GDS_EDC_GRBM_CNT__DED_MASK 0xff | ||
| 17208 | #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 | ||
| 17209 | #define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000 | ||
| 17210 | #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10 | ||
| 17211 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 | ||
| 17212 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 | ||
| 17213 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 | ||
| 17214 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 | ||
| 17215 | #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4 | ||
| 17216 | #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 | ||
| 17217 | #define GDS_EDC_OA_DED__UNUSED0_MASK 0x8 | ||
| 17218 | #define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3 | ||
| 17219 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10 | ||
| 17220 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 | ||
| 17221 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20 | ||
| 17222 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 | ||
| 17223 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40 | ||
| 17224 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 | ||
| 17225 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80 | ||
| 17226 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 | ||
| 17227 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100 | ||
| 17228 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 | ||
| 17229 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200 | ||
| 17230 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 | ||
| 17231 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400 | ||
| 17232 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa | ||
| 17233 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800 | ||
| 17234 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb | ||
| 17235 | #define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000 | ||
| 17236 | #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc | ||
| 17237 | #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f | ||
| 17238 | #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 | ||
| 17239 | #define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 | ||
| 17240 | #define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 | ||
| 17241 | #define GDS_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 17242 | #define GDS_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 17243 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1 | ||
| 17244 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0 | ||
| 17245 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2 | ||
| 17246 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1 | ||
| 17247 | #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4 | ||
| 17248 | #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 | ||
| 17249 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8 | ||
| 17250 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3 | ||
| 17251 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10 | ||
| 17252 | #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4 | ||
| 17253 | #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20 | ||
| 17254 | #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5 | ||
| 17255 | #define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0 | ||
| 17256 | #define GDS_DSM_CNTL__UNUSED__SHIFT 0x6 | ||
| 17257 | #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 17258 | #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 17259 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 17260 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 17261 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 17262 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 17263 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 | ||
| 17264 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 | ||
| 17265 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 | ||
| 17266 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a | ||
| 17267 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 17268 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 17269 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 17270 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 17271 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 17272 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 17273 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 | ||
| 17274 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e | ||
| 17275 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 | ||
| 17276 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f | ||
| 17277 | #define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff | ||
| 17278 | #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 | ||
| 17279 | #define GDS_RD_DATA__READ_DATA_MASK 0xffffffff | ||
| 17280 | #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 | ||
| 17281 | #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff | ||
| 17282 | #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 | ||
| 17283 | #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff | ||
| 17284 | #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 | ||
| 17285 | #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff | ||
| 17286 | #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 | ||
| 17287 | #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff | ||
| 17288 | #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 | ||
| 17289 | #define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff | ||
| 17290 | #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 | ||
| 17291 | #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff | ||
| 17292 | #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 | ||
| 17293 | #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff | ||
| 17294 | #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 | ||
| 17295 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff | ||
| 17296 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 | ||
| 17297 | #define GDS_ATOM_CNTL__AINC_MASK 0x3f | ||
| 17298 | #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 | ||
| 17299 | #define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 | ||
| 17300 | #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 | ||
| 17301 | #define GDS_ATOM_CNTL__DMODE_MASK 0x300 | ||
| 17302 | #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 | ||
| 17303 | #define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00 | ||
| 17304 | #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa | ||
| 17305 | #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 | ||
| 17306 | #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 | ||
| 17307 | #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe | ||
| 17308 | #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 | ||
| 17309 | #define GDS_ATOM_BASE__BASE_MASK 0xffff | ||
| 17310 | #define GDS_ATOM_BASE__BASE__SHIFT 0x0 | ||
| 17311 | #define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 | ||
| 17312 | #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 | ||
| 17313 | #define GDS_ATOM_SIZE__SIZE_MASK 0xffff | ||
| 17314 | #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 | ||
| 17315 | #define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 | ||
| 17316 | #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 | ||
| 17317 | #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff | ||
| 17318 | #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 | ||
| 17319 | #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 | ||
| 17320 | #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 | ||
| 17321 | #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff | ||
| 17322 | #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 | ||
| 17323 | #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 | ||
| 17324 | #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 | ||
| 17325 | #define GDS_ATOM_DST__DST_MASK 0xffffffff | ||
| 17326 | #define GDS_ATOM_DST__DST__SHIFT 0x0 | ||
| 17327 | #define GDS_ATOM_OP__OP_MASK 0xff | ||
| 17328 | #define GDS_ATOM_OP__OP__SHIFT 0x0 | ||
| 17329 | #define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 | ||
| 17330 | #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 | ||
| 17331 | #define GDS_ATOM_SRC0__DATA_MASK 0xffffffff | ||
| 17332 | #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 | ||
| 17333 | #define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff | ||
| 17334 | #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 | ||
| 17335 | #define GDS_ATOM_SRC1__DATA_MASK 0xffffffff | ||
| 17336 | #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 | ||
| 17337 | #define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff | ||
| 17338 | #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 | ||
| 17339 | #define GDS_ATOM_READ0__DATA_MASK 0xffffffff | ||
| 17340 | #define GDS_ATOM_READ0__DATA__SHIFT 0x0 | ||
| 17341 | #define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff | ||
| 17342 | #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 | ||
| 17343 | #define GDS_ATOM_READ1__DATA_MASK 0xffffffff | ||
| 17344 | #define GDS_ATOM_READ1__DATA__SHIFT 0x0 | ||
| 17345 | #define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff | ||
| 17346 | #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 | ||
| 17347 | #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f | ||
| 17348 | #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 | ||
| 17349 | #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 | ||
| 17350 | #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 | ||
| 17351 | #define GDS_GWS_RESOURCE__FLAG_MASK 0x1 | ||
| 17352 | #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 | ||
| 17353 | #define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe | ||
| 17354 | #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 | ||
| 17355 | #define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 | ||
| 17356 | #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd | ||
| 17357 | #define GDS_GWS_RESOURCE__DED_MASK 0x4000 | ||
| 17358 | #define GDS_GWS_RESOURCE__DED__SHIFT 0xe | ||
| 17359 | #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 | ||
| 17360 | #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf | ||
| 17361 | #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0xfff0000 | ||
| 17362 | #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 | ||
| 17363 | #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000 | ||
| 17364 | #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c | ||
| 17365 | #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000 | ||
| 17366 | #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d | ||
| 17367 | #define GDS_GWS_RESOURCE__UNUSED1_MASK 0xc0000000 | ||
| 17368 | #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1e | ||
| 17369 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff | ||
| 17370 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 | ||
| 17371 | #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 | ||
| 17372 | #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 | ||
| 17373 | #define GDS_OA_CNTL__INDEX_MASK 0xf | ||
| 17374 | #define GDS_OA_CNTL__INDEX__SHIFT 0x0 | ||
| 17375 | #define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 | ||
| 17376 | #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 | ||
| 17377 | #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff | ||
| 17378 | #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 | ||
| 17379 | #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff | ||
| 17380 | #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 | ||
| 17381 | #define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000 | ||
| 17382 | #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 | ||
| 17383 | #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000 | ||
| 17384 | #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 | ||
| 17385 | #define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000 | ||
| 17386 | #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 | ||
| 17387 | #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 | ||
| 17388 | #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e | ||
| 17389 | #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 | ||
| 17390 | #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f | ||
| 17391 | #define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff | ||
| 17392 | #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 | ||
| 17393 | #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 | ||
| 17394 | #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f | ||
| 17395 | #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff | ||
| 17396 | #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 | ||
| 17397 | #define GDS_DEBUG_REG0__spare1_MASK 0x3f | ||
| 17398 | #define GDS_DEBUG_REG0__spare1__SHIFT 0x0 | ||
| 17399 | #define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 | ||
| 17400 | #define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 | ||
| 17401 | #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 | ||
| 17402 | #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 | ||
| 17403 | #define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 | ||
| 17404 | #define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc | ||
| 17405 | #define GDS_DEBUG_REG0__cstate_MASK 0x1e000 | ||
| 17406 | #define GDS_DEBUG_REG0__cstate__SHIFT 0xd | ||
| 17407 | #define GDS_DEBUG_REG0__buff_write_MASK 0x20000 | ||
| 17408 | #define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 | ||
| 17409 | #define GDS_DEBUG_REG0__flush_request_MASK 0x40000 | ||
| 17410 | #define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 | ||
| 17411 | #define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 | ||
| 17412 | #define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 | ||
| 17413 | #define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 | ||
| 17414 | #define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 | ||
| 17415 | #define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 | ||
| 17416 | #define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 | ||
| 17417 | #define GDS_DEBUG_REG0__spare_MASK 0xffc00000 | ||
| 17418 | #define GDS_DEBUG_REG0__spare__SHIFT 0x16 | ||
| 17419 | #define GDS_DEBUG_REG1__tag_hit_MASK 0x1 | ||
| 17420 | #define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 | ||
| 17421 | #define GDS_DEBUG_REG1__tag_miss_MASK 0x2 | ||
| 17422 | #define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 | ||
| 17423 | #define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc | ||
| 17424 | #define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 | ||
| 17425 | #define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 | ||
| 17426 | #define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 | ||
| 17427 | #define GDS_DEBUG_REG1__data_ready_MASK 0x40000 | ||
| 17428 | #define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 | ||
| 17429 | #define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 | ||
| 17430 | #define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 | ||
| 17431 | #define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 | ||
| 17432 | #define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 | ||
| 17433 | #define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 | ||
| 17434 | #define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 | ||
| 17435 | #define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 | ||
| 17436 | #define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 | ||
| 17437 | #define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 | ||
| 17438 | #define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 | ||
| 17439 | #define GDS_DEBUG_REG1__spare_MASK 0xff000000 | ||
| 17440 | #define GDS_DEBUG_REG1__spare__SHIFT 0x18 | ||
| 17441 | #define GDS_DEBUG_REG2__ds_full_MASK 0x1 | ||
| 17442 | #define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 | ||
| 17443 | #define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 | ||
| 17444 | #define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 | ||
| 17445 | #define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 | ||
| 17446 | #define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 | ||
| 17447 | #define GDS_DEBUG_REG2__cmd_write_MASK 0x8 | ||
| 17448 | #define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 | ||
| 17449 | #define GDS_DEBUG_REG2__app_sel_MASK 0xf0 | ||
| 17450 | #define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 | ||
| 17451 | #define GDS_DEBUG_REG2__req_MASK 0x7fff00 | ||
| 17452 | #define GDS_DEBUG_REG2__req__SHIFT 0x8 | ||
| 17453 | #define GDS_DEBUG_REG2__spare_MASK 0xff800000 | ||
| 17454 | #define GDS_DEBUG_REG2__spare__SHIFT 0x17 | ||
| 17455 | #define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff | ||
| 17456 | #define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 | ||
| 17457 | #define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 | ||
| 17458 | #define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb | ||
| 17459 | #define GDS_DEBUG_REG3__spare_MASK 0xffff8000 | ||
| 17460 | #define GDS_DEBUG_REG3__spare__SHIFT 0xf | ||
| 17461 | #define GDS_DEBUG_REG4__gws_busy_MASK 0x1 | ||
| 17462 | #define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 | ||
| 17463 | #define GDS_DEBUG_REG4__gws_req_MASK 0x2 | ||
| 17464 | #define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 | ||
| 17465 | #define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 | ||
| 17466 | #define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 | ||
| 17467 | #define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 | ||
| 17468 | #define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 | ||
| 17469 | #define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 | ||
| 17470 | #define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 | ||
| 17471 | #define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 | ||
| 17472 | #define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa | ||
| 17473 | #define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 | ||
| 17474 | #define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb | ||
| 17475 | #define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 | ||
| 17476 | #define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc | ||
| 17477 | #define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 | ||
| 17478 | #define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd | ||
| 17479 | #define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 | ||
| 17480 | #define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe | ||
| 17481 | #define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 | ||
| 17482 | #define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf | ||
| 17483 | #define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 | ||
| 17484 | #define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 | ||
| 17485 | #define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 | ||
| 17486 | #define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 | ||
| 17487 | #define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 | ||
| 17488 | #define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 | ||
| 17489 | #define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 | ||
| 17490 | #define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 | ||
| 17491 | #define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 | ||
| 17492 | #define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 | ||
| 17493 | #define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 | ||
| 17494 | #define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 | ||
| 17495 | #define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 | ||
| 17496 | #define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 | ||
| 17497 | #define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 | ||
| 17498 | #define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 | ||
| 17499 | #define GDS_DEBUG_REG4__spare_MASK 0xff000000 | ||
| 17500 | #define GDS_DEBUG_REG4__spare__SHIFT 0x18 | ||
| 17501 | #define GDS_DEBUG_REG5__write_dis_MASK 0x1 | ||
| 17502 | #define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 | ||
| 17503 | #define GDS_DEBUG_REG5__dec_error_MASK 0x2 | ||
| 17504 | #define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 | ||
| 17505 | #define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 | ||
| 17506 | #define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 | ||
| 17507 | #define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 | ||
| 17508 | #define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 | ||
| 17509 | #define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 | ||
| 17510 | #define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 | ||
| 17511 | #define GDS_DEBUG_REG5__spare_MASK 0xe0 | ||
| 17512 | #define GDS_DEBUG_REG5__spare__SHIFT 0x5 | ||
| 17513 | #define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 | ||
| 17514 | #define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 | ||
| 17515 | #define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 | ||
| 17516 | #define GDS_DEBUG_REG5__spare1__SHIFT 0x16 | ||
| 17517 | #define GDS_DEBUG_REG6__oa_busy_MASK 0x1 | ||
| 17518 | #define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 | ||
| 17519 | #define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e | ||
| 17520 | #define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 | ||
| 17521 | #define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 | ||
| 17522 | #define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 | ||
| 17523 | #define GDS_DEBUG_REG6__spare_MASK 0xffe00000 | ||
| 17524 | #define GDS_DEBUG_REG6__spare__SHIFT 0x15 | ||
| 17525 | #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 17526 | #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 17527 | #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 17528 | #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 17529 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 17530 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 17531 | #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 17532 | #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 17533 | #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 17534 | #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 17535 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 17536 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 17537 | #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 17538 | #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 17539 | #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 17540 | #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 17541 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 17542 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 17543 | #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff | ||
| 17544 | #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 | ||
| 17545 | #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 | ||
| 17546 | #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa | ||
| 17547 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 17548 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 17549 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 17550 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 17551 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 17552 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 17553 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 17554 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 17555 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 17556 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 17557 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 17558 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 17559 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 17560 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 17561 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 17562 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 17563 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 17564 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 17565 | #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff | ||
| 17566 | #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 | ||
| 17567 | #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 | ||
| 17568 | #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa | ||
| 17569 | #define GDS_VMID0_BASE__BASE_MASK 0xffff | ||
| 17570 | #define GDS_VMID0_BASE__BASE__SHIFT 0x0 | ||
| 17571 | #define GDS_VMID1_BASE__BASE_MASK 0xffff | ||
| 17572 | #define GDS_VMID1_BASE__BASE__SHIFT 0x0 | ||
| 17573 | #define GDS_VMID2_BASE__BASE_MASK 0xffff | ||
| 17574 | #define GDS_VMID2_BASE__BASE__SHIFT 0x0 | ||
| 17575 | #define GDS_VMID3_BASE__BASE_MASK 0xffff | ||
| 17576 | #define GDS_VMID3_BASE__BASE__SHIFT 0x0 | ||
| 17577 | #define GDS_VMID4_BASE__BASE_MASK 0xffff | ||
| 17578 | #define GDS_VMID4_BASE__BASE__SHIFT 0x0 | ||
| 17579 | #define GDS_VMID5_BASE__BASE_MASK 0xffff | ||
| 17580 | #define GDS_VMID5_BASE__BASE__SHIFT 0x0 | ||
| 17581 | #define GDS_VMID6_BASE__BASE_MASK 0xffff | ||
| 17582 | #define GDS_VMID6_BASE__BASE__SHIFT 0x0 | ||
| 17583 | #define GDS_VMID7_BASE__BASE_MASK 0xffff | ||
| 17584 | #define GDS_VMID7_BASE__BASE__SHIFT 0x0 | ||
| 17585 | #define GDS_VMID8_BASE__BASE_MASK 0xffff | ||
| 17586 | #define GDS_VMID8_BASE__BASE__SHIFT 0x0 | ||
| 17587 | #define GDS_VMID9_BASE__BASE_MASK 0xffff | ||
| 17588 | #define GDS_VMID9_BASE__BASE__SHIFT 0x0 | ||
| 17589 | #define GDS_VMID10_BASE__BASE_MASK 0xffff | ||
| 17590 | #define GDS_VMID10_BASE__BASE__SHIFT 0x0 | ||
| 17591 | #define GDS_VMID11_BASE__BASE_MASK 0xffff | ||
| 17592 | #define GDS_VMID11_BASE__BASE__SHIFT 0x0 | ||
| 17593 | #define GDS_VMID12_BASE__BASE_MASK 0xffff | ||
| 17594 | #define GDS_VMID12_BASE__BASE__SHIFT 0x0 | ||
| 17595 | #define GDS_VMID13_BASE__BASE_MASK 0xffff | ||
| 17596 | #define GDS_VMID13_BASE__BASE__SHIFT 0x0 | ||
| 17597 | #define GDS_VMID14_BASE__BASE_MASK 0xffff | ||
| 17598 | #define GDS_VMID14_BASE__BASE__SHIFT 0x0 | ||
| 17599 | #define GDS_VMID15_BASE__BASE_MASK 0xffff | ||
| 17600 | #define GDS_VMID15_BASE__BASE__SHIFT 0x0 | ||
| 17601 | #define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff | ||
| 17602 | #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 | ||
| 17603 | #define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff | ||
| 17604 | #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 | ||
| 17605 | #define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff | ||
| 17606 | #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 | ||
| 17607 | #define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff | ||
| 17608 | #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 | ||
| 17609 | #define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff | ||
| 17610 | #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 | ||
| 17611 | #define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff | ||
| 17612 | #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 | ||
| 17613 | #define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff | ||
| 17614 | #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 | ||
| 17615 | #define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff | ||
| 17616 | #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 | ||
| 17617 | #define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff | ||
| 17618 | #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 | ||
| 17619 | #define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff | ||
| 17620 | #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 | ||
| 17621 | #define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff | ||
| 17622 | #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 | ||
| 17623 | #define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff | ||
| 17624 | #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 | ||
| 17625 | #define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff | ||
| 17626 | #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 | ||
| 17627 | #define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff | ||
| 17628 | #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 | ||
| 17629 | #define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff | ||
| 17630 | #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 | ||
| 17631 | #define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff | ||
| 17632 | #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 | ||
| 17633 | #define GDS_GWS_VMID0__BASE_MASK 0x3f | ||
| 17634 | #define GDS_GWS_VMID0__BASE__SHIFT 0x0 | ||
| 17635 | #define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 | ||
| 17636 | #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 | ||
| 17637 | #define GDS_GWS_VMID1__BASE_MASK 0x3f | ||
| 17638 | #define GDS_GWS_VMID1__BASE__SHIFT 0x0 | ||
| 17639 | #define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 | ||
| 17640 | #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 | ||
| 17641 | #define GDS_GWS_VMID2__BASE_MASK 0x3f | ||
| 17642 | #define GDS_GWS_VMID2__BASE__SHIFT 0x0 | ||
| 17643 | #define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 | ||
| 17644 | #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 | ||
| 17645 | #define GDS_GWS_VMID3__BASE_MASK 0x3f | ||
| 17646 | #define GDS_GWS_VMID3__BASE__SHIFT 0x0 | ||
| 17647 | #define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 | ||
| 17648 | #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 | ||
| 17649 | #define GDS_GWS_VMID4__BASE_MASK 0x3f | ||
| 17650 | #define GDS_GWS_VMID4__BASE__SHIFT 0x0 | ||
| 17651 | #define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 | ||
| 17652 | #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 | ||
| 17653 | #define GDS_GWS_VMID5__BASE_MASK 0x3f | ||
| 17654 | #define GDS_GWS_VMID5__BASE__SHIFT 0x0 | ||
| 17655 | #define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 | ||
| 17656 | #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 | ||
| 17657 | #define GDS_GWS_VMID6__BASE_MASK 0x3f | ||
| 17658 | #define GDS_GWS_VMID6__BASE__SHIFT 0x0 | ||
| 17659 | #define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 | ||
| 17660 | #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 | ||
| 17661 | #define GDS_GWS_VMID7__BASE_MASK 0x3f | ||
| 17662 | #define GDS_GWS_VMID7__BASE__SHIFT 0x0 | ||
| 17663 | #define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 | ||
| 17664 | #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 | ||
| 17665 | #define GDS_GWS_VMID8__BASE_MASK 0x3f | ||
| 17666 | #define GDS_GWS_VMID8__BASE__SHIFT 0x0 | ||
| 17667 | #define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 | ||
| 17668 | #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 | ||
| 17669 | #define GDS_GWS_VMID9__BASE_MASK 0x3f | ||
| 17670 | #define GDS_GWS_VMID9__BASE__SHIFT 0x0 | ||
| 17671 | #define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 | ||
| 17672 | #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 | ||
| 17673 | #define GDS_GWS_VMID10__BASE_MASK 0x3f | ||
| 17674 | #define GDS_GWS_VMID10__BASE__SHIFT 0x0 | ||
| 17675 | #define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 | ||
| 17676 | #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 | ||
| 17677 | #define GDS_GWS_VMID11__BASE_MASK 0x3f | ||
| 17678 | #define GDS_GWS_VMID11__BASE__SHIFT 0x0 | ||
| 17679 | #define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 | ||
| 17680 | #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 | ||
| 17681 | #define GDS_GWS_VMID12__BASE_MASK 0x3f | ||
| 17682 | #define GDS_GWS_VMID12__BASE__SHIFT 0x0 | ||
| 17683 | #define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 | ||
| 17684 | #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 | ||
| 17685 | #define GDS_GWS_VMID13__BASE_MASK 0x3f | ||
| 17686 | #define GDS_GWS_VMID13__BASE__SHIFT 0x0 | ||
| 17687 | #define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 | ||
| 17688 | #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 | ||
| 17689 | #define GDS_GWS_VMID14__BASE_MASK 0x3f | ||
| 17690 | #define GDS_GWS_VMID14__BASE__SHIFT 0x0 | ||
| 17691 | #define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 | ||
| 17692 | #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 | ||
| 17693 | #define GDS_GWS_VMID15__BASE_MASK 0x3f | ||
| 17694 | #define GDS_GWS_VMID15__BASE__SHIFT 0x0 | ||
| 17695 | #define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 | ||
| 17696 | #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 | ||
| 17697 | #define GDS_OA_VMID0__MASK_MASK 0xffff | ||
| 17698 | #define GDS_OA_VMID0__MASK__SHIFT 0x0 | ||
| 17699 | #define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 | ||
| 17700 | #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 | ||
| 17701 | #define GDS_OA_VMID1__MASK_MASK 0xffff | ||
| 17702 | #define GDS_OA_VMID1__MASK__SHIFT 0x0 | ||
| 17703 | #define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 | ||
| 17704 | #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 | ||
| 17705 | #define GDS_OA_VMID2__MASK_MASK 0xffff | ||
| 17706 | #define GDS_OA_VMID2__MASK__SHIFT 0x0 | ||
| 17707 | #define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 | ||
| 17708 | #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 | ||
| 17709 | #define GDS_OA_VMID3__MASK_MASK 0xffff | ||
| 17710 | #define GDS_OA_VMID3__MASK__SHIFT 0x0 | ||
| 17711 | #define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 | ||
| 17712 | #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 | ||
| 17713 | #define GDS_OA_VMID4__MASK_MASK 0xffff | ||
| 17714 | #define GDS_OA_VMID4__MASK__SHIFT 0x0 | ||
| 17715 | #define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 | ||
| 17716 | #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 | ||
| 17717 | #define GDS_OA_VMID5__MASK_MASK 0xffff | ||
| 17718 | #define GDS_OA_VMID5__MASK__SHIFT 0x0 | ||
| 17719 | #define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 | ||
| 17720 | #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 | ||
| 17721 | #define GDS_OA_VMID6__MASK_MASK 0xffff | ||
| 17722 | #define GDS_OA_VMID6__MASK__SHIFT 0x0 | ||
| 17723 | #define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 | ||
| 17724 | #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 | ||
| 17725 | #define GDS_OA_VMID7__MASK_MASK 0xffff | ||
| 17726 | #define GDS_OA_VMID7__MASK__SHIFT 0x0 | ||
| 17727 | #define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 | ||
| 17728 | #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 | ||
| 17729 | #define GDS_OA_VMID8__MASK_MASK 0xffff | ||
| 17730 | #define GDS_OA_VMID8__MASK__SHIFT 0x0 | ||
| 17731 | #define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 | ||
| 17732 | #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 | ||
| 17733 | #define GDS_OA_VMID9__MASK_MASK 0xffff | ||
| 17734 | #define GDS_OA_VMID9__MASK__SHIFT 0x0 | ||
| 17735 | #define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 | ||
| 17736 | #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 | ||
| 17737 | #define GDS_OA_VMID10__MASK_MASK 0xffff | ||
| 17738 | #define GDS_OA_VMID10__MASK__SHIFT 0x0 | ||
| 17739 | #define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 | ||
| 17740 | #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 | ||
| 17741 | #define GDS_OA_VMID11__MASK_MASK 0xffff | ||
| 17742 | #define GDS_OA_VMID11__MASK__SHIFT 0x0 | ||
| 17743 | #define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 | ||
| 17744 | #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 | ||
| 17745 | #define GDS_OA_VMID12__MASK_MASK 0xffff | ||
| 17746 | #define GDS_OA_VMID12__MASK__SHIFT 0x0 | ||
| 17747 | #define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 | ||
| 17748 | #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 | ||
| 17749 | #define GDS_OA_VMID13__MASK_MASK 0xffff | ||
| 17750 | #define GDS_OA_VMID13__MASK__SHIFT 0x0 | ||
| 17751 | #define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 | ||
| 17752 | #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 | ||
| 17753 | #define GDS_OA_VMID14__MASK_MASK 0xffff | ||
| 17754 | #define GDS_OA_VMID14__MASK__SHIFT 0x0 | ||
| 17755 | #define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 | ||
| 17756 | #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 | ||
| 17757 | #define GDS_OA_VMID15__MASK_MASK 0xffff | ||
| 17758 | #define GDS_OA_VMID15__MASK__SHIFT 0x0 | ||
| 17759 | #define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 | ||
| 17760 | #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 | ||
| 17761 | #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 | ||
| 17762 | #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 | ||
| 17763 | #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 | ||
| 17764 | #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 | ||
| 17765 | #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 | ||
| 17766 | #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 | ||
| 17767 | #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 | ||
| 17768 | #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 | ||
| 17769 | #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 | ||
| 17770 | #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 | ||
| 17771 | #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 | ||
| 17772 | #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 | ||
| 17773 | #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 | ||
| 17774 | #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 | ||
| 17775 | #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 | ||
| 17776 | #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 | ||
| 17777 | #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 | ||
| 17778 | #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 | ||
| 17779 | #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 | ||
| 17780 | #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 | ||
| 17781 | #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 | ||
| 17782 | #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa | ||
| 17783 | #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 | ||
| 17784 | #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb | ||
| 17785 | #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 | ||
| 17786 | #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc | ||
| 17787 | #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 | ||
| 17788 | #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd | ||
| 17789 | #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 | ||
| 17790 | #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe | ||
| 17791 | #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 | ||
| 17792 | #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf | ||
| 17793 | #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 | ||
| 17794 | #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 | ||
| 17795 | #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 | ||
| 17796 | #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 | ||
| 17797 | #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 | ||
| 17798 | #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 | ||
| 17799 | #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 | ||
| 17800 | #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 | ||
| 17801 | #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 | ||
| 17802 | #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 | ||
| 17803 | #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 | ||
| 17804 | #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 | ||
| 17805 | #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 | ||
| 17806 | #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 | ||
| 17807 | #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 | ||
| 17808 | #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 | ||
| 17809 | #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 | ||
| 17810 | #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 | ||
| 17811 | #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 | ||
| 17812 | #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 | ||
| 17813 | #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 | ||
| 17814 | #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a | ||
| 17815 | #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 | ||
| 17816 | #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b | ||
| 17817 | #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 | ||
| 17818 | #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c | ||
| 17819 | #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 | ||
| 17820 | #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d | ||
| 17821 | #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 | ||
| 17822 | #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e | ||
| 17823 | #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 | ||
| 17824 | #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f | ||
| 17825 | #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 | ||
| 17826 | #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 | ||
| 17827 | #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 | ||
| 17828 | #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 | ||
| 17829 | #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 | ||
| 17830 | #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 | ||
| 17831 | #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 | ||
| 17832 | #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 | ||
| 17833 | #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 | ||
| 17834 | #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 | ||
| 17835 | #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 | ||
| 17836 | #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 | ||
| 17837 | #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 | ||
| 17838 | #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 | ||
| 17839 | #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 | ||
| 17840 | #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 | ||
| 17841 | #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 | ||
| 17842 | #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 | ||
| 17843 | #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 | ||
| 17844 | #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 | ||
| 17845 | #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 | ||
| 17846 | #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa | ||
| 17847 | #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 | ||
| 17848 | #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb | ||
| 17849 | #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 | ||
| 17850 | #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc | ||
| 17851 | #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 | ||
| 17852 | #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd | ||
| 17853 | #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 | ||
| 17854 | #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe | ||
| 17855 | #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 | ||
| 17856 | #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf | ||
| 17857 | #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 | ||
| 17858 | #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 | ||
| 17859 | #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 | ||
| 17860 | #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 | ||
| 17861 | #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 | ||
| 17862 | #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 | ||
| 17863 | #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 | ||
| 17864 | #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 | ||
| 17865 | #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 | ||
| 17866 | #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 | ||
| 17867 | #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 | ||
| 17868 | #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 | ||
| 17869 | #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 | ||
| 17870 | #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 | ||
| 17871 | #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 | ||
| 17872 | #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 | ||
| 17873 | #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 | ||
| 17874 | #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 | ||
| 17875 | #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 | ||
| 17876 | #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 | ||
| 17877 | #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 | ||
| 17878 | #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a | ||
| 17879 | #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 | ||
| 17880 | #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b | ||
| 17881 | #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 | ||
| 17882 | #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c | ||
| 17883 | #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 | ||
| 17884 | #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d | ||
| 17885 | #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 | ||
| 17886 | #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e | ||
| 17887 | #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 | ||
| 17888 | #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f | ||
| 17889 | #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 | ||
| 17890 | #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 | ||
| 17891 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 | ||
| 17892 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 | ||
| 17893 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff | ||
| 17894 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 | ||
| 17895 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 | ||
| 17896 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 | ||
| 17897 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 | ||
| 17898 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 | ||
| 17899 | #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 | ||
| 17900 | #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 | ||
| 17901 | #define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 | ||
| 17902 | #define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 | ||
| 17903 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 | ||
| 17904 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 | ||
| 17905 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 | ||
| 17906 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 | ||
| 17907 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 | ||
| 17908 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 | ||
| 17909 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 | ||
| 17910 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 | ||
| 17911 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 | ||
| 17912 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 | ||
| 17913 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 | ||
| 17914 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 | ||
| 17915 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 | ||
| 17916 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa | ||
| 17917 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 | ||
| 17918 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb | ||
| 17919 | #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 | ||
| 17920 | #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc | ||
| 17921 | #define GDS_OA_RESET__RESET_MASK 0x1 | ||
| 17922 | #define GDS_OA_RESET__RESET__SHIFT 0x0 | ||
| 17923 | #define GDS_OA_RESET__PIPE_ID_MASK 0xff00 | ||
| 17924 | #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 | ||
| 17925 | #define GDS_ENHANCE__MISC_MASK 0xffff | ||
| 17926 | #define GDS_ENHANCE__MISC__SHIFT 0x0 | ||
| 17927 | #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 | ||
| 17928 | #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 | ||
| 17929 | #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 | ||
| 17930 | #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 | ||
| 17931 | #define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 | ||
| 17932 | #define GDS_ENHANCE__UNUSED__SHIFT 0x12 | ||
| 17933 | #define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff | ||
| 17934 | #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 | ||
| 17935 | #define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 | ||
| 17936 | #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 | ||
| 17937 | #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 | ||
| 17938 | #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc | ||
| 17939 | #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000 | ||
| 17940 | #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 | ||
| 17941 | #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000 | ||
| 17942 | #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 | ||
| 17943 | #define GDS_CS_CTXSW_STATUS__R_MASK 0x1 | ||
| 17944 | #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 | ||
| 17945 | #define GDS_CS_CTXSW_STATUS__W_MASK 0x2 | ||
| 17946 | #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 | ||
| 17947 | #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc | ||
| 17948 | #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 | ||
| 17949 | #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 17950 | #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 17951 | #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 17952 | #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 17953 | #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 17954 | #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 17955 | #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 17956 | #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 17957 | #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 17958 | #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 17959 | #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 17960 | #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 17961 | #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 17962 | #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 17963 | #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 17964 | #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 17965 | #define GDS_GFX_CTXSW_STATUS__R_MASK 0x1 | ||
| 17966 | #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 | ||
| 17967 | #define GDS_GFX_CTXSW_STATUS__W_MASK 0x2 | ||
| 17968 | #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 | ||
| 17969 | #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc | ||
| 17970 | #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 | ||
| 17971 | #define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 17972 | #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 17973 | #define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 17974 | #define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 17975 | #define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 17976 | #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 17977 | #define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 17978 | #define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 17979 | #define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 17980 | #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 17981 | #define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 17982 | #define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 17983 | #define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 17984 | #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 17985 | #define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 17986 | #define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 17987 | #define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 17988 | #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 17989 | #define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 17990 | #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 17991 | #define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 17992 | #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 17993 | #define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 17994 | #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 17995 | #define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 17996 | #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 17997 | #define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 17998 | #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 17999 | #define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 18000 | #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 18001 | #define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 18002 | #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 18003 | #define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 18004 | #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 18005 | #define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 18006 | #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 18007 | #define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 18008 | #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 18009 | #define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 18010 | #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 18011 | #define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 18012 | #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 18013 | #define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 18014 | #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 18015 | #define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff | ||
| 18016 | #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 | ||
| 18017 | #define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000 | ||
| 18018 | #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 | ||
| 18019 | #define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18020 | #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18021 | #define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18022 | #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18023 | #define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18024 | #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18025 | #define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18026 | #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18027 | #define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18028 | #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18029 | #define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18030 | #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18031 | #define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18032 | #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18033 | #define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18034 | #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18035 | #define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18036 | #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18037 | #define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18038 | #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18039 | #define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18040 | #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18041 | #define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18042 | #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18043 | #define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18044 | #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18045 | #define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18046 | #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18047 | #define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff | ||
| 18048 | #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 | ||
| 18049 | #define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000 | ||
| 18050 | #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 | ||
| 18051 | #define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18052 | #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18053 | #define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18054 | #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18055 | #define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18056 | #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18057 | #define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18058 | #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18059 | #define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18060 | #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18061 | #define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18062 | #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18063 | #define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18064 | #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18065 | #define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18066 | #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18067 | #define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18068 | #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18069 | #define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18070 | #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18071 | #define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18072 | #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18073 | #define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18074 | #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18075 | #define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18076 | #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18077 | #define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18078 | #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18079 | #define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff | ||
| 18080 | #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 | ||
| 18081 | #define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000 | ||
| 18082 | #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 | ||
| 18083 | #define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18084 | #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18085 | #define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18086 | #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18087 | #define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18088 | #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18089 | #define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18090 | #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18091 | #define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18092 | #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18093 | #define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18094 | #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18095 | #define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18096 | #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18097 | #define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18098 | #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18099 | #define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18100 | #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18101 | #define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18102 | #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18103 | #define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18104 | #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18105 | #define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18106 | #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18107 | #define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18108 | #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18109 | #define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18110 | #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18111 | #define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff | ||
| 18112 | #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 | ||
| 18113 | #define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000 | ||
| 18114 | #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 | ||
| 18115 | #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 | ||
| 18116 | #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 | ||
| 18117 | #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 | ||
| 18118 | #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 | ||
| 18119 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 | ||
| 18120 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 | ||
| 18121 | #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc | ||
| 18122 | #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 | ||
| 18123 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 | ||
| 18124 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 | ||
| 18125 | #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 | ||
| 18126 | #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 | ||
| 18127 | #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 | ||
| 18128 | #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 | ||
| 18129 | #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f | ||
| 18130 | #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 | ||
| 18131 | #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 | ||
| 18132 | #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 | ||
| 18133 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 | ||
| 18134 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b | ||
| 18135 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff | ||
| 18136 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 | ||
| 18137 | #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff | ||
| 18138 | #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 | ||
| 18139 | #define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff | ||
| 18140 | #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 | ||
| 18141 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 | ||
| 18142 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 | ||
| 18143 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc | ||
| 18144 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 | ||
| 18145 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 | ||
| 18146 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 | ||
| 18147 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40 | ||
| 18148 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 | ||
| 18149 | #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 | ||
| 18150 | #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 | ||
| 18151 | #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 | ||
| 18152 | #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa | ||
| 18153 | #define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800 | ||
| 18154 | #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb | ||
| 18155 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff | ||
| 18156 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 | ||
| 18157 | #define IA_ENHANCE__MISC_MASK 0xffffffff | ||
| 18158 | #define IA_ENHANCE__MISC__SHIFT 0x0 | ||
| 18159 | #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff | ||
| 18160 | #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 | ||
| 18161 | #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff | ||
| 18162 | #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 | ||
| 18163 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f | ||
| 18164 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 | ||
| 18165 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff | ||
| 18166 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 | ||
| 18167 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 | ||
| 18168 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 | ||
| 18169 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 | ||
| 18170 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 | ||
| 18171 | #define VGT_IMMED_DATA__DATA_MASK 0xffffffff | ||
| 18172 | #define VGT_IMMED_DATA__DATA__SHIFT 0x0 | ||
| 18173 | #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 | ||
| 18174 | #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 | ||
| 18175 | #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff | ||
| 18176 | #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 | ||
| 18177 | #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff | ||
| 18178 | #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 | ||
| 18179 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f | ||
| 18180 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 | ||
| 18181 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 | ||
| 18182 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 | ||
| 18183 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 | ||
| 18184 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 | ||
| 18185 | #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff | ||
| 18186 | #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 | ||
| 18187 | #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 | ||
| 18188 | #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 | ||
| 18189 | #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 | ||
| 18190 | #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 | ||
| 18191 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff | ||
| 18192 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 | ||
| 18193 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff | ||
| 18194 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 | ||
| 18195 | #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff | ||
| 18196 | #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 | ||
| 18197 | #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff | ||
| 18198 | #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 | ||
| 18199 | #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff | ||
| 18200 | #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 | ||
| 18201 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff | ||
| 18202 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 | ||
| 18203 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f | ||
| 18204 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 | ||
| 18205 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff | ||
| 18206 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 | ||
| 18207 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 | ||
| 18208 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 | ||
| 18209 | #define VGT_ENHANCE__MISC_MASK 0xffffffff | ||
| 18210 | #define VGT_ENHANCE__MISC__SHIFT 0x0 | ||
| 18211 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 | ||
| 18212 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 | ||
| 18213 | #define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 | ||
| 18214 | #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 | ||
| 18215 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff | ||
| 18216 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 | ||
| 18217 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff | ||
| 18218 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 | ||
| 18219 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff | ||
| 18220 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 | ||
| 18221 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f | ||
| 18222 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 | ||
| 18223 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 | ||
| 18224 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe | ||
| 18225 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 | ||
| 18226 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf | ||
| 18227 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 | ||
| 18228 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 | ||
| 18229 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf | ||
| 18230 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 | ||
| 18231 | #define VGT_GROUP_DECR__DECR_MASK 0xf | ||
| 18232 | #define VGT_GROUP_DECR__DECR__SHIFT 0x0 | ||
| 18233 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 | ||
| 18234 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 | ||
| 18235 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 | ||
| 18236 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 | ||
| 18237 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 | ||
| 18238 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 | ||
| 18239 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 | ||
| 18240 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 | ||
| 18241 | #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 | ||
| 18242 | #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 | ||
| 18243 | #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 | ||
| 18244 | #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 | ||
| 18245 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 | ||
| 18246 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 | ||
| 18247 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 | ||
| 18248 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 | ||
| 18249 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 | ||
| 18250 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 | ||
| 18251 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 | ||
| 18252 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 | ||
| 18253 | #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 | ||
| 18254 | #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 | ||
| 18255 | #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 | ||
| 18256 | #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 | ||
| 18257 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf | ||
| 18258 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 | ||
| 18259 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 | ||
| 18260 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 | ||
| 18261 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 | ||
| 18262 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 | ||
| 18263 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 | ||
| 18264 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc | ||
| 18265 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 | ||
| 18266 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 | ||
| 18267 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 | ||
| 18268 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 | ||
| 18269 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 | ||
| 18270 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 | ||
| 18271 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 | ||
| 18272 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c | ||
| 18273 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf | ||
| 18274 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 | ||
| 18275 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 | ||
| 18276 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 | ||
| 18277 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 | ||
| 18278 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 | ||
| 18279 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 | ||
| 18280 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc | ||
| 18281 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 | ||
| 18282 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 | ||
| 18283 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 | ||
| 18284 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 | ||
| 18285 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 | ||
| 18286 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 | ||
| 18287 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 | ||
| 18288 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c | ||
| 18289 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff | ||
| 18290 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 | ||
| 18291 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff | ||
| 18292 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 | ||
| 18293 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x7fe00 | ||
| 18294 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 | ||
| 18295 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f | ||
| 18296 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 | ||
| 18297 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f | ||
| 18298 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 | ||
| 18299 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 | ||
| 18300 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 | ||
| 18301 | #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 | ||
| 18302 | #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 | ||
| 18303 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 | ||
| 18304 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 | ||
| 18305 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 | ||
| 18306 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 | ||
| 18307 | #define VGT_GS_MODE__MODE_MASK 0x7 | ||
| 18308 | #define VGT_GS_MODE__MODE__SHIFT 0x0 | ||
| 18309 | #define VGT_GS_MODE__RESERVED_0_MASK 0x8 | ||
| 18310 | #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 | ||
| 18311 | #define VGT_GS_MODE__CUT_MODE_MASK 0x30 | ||
| 18312 | #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 | ||
| 18313 | #define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 | ||
| 18314 | #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 | ||
| 18315 | #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 | ||
| 18316 | #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb | ||
| 18317 | #define VGT_GS_MODE__RESERVED_2_MASK 0x1000 | ||
| 18318 | #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc | ||
| 18319 | #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 | ||
| 18320 | #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd | ||
| 18321 | #define VGT_GS_MODE__RESERVED_3_MASK 0x4000 | ||
| 18322 | #define VGT_GS_MODE__RESERVED_3__SHIFT 0xe | ||
| 18323 | #define VGT_GS_MODE__RESERVED_4_MASK 0x8000 | ||
| 18324 | #define VGT_GS_MODE__RESERVED_4__SHIFT 0xf | ||
| 18325 | #define VGT_GS_MODE__RESERVED_5_MASK 0x10000 | ||
| 18326 | #define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 | ||
| 18327 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 | ||
| 18328 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 | ||
| 18329 | #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 | ||
| 18330 | #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 | ||
| 18331 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 | ||
| 18332 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 | ||
| 18333 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 | ||
| 18334 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 | ||
| 18335 | #define VGT_GS_MODE__ONCHIP_MASK 0x600000 | ||
| 18336 | #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 | ||
| 18337 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff | ||
| 18338 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 | ||
| 18339 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 | ||
| 18340 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb | ||
| 18341 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f | ||
| 18342 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 | ||
| 18343 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 | ||
| 18344 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 | ||
| 18345 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 | ||
| 18346 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 | ||
| 18347 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 | ||
| 18348 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 | ||
| 18349 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 | ||
| 18350 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f | ||
| 18351 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 | ||
| 18352 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 | ||
| 18353 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10 | ||
| 18354 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 | ||
| 18355 | #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 | ||
| 18356 | #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 | ||
| 18357 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 | ||
| 18358 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 | ||
| 18359 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 | ||
| 18360 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 | ||
| 18361 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 | ||
| 18362 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb | ||
| 18363 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 | ||
| 18364 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc | ||
| 18365 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 | ||
| 18366 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd | ||
| 18367 | #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 | ||
| 18368 | #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 | ||
| 18369 | #define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 | ||
| 18370 | #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 | ||
| 18371 | #define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 | ||
| 18372 | #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 | ||
| 18373 | #define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 | ||
| 18374 | #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 | ||
| 18375 | #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff | ||
| 18376 | #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 | ||
| 18377 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 | ||
| 18378 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 | ||
| 18379 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 | ||
| 18380 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb | ||
| 18381 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 | ||
| 18382 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe | ||
| 18383 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 | ||
| 18384 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 | ||
| 18385 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f | ||
| 18386 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 | ||
| 18387 | #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 | ||
| 18388 | #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 | ||
| 18389 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 | ||
| 18390 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 | ||
| 18391 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000 | ||
| 18392 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 | ||
| 18393 | #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff | ||
| 18394 | #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 | ||
| 18395 | #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff | ||
| 18396 | #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 | ||
| 18397 | #define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf | ||
| 18398 | #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 | ||
| 18399 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f | ||
| 18400 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 | ||
| 18401 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 | ||
| 18402 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 | ||
| 18403 | #define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 | ||
| 18404 | #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 | ||
| 18405 | #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 | ||
| 18406 | #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 | ||
| 18407 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 | ||
| 18408 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 | ||
| 18409 | #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 | ||
| 18410 | #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 | ||
| 18411 | #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 | ||
| 18412 | #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 | ||
| 18413 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 | ||
| 18414 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 | ||
| 18415 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 | ||
| 18416 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 | ||
| 18417 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 | ||
| 18418 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 | ||
| 18419 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 | ||
| 18420 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 | ||
| 18421 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 | ||
| 18422 | #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 | ||
| 18423 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 | ||
| 18424 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 | ||
| 18425 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 | ||
| 18426 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f | ||
| 18427 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff | ||
| 18428 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 | ||
| 18429 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff | ||
| 18430 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 | ||
| 18431 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff | ||
| 18432 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 | ||
| 18433 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff | ||
| 18434 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 | ||
| 18435 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff | ||
| 18436 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 | ||
| 18437 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff | ||
| 18438 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 | ||
| 18439 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff | ||
| 18440 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 | ||
| 18441 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff | ||
| 18442 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 | ||
| 18443 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff | ||
| 18444 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 | ||
| 18445 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff | ||
| 18446 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 | ||
| 18447 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff | ||
| 18448 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 | ||
| 18449 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff | ||
| 18450 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 | ||
| 18451 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf | ||
| 18452 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 | ||
| 18453 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 | ||
| 18454 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 | ||
| 18455 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 | ||
| 18456 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 | ||
| 18457 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 | ||
| 18458 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc | ||
| 18459 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff | ||
| 18460 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 | ||
| 18461 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff | ||
| 18462 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 | ||
| 18463 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff | ||
| 18464 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 | ||
| 18465 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff | ||
| 18466 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 | ||
| 18467 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff | ||
| 18468 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 | ||
| 18469 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff | ||
| 18470 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 | ||
| 18471 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff | ||
| 18472 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 | ||
| 18473 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff | ||
| 18474 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 | ||
| 18475 | #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 | ||
| 18476 | #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 | ||
| 18477 | #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 | ||
| 18478 | #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 | ||
| 18479 | #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 | ||
| 18480 | #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 | ||
| 18481 | #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 | ||
| 18482 | #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 | ||
| 18483 | #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 | ||
| 18484 | #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 | ||
| 18485 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 | ||
| 18486 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 | ||
| 18487 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200 | ||
| 18488 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 | ||
| 18489 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400 | ||
| 18490 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa | ||
| 18491 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800 | ||
| 18492 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb | ||
| 18493 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000 | ||
| 18494 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc | ||
| 18495 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff | ||
| 18496 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 | ||
| 18497 | #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff | ||
| 18498 | #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 | ||
| 18499 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 | ||
| 18500 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 | ||
| 18501 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 | ||
| 18502 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe | ||
| 18503 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 | ||
| 18504 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 | ||
| 18505 | #define VGT_TF_PARAM__TYPE_MASK 0x3 | ||
| 18506 | #define VGT_TF_PARAM__TYPE__SHIFT 0x0 | ||
| 18507 | #define VGT_TF_PARAM__PARTITIONING_MASK 0x1c | ||
| 18508 | #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 | ||
| 18509 | #define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 | ||
| 18510 | #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 | ||
| 18511 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 | ||
| 18512 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 | ||
| 18513 | #define VGT_TF_PARAM__DEPRECATED_MASK 0x200 | ||
| 18514 | #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 | ||
| 18515 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 | ||
| 18516 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa | ||
| 18517 | #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 | ||
| 18518 | #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe | ||
| 18519 | #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000 | ||
| 18520 | #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf | ||
| 18521 | #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000 | ||
| 18522 | #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 | ||
| 18523 | #define VGT_TF_PARAM__MTYPE_MASK 0x180000 | ||
| 18524 | #define VGT_TF_PARAM__MTYPE__SHIFT 0x13 | ||
| 18525 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff | ||
| 18526 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 | ||
| 18527 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00 | ||
| 18528 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 | ||
| 18529 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 | ||
| 18530 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 | ||
| 18531 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000 | ||
| 18532 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 | ||
| 18533 | #define VGT_TF_RING_SIZE__SIZE_MASK 0xffff | ||
| 18534 | #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 | ||
| 18535 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 | ||
| 18536 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 | ||
| 18537 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e | ||
| 18538 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 | ||
| 18539 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 | ||
| 18540 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 | ||
| 18541 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff | ||
| 18542 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 | ||
| 18543 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 | ||
| 18544 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 | ||
| 18545 | #define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff | ||
| 18546 | #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 | ||
| 18547 | #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 | ||
| 18548 | #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 | ||
| 18549 | #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc | ||
| 18550 | #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 | ||
| 18551 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff | ||
| 18552 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 | ||
| 18553 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 | ||
| 18554 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 | ||
| 18555 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 | ||
| 18556 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 | ||
| 18557 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 | ||
| 18558 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 | ||
| 18559 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 | ||
| 18560 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 | ||
| 18561 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 | ||
| 18562 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 | ||
| 18563 | #define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000 | ||
| 18564 | #define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c | ||
| 18565 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff | ||
| 18566 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 | ||
| 18567 | #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff | ||
| 18568 | #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 | ||
| 18569 | #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff | ||
| 18570 | #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 | ||
| 18571 | #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff | ||
| 18572 | #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 | ||
| 18573 | #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff | ||
| 18574 | #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 | ||
| 18575 | #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff | ||
| 18576 | #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 | ||
| 18577 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff | ||
| 18578 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 | ||
| 18579 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff | ||
| 18580 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 | ||
| 18581 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff | ||
| 18582 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 | ||
| 18583 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff | ||
| 18584 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 | ||
| 18585 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff | ||
| 18586 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 | ||
| 18587 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff | ||
| 18588 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 | ||
| 18589 | #define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 | ||
| 18590 | #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 | ||
| 18591 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 | ||
| 18592 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 | ||
| 18593 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 | ||
| 18594 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 | ||
| 18595 | #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 | ||
| 18596 | #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 | ||
| 18597 | #define WD_ENHANCE__MISC_MASK 0xffffffff | ||
| 18598 | #define WD_ENHANCE__MISC__SHIFT 0x0 | ||
| 18599 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff | ||
| 18600 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 | ||
| 18601 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 | ||
| 18602 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd | ||
| 18603 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 | ||
| 18604 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 | ||
| 18605 | #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 18606 | #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 18607 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 18608 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 18609 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 18610 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 18611 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 | ||
| 18612 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 | ||
| 18613 | #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 | ||
| 18614 | #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a | ||
| 18615 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 18616 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 18617 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000 | ||
| 18618 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c | ||
| 18619 | #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 | ||
| 18620 | #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d | ||
| 18621 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 | ||
| 18622 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e | ||
| 18623 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 18624 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 18625 | #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 18626 | #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 18627 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 18628 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 18629 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 18630 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 18631 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 | ||
| 18632 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 | ||
| 18633 | #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 | ||
| 18634 | #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a | ||
| 18635 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 18636 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 18637 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 | ||
| 18638 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c | ||
| 18639 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 | ||
| 18640 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d | ||
| 18641 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 | ||
| 18642 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e | ||
| 18643 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 18644 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 18645 | #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf | ||
| 18646 | #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 | ||
| 18647 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 | ||
| 18648 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 | ||
| 18649 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 | ||
| 18650 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 | ||
| 18651 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 | ||
| 18652 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 | ||
| 18653 | #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 | ||
| 18654 | #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a | ||
| 18655 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 | ||
| 18656 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b | ||
| 18657 | #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000 | ||
| 18658 | #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c | ||
| 18659 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 | ||
| 18660 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d | ||
| 18661 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 | ||
| 18662 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e | ||
| 18663 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 | ||
| 18664 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f | ||
| 18665 | #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f | ||
| 18666 | #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 | ||
| 18667 | #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 | ||
| 18668 | #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 | ||
| 18669 | #define VGT_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 18670 | #define VGT_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 18671 | #define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f | ||
| 18672 | #define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 | ||
| 18673 | #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 | ||
| 18674 | #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 | ||
| 18675 | #define IA_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 18676 | #define IA_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 18677 | #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 | ||
| 18678 | #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 | ||
| 18679 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 | ||
| 18680 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 | ||
| 18681 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 | ||
| 18682 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 | ||
| 18683 | #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 | ||
| 18684 | #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 | ||
| 18685 | #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 | ||
| 18686 | #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 | ||
| 18687 | #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 | ||
| 18688 | #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 | ||
| 18689 | #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 | ||
| 18690 | #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 | ||
| 18691 | #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 | ||
| 18692 | #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 | ||
| 18693 | #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 | ||
| 18694 | #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 | ||
| 18695 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 | ||
| 18696 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 | ||
| 18697 | #define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f | ||
| 18698 | #define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 | ||
| 18699 | #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 | ||
| 18700 | #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 | ||
| 18701 | #define WD_DEBUG_DATA__DATA_MASK 0xffffffff | ||
| 18702 | #define WD_DEBUG_DATA__DATA__SHIFT 0x0 | ||
| 18703 | #define WD_QOS__DRAW_STALL_MASK 0x1 | ||
| 18704 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 | ||
| 18705 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 | ||
| 18706 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 | ||
| 18707 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 | ||
| 18708 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 | ||
| 18709 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 | ||
| 18710 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 | ||
| 18711 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 | ||
| 18712 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 | ||
| 18713 | #define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 | ||
| 18714 | #define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 | ||
| 18715 | #define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 | ||
| 18716 | #define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 | ||
| 18717 | #define WD_DEBUG_REG0__wd_busy_MASK 0x4 | ||
| 18718 | #define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 | ||
| 18719 | #define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 | ||
| 18720 | #define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 | ||
| 18721 | #define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 | ||
| 18722 | #define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 | ||
| 18723 | #define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 | ||
| 18724 | #define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 | ||
| 18725 | #define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 | ||
| 18726 | #define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 | ||
| 18727 | #define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 | ||
| 18728 | #define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 | ||
| 18729 | #define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 | ||
| 18730 | #define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 | ||
| 18731 | #define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 | ||
| 18732 | #define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 | ||
| 18733 | #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 | ||
| 18734 | #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa | ||
| 18735 | #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 | ||
| 18736 | #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb | ||
| 18737 | #define WD_DEBUG_REG0__SPARE2_MASK 0x1000 | ||
| 18738 | #define WD_DEBUG_REG0__SPARE2__SHIFT 0xc | ||
| 18739 | #define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 | ||
| 18740 | #define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd | ||
| 18741 | #define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 | ||
| 18742 | #define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe | ||
| 18743 | #define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 | ||
| 18744 | #define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf | ||
| 18745 | #define WD_DEBUG_REG0__SPARE3_MASK 0x10000 | ||
| 18746 | #define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 | ||
| 18747 | #define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 | ||
| 18748 | #define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 | ||
| 18749 | #define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 | ||
| 18750 | #define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 | ||
| 18751 | #define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 | ||
| 18752 | #define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 | ||
| 18753 | #define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 | ||
| 18754 | #define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 | ||
| 18755 | #define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 | ||
| 18756 | #define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 | ||
| 18757 | #define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 | ||
| 18758 | #define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 | ||
| 18759 | #define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 | ||
| 18760 | #define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 | ||
| 18761 | #define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 | ||
| 18762 | #define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 | ||
| 18763 | #define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 | ||
| 18764 | #define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 | ||
| 18765 | #define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 | ||
| 18766 | #define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a | ||
| 18767 | #define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 | ||
| 18768 | #define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b | ||
| 18769 | #define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 | ||
| 18770 | #define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c | ||
| 18771 | #define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 | ||
| 18772 | #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d | ||
| 18773 | #define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 | ||
| 18774 | #define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e | ||
| 18775 | #define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 | ||
| 18776 | #define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f | ||
| 18777 | #define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 | ||
| 18778 | #define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 | ||
| 18779 | #define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 | ||
| 18780 | #define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 | ||
| 18781 | #define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 | ||
| 18782 | #define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 | ||
| 18783 | #define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 | ||
| 18784 | #define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 | ||
| 18785 | #define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 | ||
| 18786 | #define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 | ||
| 18787 | #define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 | ||
| 18788 | #define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 | ||
| 18789 | #define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 | ||
| 18790 | #define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 | ||
| 18791 | #define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 | ||
| 18792 | #define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 | ||
| 18793 | #define WD_DEBUG_REG1__SPARE0_MASK 0x100 | ||
| 18794 | #define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 | ||
| 18795 | #define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 | ||
| 18796 | #define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 | ||
| 18797 | #define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 | ||
| 18798 | #define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa | ||
| 18799 | #define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 | ||
| 18800 | #define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb | ||
| 18801 | #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 | ||
| 18802 | #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc | ||
| 18803 | #define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 | ||
| 18804 | #define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 | ||
| 18805 | #define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 | ||
| 18806 | #define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 | ||
| 18807 | #define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 | ||
| 18808 | #define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a | ||
| 18809 | #define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 | ||
| 18810 | #define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b | ||
| 18811 | #define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 | ||
| 18812 | #define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c | ||
| 18813 | #define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 | ||
| 18814 | #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d | ||
| 18815 | #define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 | ||
| 18816 | #define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e | ||
| 18817 | #define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 | ||
| 18818 | #define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f | ||
| 18819 | #define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 | ||
| 18820 | #define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 | ||
| 18821 | #define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 | ||
| 18822 | #define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 | ||
| 18823 | #define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 | ||
| 18824 | #define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 | ||
| 18825 | #define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 | ||
| 18826 | #define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 | ||
| 18827 | #define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 | ||
| 18828 | #define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 | ||
| 18829 | #define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 | ||
| 18830 | #define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 | ||
| 18831 | #define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 | ||
| 18832 | #define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 | ||
| 18833 | #define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 | ||
| 18834 | #define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 | ||
| 18835 | #define WD_DEBUG_REG2__SPARE0_MASK 0x100 | ||
| 18836 | #define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 | ||
| 18837 | #define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 | ||
| 18838 | #define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 | ||
| 18839 | #define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 | ||
| 18840 | #define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa | ||
| 18841 | #define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 | ||
| 18842 | #define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb | ||
| 18843 | #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 | ||
| 18844 | #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc | ||
| 18845 | #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 | ||
| 18846 | #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 | ||
| 18847 | #define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 | ||
| 18848 | #define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 | ||
| 18849 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 | ||
| 18850 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a | ||
| 18851 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 | ||
| 18852 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b | ||
| 18853 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 | ||
| 18854 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c | ||
| 18855 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 | ||
| 18856 | #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d | ||
| 18857 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 | ||
| 18858 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e | ||
| 18859 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 | ||
| 18860 | #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f | ||
| 18861 | #define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 | ||
| 18862 | #define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 | ||
| 18863 | #define WD_DEBUG_REG3__SPARE0_MASK 0x2 | ||
| 18864 | #define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 | ||
| 18865 | #define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 | ||
| 18866 | #define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 | ||
| 18867 | #define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 | ||
| 18868 | #define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 | ||
| 18869 | #define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 | ||
| 18870 | #define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 | ||
| 18871 | #define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 | ||
| 18872 | #define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 | ||
| 18873 | #define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 | ||
| 18874 | #define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 | ||
| 18875 | #define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 | ||
| 18876 | #define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 | ||
| 18877 | #define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 | ||
| 18878 | #define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 | ||
| 18879 | #define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 | ||
| 18880 | #define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa | ||
| 18881 | #define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 | ||
| 18882 | #define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb | ||
| 18883 | #define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 | ||
| 18884 | #define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc | ||
| 18885 | #define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 | ||
| 18886 | #define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd | ||
| 18887 | #define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 | ||
| 18888 | #define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe | ||
| 18889 | #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 | ||
| 18890 | #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf | ||
| 18891 | #define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 | ||
| 18892 | #define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 | ||
| 18893 | #define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 | ||
| 18894 | #define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 | ||
| 18895 | #define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 | ||
| 18896 | #define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 | ||
| 18897 | #define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 | ||
| 18898 | #define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 | ||
| 18899 | #define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 | ||
| 18900 | #define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 | ||
| 18901 | #define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 | ||
| 18902 | #define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 | ||
| 18903 | #define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 | ||
| 18904 | #define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 | ||
| 18905 | #define WD_DEBUG_REG3__SPARE1_MASK 0x800000 | ||
| 18906 | #define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 | ||
| 18907 | #define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 | ||
| 18908 | #define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 | ||
| 18909 | #define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 | ||
| 18910 | #define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 | ||
| 18911 | #define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 | ||
| 18912 | #define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a | ||
| 18913 | #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 | ||
| 18914 | #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b | ||
| 18915 | #define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 | ||
| 18916 | #define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c | ||
| 18917 | #define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 | ||
| 18918 | #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d | ||
| 18919 | #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 | ||
| 18920 | #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e | ||
| 18921 | #define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 | ||
| 18922 | #define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f | ||
| 18923 | #define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 | ||
| 18924 | #define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 | ||
| 18925 | #define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 | ||
| 18926 | #define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 | ||
| 18927 | #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 | ||
| 18928 | #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 | ||
| 18929 | #define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 | ||
| 18930 | #define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 | ||
| 18931 | #define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 | ||
| 18932 | #define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 | ||
| 18933 | #define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 | ||
| 18934 | #define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 | ||
| 18935 | #define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 | ||
| 18936 | #define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 | ||
| 18937 | #define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 | ||
| 18938 | #define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 | ||
| 18939 | #define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 | ||
| 18940 | #define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 | ||
| 18941 | #define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 | ||
| 18942 | #define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 | ||
| 18943 | #define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 | ||
| 18944 | #define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa | ||
| 18945 | #define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 | ||
| 18946 | #define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb | ||
| 18947 | #define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 | ||
| 18948 | #define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc | ||
| 18949 | #define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 | ||
| 18950 | #define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd | ||
| 18951 | #define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 | ||
| 18952 | #define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe | ||
| 18953 | #define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 | ||
| 18954 | #define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 | ||
| 18955 | #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 | ||
| 18956 | #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 | ||
| 18957 | #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 | ||
| 18958 | #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 | ||
| 18959 | #define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 | ||
| 18960 | #define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 | ||
| 18961 | #define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 | ||
| 18962 | #define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 | ||
| 18963 | #define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 | ||
| 18964 | #define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 | ||
| 18965 | #define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 | ||
| 18966 | #define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 | ||
| 18967 | #define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 | ||
| 18968 | #define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 | ||
| 18969 | #define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 | ||
| 18970 | #define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a | ||
| 18971 | #define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 | ||
| 18972 | #define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b | ||
| 18973 | #define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 | ||
| 18974 | #define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c | ||
| 18975 | #define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 | ||
| 18976 | #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d | ||
| 18977 | #define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 | ||
| 18978 | #define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e | ||
| 18979 | #define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 | ||
| 18980 | #define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f | ||
| 18981 | #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 | ||
| 18982 | #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 | ||
| 18983 | #define WD_DEBUG_REG5__SPARE0_MASK 0x2 | ||
| 18984 | #define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 | ||
| 18985 | #define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 | ||
| 18986 | #define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 | ||
| 18987 | #define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 | ||
| 18988 | #define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 | ||
| 18989 | #define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 | ||
| 18990 | #define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 | ||
| 18991 | #define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 | ||
| 18992 | #define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 | ||
| 18993 | #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 | ||
| 18994 | #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 | ||
| 18995 | #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 | ||
| 18996 | #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 | ||
| 18997 | #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 | ||
| 18998 | #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 | ||
| 18999 | #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 | ||
| 19000 | #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa | ||
| 19001 | #define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 | ||
| 19002 | #define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb | ||
| 19003 | #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 | ||
| 19004 | #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc | ||
| 19005 | #define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 | ||
| 19006 | #define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd | ||
| 19007 | #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 | ||
| 19008 | #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe | ||
| 19009 | #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 | ||
| 19010 | #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf | ||
| 19011 | #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 | ||
| 19012 | #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 | ||
| 19013 | #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 | ||
| 19014 | #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 | ||
| 19015 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 | ||
| 19016 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 | ||
| 19017 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 | ||
| 19018 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 | ||
| 19019 | #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 | ||
| 19020 | #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 | ||
| 19021 | #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 | ||
| 19022 | #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 | ||
| 19023 | #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 | ||
| 19024 | #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 | ||
| 19025 | #define WD_DEBUG_REG5__SPARE1_MASK 0x800000 | ||
| 19026 | #define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 | ||
| 19027 | #define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 | ||
| 19028 | #define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 | ||
| 19029 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 | ||
| 19030 | #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 | ||
| 19031 | #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 | ||
| 19032 | #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a | ||
| 19033 | #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 | ||
| 19034 | #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b | ||
| 19035 | #define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 | ||
| 19036 | #define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c | ||
| 19037 | #define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 | ||
| 19038 | #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d | ||
| 19039 | #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 | ||
| 19040 | #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e | ||
| 19041 | #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 | ||
| 19042 | #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f | ||
| 19043 | #define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff | ||
| 19044 | #define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0 | ||
| 19045 | #define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1 | ||
| 19046 | #define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0 | ||
| 19047 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2 | ||
| 19048 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1 | ||
| 19049 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4 | ||
| 19050 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2 | ||
| 19051 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8 | ||
| 19052 | #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3 | ||
| 19053 | #define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in_MASK 0x10 | ||
| 19054 | #define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in__SHIFT 0x4 | ||
| 19055 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re_MASK 0x20 | ||
| 19056 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re__SHIFT 0x5 | ||
| 19057 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty_MASK 0x40 | ||
| 19058 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty__SHIFT 0x6 | ||
| 19059 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full_MASK 0x80 | ||
| 19060 | #define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full__SHIFT 0x7 | ||
| 19061 | #define WD_DEBUG_REG7__SPARE1_MASK 0xf00 | ||
| 19062 | #define WD_DEBUG_REG7__SPARE1__SHIFT 0x8 | ||
| 19063 | #define WD_DEBUG_REG7__SPARE2_MASK 0xf000 | ||
| 19064 | #define WD_DEBUG_REG7__SPARE2__SHIFT 0xc | ||
| 19065 | #define WD_DEBUG_REG7__te11_arb_state_q_MASK 0x70000 | ||
| 19066 | #define WD_DEBUG_REG7__te11_arb_state_q__SHIFT 0x10 | ||
| 19067 | #define WD_DEBUG_REG7__SPARE5_MASK 0x80000 | ||
| 19068 | #define WD_DEBUG_REG7__SPARE5__SHIFT 0x13 | ||
| 19069 | #define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000 | ||
| 19070 | #define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14 | ||
| 19071 | #define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000 | ||
| 19072 | #define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15 | ||
| 19073 | #define WD_DEBUG_REG7__se1_thdgrp_is_event_MASK 0x400000 | ||
| 19074 | #define WD_DEBUG_REG7__se1_thdgrp_is_event__SHIFT 0x16 | ||
| 19075 | #define WD_DEBUG_REG7__se1_thdgrp_eop_MASK 0x800000 | ||
| 19076 | #define WD_DEBUG_REG7__se1_thdgrp_eop__SHIFT 0x17 | ||
| 19077 | #define WD_DEBUG_REG7__SPARE6_MASK 0xf000000 | ||
| 19078 | #define WD_DEBUG_REG7__SPARE6__SHIFT 0x18 | ||
| 19079 | #define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000 | ||
| 19080 | #define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c | ||
| 19081 | #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000 | ||
| 19082 | #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d | ||
| 19083 | #define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000 | ||
| 19084 | #define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e | ||
| 19085 | #define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000 | ||
| 19086 | #define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f | ||
| 19087 | #define WD_DEBUG_REG8__pipe0_dr_MASK 0x1 | ||
| 19088 | #define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0 | ||
| 19089 | #define WD_DEBUG_REG8__pipe1_dr_MASK 0x2 | ||
| 19090 | #define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1 | ||
| 19091 | #define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4 | ||
| 19092 | #define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2 | ||
| 19093 | #define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8 | ||
| 19094 | #define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3 | ||
| 19095 | #define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10 | ||
| 19096 | #define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4 | ||
| 19097 | #define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20 | ||
| 19098 | #define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5 | ||
| 19099 | #define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40 | ||
| 19100 | #define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6 | ||
| 19101 | #define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80 | ||
| 19102 | #define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7 | ||
| 19103 | #define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100 | ||
| 19104 | #define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8 | ||
| 19105 | #define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200 | ||
| 19106 | #define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9 | ||
| 19107 | #define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400 | ||
| 19108 | #define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa | ||
| 19109 | #define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800 | ||
| 19110 | #define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb | ||
| 19111 | #define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000 | ||
| 19112 | #define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc | ||
| 19113 | #define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000 | ||
| 19114 | #define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12 | ||
| 19115 | #define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000 | ||
| 19116 | #define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13 | ||
| 19117 | #define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000 | ||
| 19118 | #define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14 | ||
| 19119 | #define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000 | ||
| 19120 | #define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b | ||
| 19121 | #define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000 | ||
| 19122 | #define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c | ||
| 19123 | #define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000 | ||
| 19124 | #define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d | ||
| 19125 | #define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000 | ||
| 19126 | #define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e | ||
| 19127 | #define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000 | ||
| 19128 | #define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f | ||
| 19129 | #define WD_DEBUG_REG9__pipe0_dr_MASK 0x1 | ||
| 19130 | #define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0 | ||
| 19131 | #define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2 | ||
| 19132 | #define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1 | ||
| 19133 | #define WD_DEBUG_REG9__pipe2_dr_MASK 0x4 | ||
| 19134 | #define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2 | ||
| 19135 | #define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8 | ||
| 19136 | #define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3 | ||
| 19137 | #define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10 | ||
| 19138 | #define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4 | ||
| 19139 | #define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20 | ||
| 19140 | #define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5 | ||
| 19141 | #define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40 | ||
| 19142 | #define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6 | ||
| 19143 | #define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80 | ||
| 19144 | #define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7 | ||
| 19145 | #define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100 | ||
| 19146 | #define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8 | ||
| 19147 | #define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200 | ||
| 19148 | #define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9 | ||
| 19149 | #define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400 | ||
| 19150 | #define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa | ||
| 19151 | #define WD_DEBUG_REG9__SPARE0_MASK 0xf800 | ||
| 19152 | #define WD_DEBUG_REG9__SPARE0__SHIFT 0xb | ||
| 19153 | #define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000 | ||
| 19154 | #define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10 | ||
| 19155 | #define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000 | ||
| 19156 | #define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13 | ||
| 19157 | #define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000 | ||
| 19158 | #define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14 | ||
| 19159 | #define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000 | ||
| 19160 | #define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18 | ||
| 19161 | #define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000 | ||
| 19162 | #define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19 | ||
| 19163 | #define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000 | ||
| 19164 | #define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a | ||
| 19165 | #define WD_DEBUG_REG9__SPARE1_MASK 0x8000000 | ||
| 19166 | #define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b | ||
| 19167 | #define WD_DEBUG_REG9__SPARE2_MASK 0x30000000 | ||
| 19168 | #define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c | ||
| 19169 | #define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000 | ||
| 19170 | #define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e | ||
| 19171 | #define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000 | ||
| 19172 | #define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f | ||
| 19173 | #define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1 | ||
| 19174 | #define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0 | ||
| 19175 | #define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2 | ||
| 19176 | #define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1 | ||
| 19177 | #define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4 | ||
| 19178 | #define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2 | ||
| 19179 | #define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8 | ||
| 19180 | #define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3 | ||
| 19181 | #define WD_DEBUG_REG10__pipe0_dr_MASK 0x10 | ||
| 19182 | #define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4 | ||
| 19183 | #define WD_DEBUG_REG10__pipe1_dr_MASK 0x20 | ||
| 19184 | #define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5 | ||
| 19185 | #define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40 | ||
| 19186 | #define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6 | ||
| 19187 | #define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80 | ||
| 19188 | #define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7 | ||
| 19189 | #define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100 | ||
| 19190 | #define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8 | ||
| 19191 | #define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200 | ||
| 19192 | #define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9 | ||
| 19193 | #define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400 | ||
| 19194 | #define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa | ||
| 19195 | #define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800 | ||
| 19196 | #define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb | ||
| 19197 | #define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000 | ||
| 19198 | #define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc | ||
| 19199 | #define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000 | ||
| 19200 | #define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd | ||
| 19201 | #define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000 | ||
| 19202 | #define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe | ||
| 19203 | #define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000 | ||
| 19204 | #define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf | ||
| 19205 | #define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000 | ||
| 19206 | #define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10 | ||
| 19207 | #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000 | ||
| 19208 | #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18 | ||
| 19209 | #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000 | ||
| 19210 | #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19 | ||
| 19211 | #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000 | ||
| 19212 | #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a | ||
| 19213 | #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000 | ||
| 19214 | #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b | ||
| 19215 | #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000 | ||
| 19216 | #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c | ||
| 19217 | #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000 | ||
| 19218 | #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d | ||
| 19219 | #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000 | ||
| 19220 | #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e | ||
| 19221 | #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000 | ||
| 19222 | #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f | ||
| 19223 | #define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 | ||
| 19224 | #define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 | ||
| 19225 | #define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 | ||
| 19226 | #define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 | ||
| 19227 | #define IA_DEBUG_REG0__ia_busy_MASK 0x4 | ||
| 19228 | #define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 | ||
| 19229 | #define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 | ||
| 19230 | #define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 | ||
| 19231 | #define IA_DEBUG_REG0__SPARE0_MASK 0x10 | ||
| 19232 | #define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 | ||
| 19233 | #define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 | ||
| 19234 | #define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 | ||
| 19235 | #define IA_DEBUG_REG0__dma_busy_MASK 0x40 | ||
| 19236 | #define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 | ||
| 19237 | #define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 | ||
| 19238 | #define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 | ||
| 19239 | #define IA_DEBUG_REG0__grp_busy_MASK 0x100 | ||
| 19240 | #define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 | ||
| 19241 | #define IA_DEBUG_REG0__SPARE1_MASK 0x200 | ||
| 19242 | #define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 | ||
| 19243 | #define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 | ||
| 19244 | #define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa | ||
| 19245 | #define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 | ||
| 19246 | #define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb | ||
| 19247 | #define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 | ||
| 19248 | #define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc | ||
| 19249 | #define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 | ||
| 19250 | #define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd | ||
| 19251 | #define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 | ||
| 19252 | #define IA_DEBUG_REG0__SPARE2__SHIFT 0xe | ||
| 19253 | #define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 | ||
| 19254 | #define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 | ||
| 19255 | #define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 | ||
| 19256 | #define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 | ||
| 19257 | #define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 | ||
| 19258 | #define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a | ||
| 19259 | #define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 | ||
| 19260 | #define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b | ||
| 19261 | #define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 | ||
| 19262 | #define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c | ||
| 19263 | #define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 | ||
| 19264 | #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d | ||
| 19265 | #define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 | ||
| 19266 | #define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e | ||
| 19267 | #define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 | ||
| 19268 | #define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f | ||
| 19269 | #define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 | ||
| 19270 | #define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 | ||
| 19271 | #define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 | ||
| 19272 | #define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 | ||
| 19273 | #define IA_DEBUG_REG1__start_new_packet_MASK 0x4 | ||
| 19274 | #define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 | ||
| 19275 | #define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 | ||
| 19276 | #define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 | ||
| 19277 | #define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 | ||
| 19278 | #define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 | ||
| 19279 | #define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 | ||
| 19280 | #define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 | ||
| 19281 | #define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 | ||
| 19282 | #define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 | ||
| 19283 | #define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 | ||
| 19284 | #define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 | ||
| 19285 | #define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 | ||
| 19286 | #define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 | ||
| 19287 | #define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 | ||
| 19288 | #define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa | ||
| 19289 | #define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 | ||
| 19290 | #define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb | ||
| 19291 | #define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 | ||
| 19292 | #define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc | ||
| 19293 | #define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 | ||
| 19294 | #define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd | ||
| 19295 | #define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 | ||
| 19296 | #define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe | ||
| 19297 | #define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 | ||
| 19298 | #define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf | ||
| 19299 | #define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 | ||
| 19300 | #define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 | ||
| 19301 | #define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 | ||
| 19302 | #define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 | ||
| 19303 | #define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 | ||
| 19304 | #define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 | ||
| 19305 | #define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 | ||
| 19306 | #define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 | ||
| 19307 | #define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 | ||
| 19308 | #define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 | ||
| 19309 | #define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 | ||
| 19310 | #define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 | ||
| 19311 | #define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 | ||
| 19312 | #define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 | ||
| 19313 | #define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 | ||
| 19314 | #define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 | ||
| 19315 | #define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 | ||
| 19316 | #define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 | ||
| 19317 | #define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 | ||
| 19318 | #define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 | ||
| 19319 | #define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 | ||
| 19320 | #define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a | ||
| 19321 | #define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 | ||
| 19322 | #define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b | ||
| 19323 | #define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 | ||
| 19324 | #define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c | ||
| 19325 | #define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 | ||
| 19326 | #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d | ||
| 19327 | #define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 | ||
| 19328 | #define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e | ||
| 19329 | #define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 | ||
| 19330 | #define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f | ||
| 19331 | #define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 | ||
| 19332 | #define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 | ||
| 19333 | #define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 | ||
| 19334 | #define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 | ||
| 19335 | #define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 | ||
| 19336 | #define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 | ||
| 19337 | #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 | ||
| 19338 | #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 | ||
| 19339 | #define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 | ||
| 19340 | #define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 | ||
| 19341 | #define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 | ||
| 19342 | #define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 | ||
| 19343 | #define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 | ||
| 19344 | #define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 | ||
| 19345 | #define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 | ||
| 19346 | #define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 | ||
| 19347 | #define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 | ||
| 19348 | #define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 | ||
| 19349 | #define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 | ||
| 19350 | #define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa | ||
| 19351 | #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 | ||
| 19352 | #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb | ||
| 19353 | #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 | ||
| 19354 | #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc | ||
| 19355 | #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 | ||
| 19356 | #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd | ||
| 19357 | #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 | ||
| 19358 | #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe | ||
| 19359 | #define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 | ||
| 19360 | #define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf | ||
| 19361 | #define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 | ||
| 19362 | #define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 | ||
| 19363 | #define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 | ||
| 19364 | #define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 | ||
| 19365 | #define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 | ||
| 19366 | #define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 | ||
| 19367 | #define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 | ||
| 19368 | #define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 | ||
| 19369 | #define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 | ||
| 19370 | #define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 | ||
| 19371 | #define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 | ||
| 19372 | #define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 | ||
| 19373 | #define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 | ||
| 19374 | #define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 | ||
| 19375 | #define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 | ||
| 19376 | #define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 | ||
| 19377 | #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 | ||
| 19378 | #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 | ||
| 19379 | #define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 | ||
| 19380 | #define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 | ||
| 19381 | #define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 | ||
| 19382 | #define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a | ||
| 19383 | #define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 | ||
| 19384 | #define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b | ||
| 19385 | #define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 | ||
| 19386 | #define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c | ||
| 19387 | #define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 | ||
| 19388 | #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d | ||
| 19389 | #define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 | ||
| 19390 | #define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e | ||
| 19391 | #define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 | ||
| 19392 | #define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f | ||
| 19393 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 | ||
| 19394 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 | ||
| 19395 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 | ||
| 19396 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 | ||
| 19397 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 | ||
| 19398 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 | ||
| 19399 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 | ||
| 19400 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 | ||
| 19401 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 | ||
| 19402 | #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 | ||
| 19403 | #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 | ||
| 19404 | #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 | ||
| 19405 | #define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 | ||
| 19406 | #define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 | ||
| 19407 | #define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 | ||
| 19408 | #define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 | ||
| 19409 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 | ||
| 19410 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 | ||
| 19411 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 | ||
| 19412 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 | ||
| 19413 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 | ||
| 19414 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa | ||
| 19415 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 | ||
| 19416 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb | ||
| 19417 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 | ||
| 19418 | #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc | ||
| 19419 | #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 | ||
| 19420 | #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd | ||
| 19421 | #define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 | ||
| 19422 | #define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe | ||
| 19423 | #define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 | ||
| 19424 | #define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf | ||
| 19425 | #define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 | ||
| 19426 | #define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 | ||
| 19427 | #define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 | ||
| 19428 | #define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 | ||
| 19429 | #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 | ||
| 19430 | #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 | ||
| 19431 | #define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 | ||
| 19432 | #define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 | ||
| 19433 | #define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 | ||
| 19434 | #define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 | ||
| 19435 | #define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 | ||
| 19436 | #define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 | ||
| 19437 | #define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 | ||
| 19438 | #define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 | ||
| 19439 | #define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 | ||
| 19440 | #define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 | ||
| 19441 | #define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 | ||
| 19442 | #define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 | ||
| 19443 | #define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 | ||
| 19444 | #define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a | ||
| 19445 | #define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 | ||
| 19446 | #define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b | ||
| 19447 | #define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 | ||
| 19448 | #define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c | ||
| 19449 | #define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 | ||
| 19450 | #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d | ||
| 19451 | #define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 | ||
| 19452 | #define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e | ||
| 19453 | #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 | ||
| 19454 | #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f | ||
| 19455 | #define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 | ||
| 19456 | #define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 | ||
| 19457 | #define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 | ||
| 19458 | #define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 | ||
| 19459 | #define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 | ||
| 19460 | #define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 | ||
| 19461 | #define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 | ||
| 19462 | #define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 | ||
| 19463 | #define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 | ||
| 19464 | #define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 | ||
| 19465 | #define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 | ||
| 19466 | #define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 | ||
| 19467 | #define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 | ||
| 19468 | #define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 | ||
| 19469 | #define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 | ||
| 19470 | #define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 | ||
| 19471 | #define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 | ||
| 19472 | #define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 | ||
| 19473 | #define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 | ||
| 19474 | #define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 | ||
| 19475 | #define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 | ||
| 19476 | #define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa | ||
| 19477 | #define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 | ||
| 19478 | #define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb | ||
| 19479 | #define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 | ||
| 19480 | #define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc | ||
| 19481 | #define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 | ||
| 19482 | #define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd | ||
| 19483 | #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 | ||
| 19484 | #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe | ||
| 19485 | #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 | ||
| 19486 | #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf | ||
| 19487 | #define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 | ||
| 19488 | #define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 | ||
| 19489 | #define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 | ||
| 19490 | #define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 | ||
| 19491 | #define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 | ||
| 19492 | #define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 | ||
| 19493 | #define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 | ||
| 19494 | #define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 | ||
| 19495 | #define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 | ||
| 19496 | #define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 | ||
| 19497 | #define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 | ||
| 19498 | #define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 | ||
| 19499 | #define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 | ||
| 19500 | #define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a | ||
| 19501 | #define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 | ||
| 19502 | #define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c | ||
| 19503 | #define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 | ||
| 19504 | #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d | ||
| 19505 | #define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 | ||
| 19506 | #define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e | ||
| 19507 | #define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 | ||
| 19508 | #define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f | ||
| 19509 | #define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff | ||
| 19510 | #define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 | ||
| 19511 | #define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 | ||
| 19512 | #define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 | ||
| 19513 | #define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 | ||
| 19514 | #define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e | ||
| 19515 | #define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 | ||
| 19516 | #define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f | ||
| 19517 | #define IA_DEBUG_REG6__current_shift_q_MASK 0xf | ||
| 19518 | #define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 | ||
| 19519 | #define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 | ||
| 19520 | #define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 | ||
| 19521 | #define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 | ||
| 19522 | #define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 | ||
| 19523 | #define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 | ||
| 19524 | #define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd | ||
| 19525 | #define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 | ||
| 19526 | #define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe | ||
| 19527 | #define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 | ||
| 19528 | #define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf | ||
| 19529 | #define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 | ||
| 19530 | #define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 | ||
| 19531 | #define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 | ||
| 19532 | #define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 | ||
| 19533 | #define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 | ||
| 19534 | #define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 | ||
| 19535 | #define IA_DEBUG_REG6__extract_group_MASK 0x800000 | ||
| 19536 | #define IA_DEBUG_REG6__extract_group__SHIFT 0x17 | ||
| 19537 | #define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 | ||
| 19538 | #define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 | ||
| 19539 | #define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf | ||
| 19540 | #define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 | ||
| 19541 | #define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 | ||
| 19542 | #define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 | ||
| 19543 | #define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 | ||
| 19544 | #define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 | ||
| 19545 | #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 | ||
| 19546 | #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc | ||
| 19547 | #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 | ||
| 19548 | #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 | ||
| 19549 | #define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 | ||
| 19550 | #define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 | ||
| 19551 | #define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 | ||
| 19552 | #define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 | ||
| 19553 | #define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 | ||
| 19554 | #define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 | ||
| 19555 | #define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 | ||
| 19556 | #define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 | ||
| 19557 | #define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 | ||
| 19558 | #define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a | ||
| 19559 | #define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 | ||
| 19560 | #define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b | ||
| 19561 | #define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 | ||
| 19562 | #define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c | ||
| 19563 | #define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 | ||
| 19564 | #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d | ||
| 19565 | #define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 | ||
| 19566 | #define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e | ||
| 19567 | #define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 | ||
| 19568 | #define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f | ||
| 19569 | #define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f | ||
| 19570 | #define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 | ||
| 19571 | #define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 | ||
| 19572 | #define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 | ||
| 19573 | #define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 | ||
| 19574 | #define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 | ||
| 19575 | #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 | ||
| 19576 | #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 | ||
| 19577 | #define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 | ||
| 19578 | #define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 | ||
| 19579 | #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 | ||
| 19580 | #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 | ||
| 19581 | #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 | ||
| 19582 | #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa | ||
| 19583 | #define IA_DEBUG_REG8__grp_continued_MASK 0x800 | ||
| 19584 | #define IA_DEBUG_REG8__grp_continued__SHIFT 0xb | ||
| 19585 | #define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 | ||
| 19586 | #define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc | ||
| 19587 | #define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 | ||
| 19588 | #define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf | ||
| 19589 | #define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 | ||
| 19590 | #define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 | ||
| 19591 | #define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 | ||
| 19592 | #define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 | ||
| 19593 | #define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 | ||
| 19594 | #define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 | ||
| 19595 | #define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 | ||
| 19596 | #define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a | ||
| 19597 | #define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 | ||
| 19598 | #define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b | ||
| 19599 | #define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 | ||
| 19600 | #define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c | ||
| 19601 | #define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 | ||
| 19602 | #define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 | ||
| 19603 | #define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 | ||
| 19604 | #define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 | ||
| 19605 | #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 | ||
| 19606 | #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 | ||
| 19607 | #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 | ||
| 19608 | #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 | ||
| 19609 | #define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 | ||
| 19610 | #define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 | ||
| 19611 | #define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 | ||
| 19612 | #define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 | ||
| 19613 | #define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 | ||
| 19614 | #define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 | ||
| 19615 | #define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 | ||
| 19616 | #define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 | ||
| 19617 | #define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 | ||
| 19618 | #define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 | ||
| 19619 | #define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 | ||
| 19620 | #define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 | ||
| 19621 | #define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 | ||
| 19622 | #define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa | ||
| 19623 | #define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 | ||
| 19624 | #define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb | ||
| 19625 | #define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 | ||
| 19626 | #define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc | ||
| 19627 | #define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 | ||
| 19628 | #define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd | ||
| 19629 | #define IA_DEBUG_REG9__SPARE0_MASK 0x4000 | ||
| 19630 | #define IA_DEBUG_REG9__SPARE0__SHIFT 0xe | ||
| 19631 | #define IA_DEBUG_REG9__SPARE1_MASK 0x8000 | ||
| 19632 | #define IA_DEBUG_REG9__SPARE1__SHIFT 0xf | ||
| 19633 | #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 | ||
| 19634 | #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 | ||
| 19635 | #define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 | ||
| 19636 | #define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 | ||
| 19637 | #define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 | ||
| 19638 | #define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 | ||
| 19639 | #define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 | ||
| 19640 | #define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 | ||
| 19641 | #define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 | ||
| 19642 | #define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 | ||
| 19643 | #define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 | ||
| 19644 | #define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 | ||
| 19645 | #define VGT_DEBUG_REG0__SPARE9_MASK 0x2 | ||
| 19646 | #define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 | ||
| 19647 | #define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 | ||
| 19648 | #define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 | ||
| 19649 | #define VGT_DEBUG_REG0__SPARE8_MASK 0x8 | ||
| 19650 | #define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 | ||
| 19651 | #define VGT_DEBUG_REG0__SPARE7_MASK 0x10 | ||
| 19652 | #define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 | ||
| 19653 | #define VGT_DEBUG_REG0__SPARE6_MASK 0x20 | ||
| 19654 | #define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 | ||
| 19655 | #define VGT_DEBUG_REG0__SPARE5_MASK 0x40 | ||
| 19656 | #define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 | ||
| 19657 | #define VGT_DEBUG_REG0__SPARE4_MASK 0x80 | ||
| 19658 | #define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 | ||
| 19659 | #define VGT_DEBUG_REG0__pi_busy_MASK 0x100 | ||
| 19660 | #define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 | ||
| 19661 | #define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 | ||
| 19662 | #define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 | ||
| 19663 | #define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 | ||
| 19664 | #define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa | ||
| 19665 | #define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 | ||
| 19666 | #define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb | ||
| 19667 | #define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 | ||
| 19668 | #define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc | ||
| 19669 | #define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 | ||
| 19670 | #define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd | ||
| 19671 | #define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 | ||
| 19672 | #define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe | ||
| 19673 | #define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 | ||
| 19674 | #define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf | ||
| 19675 | #define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 | ||
| 19676 | #define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 | ||
| 19677 | #define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 | ||
| 19678 | #define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 | ||
| 19679 | #define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 | ||
| 19680 | #define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 | ||
| 19681 | #define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 | ||
| 19682 | #define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 | ||
| 19683 | #define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 | ||
| 19684 | #define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 | ||
| 19685 | #define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 | ||
| 19686 | #define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 | ||
| 19687 | #define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 | ||
| 19688 | #define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 | ||
| 19689 | #define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 | ||
| 19690 | #define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 | ||
| 19691 | #define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 | ||
| 19692 | #define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 | ||
| 19693 | #define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 | ||
| 19694 | #define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 | ||
| 19695 | #define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 | ||
| 19696 | #define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a | ||
| 19697 | #define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 | ||
| 19698 | #define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b | ||
| 19699 | #define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 | ||
| 19700 | #define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c | ||
| 19701 | #define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 | ||
| 19702 | #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d | ||
| 19703 | #define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 | ||
| 19704 | #define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e | ||
| 19705 | #define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 | ||
| 19706 | #define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f | ||
| 19707 | #define VGT_DEBUG_REG1__SPARE9_MASK 0x1 | ||
| 19708 | #define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 | ||
| 19709 | #define VGT_DEBUG_REG1__SPARE8_MASK 0x2 | ||
| 19710 | #define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 | ||
| 19711 | #define VGT_DEBUG_REG1__SPARE7_MASK 0x4 | ||
| 19712 | #define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 | ||
| 19713 | #define VGT_DEBUG_REG1__SPARE6_MASK 0x8 | ||
| 19714 | #define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 | ||
| 19715 | #define VGT_DEBUG_REG1__SPARE5_MASK 0x10 | ||
| 19716 | #define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 | ||
| 19717 | #define VGT_DEBUG_REG1__SPARE4_MASK 0x20 | ||
| 19718 | #define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 | ||
| 19719 | #define VGT_DEBUG_REG1__SPARE3_MASK 0x40 | ||
| 19720 | #define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 | ||
| 19721 | #define VGT_DEBUG_REG1__SPARE2_MASK 0x80 | ||
| 19722 | #define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 | ||
| 19723 | #define VGT_DEBUG_REG1__SPARE1_MASK 0x100 | ||
| 19724 | #define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 | ||
| 19725 | #define VGT_DEBUG_REG1__SPARE0_MASK 0x200 | ||
| 19726 | #define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 | ||
| 19727 | #define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 | ||
| 19728 | #define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa | ||
| 19729 | #define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 | ||
| 19730 | #define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb | ||
| 19731 | #define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 | ||
| 19732 | #define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc | ||
| 19733 | #define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 | ||
| 19734 | #define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd | ||
| 19735 | #define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 | ||
| 19736 | #define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe | ||
| 19737 | #define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 | ||
| 19738 | #define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf | ||
| 19739 | #define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 | ||
| 19740 | #define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 | ||
| 19741 | #define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 | ||
| 19742 | #define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 | ||
| 19743 | #define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 | ||
| 19744 | #define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 | ||
| 19745 | #define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 | ||
| 19746 | #define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 | ||
| 19747 | #define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 | ||
| 19748 | #define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 | ||
| 19749 | #define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 | ||
| 19750 | #define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 | ||
| 19751 | #define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 | ||
| 19752 | #define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 | ||
| 19753 | #define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 | ||
| 19754 | #define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 | ||
| 19755 | #define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 | ||
| 19756 | #define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 | ||
| 19757 | #define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 | ||
| 19758 | #define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 | ||
| 19759 | #define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 | ||
| 19760 | #define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a | ||
| 19761 | #define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 | ||
| 19762 | #define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b | ||
| 19763 | #define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 | ||
| 19764 | #define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c | ||
| 19765 | #define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 | ||
| 19766 | #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d | ||
| 19767 | #define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 | ||
| 19768 | #define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e | ||
| 19769 | #define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 | ||
| 19770 | #define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f | ||
| 19771 | #define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 | ||
| 19772 | #define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 | ||
| 19773 | #define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 | ||
| 19774 | #define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 | ||
| 19775 | #define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 | ||
| 19776 | #define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 | ||
| 19777 | #define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 | ||
| 19778 | #define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 | ||
| 19779 | #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 | ||
| 19780 | #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 | ||
| 19781 | #define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 | ||
| 19782 | #define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 | ||
| 19783 | #define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 | ||
| 19784 | #define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 | ||
| 19785 | #define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 | ||
| 19786 | #define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 | ||
| 19787 | #define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 | ||
| 19788 | #define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 | ||
| 19789 | #define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 | ||
| 19790 | #define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 | ||
| 19791 | #define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 | ||
| 19792 | #define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa | ||
| 19793 | #define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 | ||
| 19794 | #define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb | ||
| 19795 | #define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 | ||
| 19796 | #define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc | ||
| 19797 | #define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 | ||
| 19798 | #define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd | ||
| 19799 | #define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 | ||
| 19800 | #define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe | ||
| 19801 | #define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 | ||
| 19802 | #define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf | ||
| 19803 | #define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 | ||
| 19804 | #define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 | ||
| 19805 | #define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 | ||
| 19806 | #define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 | ||
| 19807 | #define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 | ||
| 19808 | #define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 | ||
| 19809 | #define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 | ||
| 19810 | #define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 | ||
| 19811 | #define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 | ||
| 19812 | #define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 | ||
| 19813 | #define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 | ||
| 19814 | #define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 | ||
| 19815 | #define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 | ||
| 19816 | #define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 | ||
| 19817 | #define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 | ||
| 19818 | #define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 | ||
| 19819 | #define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 | ||
| 19820 | #define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 | ||
| 19821 | #define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 | ||
| 19822 | #define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 | ||
| 19823 | #define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 | ||
| 19824 | #define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a | ||
| 19825 | #define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 | ||
| 19826 | #define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b | ||
| 19827 | #define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 | ||
| 19828 | #define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c | ||
| 19829 | #define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 | ||
| 19830 | #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d | ||
| 19831 | #define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff | ||
| 19832 | #define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 | ||
| 19833 | #define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 | ||
| 19834 | #define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc | ||
| 19835 | #define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 | ||
| 19836 | #define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 | ||
| 19837 | #define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 | ||
| 19838 | #define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a | ||
| 19839 | #define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff | ||
| 19840 | #define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 | ||
| 19841 | #define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 | ||
| 19842 | #define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 | ||
| 19843 | #define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 | ||
| 19844 | #define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 | ||
| 19845 | #define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 | ||
| 19846 | #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d | ||
| 19847 | #define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 | ||
| 19848 | #define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e | ||
| 19849 | #define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 | ||
| 19850 | #define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f | ||
| 19851 | #define VGT_DEBUG_REG5__SPARE4_MASK 0x7 | ||
| 19852 | #define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 | ||
| 19853 | #define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 | ||
| 19854 | #define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 | ||
| 19855 | #define VGT_DEBUG_REG5__SPARE3_MASK 0x700 | ||
| 19856 | #define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 | ||
| 19857 | #define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 | ||
| 19858 | #define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb | ||
| 19859 | #define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 | ||
| 19860 | #define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 | ||
| 19861 | #define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 | ||
| 19862 | #define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 | ||
| 19863 | #define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 | ||
| 19864 | #define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 | ||
| 19865 | #define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 | ||
| 19866 | #define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b | ||
| 19867 | #define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff | ||
| 19868 | #define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 | ||
| 19869 | #define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 | ||
| 19870 | #define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 | ||
| 19871 | #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 | ||
| 19872 | #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 | ||
| 19873 | #define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 | ||
| 19874 | #define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 | ||
| 19875 | #define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 | ||
| 19876 | #define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 | ||
| 19877 | #define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 | ||
| 19878 | #define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 | ||
| 19879 | #define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 | ||
| 19880 | #define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 | ||
| 19881 | #define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 | ||
| 19882 | #define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 | ||
| 19883 | #define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 | ||
| 19884 | #define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 | ||
| 19885 | #define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 | ||
| 19886 | #define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 | ||
| 19887 | #define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 | ||
| 19888 | #define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 | ||
| 19889 | #define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 | ||
| 19890 | #define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 | ||
| 19891 | #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 | ||
| 19892 | #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 | ||
| 19893 | #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 | ||
| 19894 | #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 | ||
| 19895 | #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 | ||
| 19896 | #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 | ||
| 19897 | #define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 | ||
| 19898 | #define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 | ||
| 19899 | #define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 | ||
| 19900 | #define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 | ||
| 19901 | #define VGT_DEBUG_REG8__valid_r2_MASK 0x100 | ||
| 19902 | #define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 | ||
| 19903 | #define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 | ||
| 19904 | #define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 | ||
| 19905 | #define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 | ||
| 19906 | #define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa | ||
| 19907 | #define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 | ||
| 19908 | #define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb | ||
| 19909 | #define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 | ||
| 19910 | #define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc | ||
| 19911 | #define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 | ||
| 19912 | #define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd | ||
| 19913 | #define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 | ||
| 19914 | #define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe | ||
| 19915 | #define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 | ||
| 19916 | #define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf | ||
| 19917 | #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 | ||
| 19918 | #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 | ||
| 19919 | #define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 | ||
| 19920 | #define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 | ||
| 19921 | #define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 | ||
| 19922 | #define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 | ||
| 19923 | #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 | ||
| 19924 | #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 | ||
| 19925 | #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 | ||
| 19926 | #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 | ||
| 19927 | #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 | ||
| 19928 | #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 | ||
| 19929 | #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 | ||
| 19930 | #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 | ||
| 19931 | #define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 | ||
| 19932 | #define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 | ||
| 19933 | #define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 | ||
| 19934 | #define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 | ||
| 19935 | #define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 | ||
| 19936 | #define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 | ||
| 19937 | #define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 | ||
| 19938 | #define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a | ||
| 19939 | #define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 | ||
| 19940 | #define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b | ||
| 19941 | #define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 | ||
| 19942 | #define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c | ||
| 19943 | #define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 | ||
| 19944 | #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d | ||
| 19945 | #define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 | ||
| 19946 | #define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e | ||
| 19947 | #define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 | ||
| 19948 | #define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f | ||
| 19949 | #define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 | ||
| 19950 | #define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 | ||
| 19951 | #define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 | ||
| 19952 | #define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 | ||
| 19953 | #define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 | ||
| 19954 | #define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 | ||
| 19955 | #define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 | ||
| 19956 | #define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 | ||
| 19957 | #define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 | ||
| 19958 | #define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 | ||
| 19959 | #define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 | ||
| 19960 | #define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 | ||
| 19961 | #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 | ||
| 19962 | #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 | ||
| 19963 | #define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 | ||
| 19964 | #define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 | ||
| 19965 | #define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 | ||
| 19966 | #define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 | ||
| 19967 | #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 | ||
| 19968 | #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa | ||
| 19969 | #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 | ||
| 19970 | #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb | ||
| 19971 | #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 | ||
| 19972 | #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 | ||
| 19973 | #define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 | ||
| 19974 | #define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 | ||
| 19975 | #define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 | ||
| 19976 | #define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 | ||
| 19977 | #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 | ||
| 19978 | #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 | ||
| 19979 | #define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 | ||
| 19980 | #define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 | ||
| 19981 | #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 | ||
| 19982 | #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 | ||
| 19983 | #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 | ||
| 19984 | #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a | ||
| 19985 | #define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 | ||
| 19986 | #define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b | ||
| 19987 | #define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 | ||
| 19988 | #define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c | ||
| 19989 | #define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 | ||
| 19990 | #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d | ||
| 19991 | #define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 | ||
| 19992 | #define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e | ||
| 19993 | #define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 | ||
| 19994 | #define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f | ||
| 19995 | #define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f | ||
| 19996 | #define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 | ||
| 19997 | #define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 | ||
| 19998 | #define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 | ||
| 19999 | #define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 | ||
| 20000 | #define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 | ||
| 20001 | #define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 | ||
| 20002 | #define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 | ||
| 20003 | #define VGT_DEBUG_REG10__SPARE2_MASK 0x600 | ||
| 20004 | #define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 | ||
| 20005 | #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 | ||
| 20006 | #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb | ||
| 20007 | #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 | ||
| 20008 | #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc | ||
| 20009 | #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 | ||
| 20010 | #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd | ||
| 20011 | #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 | ||
| 20012 | #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 | ||
| 20013 | #define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 | ||
| 20014 | #define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 | ||
| 20015 | #define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 | ||
| 20016 | #define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 | ||
| 20017 | #define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 | ||
| 20018 | #define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 | ||
| 20019 | #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 | ||
| 20020 | #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 | ||
| 20021 | #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 | ||
| 20022 | #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 | ||
| 20023 | #define VGT_DEBUG_REG11__SPARE1_MASK 0x20 | ||
| 20024 | #define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 | ||
| 20025 | #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 | ||
| 20026 | #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 | ||
| 20027 | #define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 | ||
| 20028 | #define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 | ||
| 20029 | #define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 | ||
| 20030 | #define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 | ||
| 20031 | #define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 | ||
| 20032 | #define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 | ||
| 20033 | #define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 | ||
| 20034 | #define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa | ||
| 20035 | #define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 | ||
| 20036 | #define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb | ||
| 20037 | #define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 | ||
| 20038 | #define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc | ||
| 20039 | #define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 | ||
| 20040 | #define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd | ||
| 20041 | #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 | ||
| 20042 | #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe | ||
| 20043 | #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 | ||
| 20044 | #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf | ||
| 20045 | #define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 | ||
| 20046 | #define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 | ||
| 20047 | #define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 | ||
| 20048 | #define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 | ||
| 20049 | #define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 | ||
| 20050 | #define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 | ||
| 20051 | #define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 | ||
| 20052 | #define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 | ||
| 20053 | #define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 | ||
| 20054 | #define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 | ||
| 20055 | #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 | ||
| 20056 | #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 | ||
| 20057 | #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 | ||
| 20058 | #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 | ||
| 20059 | #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 | ||
| 20060 | #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 | ||
| 20061 | #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 | ||
| 20062 | #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 | ||
| 20063 | #define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 | ||
| 20064 | #define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 | ||
| 20065 | #define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 | ||
| 20066 | #define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a | ||
| 20067 | #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 | ||
| 20068 | #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b | ||
| 20069 | #define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 | ||
| 20070 | #define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c | ||
| 20071 | #define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 | ||
| 20072 | #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d | ||
| 20073 | #define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 | ||
| 20074 | #define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e | ||
| 20075 | #define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 | ||
| 20076 | #define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f | ||
| 20077 | #define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 | ||
| 20078 | #define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 | ||
| 20079 | #define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 | ||
| 20080 | #define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 | ||
| 20081 | #define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 | ||
| 20082 | #define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 | ||
| 20083 | #define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 | ||
| 20084 | #define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 | ||
| 20085 | #define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 | ||
| 20086 | #define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc | ||
| 20087 | #define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 | ||
| 20088 | #define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf | ||
| 20089 | #define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 | ||
| 20090 | #define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 | ||
| 20091 | #define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 | ||
| 20092 | #define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 | ||
| 20093 | #define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 | ||
| 20094 | #define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 | ||
| 20095 | #define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 | ||
| 20096 | #define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b | ||
| 20097 | #define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 | ||
| 20098 | #define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e | ||
| 20099 | #define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 | ||
| 20100 | #define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f | ||
| 20101 | #define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 | ||
| 20102 | #define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 | ||
| 20103 | #define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 | ||
| 20104 | #define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 | ||
| 20105 | #define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 | ||
| 20106 | #define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 | ||
| 20107 | #define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 | ||
| 20108 | #define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 | ||
| 20109 | #define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 | ||
| 20110 | #define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc | ||
| 20111 | #define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 | ||
| 20112 | #define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf | ||
| 20113 | #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 | ||
| 20114 | #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 | ||
| 20115 | #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 | ||
| 20116 | #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 | ||
| 20117 | #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 | ||
| 20118 | #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 | ||
| 20119 | #define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 | ||
| 20120 | #define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 | ||
| 20121 | #define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 | ||
| 20122 | #define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 | ||
| 20123 | #define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 | ||
| 20124 | #define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a | ||
| 20125 | #define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 | ||
| 20126 | #define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b | ||
| 20127 | #define VGT_DEBUG_REG14__SPARE3_MASK 0xf | ||
| 20128 | #define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 | ||
| 20129 | #define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 | ||
| 20130 | #define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 | ||
| 20131 | #define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 | ||
| 20132 | #define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 | ||
| 20133 | #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 | ||
| 20134 | #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 | ||
| 20135 | #define VGT_DEBUG_REG14__SPARE8_MASK 0x180 | ||
| 20136 | #define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 | ||
| 20137 | #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 | ||
| 20138 | #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 | ||
| 20139 | #define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 | ||
| 20140 | #define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa | ||
| 20141 | #define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 | ||
| 20142 | #define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb | ||
| 20143 | #define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 | ||
| 20144 | #define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc | ||
| 20145 | #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 | ||
| 20146 | #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 | ||
| 20147 | #define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 | ||
| 20148 | #define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 | ||
| 20149 | #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 | ||
| 20150 | #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 | ||
| 20151 | #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 | ||
| 20152 | #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a | ||
| 20153 | #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 | ||
| 20154 | #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b | ||
| 20155 | #define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 | ||
| 20156 | #define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c | ||
| 20157 | #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 | ||
| 20158 | #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d | ||
| 20159 | #define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 | ||
| 20160 | #define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e | ||
| 20161 | #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 | ||
| 20162 | #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f | ||
| 20163 | #define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 | ||
| 20164 | #define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 | ||
| 20165 | #define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 | ||
| 20166 | #define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 | ||
| 20167 | #define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 | ||
| 20168 | #define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 | ||
| 20169 | #define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 | ||
| 20170 | #define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 | ||
| 20171 | #define VGT_DEBUG_REG15__counters_full_MASK 0x10 | ||
| 20172 | #define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 | ||
| 20173 | #define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 | ||
| 20174 | #define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 | ||
| 20175 | #define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 | ||
| 20176 | #define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa | ||
| 20177 | #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 | ||
| 20178 | #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf | ||
| 20179 | #define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 | ||
| 20180 | #define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 | ||
| 20181 | #define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 | ||
| 20182 | #define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a | ||
| 20183 | #define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 | ||
| 20184 | #define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c | ||
| 20185 | #define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 | ||
| 20186 | #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d | ||
| 20187 | #define VGT_DEBUG_REG16__gog_busy_MASK 0x1 | ||
| 20188 | #define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 | ||
| 20189 | #define VGT_DEBUG_REG16__gog_state_q_MASK 0xe | ||
| 20190 | #define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 | ||
| 20191 | #define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 | ||
| 20192 | #define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 | ||
| 20193 | #define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 | ||
| 20194 | #define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 | ||
| 20195 | #define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 | ||
| 20196 | #define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 | ||
| 20197 | #define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 | ||
| 20198 | #define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 | ||
| 20199 | #define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 | ||
| 20200 | #define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 | ||
| 20201 | #define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 | ||
| 20202 | #define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 | ||
| 20203 | #define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 | ||
| 20204 | #define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa | ||
| 20205 | #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 | ||
| 20206 | #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb | ||
| 20207 | #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 | ||
| 20208 | #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc | ||
| 20209 | #define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 | ||
| 20210 | #define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd | ||
| 20211 | #define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 | ||
| 20212 | #define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe | ||
| 20213 | #define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 | ||
| 20214 | #define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf | ||
| 20215 | #define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 | ||
| 20216 | #define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 | ||
| 20217 | #define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 | ||
| 20218 | #define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 | ||
| 20219 | #define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 | ||
| 20220 | #define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 | ||
| 20221 | #define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 | ||
| 20222 | #define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 | ||
| 20223 | #define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 | ||
| 20224 | #define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 | ||
| 20225 | #define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 | ||
| 20226 | #define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 | ||
| 20227 | #define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 | ||
| 20228 | #define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 | ||
| 20229 | #define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 | ||
| 20230 | #define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 | ||
| 20231 | #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 | ||
| 20232 | #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 | ||
| 20233 | #define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 | ||
| 20234 | #define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 | ||
| 20235 | #define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 | ||
| 20236 | #define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c | ||
| 20237 | #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 | ||
| 20238 | #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d | ||
| 20239 | #define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 | ||
| 20240 | #define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e | ||
| 20241 | #define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 | ||
| 20242 | #define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f | ||
| 20243 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f | ||
| 20244 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 | ||
| 20245 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 | ||
| 20246 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 | ||
| 20247 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 | ||
| 20248 | #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc | ||
| 20249 | #define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 | ||
| 20250 | #define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 | ||
| 20251 | #define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 | ||
| 20252 | #define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 | ||
| 20253 | #define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 | ||
| 20254 | #define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 | ||
| 20255 | #define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 | ||
| 20256 | #define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 | ||
| 20257 | #define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 | ||
| 20258 | #define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 | ||
| 20259 | #define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 | ||
| 20260 | #define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 | ||
| 20261 | #define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 | ||
| 20262 | #define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 | ||
| 20263 | #define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 | ||
| 20264 | #define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 | ||
| 20265 | #define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 | ||
| 20266 | #define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 | ||
| 20267 | #define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 | ||
| 20268 | #define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 | ||
| 20269 | #define VGT_DEBUG_REG18__valid_indices_MASK 0x800 | ||
| 20270 | #define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb | ||
| 20271 | #define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 | ||
| 20272 | #define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc | ||
| 20273 | #define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 | ||
| 20274 | #define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd | ||
| 20275 | #define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 | ||
| 20276 | #define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe | ||
| 20277 | #define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 | ||
| 20278 | #define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf | ||
| 20279 | #define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 | ||
| 20280 | #define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 | ||
| 20281 | #define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 | ||
| 20282 | #define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 | ||
| 20283 | #define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 | ||
| 20284 | #define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 | ||
| 20285 | #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 | ||
| 20286 | #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 | ||
| 20287 | #define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 | ||
| 20288 | #define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 | ||
| 20289 | #define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 | ||
| 20290 | #define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 | ||
| 20291 | #define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 | ||
| 20292 | #define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 | ||
| 20293 | #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 | ||
| 20294 | #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 | ||
| 20295 | #define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 | ||
| 20296 | #define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 | ||
| 20297 | #define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 | ||
| 20298 | #define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b | ||
| 20299 | #define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 | ||
| 20300 | #define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c | ||
| 20301 | #define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 | ||
| 20302 | #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d | ||
| 20303 | #define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 | ||
| 20304 | #define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 | ||
| 20305 | #define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 | ||
| 20306 | #define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 | ||
| 20307 | #define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 | ||
| 20308 | #define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 | ||
| 20309 | #define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 | ||
| 20310 | #define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 | ||
| 20311 | #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 | ||
| 20312 | #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 | ||
| 20313 | #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 | ||
| 20314 | #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 | ||
| 20315 | #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 | ||
| 20316 | #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 | ||
| 20317 | #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 | ||
| 20318 | #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 | ||
| 20319 | #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 | ||
| 20320 | #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 | ||
| 20321 | #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 | ||
| 20322 | #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 | ||
| 20323 | #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 | ||
| 20324 | #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa | ||
| 20325 | #define VGT_DEBUG_REG19__hold_prim_MASK 0x800 | ||
| 20326 | #define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb | ||
| 20327 | #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 | ||
| 20328 | #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc | ||
| 20329 | #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 | ||
| 20330 | #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd | ||
| 20331 | #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 | ||
| 20332 | #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe | ||
| 20333 | #define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 | ||
| 20334 | #define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf | ||
| 20335 | #define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 | ||
| 20336 | #define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 | ||
| 20337 | #define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 | ||
| 20338 | #define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 | ||
| 20339 | #define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 | ||
| 20340 | #define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 | ||
| 20341 | #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 | ||
| 20342 | #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 | ||
| 20343 | #define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 | ||
| 20344 | #define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 | ||
| 20345 | #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 | ||
| 20346 | #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a | ||
| 20347 | #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 | ||
| 20348 | #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b | ||
| 20349 | #define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 | ||
| 20350 | #define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c | ||
| 20351 | #define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 | ||
| 20352 | #define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e | ||
| 20353 | #define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 | ||
| 20354 | #define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f | ||
| 20355 | #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff | ||
| 20356 | #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 | ||
| 20357 | #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 | ||
| 20358 | #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 | ||
| 20359 | #define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 | ||
| 20360 | #define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 | ||
| 20361 | #define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 | ||
| 20362 | #define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 | ||
| 20363 | #define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 | ||
| 20364 | #define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 | ||
| 20365 | #define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 | ||
| 20366 | #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d | ||
| 20367 | #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 | ||
| 20368 | #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e | ||
| 20369 | #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 | ||
| 20370 | #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f | ||
| 20371 | #define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 | ||
| 20372 | #define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 | ||
| 20373 | #define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 | ||
| 20374 | #define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 | ||
| 20375 | #define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 | ||
| 20376 | #define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 | ||
| 20377 | #define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 | ||
| 20378 | #define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 | ||
| 20379 | #define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 | ||
| 20380 | #define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 | ||
| 20381 | #define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 | ||
| 20382 | #define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 | ||
| 20383 | #define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 | ||
| 20384 | #define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 | ||
| 20385 | #define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 | ||
| 20386 | #define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 | ||
| 20387 | #define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 | ||
| 20388 | #define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 | ||
| 20389 | #define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 | ||
| 20390 | #define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 | ||
| 20391 | #define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 | ||
| 20392 | #define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa | ||
| 20393 | #define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 | ||
| 20394 | #define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb | ||
| 20395 | #define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 | ||
| 20396 | #define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc | ||
| 20397 | #define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 | ||
| 20398 | #define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd | ||
| 20399 | #define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 | ||
| 20400 | #define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe | ||
| 20401 | #define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 | ||
| 20402 | #define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf | ||
| 20403 | #define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 | ||
| 20404 | #define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 | ||
| 20405 | #define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 | ||
| 20406 | #define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 | ||
| 20407 | #define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 | ||
| 20408 | #define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 | ||
| 20409 | #define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 | ||
| 20410 | #define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 | ||
| 20411 | #define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 | ||
| 20412 | #define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 | ||
| 20413 | #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 | ||
| 20414 | #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 | ||
| 20415 | #define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 | ||
| 20416 | #define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 | ||
| 20417 | #define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 | ||
| 20418 | #define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 | ||
| 20419 | #define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 | ||
| 20420 | #define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a | ||
| 20421 | #define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 | ||
| 20422 | #define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b | ||
| 20423 | #define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 | ||
| 20424 | #define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c | ||
| 20425 | #define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 | ||
| 20426 | #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d | ||
| 20427 | #define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 | ||
| 20428 | #define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e | ||
| 20429 | #define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 | ||
| 20430 | #define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f | ||
| 20431 | #define VGT_DEBUG_REG22__cm_state16_MASK 0x3 | ||
| 20432 | #define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 | ||
| 20433 | #define VGT_DEBUG_REG22__cm_state17_MASK 0xc | ||
| 20434 | #define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 | ||
| 20435 | #define VGT_DEBUG_REG22__cm_state18_MASK 0x30 | ||
| 20436 | #define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 | ||
| 20437 | #define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 | ||
| 20438 | #define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 | ||
| 20439 | #define VGT_DEBUG_REG22__cm_state20_MASK 0x300 | ||
| 20440 | #define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 | ||
| 20441 | #define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 | ||
| 20442 | #define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa | ||
| 20443 | #define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 | ||
| 20444 | #define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc | ||
| 20445 | #define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 | ||
| 20446 | #define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe | ||
| 20447 | #define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 | ||
| 20448 | #define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 | ||
| 20449 | #define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 | ||
| 20450 | #define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 | ||
| 20451 | #define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 | ||
| 20452 | #define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 | ||
| 20453 | #define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 | ||
| 20454 | #define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 | ||
| 20455 | #define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 | ||
| 20456 | #define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 | ||
| 20457 | #define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 | ||
| 20458 | #define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a | ||
| 20459 | #define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 | ||
| 20460 | #define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c | ||
| 20461 | #define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 | ||
| 20462 | #define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e | ||
| 20463 | #define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 | ||
| 20464 | #define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 | ||
| 20465 | #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 | ||
| 20466 | #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 | ||
| 20467 | #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 | ||
| 20468 | #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 | ||
| 20469 | #define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 | ||
| 20470 | #define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 | ||
| 20471 | #define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 | ||
| 20472 | #define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 | ||
| 20473 | #define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 | ||
| 20474 | #define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 | ||
| 20475 | #define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 | ||
| 20476 | #define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 | ||
| 20477 | #define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 | ||
| 20478 | #define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 | ||
| 20479 | #define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 | ||
| 20480 | #define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 | ||
| 20481 | #define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 | ||
| 20482 | #define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 | ||
| 20483 | #define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 | ||
| 20484 | #define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa | ||
| 20485 | #define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 | ||
| 20486 | #define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb | ||
| 20487 | #define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 | ||
| 20488 | #define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc | ||
| 20489 | #define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 | ||
| 20490 | #define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd | ||
| 20491 | #define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 | ||
| 20492 | #define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe | ||
| 20493 | #define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 | ||
| 20494 | #define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf | ||
| 20495 | #define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 | ||
| 20496 | #define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 | ||
| 20497 | #define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 | ||
| 20498 | #define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 | ||
| 20499 | #define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 | ||
| 20500 | #define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 | ||
| 20501 | #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff | ||
| 20502 | #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 | ||
| 20503 | #define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 | ||
| 20504 | #define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 | ||
| 20505 | #define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 | ||
| 20506 | #define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a | ||
| 20507 | #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff | ||
| 20508 | #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 | ||
| 20509 | #define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 | ||
| 20510 | #define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a | ||
| 20511 | #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 | ||
| 20512 | #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e | ||
| 20513 | #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 | ||
| 20514 | #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f | ||
| 20515 | #define VGT_DEBUG_REG26__cm_state0_MASK 0x3 | ||
| 20516 | #define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 | ||
| 20517 | #define VGT_DEBUG_REG26__cm_state1_MASK 0xc | ||
| 20518 | #define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 | ||
| 20519 | #define VGT_DEBUG_REG26__cm_state2_MASK 0x30 | ||
| 20520 | #define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 | ||
| 20521 | #define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 | ||
| 20522 | #define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 | ||
| 20523 | #define VGT_DEBUG_REG26__cm_state4_MASK 0x300 | ||
| 20524 | #define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 | ||
| 20525 | #define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 | ||
| 20526 | #define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa | ||
| 20527 | #define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 | ||
| 20528 | #define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc | ||
| 20529 | #define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 | ||
| 20530 | #define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe | ||
| 20531 | #define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 | ||
| 20532 | #define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 | ||
| 20533 | #define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 | ||
| 20534 | #define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 | ||
| 20535 | #define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 | ||
| 20536 | #define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 | ||
| 20537 | #define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 | ||
| 20538 | #define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 | ||
| 20539 | #define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 | ||
| 20540 | #define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 | ||
| 20541 | #define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 | ||
| 20542 | #define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a | ||
| 20543 | #define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 | ||
| 20544 | #define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c | ||
| 20545 | #define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 | ||
| 20546 | #define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e | ||
| 20547 | #define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 | ||
| 20548 | #define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 | ||
| 20549 | #define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 | ||
| 20550 | #define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 | ||
| 20551 | #define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 | ||
| 20552 | #define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 | ||
| 20553 | #define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 | ||
| 20554 | #define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 | ||
| 20555 | #define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 | ||
| 20556 | #define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 | ||
| 20557 | #define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 | ||
| 20558 | #define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 | ||
| 20559 | #define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 | ||
| 20560 | #define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 | ||
| 20561 | #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 | ||
| 20562 | #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 | ||
| 20563 | #define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 | ||
| 20564 | #define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 | ||
| 20565 | #define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 | ||
| 20566 | #define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa | ||
| 20567 | #define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 | ||
| 20568 | #define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb | ||
| 20569 | #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 | ||
| 20570 | #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc | ||
| 20571 | #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 | ||
| 20572 | #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe | ||
| 20573 | #define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 | ||
| 20574 | #define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf | ||
| 20575 | #define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 | ||
| 20576 | #define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 | ||
| 20577 | #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 | ||
| 20578 | #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 | ||
| 20579 | #define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 | ||
| 20580 | #define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 | ||
| 20581 | #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 | ||
| 20582 | #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 | ||
| 20583 | #define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 | ||
| 20584 | #define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 | ||
| 20585 | #define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 | ||
| 20586 | #define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f | ||
| 20587 | #define VGT_DEBUG_REG28__con_state_q_MASK 0xf | ||
| 20588 | #define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 | ||
| 20589 | #define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 | ||
| 20590 | #define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 | ||
| 20591 | #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 | ||
| 20592 | #define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 | ||
| 20593 | #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 | ||
| 20594 | #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 | ||
| 20595 | #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 | ||
| 20596 | #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 | ||
| 20597 | #define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 | ||
| 20598 | #define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 | ||
| 20599 | #define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 | ||
| 20600 | #define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 | ||
| 20601 | #define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 | ||
| 20602 | #define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa | ||
| 20603 | #define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 | ||
| 20604 | #define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb | ||
| 20605 | #define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 | ||
| 20606 | #define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc | ||
| 20607 | #define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 | ||
| 20608 | #define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd | ||
| 20609 | #define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 | ||
| 20610 | #define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe | ||
| 20611 | #define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 | ||
| 20612 | #define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf | ||
| 20613 | #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 | ||
| 20614 | #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 | ||
| 20615 | #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 | ||
| 20616 | #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 | ||
| 20617 | #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 | ||
| 20618 | #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 | ||
| 20619 | #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 | ||
| 20620 | #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 | ||
| 20621 | #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 | ||
| 20622 | #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 | ||
| 20623 | #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 | ||
| 20624 | #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 | ||
| 20625 | #define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 | ||
| 20626 | #define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 | ||
| 20627 | #define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 | ||
| 20628 | #define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 | ||
| 20629 | #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 | ||
| 20630 | #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 | ||
| 20631 | #define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 | ||
| 20632 | #define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 | ||
| 20633 | #define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 | ||
| 20634 | #define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a | ||
| 20635 | #define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 | ||
| 20636 | #define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b | ||
| 20637 | #define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 | ||
| 20638 | #define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c | ||
| 20639 | #define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 | ||
| 20640 | #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d | ||
| 20641 | #define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 | ||
| 20642 | #define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e | ||
| 20643 | #define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 | ||
| 20644 | #define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f | ||
| 20645 | #define VGT_DEBUG_REG29__con_state_q_MASK 0xf | ||
| 20646 | #define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 | ||
| 20647 | #define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 | ||
| 20648 | #define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 | ||
| 20649 | #define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 | ||
| 20650 | #define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 | ||
| 20651 | #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 | ||
| 20652 | #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 | ||
| 20653 | #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 | ||
| 20654 | #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 | ||
| 20655 | #define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 | ||
| 20656 | #define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 | ||
| 20657 | #define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 | ||
| 20658 | #define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 | ||
| 20659 | #define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 | ||
| 20660 | #define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa | ||
| 20661 | #define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 | ||
| 20662 | #define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb | ||
| 20663 | #define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 | ||
| 20664 | #define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc | ||
| 20665 | #define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 | ||
| 20666 | #define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd | ||
| 20667 | #define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 | ||
| 20668 | #define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe | ||
| 20669 | #define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 | ||
| 20670 | #define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf | ||
| 20671 | #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 | ||
| 20672 | #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 | ||
| 20673 | #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 | ||
| 20674 | #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 | ||
| 20675 | #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 | ||
| 20676 | #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 | ||
| 20677 | #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 | ||
| 20678 | #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 | ||
| 20679 | #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 | ||
| 20680 | #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 | ||
| 20681 | #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 | ||
| 20682 | #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 | ||
| 20683 | #define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 | ||
| 20684 | #define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 | ||
| 20685 | #define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 | ||
| 20686 | #define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 | ||
| 20687 | #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 | ||
| 20688 | #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 | ||
| 20689 | #define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 | ||
| 20690 | #define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 | ||
| 20691 | #define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 | ||
| 20692 | #define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a | ||
| 20693 | #define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 | ||
| 20694 | #define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b | ||
| 20695 | #define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 | ||
| 20696 | #define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c | ||
| 20697 | #define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 | ||
| 20698 | #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d | ||
| 20699 | #define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 | ||
| 20700 | #define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e | ||
| 20701 | #define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 | ||
| 20702 | #define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f | ||
| 20703 | #define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 | ||
| 20704 | #define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 | ||
| 20705 | #define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 | ||
| 20706 | #define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 | ||
| 20707 | #define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 | ||
| 20708 | #define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 | ||
| 20709 | #define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 | ||
| 20710 | #define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 | ||
| 20711 | #define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 | ||
| 20712 | #define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 | ||
| 20713 | #define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 | ||
| 20714 | #define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 | ||
| 20715 | #define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 | ||
| 20716 | #define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 | ||
| 20717 | #define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 | ||
| 20718 | #define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 | ||
| 20719 | #define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 | ||
| 20720 | #define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 | ||
| 20721 | #define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 | ||
| 20722 | #define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 | ||
| 20723 | #define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 | ||
| 20724 | #define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa | ||
| 20725 | #define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 | ||
| 20726 | #define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb | ||
| 20727 | #define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 | ||
| 20728 | #define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc | ||
| 20729 | #define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 | ||
| 20730 | #define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd | ||
| 20731 | #define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 | ||
| 20732 | #define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe | ||
| 20733 | #define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 | ||
| 20734 | #define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf | ||
| 20735 | #define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 | ||
| 20736 | #define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 | ||
| 20737 | #define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 | ||
| 20738 | #define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 | ||
| 20739 | #define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 | ||
| 20740 | #define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 | ||
| 20741 | #define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 | ||
| 20742 | #define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 | ||
| 20743 | #define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 | ||
| 20744 | #define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 | ||
| 20745 | #define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 | ||
| 20746 | #define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 | ||
| 20747 | #define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 | ||
| 20748 | #define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 | ||
| 20749 | #define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 | ||
| 20750 | #define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 | ||
| 20751 | #define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 | ||
| 20752 | #define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 | ||
| 20753 | #define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 | ||
| 20754 | #define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 | ||
| 20755 | #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 | ||
| 20756 | #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a | ||
| 20757 | #define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 | ||
| 20758 | #define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b | ||
| 20759 | #define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 | ||
| 20760 | #define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c | ||
| 20761 | #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 | ||
| 20762 | #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d | ||
| 20763 | #define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 | ||
| 20764 | #define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e | ||
| 20765 | #define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 | ||
| 20766 | #define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f | ||
| 20767 | #define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 | ||
| 20768 | #define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 | ||
| 20769 | #define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 | ||
| 20770 | #define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 | ||
| 20771 | #define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 | ||
| 20772 | #define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 | ||
| 20773 | #define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 | ||
| 20774 | #define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 | ||
| 20775 | #define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 | ||
| 20776 | #define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 | ||
| 20777 | #define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 | ||
| 20778 | #define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 | ||
| 20779 | #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 | ||
| 20780 | #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 | ||
| 20781 | #define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 | ||
| 20782 | #define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 | ||
| 20783 | #define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 | ||
| 20784 | #define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 | ||
| 20785 | #define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 | ||
| 20786 | #define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 | ||
| 20787 | #define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 | ||
| 20788 | #define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa | ||
| 20789 | #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 | ||
| 20790 | #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb | ||
| 20791 | #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 | ||
| 20792 | #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc | ||
| 20793 | #define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 | ||
| 20794 | #define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe | ||
| 20795 | #define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 | ||
| 20796 | #define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf | ||
| 20797 | #define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 | ||
| 20798 | #define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 | ||
| 20799 | #define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 | ||
| 20800 | #define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 | ||
| 20801 | #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 | ||
| 20802 | #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 | ||
| 20803 | #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 | ||
| 20804 | #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 | ||
| 20805 | #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 | ||
| 20806 | #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 | ||
| 20807 | #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 | ||
| 20808 | #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 | ||
| 20809 | #define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 | ||
| 20810 | #define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 | ||
| 20811 | #define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 | ||
| 20812 | #define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 | ||
| 20813 | #define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 | ||
| 20814 | #define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 | ||
| 20815 | #define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 | ||
| 20816 | #define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 | ||
| 20817 | #define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 | ||
| 20818 | #define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a | ||
| 20819 | #define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 | ||
| 20820 | #define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b | ||
| 20821 | #define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 | ||
| 20822 | #define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c | ||
| 20823 | #define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 | ||
| 20824 | #define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 | ||
| 20825 | #define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 | ||
| 20826 | #define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 | ||
| 20827 | #define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 | ||
| 20828 | #define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 | ||
| 20829 | #define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 | ||
| 20830 | #define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 | ||
| 20831 | #define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 | ||
| 20832 | #define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 | ||
| 20833 | #define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 | ||
| 20834 | #define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 | ||
| 20835 | #define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 | ||
| 20836 | #define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 | ||
| 20837 | #define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 | ||
| 20838 | #define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 | ||
| 20839 | #define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 | ||
| 20840 | #define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 | ||
| 20841 | #define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 | ||
| 20842 | #define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 | ||
| 20843 | #define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 | ||
| 20844 | #define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa | ||
| 20845 | #define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 | ||
| 20846 | #define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb | ||
| 20847 | #define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 | ||
| 20848 | #define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc | ||
| 20849 | #define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 | ||
| 20850 | #define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd | ||
| 20851 | #define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 | ||
| 20852 | #define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe | ||
| 20853 | #define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 | ||
| 20854 | #define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf | ||
| 20855 | #define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 | ||
| 20856 | #define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 | ||
| 20857 | #define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 | ||
| 20858 | #define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 | ||
| 20859 | #define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 | ||
| 20860 | #define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 | ||
| 20861 | #define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 | ||
| 20862 | #define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 | ||
| 20863 | #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 | ||
| 20864 | #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 | ||
| 20865 | #define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 | ||
| 20866 | #define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 | ||
| 20867 | #define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 | ||
| 20868 | #define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 | ||
| 20869 | #define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 | ||
| 20870 | #define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 | ||
| 20871 | #define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 | ||
| 20872 | #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 | ||
| 20873 | #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 | ||
| 20874 | #define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a | ||
| 20875 | #define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 | ||
| 20876 | #define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c | ||
| 20877 | #define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 | ||
| 20878 | #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d | ||
| 20879 | #define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 | ||
| 20880 | #define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e | ||
| 20881 | #define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 | ||
| 20882 | #define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f | ||
| 20883 | #define VGT_DEBUG_REG34__con_state_q_MASK 0xf | ||
| 20884 | #define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 | ||
| 20885 | #define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 | ||
| 20886 | #define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 | ||
| 20887 | #define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 | ||
| 20888 | #define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 | ||
| 20889 | #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 | ||
| 20890 | #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 | ||
| 20891 | #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 | ||
| 20892 | #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 | ||
| 20893 | #define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 | ||
| 20894 | #define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 | ||
| 20895 | #define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 | ||
| 20896 | #define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 | ||
| 20897 | #define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 | ||
| 20898 | #define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa | ||
| 20899 | #define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 | ||
| 20900 | #define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb | ||
| 20901 | #define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 | ||
| 20902 | #define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc | ||
| 20903 | #define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 | ||
| 20904 | #define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd | ||
| 20905 | #define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 | ||
| 20906 | #define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe | ||
| 20907 | #define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 | ||
| 20908 | #define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf | ||
| 20909 | #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 | ||
| 20910 | #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 | ||
| 20911 | #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 | ||
| 20912 | #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 | ||
| 20913 | #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 | ||
| 20914 | #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 | ||
| 20915 | #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 | ||
| 20916 | #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 | ||
| 20917 | #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 | ||
| 20918 | #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 | ||
| 20919 | #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 | ||
| 20920 | #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 | ||
| 20921 | #define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 | ||
| 20922 | #define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 | ||
| 20923 | #define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 | ||
| 20924 | #define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 | ||
| 20925 | #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 | ||
| 20926 | #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 | ||
| 20927 | #define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 | ||
| 20928 | #define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 | ||
| 20929 | #define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 | ||
| 20930 | #define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a | ||
| 20931 | #define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 | ||
| 20932 | #define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b | ||
| 20933 | #define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 | ||
| 20934 | #define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c | ||
| 20935 | #define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 | ||
| 20936 | #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d | ||
| 20937 | #define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 | ||
| 20938 | #define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e | ||
| 20939 | #define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 | ||
| 20940 | #define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f | ||
| 20941 | #define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff | ||
| 20942 | #define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0 | ||
| 20943 | #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff | ||
| 20944 | #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 | ||
| 20945 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 20946 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 20947 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 20948 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 20949 | #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 20950 | #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 20951 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 20952 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 20953 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 20954 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 20955 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff | ||
| 20956 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 20957 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 20958 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 20959 | #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 20960 | #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 20961 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 20962 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 20963 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 20964 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 20965 | #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff | ||
| 20966 | #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 20967 | #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 20968 | #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 20969 | #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff | ||
| 20970 | #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 20971 | #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 20972 | #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 20973 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 20974 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 20975 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 20976 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 20977 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 20978 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 20979 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 20980 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 20981 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 20982 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 20983 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 20984 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 20985 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 20986 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 20987 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 20988 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 20989 | #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 20990 | #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 20991 | #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 20992 | #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 20993 | #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 20994 | #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 20995 | #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 20996 | #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 20997 | #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 20998 | #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 20999 | #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21000 | #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21001 | #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21002 | #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21003 | #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21004 | #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21005 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff | ||
| 21006 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21007 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 | ||
| 21008 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa | ||
| 21009 | #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 | ||
| 21010 | #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 | ||
| 21011 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 | ||
| 21012 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 | ||
| 21013 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21014 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21015 | #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff | ||
| 21016 | #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21017 | #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21018 | #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21019 | #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff | ||
| 21020 | #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21021 | #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21022 | #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21023 | #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff | ||
| 21024 | #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21025 | #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21026 | #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21027 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff | ||
| 21028 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 | ||
| 21029 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 | ||
| 21030 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa | ||
| 21031 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 | ||
| 21032 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 | ||
| 21033 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 | ||
| 21034 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c | ||
| 21035 | #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21036 | #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21037 | #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21038 | #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21039 | #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21040 | #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21041 | #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21042 | #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21043 | #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21044 | #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21045 | #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21046 | #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21047 | #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21048 | #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21049 | #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21050 | #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21051 | #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff | ||
| 21052 | #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21053 | #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21054 | #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21055 | #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff | ||
| 21056 | #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21057 | #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21058 | #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21059 | #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff | ||
| 21060 | #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21061 | #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21062 | #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21063 | #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff | ||
| 21064 | #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 | ||
| 21065 | #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 | ||
| 21066 | #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c | ||
| 21067 | #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21068 | #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21069 | #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21070 | #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21071 | #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21072 | #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21073 | #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff | ||
| 21074 | #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 | ||
| 21075 | #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21076 | #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21077 | #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21078 | #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21079 | #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21080 | #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21081 | #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff | ||
| 21082 | #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 | ||
| 21083 | #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff | ||
| 21084 | #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 | ||
| 21085 | #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff | ||
| 21086 | #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 | ||
| 21087 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 | ||
| 21088 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 | ||
| 21089 | #define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 | ||
| 21090 | #define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 | ||
| 21091 | #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc | ||
| 21092 | #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 | ||
| 21093 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 | ||
| 21094 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 | ||
| 21095 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 | ||
| 21096 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 | ||
| 21097 | #define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0 | ||
| 21098 | #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6 | ||
| 21099 | #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff | ||
| 21100 | #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 | ||
| 21101 | #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 | ||
| 21102 | #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 | ||
| 21103 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 21104 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 21105 | #define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000 | ||
| 21106 | #define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe | ||
| 21107 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 21108 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 21109 | #define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000 | ||
| 21110 | #define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a | ||
| 21111 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 21112 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 21113 | #define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000 | ||
| 21114 | #define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f | ||
| 21115 | #define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff | ||
| 21116 | #define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0 | ||
| 21117 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 | ||
| 21118 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 | ||
| 21119 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff | ||
| 21120 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 | ||
| 21121 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 | ||
| 21122 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 | ||
| 21123 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 | ||
| 21124 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 | ||
| 21125 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 | ||
| 21126 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 | ||
| 21127 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff | ||
| 21128 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 | ||
| 21129 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 | ||
| 21130 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 | ||
| 21131 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 | ||
| 21132 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 | ||
| 21133 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 | ||
| 21134 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 | ||
| 21135 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff | ||
| 21136 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 | ||
| 21137 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 | ||
| 21138 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 | ||
| 21139 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 | ||
| 21140 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 | ||
| 21141 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 | ||
| 21142 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 | ||
| 21143 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 | ||
| 21144 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 | ||
| 21145 | #define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 | ||
| 21146 | #define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 | ||
| 21147 | #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc | ||
| 21148 | #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 | ||
| 21149 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 | ||
| 21150 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 | ||
| 21151 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 | ||
| 21152 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 | ||
| 21153 | #define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0 | ||
| 21154 | #define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6 | ||
| 21155 | #define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff | ||
| 21156 | #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 | ||
| 21157 | #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 | ||
| 21158 | #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 | ||
| 21159 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 21160 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 21161 | #define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000 | ||
| 21162 | #define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe | ||
| 21163 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 21164 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 21165 | #define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000 | ||
| 21166 | #define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a | ||
| 21167 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 21168 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 21169 | #define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000 | ||
| 21170 | #define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f | ||
| 21171 | #define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff | ||
| 21172 | #define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0 | ||
| 21173 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 | ||
| 21174 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 | ||
| 21175 | #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff | ||
| 21176 | #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 | ||
| 21177 | #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 | ||
| 21178 | #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 | ||
| 21179 | #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 | ||
| 21180 | #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 | ||
| 21181 | #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 | ||
| 21182 | #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 | ||
| 21183 | #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff | ||
| 21184 | #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 | ||
| 21185 | #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 | ||
| 21186 | #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 | ||
| 21187 | #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 | ||
| 21188 | #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 | ||
| 21189 | #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 | ||
| 21190 | #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 | ||
| 21191 | #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff | ||
| 21192 | #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 | ||
| 21193 | #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 | ||
| 21194 | #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 | ||
| 21195 | #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 | ||
| 21196 | #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 | ||
| 21197 | #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 | ||
| 21198 | #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 | ||
| 21199 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 | ||
| 21200 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 | ||
| 21201 | #define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 | ||
| 21202 | #define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 | ||
| 21203 | #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc | ||
| 21204 | #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 | ||
| 21205 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 | ||
| 21206 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 | ||
| 21207 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 | ||
| 21208 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 | ||
| 21209 | #define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0 | ||
| 21210 | #define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6 | ||
| 21211 | #define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff | ||
| 21212 | #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 | ||
| 21213 | #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 | ||
| 21214 | #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 | ||
| 21215 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 21216 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 21217 | #define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000 | ||
| 21218 | #define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe | ||
| 21219 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 21220 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 21221 | #define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000 | ||
| 21222 | #define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a | ||
| 21223 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 21224 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 21225 | #define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000 | ||
| 21226 | #define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f | ||
| 21227 | #define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff | ||
| 21228 | #define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0 | ||
| 21229 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 | ||
| 21230 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 | ||
| 21231 | #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff | ||
| 21232 | #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 | ||
| 21233 | #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 | ||
| 21234 | #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 | ||
| 21235 | #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 | ||
| 21236 | #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 | ||
| 21237 | #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 | ||
| 21238 | #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 | ||
| 21239 | #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff | ||
| 21240 | #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 | ||
| 21241 | #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 | ||
| 21242 | #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 | ||
| 21243 | #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 | ||
| 21244 | #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 | ||
| 21245 | #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 | ||
| 21246 | #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 | ||
| 21247 | #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff | ||
| 21248 | #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 | ||
| 21249 | #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 | ||
| 21250 | #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 | ||
| 21251 | #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 | ||
| 21252 | #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 | ||
| 21253 | #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 | ||
| 21254 | #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 | ||
| 21255 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 | ||
| 21256 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 | ||
| 21257 | #define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 | ||
| 21258 | #define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 | ||
| 21259 | #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc | ||
| 21260 | #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 | ||
| 21261 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 | ||
| 21262 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 | ||
| 21263 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 | ||
| 21264 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 | ||
| 21265 | #define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0 | ||
| 21266 | #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6 | ||
| 21267 | #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff | ||
| 21268 | #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 | ||
| 21269 | #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 | ||
| 21270 | #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 | ||
| 21271 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 21272 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 21273 | #define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000 | ||
| 21274 | #define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe | ||
| 21275 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 21276 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 21277 | #define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000 | ||
| 21278 | #define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a | ||
| 21279 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 21280 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 21281 | #define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000 | ||
| 21282 | #define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f | ||
| 21283 | #define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff | ||
| 21284 | #define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0 | ||
| 21285 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 | ||
| 21286 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 | ||
| 21287 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff | ||
| 21288 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 | ||
| 21289 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 | ||
| 21290 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 | ||
| 21291 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 | ||
| 21292 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 | ||
| 21293 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 | ||
| 21294 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 | ||
| 21295 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff | ||
| 21296 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 | ||
| 21297 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 | ||
| 21298 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 | ||
| 21299 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 | ||
| 21300 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 | ||
| 21301 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 | ||
| 21302 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 | ||
| 21303 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff | ||
| 21304 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 | ||
| 21305 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 | ||
| 21306 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 | ||
| 21307 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 | ||
| 21308 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 | ||
| 21309 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 | ||
| 21310 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 | ||
| 21311 | #define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1 | ||
| 21312 | #define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 | ||
| 21313 | #define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2 | ||
| 21314 | #define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1 | ||
| 21315 | #define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc | ||
| 21316 | #define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2 | ||
| 21317 | #define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10 | ||
| 21318 | #define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 | ||
| 21319 | #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 | ||
| 21320 | #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 | ||
| 21321 | #define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0 | ||
| 21322 | #define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6 | ||
| 21323 | #define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff | ||
| 21324 | #define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 | ||
| 21325 | #define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000 | ||
| 21326 | #define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 | ||
| 21327 | #define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff | ||
| 21328 | #define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 | ||
| 21329 | #define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000 | ||
| 21330 | #define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe | ||
| 21331 | #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 | ||
| 21332 | #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 | ||
| 21333 | #define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000 | ||
| 21334 | #define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a | ||
| 21335 | #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 | ||
| 21336 | #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b | ||
| 21337 | #define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000 | ||
| 21338 | #define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f | ||
| 21339 | #define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff | ||
| 21340 | #define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0 | ||
| 21341 | #define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 | ||
| 21342 | #define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 | ||
| 21343 | #define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff | ||
| 21344 | #define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 | ||
| 21345 | #define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00 | ||
| 21346 | #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 | ||
| 21347 | #define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000 | ||
| 21348 | #define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 | ||
| 21349 | #define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000 | ||
| 21350 | #define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 | ||
| 21351 | #define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff | ||
| 21352 | #define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 | ||
| 21353 | #define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00 | ||
| 21354 | #define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 | ||
| 21355 | #define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000 | ||
| 21356 | #define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 | ||
| 21357 | #define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000 | ||
| 21358 | #define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 | ||
| 21359 | #define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff | ||
| 21360 | #define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 | ||
| 21361 | #define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00 | ||
| 21362 | #define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 | ||
| 21363 | #define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000 | ||
| 21364 | #define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 | ||
| 21365 | #define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000 | ||
| 21366 | #define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 | ||
| 21367 | |||
| 21368 | #endif /* GFX_8_1_SH_MASK_H */ | ||