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authorKen Wang <Qingqing.Wang@amd.com>2016-01-19 00:53:10 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-08-31 12:09:08 -0400
commit0f27e46258ee73e2fd149f91cb176475ce9b7537 (patch)
tree86ee4c4482c405bd260bb90fb70ac712fd1b8e4c /drivers/gpu/drm/amd/include
parent26d721c5f5f1d2b140c6df5a361dcebc8cbf090b (diff)
drm/amdgpu: add si header files v4
v4: drop unused DCE6 macro Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h941
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h105
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/si/sid.h2408
3 files changed, 3454 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h b/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
new file mode 100644
index 000000000000..66e39cdb5cb0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
@@ -0,0 +1,941 @@
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24static const u32 si_SECT_CONTEXT_def_1[] =
25{
26 0x00000000, // DB_RENDER_CONTROL
27 0x00000000, // DB_COUNT_CONTROL
28 0x00000000, // DB_DEPTH_VIEW
29 0x00000000, // DB_RENDER_OVERRIDE
30 0x00000000, // DB_RENDER_OVERRIDE2
31 0x00000000, // DB_HTILE_DATA_BASE
32 0, // HOLE
33 0, // HOLE
34 0x00000000, // DB_DEPTH_BOUNDS_MIN
35 0x00000000, // DB_DEPTH_BOUNDS_MAX
36 0x00000000, // DB_STENCIL_CLEAR
37 0x00000000, // DB_DEPTH_CLEAR
38 0x00000000, // PA_SC_SCREEN_SCISSOR_TL
39 0x40004000, // PA_SC_SCREEN_SCISSOR_BR
40 0, // HOLE
41 0x00000000, // DB_DEPTH_INFO
42 0x00000000, // DB_Z_INFO
43 0x00000000, // DB_STENCIL_INFO
44 0x00000000, // DB_Z_READ_BASE
45 0x00000000, // DB_STENCIL_READ_BASE
46 0x00000000, // DB_Z_WRITE_BASE
47 0x00000000, // DB_STENCIL_WRITE_BASE
48 0x00000000, // DB_DEPTH_SIZE
49 0x00000000, // DB_DEPTH_SLICE
50 0, // HOLE
51 0, // HOLE
52 0, // HOLE
53 0, // HOLE
54 0, // HOLE
55 0, // HOLE
56 0, // HOLE
57 0, // HOLE
58 0x00000000, // TA_BC_BASE_ADDR
59 0, // HOLE
60 0, // HOLE
61 0, // HOLE
62 0, // HOLE
63 0, // HOLE
64 0, // HOLE
65 0, // HOLE
66 0, // HOLE
67 0, // HOLE
68 0, // HOLE
69 0, // HOLE
70 0, // HOLE
71 0, // HOLE
72 0, // HOLE
73 0, // HOLE
74 0, // HOLE
75 0, // HOLE
76 0, // HOLE
77 0, // HOLE
78 0, // HOLE
79 0, // HOLE
80 0, // HOLE
81 0, // HOLE
82 0, // HOLE
83 0, // HOLE
84 0, // HOLE
85 0, // HOLE
86 0, // HOLE
87 0, // HOLE
88 0, // HOLE
89 0, // HOLE
90 0, // HOLE
91 0, // HOLE
92 0, // HOLE
93 0, // HOLE
94 0, // HOLE
95 0, // HOLE
96 0, // HOLE
97 0, // HOLE
98 0, // HOLE
99 0, // HOLE
100 0, // HOLE
101 0, // HOLE
102 0, // HOLE
103 0, // HOLE
104 0, // HOLE
105 0, // HOLE
106 0, // HOLE
107 0, // HOLE
108 0, // HOLE
109 0, // HOLE
110 0, // HOLE
111 0, // HOLE
112 0, // HOLE
113 0, // HOLE
114 0, // HOLE
115 0, // HOLE
116 0, // HOLE
117 0, // HOLE
118 0, // HOLE
119 0, // HOLE
120 0, // HOLE
121 0, // HOLE
122 0, // HOLE
123 0, // HOLE
124 0, // HOLE
125 0, // HOLE
126 0, // HOLE
127 0, // HOLE
128 0, // HOLE
129 0, // HOLE
130 0, // HOLE
131 0, // HOLE
132 0, // HOLE
133 0, // HOLE
134 0, // HOLE
135 0, // HOLE
136 0, // HOLE
137 0, // HOLE
138 0, // HOLE
139 0, // HOLE
140 0, // HOLE
141 0, // HOLE
142 0, // HOLE
143 0, // HOLE
144 0, // HOLE
145 0, // HOLE
146 0, // HOLE
147 0, // HOLE
148 0, // HOLE
149 0, // HOLE
150 0, // HOLE
151 0, // HOLE
152 0x00000000, // COHER_DEST_BASE_2
153 0x00000000, // COHER_DEST_BASE_3
154 0x00000000, // PA_SC_WINDOW_OFFSET
155 0x80000000, // PA_SC_WINDOW_SCISSOR_TL
156 0x40004000, // PA_SC_WINDOW_SCISSOR_BR
157 0x0000ffff, // PA_SC_CLIPRECT_RULE
158 0x00000000, // PA_SC_CLIPRECT_0_TL
159 0x40004000, // PA_SC_CLIPRECT_0_BR
160 0x00000000, // PA_SC_CLIPRECT_1_TL
161 0x40004000, // PA_SC_CLIPRECT_1_BR
162 0x00000000, // PA_SC_CLIPRECT_2_TL
163 0x40004000, // PA_SC_CLIPRECT_2_BR
164 0x00000000, // PA_SC_CLIPRECT_3_TL
165 0x40004000, // PA_SC_CLIPRECT_3_BR
166 0xaa99aaaa, // PA_SC_EDGERULE
167 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
168 0xffffffff, // CB_TARGET_MASK
169 0xffffffff, // CB_SHADER_MASK
170 0x80000000, // PA_SC_GENERIC_SCISSOR_TL
171 0x40004000, // PA_SC_GENERIC_SCISSOR_BR
172 0x00000000, // COHER_DEST_BASE_0
173 0x00000000, // COHER_DEST_BASE_1
174 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
175 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
176 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
177 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
178 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
179 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
180 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
181 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
182 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
183 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
184 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
185 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
186 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
187 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
188 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
189 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
190 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
191 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
192 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
193 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
194 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
195 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
196 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
197 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
198 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
199 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
200 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
201 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
202 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
203 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
204 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
205 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
206 0x00000000, // PA_SC_VPORT_ZMIN_0
207 0x3f800000, // PA_SC_VPORT_ZMAX_0
208 0x00000000, // PA_SC_VPORT_ZMIN_1
209 0x3f800000, // PA_SC_VPORT_ZMAX_1
210 0x00000000, // PA_SC_VPORT_ZMIN_2
211 0x3f800000, // PA_SC_VPORT_ZMAX_2
212 0x00000000, // PA_SC_VPORT_ZMIN_3
213 0x3f800000, // PA_SC_VPORT_ZMAX_3
214 0x00000000, // PA_SC_VPORT_ZMIN_4
215 0x3f800000, // PA_SC_VPORT_ZMAX_4
216 0x00000000, // PA_SC_VPORT_ZMIN_5
217 0x3f800000, // PA_SC_VPORT_ZMAX_5
218 0x00000000, // PA_SC_VPORT_ZMIN_6
219 0x3f800000, // PA_SC_VPORT_ZMAX_6
220 0x00000000, // PA_SC_VPORT_ZMIN_7
221 0x3f800000, // PA_SC_VPORT_ZMAX_7
222 0x00000000, // PA_SC_VPORT_ZMIN_8
223 0x3f800000, // PA_SC_VPORT_ZMAX_8
224 0x00000000, // PA_SC_VPORT_ZMIN_9
225 0x3f800000, // PA_SC_VPORT_ZMAX_9
226 0x00000000, // PA_SC_VPORT_ZMIN_10
227 0x3f800000, // PA_SC_VPORT_ZMAX_10
228 0x00000000, // PA_SC_VPORT_ZMIN_11
229 0x3f800000, // PA_SC_VPORT_ZMAX_11
230 0x00000000, // PA_SC_VPORT_ZMIN_12
231 0x3f800000, // PA_SC_VPORT_ZMAX_12
232 0x00000000, // PA_SC_VPORT_ZMIN_13
233 0x3f800000, // PA_SC_VPORT_ZMAX_13
234 0x00000000, // PA_SC_VPORT_ZMIN_14
235 0x3f800000, // PA_SC_VPORT_ZMAX_14
236 0x00000000, // PA_SC_VPORT_ZMIN_15
237 0x3f800000, // PA_SC_VPORT_ZMAX_15
238};
239static const u32 si_SECT_CONTEXT_def_2[] =
240{
241 0x00000000, // CP_PERFMON_CNTX_CNTL
242 0x00000000, // CP_RINGID
243 0x00000000, // CP_VMID
244 0, // HOLE
245 0, // HOLE
246 0, // HOLE
247 0, // HOLE
248 0, // HOLE
249 0, // HOLE
250 0, // HOLE
251 0, // HOLE
252 0, // HOLE
253 0, // HOLE
254 0, // HOLE
255 0, // HOLE
256 0, // HOLE
257 0, // HOLE
258 0, // HOLE
259 0, // HOLE
260 0, // HOLE
261 0, // HOLE
262 0, // HOLE
263 0, // HOLE
264 0, // HOLE
265 0, // HOLE
266 0, // HOLE
267 0, // HOLE
268 0, // HOLE
269 0, // HOLE
270 0, // HOLE
271 0, // HOLE
272 0, // HOLE
273 0, // HOLE
274 0, // HOLE
275 0, // HOLE
276 0, // HOLE
277 0, // HOLE
278 0, // HOLE
279 0, // HOLE
280 0, // HOLE
281 0xffffffff, // VGT_MAX_VTX_INDX
282 0x00000000, // VGT_MIN_VTX_INDX
283 0x00000000, // VGT_INDX_OFFSET
284 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
285 0, // HOLE
286 0x00000000, // CB_BLEND_RED
287 0x00000000, // CB_BLEND_GREEN
288 0x00000000, // CB_BLEND_BLUE
289 0x00000000, // CB_BLEND_ALPHA
290 0, // HOLE
291 0, // HOLE
292 0x00000000, // DB_STENCIL_CONTROL
293 0x00000000, // DB_STENCILREFMASK
294 0x00000000, // DB_STENCILREFMASK_BF
295 0, // HOLE
296 0x00000000, // PA_CL_VPORT_XSCALE
297 0x00000000, // PA_CL_VPORT_XOFFSET
298 0x00000000, // PA_CL_VPORT_YSCALE
299 0x00000000, // PA_CL_VPORT_YOFFSET
300 0x00000000, // PA_CL_VPORT_ZSCALE
301 0x00000000, // PA_CL_VPORT_ZOFFSET
302 0x00000000, // PA_CL_VPORT_XSCALE_1
303 0x00000000, // PA_CL_VPORT_XOFFSET_1
304 0x00000000, // PA_CL_VPORT_YSCALE_1
305 0x00000000, // PA_CL_VPORT_YOFFSET_1
306 0x00000000, // PA_CL_VPORT_ZSCALE_1
307 0x00000000, // PA_CL_VPORT_ZOFFSET_1
308 0x00000000, // PA_CL_VPORT_XSCALE_2
309 0x00000000, // PA_CL_VPORT_XOFFSET_2
310 0x00000000, // PA_CL_VPORT_YSCALE_2
311 0x00000000, // PA_CL_VPORT_YOFFSET_2
312 0x00000000, // PA_CL_VPORT_ZSCALE_2
313 0x00000000, // PA_CL_VPORT_ZOFFSET_2
314 0x00000000, // PA_CL_VPORT_XSCALE_3
315 0x00000000, // PA_CL_VPORT_XOFFSET_3
316 0x00000000, // PA_CL_VPORT_YSCALE_3
317 0x00000000, // PA_CL_VPORT_YOFFSET_3
318 0x00000000, // PA_CL_VPORT_ZSCALE_3
319 0x00000000, // PA_CL_VPORT_ZOFFSET_3
320 0x00000000, // PA_CL_VPORT_XSCALE_4
321 0x00000000, // PA_CL_VPORT_XOFFSET_4
322 0x00000000, // PA_CL_VPORT_YSCALE_4
323 0x00000000, // PA_CL_VPORT_YOFFSET_4
324 0x00000000, // PA_CL_VPORT_ZSCALE_4
325 0x00000000, // PA_CL_VPORT_ZOFFSET_4
326 0x00000000, // PA_CL_VPORT_XSCALE_5
327 0x00000000, // PA_CL_VPORT_XOFFSET_5
328 0x00000000, // PA_CL_VPORT_YSCALE_5
329 0x00000000, // PA_CL_VPORT_YOFFSET_5
330 0x00000000, // PA_CL_VPORT_ZSCALE_5
331 0x00000000, // PA_CL_VPORT_ZOFFSET_5
332 0x00000000, // PA_CL_VPORT_XSCALE_6
333 0x00000000, // PA_CL_VPORT_XOFFSET_6
334 0x00000000, // PA_CL_VPORT_YSCALE_6
335 0x00000000, // PA_CL_VPORT_YOFFSET_6
336 0x00000000, // PA_CL_VPORT_ZSCALE_6
337 0x00000000, // PA_CL_VPORT_ZOFFSET_6
338 0x00000000, // PA_CL_VPORT_XSCALE_7
339 0x00000000, // PA_CL_VPORT_XOFFSET_7
340 0x00000000, // PA_CL_VPORT_YSCALE_7
341 0x00000000, // PA_CL_VPORT_YOFFSET_7
342 0x00000000, // PA_CL_VPORT_ZSCALE_7
343 0x00000000, // PA_CL_VPORT_ZOFFSET_7
344 0x00000000, // PA_CL_VPORT_XSCALE_8
345 0x00000000, // PA_CL_VPORT_XOFFSET_8
346 0x00000000, // PA_CL_VPORT_YSCALE_8
347 0x00000000, // PA_CL_VPORT_YOFFSET_8
348 0x00000000, // PA_CL_VPORT_ZSCALE_8
349 0x00000000, // PA_CL_VPORT_ZOFFSET_8
350 0x00000000, // PA_CL_VPORT_XSCALE_9
351 0x00000000, // PA_CL_VPORT_XOFFSET_9
352 0x00000000, // PA_CL_VPORT_YSCALE_9
353 0x00000000, // PA_CL_VPORT_YOFFSET_9
354 0x00000000, // PA_CL_VPORT_ZSCALE_9
355 0x00000000, // PA_CL_VPORT_ZOFFSET_9
356 0x00000000, // PA_CL_VPORT_XSCALE_10
357 0x00000000, // PA_CL_VPORT_XOFFSET_10
358 0x00000000, // PA_CL_VPORT_YSCALE_10
359 0x00000000, // PA_CL_VPORT_YOFFSET_10
360 0x00000000, // PA_CL_VPORT_ZSCALE_10
361 0x00000000, // PA_CL_VPORT_ZOFFSET_10
362 0x00000000, // PA_CL_VPORT_XSCALE_11
363 0x00000000, // PA_CL_VPORT_XOFFSET_11
364 0x00000000, // PA_CL_VPORT_YSCALE_11
365 0x00000000, // PA_CL_VPORT_YOFFSET_11
366 0x00000000, // PA_CL_VPORT_ZSCALE_11
367 0x00000000, // PA_CL_VPORT_ZOFFSET_11
368 0x00000000, // PA_CL_VPORT_XSCALE_12
369 0x00000000, // PA_CL_VPORT_XOFFSET_12
370 0x00000000, // PA_CL_VPORT_YSCALE_12
371 0x00000000, // PA_CL_VPORT_YOFFSET_12
372 0x00000000, // PA_CL_VPORT_ZSCALE_12
373 0x00000000, // PA_CL_VPORT_ZOFFSET_12
374 0x00000000, // PA_CL_VPORT_XSCALE_13
375 0x00000000, // PA_CL_VPORT_XOFFSET_13
376 0x00000000, // PA_CL_VPORT_YSCALE_13
377 0x00000000, // PA_CL_VPORT_YOFFSET_13
378 0x00000000, // PA_CL_VPORT_ZSCALE_13
379 0x00000000, // PA_CL_VPORT_ZOFFSET_13
380 0x00000000, // PA_CL_VPORT_XSCALE_14
381 0x00000000, // PA_CL_VPORT_XOFFSET_14
382 0x00000000, // PA_CL_VPORT_YSCALE_14
383 0x00000000, // PA_CL_VPORT_YOFFSET_14
384 0x00000000, // PA_CL_VPORT_ZSCALE_14
385 0x00000000, // PA_CL_VPORT_ZOFFSET_14
386 0x00000000, // PA_CL_VPORT_XSCALE_15
387 0x00000000, // PA_CL_VPORT_XOFFSET_15
388 0x00000000, // PA_CL_VPORT_YSCALE_15
389 0x00000000, // PA_CL_VPORT_YOFFSET_15
390 0x00000000, // PA_CL_VPORT_ZSCALE_15
391 0x00000000, // PA_CL_VPORT_ZOFFSET_15
392 0x00000000, // PA_CL_UCP_0_X
393 0x00000000, // PA_CL_UCP_0_Y
394 0x00000000, // PA_CL_UCP_0_Z
395 0x00000000, // PA_CL_UCP_0_W
396 0x00000000, // PA_CL_UCP_1_X
397 0x00000000, // PA_CL_UCP_1_Y
398 0x00000000, // PA_CL_UCP_1_Z
399 0x00000000, // PA_CL_UCP_1_W
400 0x00000000, // PA_CL_UCP_2_X
401 0x00000000, // PA_CL_UCP_2_Y
402 0x00000000, // PA_CL_UCP_2_Z
403 0x00000000, // PA_CL_UCP_2_W
404 0x00000000, // PA_CL_UCP_3_X
405 0x00000000, // PA_CL_UCP_3_Y
406 0x00000000, // PA_CL_UCP_3_Z
407 0x00000000, // PA_CL_UCP_3_W
408 0x00000000, // PA_CL_UCP_4_X
409 0x00000000, // PA_CL_UCP_4_Y
410 0x00000000, // PA_CL_UCP_4_Z
411 0x00000000, // PA_CL_UCP_4_W
412 0x00000000, // PA_CL_UCP_5_X
413 0x00000000, // PA_CL_UCP_5_Y
414 0x00000000, // PA_CL_UCP_5_Z
415 0x00000000, // PA_CL_UCP_5_W
416 0, // HOLE
417 0, // HOLE
418 0, // HOLE
419 0, // HOLE
420 0, // HOLE
421 0, // HOLE
422 0, // HOLE
423 0, // HOLE
424 0, // HOLE
425 0, // HOLE
426 0x00000000, // SPI_PS_INPUT_CNTL_0
427 0x00000000, // SPI_PS_INPUT_CNTL_1
428 0x00000000, // SPI_PS_INPUT_CNTL_2
429 0x00000000, // SPI_PS_INPUT_CNTL_3
430 0x00000000, // SPI_PS_INPUT_CNTL_4
431 0x00000000, // SPI_PS_INPUT_CNTL_5
432 0x00000000, // SPI_PS_INPUT_CNTL_6
433 0x00000000, // SPI_PS_INPUT_CNTL_7
434 0x00000000, // SPI_PS_INPUT_CNTL_8
435 0x00000000, // SPI_PS_INPUT_CNTL_9
436 0x00000000, // SPI_PS_INPUT_CNTL_10
437 0x00000000, // SPI_PS_INPUT_CNTL_11
438 0x00000000, // SPI_PS_INPUT_CNTL_12
439 0x00000000, // SPI_PS_INPUT_CNTL_13
440 0x00000000, // SPI_PS_INPUT_CNTL_14
441 0x00000000, // SPI_PS_INPUT_CNTL_15
442 0x00000000, // SPI_PS_INPUT_CNTL_16
443 0x00000000, // SPI_PS_INPUT_CNTL_17
444 0x00000000, // SPI_PS_INPUT_CNTL_18
445 0x00000000, // SPI_PS_INPUT_CNTL_19
446 0x00000000, // SPI_PS_INPUT_CNTL_20
447 0x00000000, // SPI_PS_INPUT_CNTL_21
448 0x00000000, // SPI_PS_INPUT_CNTL_22
449 0x00000000, // SPI_PS_INPUT_CNTL_23
450 0x00000000, // SPI_PS_INPUT_CNTL_24
451 0x00000000, // SPI_PS_INPUT_CNTL_25
452 0x00000000, // SPI_PS_INPUT_CNTL_26
453 0x00000000, // SPI_PS_INPUT_CNTL_27
454 0x00000000, // SPI_PS_INPUT_CNTL_28
455 0x00000000, // SPI_PS_INPUT_CNTL_29
456 0x00000000, // SPI_PS_INPUT_CNTL_30
457 0x00000000, // SPI_PS_INPUT_CNTL_31
458 0x00000000, // SPI_VS_OUT_CONFIG
459 0, // HOLE
460 0x00000000, // SPI_PS_INPUT_ENA
461 0x00000000, // SPI_PS_INPUT_ADDR
462 0x00000000, // SPI_INTERP_CONTROL_0
463 0x00000002, // SPI_PS_IN_CONTROL
464 0, // HOLE
465 0x00000000, // SPI_BARYC_CNTL
466 0, // HOLE
467 0x00000000, // SPI_TMPRING_SIZE
468 0, // HOLE
469 0, // HOLE
470 0, // HOLE
471 0, // HOLE
472 0, // HOLE
473 0, // HOLE
474 0x00000000, // SPI_WAVE_MGMT_1
475 0x00000000, // SPI_WAVE_MGMT_2
476 0x00000000, // SPI_SHADER_POS_FORMAT
477 0x00000000, // SPI_SHADER_Z_FORMAT
478 0x00000000, // SPI_SHADER_COL_FORMAT
479 0, // HOLE
480 0, // HOLE
481 0, // HOLE
482 0, // HOLE
483 0, // HOLE
484 0, // HOLE
485 0, // HOLE
486 0, // HOLE
487 0, // HOLE
488 0, // HOLE
489 0, // HOLE
490 0, // HOLE
491 0, // HOLE
492 0, // HOLE
493 0, // HOLE
494 0, // HOLE
495 0, // HOLE
496 0, // HOLE
497 0, // HOLE
498 0, // HOLE
499 0, // HOLE
500 0, // HOLE
501 0, // HOLE
502 0, // HOLE
503 0, // HOLE
504 0, // HOLE
505 0x00000000, // CB_BLEND0_CONTROL
506 0x00000000, // CB_BLEND1_CONTROL
507 0x00000000, // CB_BLEND2_CONTROL
508 0x00000000, // CB_BLEND3_CONTROL
509 0x00000000, // CB_BLEND4_CONTROL
510 0x00000000, // CB_BLEND5_CONTROL
511 0x00000000, // CB_BLEND6_CONTROL
512 0x00000000, // CB_BLEND7_CONTROL
513};
514static const u32 si_SECT_CONTEXT_def_3[] =
515{
516 0x00000000, // PA_CL_POINT_X_RAD
517 0x00000000, // PA_CL_POINT_Y_RAD
518 0x00000000, // PA_CL_POINT_SIZE
519 0x00000000, // PA_CL_POINT_CULL_RAD
520 0x00000000, // VGT_DMA_BASE_HI
521 0x00000000, // VGT_DMA_BASE
522};
523static const u32 si_SECT_CONTEXT_def_4[] =
524{
525 0x00000000, // DB_DEPTH_CONTROL
526 0x00000000, // DB_EQAA
527 0x00000000, // CB_COLOR_CONTROL
528 0x00000000, // DB_SHADER_CONTROL
529 0x00090000, // PA_CL_CLIP_CNTL
530 0x00000004, // PA_SU_SC_MODE_CNTL
531 0x00000000, // PA_CL_VTE_CNTL
532 0x00000000, // PA_CL_VS_OUT_CNTL
533 0x00000000, // PA_CL_NANINF_CNTL
534 0x00000000, // PA_SU_LINE_STIPPLE_CNTL
535 0x00000000, // PA_SU_LINE_STIPPLE_SCALE
536 0x00000000, // PA_SU_PRIM_FILTER_CNTL
537 0, // HOLE
538 0, // HOLE
539 0, // HOLE
540 0, // HOLE
541 0, // HOLE
542 0, // HOLE
543 0, // HOLE
544 0, // HOLE
545 0, // HOLE
546 0, // HOLE
547 0, // HOLE
548 0, // HOLE
549 0, // HOLE
550 0, // HOLE
551 0, // HOLE
552 0, // HOLE
553 0, // HOLE
554 0, // HOLE
555 0, // HOLE
556 0, // HOLE
557 0, // HOLE
558 0, // HOLE
559 0, // HOLE
560 0, // HOLE
561 0, // HOLE
562 0, // HOLE
563 0, // HOLE
564 0, // HOLE
565 0, // HOLE
566 0, // HOLE
567 0, // HOLE
568 0, // HOLE
569 0, // HOLE
570 0, // HOLE
571 0, // HOLE
572 0, // HOLE
573 0, // HOLE
574 0, // HOLE
575 0, // HOLE
576 0, // HOLE
577 0, // HOLE
578 0, // HOLE
579 0, // HOLE
580 0, // HOLE
581 0, // HOLE
582 0, // HOLE
583 0, // HOLE
584 0, // HOLE
585 0, // HOLE
586 0, // HOLE
587 0, // HOLE
588 0, // HOLE
589 0, // HOLE
590 0, // HOLE
591 0, // HOLE
592 0, // HOLE
593 0, // HOLE
594 0, // HOLE
595 0, // HOLE
596 0, // HOLE
597 0, // HOLE
598 0, // HOLE
599 0, // HOLE
600 0, // HOLE
601 0, // HOLE
602 0, // HOLE
603 0, // HOLE
604 0, // HOLE
605 0, // HOLE
606 0, // HOLE
607 0, // HOLE
608 0, // HOLE
609 0, // HOLE
610 0, // HOLE
611 0, // HOLE
612 0, // HOLE
613 0, // HOLE
614 0, // HOLE
615 0, // HOLE
616 0, // HOLE
617 0, // HOLE
618 0, // HOLE
619 0, // HOLE
620 0, // HOLE
621 0, // HOLE
622 0, // HOLE
623 0, // HOLE
624 0, // HOLE
625 0, // HOLE
626 0, // HOLE
627 0, // HOLE
628 0, // HOLE
629 0, // HOLE
630 0, // HOLE
631 0, // HOLE
632 0, // HOLE
633 0, // HOLE
634 0, // HOLE
635 0, // HOLE
636 0, // HOLE
637 0, // HOLE
638 0, // HOLE
639 0, // HOLE
640 0, // HOLE
641 0, // HOLE
642 0, // HOLE
643 0, // HOLE
644 0, // HOLE
645 0, // HOLE
646 0, // HOLE
647 0, // HOLE
648 0, // HOLE
649 0, // HOLE
650 0, // HOLE
651 0, // HOLE
652 0, // HOLE
653 0x00000000, // PA_SU_POINT_SIZE
654 0x00000000, // PA_SU_POINT_MINMAX
655 0x00000000, // PA_SU_LINE_CNTL
656 0x00000000, // PA_SC_LINE_STIPPLE
657 0x00000000, // VGT_OUTPUT_PATH_CNTL
658 0x00000000, // VGT_HOS_CNTL
659 0x00000000, // VGT_HOS_MAX_TESS_LEVEL
660 0x00000000, // VGT_HOS_MIN_TESS_LEVEL
661 0x00000000, // VGT_HOS_REUSE_DEPTH
662 0x00000000, // VGT_GROUP_PRIM_TYPE
663 0x00000000, // VGT_GROUP_FIRST_DECR
664 0x00000000, // VGT_GROUP_DECR
665 0x00000000, // VGT_GROUP_VECT_0_CNTL
666 0x00000000, // VGT_GROUP_VECT_1_CNTL
667 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
668 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
669 0x00000000, // VGT_GS_MODE
670 0, // HOLE
671 0x00000000, // PA_SC_MODE_CNTL_0
672 0x00000000, // PA_SC_MODE_CNTL_1
673 0x00000000, // VGT_ENHANCE
674 0x00000100, // VGT_GS_PER_ES
675 0x00000080, // VGT_ES_PER_GS
676 0x00000002, // VGT_GS_PER_VS
677 0x00000000, // VGT_GSVS_RING_OFFSET_1
678 0x00000000, // VGT_GSVS_RING_OFFSET_2
679 0x00000000, // VGT_GSVS_RING_OFFSET_3
680 0x00000000, // VGT_GS_OUT_PRIM_TYPE
681 0x00000000, // IA_ENHANCE
682};
683static const u32 si_SECT_CONTEXT_def_5[] =
684{
685 0x00000000, // VGT_PRIMITIVEID_EN
686};
687static const u32 si_SECT_CONTEXT_def_6[] =
688{
689 0x00000000, // VGT_PRIMITIVEID_RESET
690};
691static const u32 si_SECT_CONTEXT_def_7[] =
692{
693 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
694 0, // HOLE
695 0, // HOLE
696 0x00000000, // VGT_INSTANCE_STEP_RATE_0
697 0x00000000, // VGT_INSTANCE_STEP_RATE_1
698 0x000000ff, // IA_MULTI_VGT_PARAM
699 0x00000000, // VGT_ESGS_RING_ITEMSIZE
700 0x00000000, // VGT_GSVS_RING_ITEMSIZE
701 0x00000000, // VGT_REUSE_OFF
702 0x00000000, // VGT_VTX_CNT_EN
703 0x00000000, // DB_HTILE_SURFACE
704 0x00000000, // DB_SRESULTS_COMPARE_STATE0
705 0x00000000, // DB_SRESULTS_COMPARE_STATE1
706 0x00000000, // DB_PRELOAD_CONTROL
707 0, // HOLE
708 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
709 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
710 0, // HOLE
711 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
712 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
713 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
714 0, // HOLE
715 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
716 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
717 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
718 0, // HOLE
719 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
720 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
721 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
722 0, // HOLE
723 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
724 0, // HOLE
725 0, // HOLE
726 0, // HOLE
727 0, // HOLE
728 0, // HOLE
729 0, // HOLE
730 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
731 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
732 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
733 0, // HOLE
734 0x00000000, // VGT_GS_MAX_VERT_OUT
735 0, // HOLE
736 0, // HOLE
737 0, // HOLE
738 0, // HOLE
739 0, // HOLE
740 0, // HOLE
741 0x00000000, // VGT_SHADER_STAGES_EN
742 0x00000000, // VGT_LS_HS_CONFIG
743 0x00000000, // VGT_GS_VERT_ITEMSIZE
744 0x00000000, // VGT_GS_VERT_ITEMSIZE_1
745 0x00000000, // VGT_GS_VERT_ITEMSIZE_2
746 0x00000000, // VGT_GS_VERT_ITEMSIZE_3
747 0x00000000, // VGT_TF_PARAM
748 0x00000000, // DB_ALPHA_TO_MASK
749 0, // HOLE
750 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
751 0x00000000, // PA_SU_POLY_OFFSET_CLAMP
752 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
753 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
754 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
755 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
756 0x00000000, // VGT_GS_INSTANCE_CNT
757 0x00000000, // VGT_STRMOUT_CONFIG
758 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
759 0, // HOLE
760 0, // HOLE
761 0, // HOLE
762 0, // HOLE
763 0, // HOLE
764 0, // HOLE
765 0, // HOLE
766 0, // HOLE
767 0, // HOLE
768 0, // HOLE
769 0, // HOLE
770 0, // HOLE
771 0, // HOLE
772 0, // HOLE
773 0x00000000, // PA_SC_CENTROID_PRIORITY_0
774 0x00000000, // PA_SC_CENTROID_PRIORITY_1
775 0x00001000, // PA_SC_LINE_CNTL
776 0x00000000, // PA_SC_AA_CONFIG
777 0x00000005, // PA_SU_VTX_CNTL
778 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
779 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
780 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
781 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
782 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
783 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
784 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
785 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
786 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
787 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
788 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
789 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
790 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
791 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
792 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
793 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
794 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
795 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
796 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
797 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
798 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
799 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
800 0, // HOLE
801 0, // HOLE
802 0, // HOLE
803 0, // HOLE
804 0, // HOLE
805 0, // HOLE
806 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
807 0x00000010, // VGT_OUT_DEALLOC_CNTL
808 0x00000000, // CB_COLOR0_BASE
809 0x00000000, // CB_COLOR0_PITCH
810 0x00000000, // CB_COLOR0_SLICE
811 0x00000000, // CB_COLOR0_VIEW
812 0x00000000, // CB_COLOR0_INFO
813 0x00000000, // CB_COLOR0_ATTRIB
814 0, // HOLE
815 0x00000000, // CB_COLOR0_CMASK
816 0x00000000, // CB_COLOR0_CMASK_SLICE
817 0x00000000, // CB_COLOR0_FMASK
818 0x00000000, // CB_COLOR0_FMASK_SLICE
819 0x00000000, // CB_COLOR0_CLEAR_WORD0
820 0x00000000, // CB_COLOR0_CLEAR_WORD1
821 0, // HOLE
822 0, // HOLE
823 0x00000000, // CB_COLOR1_BASE
824 0x00000000, // CB_COLOR1_PITCH
825 0x00000000, // CB_COLOR1_SLICE
826 0x00000000, // CB_COLOR1_VIEW
827 0x00000000, // CB_COLOR1_INFO
828 0x00000000, // CB_COLOR1_ATTRIB
829 0, // HOLE
830 0x00000000, // CB_COLOR1_CMASK
831 0x00000000, // CB_COLOR1_CMASK_SLICE
832 0x00000000, // CB_COLOR1_FMASK
833 0x00000000, // CB_COLOR1_FMASK_SLICE
834 0x00000000, // CB_COLOR1_CLEAR_WORD0
835 0x00000000, // CB_COLOR1_CLEAR_WORD1
836 0, // HOLE
837 0, // HOLE
838 0x00000000, // CB_COLOR2_BASE
839 0x00000000, // CB_COLOR2_PITCH
840 0x00000000, // CB_COLOR2_SLICE
841 0x00000000, // CB_COLOR2_VIEW
842 0x00000000, // CB_COLOR2_INFO
843 0x00000000, // CB_COLOR2_ATTRIB
844 0, // HOLE
845 0x00000000, // CB_COLOR2_CMASK
846 0x00000000, // CB_COLOR2_CMASK_SLICE
847 0x00000000, // CB_COLOR2_FMASK
848 0x00000000, // CB_COLOR2_FMASK_SLICE
849 0x00000000, // CB_COLOR2_CLEAR_WORD0
850 0x00000000, // CB_COLOR2_CLEAR_WORD1
851 0, // HOLE
852 0, // HOLE
853 0x00000000, // CB_COLOR3_BASE
854 0x00000000, // CB_COLOR3_PITCH
855 0x00000000, // CB_COLOR3_SLICE
856 0x00000000, // CB_COLOR3_VIEW
857 0x00000000, // CB_COLOR3_INFO
858 0x00000000, // CB_COLOR3_ATTRIB
859 0, // HOLE
860 0x00000000, // CB_COLOR3_CMASK
861 0x00000000, // CB_COLOR3_CMASK_SLICE
862 0x00000000, // CB_COLOR3_FMASK
863 0x00000000, // CB_COLOR3_FMASK_SLICE
864 0x00000000, // CB_COLOR3_CLEAR_WORD0
865 0x00000000, // CB_COLOR3_CLEAR_WORD1
866 0, // HOLE
867 0, // HOLE
868 0x00000000, // CB_COLOR4_BASE
869 0x00000000, // CB_COLOR4_PITCH
870 0x00000000, // CB_COLOR4_SLICE
871 0x00000000, // CB_COLOR4_VIEW
872 0x00000000, // CB_COLOR4_INFO
873 0x00000000, // CB_COLOR4_ATTRIB
874 0, // HOLE
875 0x00000000, // CB_COLOR4_CMASK
876 0x00000000, // CB_COLOR4_CMASK_SLICE
877 0x00000000, // CB_COLOR4_FMASK
878 0x00000000, // CB_COLOR4_FMASK_SLICE
879 0x00000000, // CB_COLOR4_CLEAR_WORD0
880 0x00000000, // CB_COLOR4_CLEAR_WORD1
881 0, // HOLE
882 0, // HOLE
883 0x00000000, // CB_COLOR5_BASE
884 0x00000000, // CB_COLOR5_PITCH
885 0x00000000, // CB_COLOR5_SLICE
886 0x00000000, // CB_COLOR5_VIEW
887 0x00000000, // CB_COLOR5_INFO
888 0x00000000, // CB_COLOR5_ATTRIB
889 0, // HOLE
890 0x00000000, // CB_COLOR5_CMASK
891 0x00000000, // CB_COLOR5_CMASK_SLICE
892 0x00000000, // CB_COLOR5_FMASK
893 0x00000000, // CB_COLOR5_FMASK_SLICE
894 0x00000000, // CB_COLOR5_CLEAR_WORD0
895 0x00000000, // CB_COLOR5_CLEAR_WORD1
896 0, // HOLE
897 0, // HOLE
898 0x00000000, // CB_COLOR6_BASE
899 0x00000000, // CB_COLOR6_PITCH
900 0x00000000, // CB_COLOR6_SLICE
901 0x00000000, // CB_COLOR6_VIEW
902 0x00000000, // CB_COLOR6_INFO
903 0x00000000, // CB_COLOR6_ATTRIB
904 0, // HOLE
905 0x00000000, // CB_COLOR6_CMASK
906 0x00000000, // CB_COLOR6_CMASK_SLICE
907 0x00000000, // CB_COLOR6_FMASK
908 0x00000000, // CB_COLOR6_FMASK_SLICE
909 0x00000000, // CB_COLOR6_CLEAR_WORD0
910 0x00000000, // CB_COLOR6_CLEAR_WORD1
911 0, // HOLE
912 0, // HOLE
913 0x00000000, // CB_COLOR7_BASE
914 0x00000000, // CB_COLOR7_PITCH
915 0x00000000, // CB_COLOR7_SLICE
916 0x00000000, // CB_COLOR7_VIEW
917 0x00000000, // CB_COLOR7_INFO
918 0x00000000, // CB_COLOR7_ATTRIB
919 0, // HOLE
920 0x00000000, // CB_COLOR7_CMASK
921 0x00000000, // CB_COLOR7_CMASK_SLICE
922 0x00000000, // CB_COLOR7_FMASK
923 0x00000000, // CB_COLOR7_FMASK_SLICE
924 0x00000000, // CB_COLOR7_CLEAR_WORD0
925 0x00000000, // CB_COLOR7_CLEAR_WORD1
926};
927static const struct cs_extent_def si_SECT_CONTEXT_defs[] =
928{
929 {si_SECT_CONTEXT_def_1, 0x0000a000, 212 },
930 {si_SECT_CONTEXT_def_2, 0x0000a0d8, 272 },
931 {si_SECT_CONTEXT_def_3, 0x0000a1f5, 6 },
932 {si_SECT_CONTEXT_def_4, 0x0000a200, 157 },
933 {si_SECT_CONTEXT_def_5, 0x0000a2a1, 1 },
934 {si_SECT_CONTEXT_def_6, 0x0000a2a3, 1 },
935 {si_SECT_CONTEXT_def_7, 0x0000a2a5, 233 },
936 { NULL, 0, 0 }
937};
938static const struct cs_section_def si_cs_data[] = {
939 { si_SECT_CONTEXT_defs, SECT_CONTEXT },
940 { NULL, SECT_NONE }
941};
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h b/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
new file mode 100644
index 000000000000..895c8e2353e3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef __SI_REG_H__
25#define __SI_REG_H__
26
27/* SI */
28#define SI_DC_GPIO_HPD_MASK 0x196c
29#define SI_DC_GPIO_HPD_A 0x196d
30#define SI_DC_GPIO_HPD_EN 0x196e
31#define SI_DC_GPIO_HPD_Y 0x196f
32
33#define SI_GRPH_CONTROL 0x1a01
34# define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
35# define SI_GRPH_DEPTH_8BPP 0
36# define SI_GRPH_DEPTH_16BPP 1
37# define SI_GRPH_DEPTH_32BPP 2
38# define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
39# define SI_ADDR_SURF_2_BANK 0
40# define SI_ADDR_SURF_4_BANK 1
41# define SI_ADDR_SURF_8_BANK 2
42# define SI_ADDR_SURF_16_BANK 3
43# define SI_GRPH_Z(x) (((x) & 0x3) << 4)
44# define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
45# define SI_ADDR_SURF_BANK_WIDTH_1 0
46# define SI_ADDR_SURF_BANK_WIDTH_2 1
47# define SI_ADDR_SURF_BANK_WIDTH_4 2
48# define SI_ADDR_SURF_BANK_WIDTH_8 3
49# define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
50/* 8 BPP */
51# define SI_GRPH_FORMAT_INDEXED 0
52/* 16 BPP */
53# define SI_GRPH_FORMAT_ARGB1555 0
54# define SI_GRPH_FORMAT_ARGB565 1
55# define SI_GRPH_FORMAT_ARGB4444 2
56# define SI_GRPH_FORMAT_AI88 3
57# define SI_GRPH_FORMAT_MONO16 4
58# define SI_GRPH_FORMAT_BGRA5551 5
59/* 32 BPP */
60# define SI_GRPH_FORMAT_ARGB8888 0
61# define SI_GRPH_FORMAT_ARGB2101010 1
62# define SI_GRPH_FORMAT_32BPP_DIG 2
63# define SI_GRPH_FORMAT_8B_ARGB2101010 3
64# define SI_GRPH_FORMAT_BGRA1010102 4
65# define SI_GRPH_FORMAT_8B_BGRA1010102 5
66# define SI_GRPH_FORMAT_RGB111110 6
67# define SI_GRPH_FORMAT_BGR101111 7
68# define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
69# define SI_ADDR_SURF_BANK_HEIGHT_1 0
70# define SI_ADDR_SURF_BANK_HEIGHT_2 1
71# define SI_ADDR_SURF_BANK_HEIGHT_4 2
72# define SI_ADDR_SURF_BANK_HEIGHT_8 3
73# define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
74# define SI_ADDR_SURF_TILE_SPLIT_64B 0
75# define SI_ADDR_SURF_TILE_SPLIT_128B 1
76# define SI_ADDR_SURF_TILE_SPLIT_256B 2
77# define SI_ADDR_SURF_TILE_SPLIT_512B 3
78# define SI_ADDR_SURF_TILE_SPLIT_1KB 4
79# define SI_ADDR_SURF_TILE_SPLIT_2KB 5
80# define SI_ADDR_SURF_TILE_SPLIT_4KB 6
81# define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
82# define SI_ADDR_SURF_MACRO_TILE_ASPECT_1 0
83# define SI_ADDR_SURF_MACRO_TILE_ASPECT_2 1
84# define SI_ADDR_SURF_MACRO_TILE_ASPECT_4 2
85# define SI_ADDR_SURF_MACRO_TILE_ASPECT_8 3
86# define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
87# define SI_GRPH_ARRAY_LINEAR_GENERAL 0
88# define SI_GRPH_ARRAY_LINEAR_ALIGNED 1
89# define SI_GRPH_ARRAY_1D_TILED_THIN1 2
90# define SI_GRPH_ARRAY_2D_TILED_THIN1 4
91# define SI_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
92# define SI_ADDR_SURF_P2 0
93# define SI_ADDR_SURF_P4_8x16 4
94# define SI_ADDR_SURF_P4_16x16 5
95# define SI_ADDR_SURF_P4_16x32 6
96# define SI_ADDR_SURF_P4_32x32 7
97# define SI_ADDR_SURF_P8_16x16_8x16 8
98# define SI_ADDR_SURF_P8_16x32_8x16 9
99# define SI_ADDR_SURF_P8_32x32_8x16 10
100# define SI_ADDR_SURF_P8_16x32_16x16 11
101# define SI_ADDR_SURF_P8_32x32_16x16 12
102# define SI_ADDR_SURF_P8_32x32_16x32 13
103# define SI_ADDR_SURF_P8_32x64_32x32 14
104
105#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
new file mode 100644
index 000000000000..15358cde2bdf
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -0,0 +1,2408 @@
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef SI_H
25#define SI_H
26
27#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
28
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
32
33#define SI_MAX_SH_GPRS 256
34#define SI_MAX_TEMP_GPRS 16
35#define SI_MAX_SH_THREADS 256
36#define SI_MAX_SH_STACK_ENTRIES 4096
37#define SI_MAX_FRC_EOV_CNT 16384
38#define SI_MAX_BACKENDS 8
39#define SI_MAX_BACKENDS_MASK 0xFF
40#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
41#define SI_MAX_SIMDS 12
42#define SI_MAX_SIMDS_MASK 0x0FFF
43#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
44#define SI_MAX_PIPES 8
45#define SI_MAX_PIPES_MASK 0xFF
46#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47#define SI_MAX_LDS_NUM 0xFFFF
48#define SI_MAX_TCC 16
49#define SI_MAX_TCC_MASK 0xFFFF
50
51#define AMDGPU_NUM_OF_VMIDS 8
52
53/* SMC IND accessor regs */
54#define SMC_IND_INDEX_0 0x80
55#define SMC_IND_DATA_0 0x81
56
57#define SMC_IND_ACCESS_CNTL 0x8A
58# define AUTO_INCREMENT_IND_0 (1 << 0)
59#define SMC_MESSAGE_0 0x8B
60#define SMC_RESP_0 0x8C
61
62/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
63#define SMC_CG_IND_START 0xc0030000
64#define SMC_CG_IND_END 0xc0040000
65
66#define CG_CGTT_LOCAL_0 0x400
67#define CG_CGTT_LOCAL_1 0x401
68
69/* SMC IND registers */
70#define SMC_SYSCON_RESET_CNTL 0x80000000
71# define RST_REG (1 << 0)
72#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
73# define CK_DISABLE (1 << 0)
74# define CKEN (1 << 24)
75
76#define VGA_HDP_CONTROL 0xCA
77#define VGA_MEMORY_DISABLE (1 << 4)
78
79#define DCCG_DISP_SLOW_SELECT_REG 0x13F
80#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
81#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
82#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
83#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
84#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
85#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
86
87#define CG_SPLL_FUNC_CNTL 0x180
88#define SPLL_RESET (1 << 0)
89#define SPLL_SLEEP (1 << 1)
90#define SPLL_BYPASS_EN (1 << 3)
91#define SPLL_REF_DIV(x) ((x) << 4)
92#define SPLL_REF_DIV_MASK (0x3f << 4)
93#define SPLL_PDIV_A(x) ((x) << 20)
94#define SPLL_PDIV_A_MASK (0x7f << 20)
95#define SPLL_PDIV_A_SHIFT 20
96#define CG_SPLL_FUNC_CNTL_2 0x181
97#define SCLK_MUX_SEL(x) ((x) << 0)
98#define SCLK_MUX_SEL_MASK (0x1ff << 0)
99#define SPLL_CTLREQ_CHG (1 << 23)
100#define SCLK_MUX_UPDATE (1 << 26)
101#define CG_SPLL_FUNC_CNTL_3 0x182
102#define SPLL_FB_DIV(x) ((x) << 0)
103#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
104#define SPLL_FB_DIV_SHIFT 0
105#define SPLL_DITHEN (1 << 28)
106#define CG_SPLL_FUNC_CNTL_4 0x183
107
108#define SPLL_STATUS 0x185
109#define SPLL_CHG_STATUS (1 << 1)
110#define SPLL_CNTL_MODE 0x186
111#define SPLL_SW_DIR_CONTROL (1 << 0)
112# define SPLL_REFCLK_SEL(x) ((x) << 26)
113# define SPLL_REFCLK_SEL_MASK (3 << 26)
114
115#define CG_SPLL_SPREAD_SPECTRUM 0x188
116#define SSEN (1 << 0)
117#define CLK_S(x) ((x) << 4)
118#define CLK_S_MASK (0xfff << 4)
119#define CLK_S_SHIFT 4
120#define CG_SPLL_SPREAD_SPECTRUM_2 0x189
121#define CLK_V(x) ((x) << 0)
122#define CLK_V_MASK (0x3ffffff << 0)
123#define CLK_V_SHIFT 0
124
125#define CG_SPLL_AUTOSCALE_CNTL 0x18b
126# define AUTOSCALE_ON_SS_CLEAR (1 << 9)
127
128/* discrete uvd clocks */
129#define CG_UPLL_FUNC_CNTL 0x18d
130# define UPLL_RESET_MASK 0x00000001
131# define UPLL_SLEEP_MASK 0x00000002
132# define UPLL_BYPASS_EN_MASK 0x00000004
133# define UPLL_CTLREQ_MASK 0x00000008
134# define UPLL_VCO_MODE_MASK 0x00000600
135# define UPLL_REF_DIV_MASK 0x003F0000
136# define UPLL_CTLACK_MASK 0x40000000
137# define UPLL_CTLACK2_MASK 0x80000000
138#define CG_UPLL_FUNC_CNTL_2 0x18e
139# define UPLL_PDIV_A(x) ((x) << 0)
140# define UPLL_PDIV_A_MASK 0x0000007F
141# define UPLL_PDIV_B(x) ((x) << 8)
142# define UPLL_PDIV_B_MASK 0x00007F00
143# define VCLK_SRC_SEL(x) ((x) << 20)
144# define VCLK_SRC_SEL_MASK 0x01F00000
145# define DCLK_SRC_SEL(x) ((x) << 25)
146# define DCLK_SRC_SEL_MASK 0x3E000000
147#define CG_UPLL_FUNC_CNTL_3 0x18f
148# define UPLL_FB_DIV(x) ((x) << 0)
149# define UPLL_FB_DIV_MASK 0x01FFFFFF
150#define CG_UPLL_FUNC_CNTL_4 0x191
151# define UPLL_SPARE_ISPARE9 0x00020000
152#define CG_UPLL_FUNC_CNTL_5 0x192
153# define RESET_ANTI_MUX_MASK 0x00000200
154#define CG_UPLL_SPREAD_SPECTRUM 0x194
155# define SSEN_MASK 0x00000001
156
157#define MPLL_BYPASSCLK_SEL 0x197
158# define MPLL_CLKOUT_SEL(x) ((x) << 8)
159# define MPLL_CLKOUT_SEL_MASK 0xFF00
160
161#define CG_CLKPIN_CNTL 0x198
162# define XTALIN_DIVIDE (1 << 1)
163# define BCLK_AS_XCLK (1 << 2)
164#define CG_CLKPIN_CNTL_2 0x199
165# define FORCE_BIF_REFCLK_EN (1 << 3)
166# define MUX_TCLK_TO_XCLK (1 << 8)
167
168#define THM_CLK_CNTL 0x19b
169# define CMON_CLK_SEL(x) ((x) << 0)
170# define CMON_CLK_SEL_MASK 0xFF
171# define TMON_CLK_SEL(x) ((x) << 8)
172# define TMON_CLK_SEL_MASK 0xFF00
173#define MISC_CLK_CNTL 0x19c
174# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
175# define DEEP_SLEEP_CLK_SEL_MASK 0xFF
176# define ZCLK_SEL(x) ((x) << 8)
177# define ZCLK_SEL_MASK 0xFF00
178
179#define CG_THERMAL_CTRL 0x1c0
180#define DPM_EVENT_SRC(x) ((x) << 0)
181#define DPM_EVENT_SRC_MASK (7 << 0)
182#define DIG_THERM_DPM(x) ((x) << 14)
183#define DIG_THERM_DPM_MASK 0x003FC000
184#define DIG_THERM_DPM_SHIFT 14
185#define CG_THERMAL_STATUS 0x1c1
186#define FDO_PWM_DUTY(x) ((x) << 9)
187#define FDO_PWM_DUTY_MASK (0xff << 9)
188#define FDO_PWM_DUTY_SHIFT 9
189#define CG_THERMAL_INT 0x1c2
190#define DIG_THERM_INTH(x) ((x) << 8)
191#define DIG_THERM_INTH_MASK 0x0000FF00
192#define DIG_THERM_INTH_SHIFT 8
193#define DIG_THERM_INTL(x) ((x) << 16)
194#define DIG_THERM_INTL_MASK 0x00FF0000
195#define DIG_THERM_INTL_SHIFT 16
196#define THERM_INT_MASK_HIGH (1 << 24)
197#define THERM_INT_MASK_LOW (1 << 25)
198
199#define CG_MULT_THERMAL_CTRL 0x1c4
200#define TEMP_SEL(x) ((x) << 20)
201#define TEMP_SEL_MASK (0xff << 20)
202#define TEMP_SEL_SHIFT 20
203#define CG_MULT_THERMAL_STATUS 0x1c5
204#define ASIC_MAX_TEMP(x) ((x) << 0)
205#define ASIC_MAX_TEMP_MASK 0x000001ff
206#define ASIC_MAX_TEMP_SHIFT 0
207#define CTF_TEMP(x) ((x) << 9)
208#define CTF_TEMP_MASK 0x0003fe00
209#define CTF_TEMP_SHIFT 9
210
211#define CG_FDO_CTRL0 0x1d5
212#define FDO_STATIC_DUTY(x) ((x) << 0)
213#define FDO_STATIC_DUTY_MASK 0x000000FF
214#define FDO_STATIC_DUTY_SHIFT 0
215#define CG_FDO_CTRL1 0x1d6
216#define FMAX_DUTY100(x) ((x) << 0)
217#define FMAX_DUTY100_MASK 0x000000FF
218#define FMAX_DUTY100_SHIFT 0
219#define CG_FDO_CTRL2 0x1d7
220#define TMIN(x) ((x) << 0)
221#define TMIN_MASK 0x000000FF
222#define TMIN_SHIFT 0
223#define FDO_PWM_MODE(x) ((x) << 11)
224#define FDO_PWM_MODE_MASK (7 << 11)
225#define FDO_PWM_MODE_SHIFT 11
226#define TACH_PWM_RESP_RATE(x) ((x) << 25)
227#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
228#define TACH_PWM_RESP_RATE_SHIFT 25
229
230#define CG_TACH_CTRL 0x1dc
231# define EDGE_PER_REV(x) ((x) << 0)
232# define EDGE_PER_REV_MASK (0x7 << 0)
233# define EDGE_PER_REV_SHIFT 0
234# define TARGET_PERIOD(x) ((x) << 3)
235# define TARGET_PERIOD_MASK 0xfffffff8
236# define TARGET_PERIOD_SHIFT 3
237#define CG_TACH_STATUS 0x1dd
238# define TACH_PERIOD(x) ((x) << 0)
239# define TACH_PERIOD_MASK 0xffffffff
240# define TACH_PERIOD_SHIFT 0
241
242#define GENERAL_PWRMGT 0x1e0
243# define GLOBAL_PWRMGT_EN (1 << 0)
244# define STATIC_PM_EN (1 << 1)
245# define THERMAL_PROTECTION_DIS (1 << 2)
246# define THERMAL_PROTECTION_TYPE (1 << 3)
247# define SW_SMIO_INDEX(x) ((x) << 6)
248# define SW_SMIO_INDEX_MASK (1 << 6)
249# define SW_SMIO_INDEX_SHIFT 6
250# define VOLT_PWRMGT_EN (1 << 10)
251# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
252#define CG_TPC 0x1e1
253#define SCLK_PWRMGT_CNTL 0x1e2
254# define SCLK_PWRMGT_OFF (1 << 0)
255# define SCLK_LOW_D1 (1 << 1)
256# define FIR_RESET (1 << 4)
257# define FIR_FORCE_TREND_SEL (1 << 5)
258# define FIR_TREND_MODE (1 << 6)
259# define DYN_GFX_CLK_OFF_EN (1 << 7)
260# define GFX_CLK_FORCE_ON (1 << 8)
261# define GFX_CLK_REQUEST_OFF (1 << 9)
262# define GFX_CLK_FORCE_OFF (1 << 10)
263# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
264# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
265# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
266# define DYN_LIGHT_SLEEP_EN (1 << 14)
267
268#define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6
269# define CURRENT_STATE_INDEX_MASK (0xf << 4)
270# define CURRENT_STATE_INDEX_SHIFT 4
271
272#define CG_FTV 0x1ef
273
274#define CG_FFCT_0 0x1f0
275# define UTC_0(x) ((x) << 0)
276# define UTC_0_MASK (0x3ff << 0)
277# define DTC_0(x) ((x) << 10)
278# define DTC_0_MASK (0x3ff << 10)
279
280#define CG_BSP 0x1ff
281# define BSP(x) ((x) << 0)
282# define BSP_MASK (0xffff << 0)
283# define BSU(x) ((x) << 16)
284# define BSU_MASK (0xf << 16)
285#define CG_AT 0x200
286# define CG_R(x) ((x) << 0)
287# define CG_R_MASK (0xffff << 0)
288# define CG_L(x) ((x) << 16)
289# define CG_L_MASK (0xffff << 16)
290
291#define CG_GIT 0x201
292# define CG_GICST(x) ((x) << 0)
293# define CG_GICST_MASK (0xffff << 0)
294# define CG_GIPOT(x) ((x) << 16)
295# define CG_GIPOT_MASK (0xffff << 16)
296
297#define CG_SSP 0x203
298# define SST(x) ((x) << 0)
299# define SST_MASK (0xffff << 0)
300# define SSTU(x) ((x) << 16)
301# define SSTU_MASK (0xf << 16)
302
303#define CG_DISPLAY_GAP_CNTL 0x20a
304# define DISP1_GAP(x) ((x) << 0)
305# define DISP1_GAP_MASK (3 << 0)
306# define DISP2_GAP(x) ((x) << 2)
307# define DISP2_GAP_MASK (3 << 2)
308# define VBI_TIMER_COUNT(x) ((x) << 4)
309# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
310# define VBI_TIMER_UNIT(x) ((x) << 20)
311# define VBI_TIMER_UNIT_MASK (7 << 20)
312# define DISP1_GAP_MCHG(x) ((x) << 24)
313# define DISP1_GAP_MCHG_MASK (3 << 24)
314# define DISP2_GAP_MCHG(x) ((x) << 26)
315# define DISP2_GAP_MCHG_MASK (3 << 26)
316
317#define CG_ULV_CONTROL 0x21e
318#define CG_ULV_PARAMETER 0x21f
319
320#define SMC_SCRATCH0 0x221
321
322#define CG_CAC_CTRL 0x22e
323# define CAC_WINDOW(x) ((x) << 0)
324# define CAC_WINDOW_MASK 0x00ffffff
325
326#define DMIF_ADDR_CONFIG 0x2F5
327
328#define DMIF_ADDR_CALC 0x300
329
330#define PIPE0_DMIF_BUFFER_CONTROL 0x0328
331# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
332# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
333
334#define SRBM_STATUS 0x394
335#define GRBM_RQ_PENDING (1 << 5)
336#define VMC_BUSY (1 << 8)
337#define MCB_BUSY (1 << 9)
338#define MCB_NON_DISPLAY_BUSY (1 << 10)
339#define MCC_BUSY (1 << 11)
340#define MCD_BUSY (1 << 12)
341#define SEM_BUSY (1 << 14)
342#define IH_BUSY (1 << 17)
343
344#define SRBM_SOFT_RESET 0x398
345#define SOFT_RESET_BIF (1 << 1)
346#define SOFT_RESET_DC (1 << 5)
347#define SOFT_RESET_DMA1 (1 << 6)
348#define SOFT_RESET_GRBM (1 << 8)
349#define SOFT_RESET_HDP (1 << 9)
350#define SOFT_RESET_IH (1 << 10)
351#define SOFT_RESET_MC (1 << 11)
352#define SOFT_RESET_ROM (1 << 14)
353#define SOFT_RESET_SEM (1 << 15)
354#define SOFT_RESET_VMC (1 << 17)
355#define SOFT_RESET_DMA (1 << 20)
356#define SOFT_RESET_TST (1 << 21)
357#define SOFT_RESET_REGBB (1 << 22)
358#define SOFT_RESET_ORB (1 << 23)
359
360#define CC_SYS_RB_BACKEND_DISABLE 0x3A0
361#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1
362
363#define SRBM_READ_ERROR 0x3A6
364#define SRBM_INT_CNTL 0x3A8
365#define SRBM_INT_ACK 0x3AA
366
367#define SRBM_STATUS2 0x3B1
368#define DMA_BUSY (1 << 5)
369#define DMA1_BUSY (1 << 6)
370
371#define VM_L2_CNTL 0x500
372#define ENABLE_L2_CACHE (1 << 0)
373#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
374#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
375#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
376#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
377#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
378#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
379#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
380#define VM_L2_CNTL2 0x501
381#define INVALIDATE_ALL_L1_TLBS (1 << 0)
382#define INVALIDATE_L2_CACHE (1 << 1)
383#define INVALIDATE_CACHE_MODE(x) ((x) << 26)
384#define INVALIDATE_PTE_AND_PDE_CACHES 0
385#define INVALIDATE_ONLY_PTE_CACHES 1
386#define INVALIDATE_ONLY_PDE_CACHES 2
387#define VM_L2_CNTL3 0x502
388#define BANK_SELECT(x) ((x) << 0)
389#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
390#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
391#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
392#define VM_L2_STATUS 0x503
393#define L2_BUSY (1 << 0)
394#define VM_CONTEXT0_CNTL 0x504
395#define ENABLE_CONTEXT (1 << 0)
396#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
397#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
398#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
399#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
400#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
401#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
402#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
403#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
404#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
405#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
406#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
407#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
408#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
409#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
410#define VM_CONTEXT1_CNTL 0x505
411#define VM_CONTEXT0_CNTL2 0x50C
412#define VM_CONTEXT1_CNTL2 0x50D
413#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E
414#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F
415#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
416#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
417#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
418#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
419#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
420#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
421
422#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
423#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
424#define PROTECTIONS_MASK (0xf << 0)
425#define PROTECTIONS_SHIFT 0
426 /* bit 0: range
427 * bit 1: pde0
428 * bit 2: valid
429 * bit 3: read
430 * bit 4: write
431 */
432#define MEMORY_CLIENT_ID_MASK (0xff << 12)
433#define MEMORY_CLIENT_ID_SHIFT 12
434#define MEMORY_CLIENT_RW_MASK (1 << 24)
435#define MEMORY_CLIENT_RW_SHIFT 24
436#define FAULT_VMID_MASK (0xf << 25)
437#define FAULT_VMID_SHIFT 25
438
439#define VM_INVALIDATE_REQUEST 0x51E
440#define VM_INVALIDATE_RESPONSE 0x51F
441
442#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
443#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
444
445#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F
446#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
447#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
448#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
449#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
450#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
451#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
452#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
453#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
454#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
455
456#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F
457#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
458
459#define VM_L2_CG 0x570
460#define MC_CG_ENABLE (1 << 18)
461#define MC_LS_ENABLE (1 << 19)
462
463#define MC_SHARED_CHMAP 0x801
464#define NOOFCHAN_SHIFT 12
465#define NOOFCHAN_MASK 0x0000f000
466#define MC_SHARED_CHREMAP 0x802
467
468#define MC_VM_FB_LOCATION 0x809
469#define MC_VM_AGP_TOP 0x80A
470#define MC_VM_AGP_BOT 0x80B
471#define MC_VM_AGP_BASE 0x80C
472#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D
473#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E
474#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F
475
476#define MC_VM_MX_L1_TLB_CNTL 0x819
477#define ENABLE_L1_TLB (1 << 0)
478#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
479#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
480#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
481#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
482#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
483#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
484#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
485
486#define MC_SHARED_BLACKOUT_CNTL 0x82B
487
488#define MC_HUB_MISC_HUB_CG 0x82E
489#define MC_HUB_MISC_VM_CG 0x82F
490
491#define MC_HUB_MISC_SIP_CG 0x830
492
493#define MC_XPB_CLK_GAT 0x91E
494
495#define MC_CITF_MISC_RD_CG 0x992
496#define MC_CITF_MISC_WR_CG 0x993
497#define MC_CITF_MISC_VM_CG 0x994
498
499#define MC_ARB_RAMCFG 0x9D8
500#define NOOFBANK_SHIFT 0
501#define NOOFBANK_MASK 0x00000003
502#define NOOFRANK_SHIFT 2
503#define NOOFRANK_MASK 0x00000004
504#define NOOFROWS_SHIFT 3
505#define NOOFROWS_MASK 0x00000038
506#define NOOFCOLS_SHIFT 6
507#define NOOFCOLS_MASK 0x000000C0
508#define CHANSIZE_SHIFT 8
509#define CHANSIZE_MASK 0x00000100
510#define CHANSIZE_OVERRIDE (1 << 11)
511#define NOOFGROUPS_SHIFT 12
512#define NOOFGROUPS_MASK 0x00001000
513
514#define MC_ARB_DRAM_TIMING 0x9DD
515#define MC_ARB_DRAM_TIMING2 0x9DE
516
517#define MC_ARB_BURST_TIME 0xA02
518#define STATE0(x) ((x) << 0)
519#define STATE0_MASK (0x1f << 0)
520#define STATE0_SHIFT 0
521#define STATE1(x) ((x) << 5)
522#define STATE1_MASK (0x1f << 5)
523#define STATE1_SHIFT 5
524#define STATE2(x) ((x) << 10)
525#define STATE2_MASK (0x1f << 10)
526#define STATE2_SHIFT 10
527#define STATE3(x) ((x) << 15)
528#define STATE3_MASK (0x1f << 15)
529#define STATE3_SHIFT 15
530
531#define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A
532#define TRAIN_DONE_D0 (1 << 30)
533#define TRAIN_DONE_D1 (1 << 31)
534
535#define MC_SEQ_SUP_CNTL 0xA32
536#define RUN_MASK (1 << 0)
537#define MC_SEQ_SUP_PGM 0xA33
538#define MC_PMG_AUTO_CMD 0xA34
539
540#define MC_IO_PAD_CNTL_D0 0xA74
541#define MEM_FALL_OUT_CMD (1 << 8)
542
543#define MC_SEQ_RAS_TIMING 0xA28
544#define MC_SEQ_CAS_TIMING 0xA29
545#define MC_SEQ_MISC_TIMING 0xA2A
546#define MC_SEQ_MISC_TIMING2 0xA2B
547#define MC_SEQ_PMG_TIMING 0xA2C
548#define MC_SEQ_RD_CTL_D0 0xA2D
549#define MC_SEQ_RD_CTL_D1 0xA2E
550#define MC_SEQ_WR_CTL_D0 0xA2F
551#define MC_SEQ_WR_CTL_D1 0xA30
552
553#define MC_SEQ_MISC0 0xA80
554#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
555#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
556#define MC_SEQ_MISC0_VEN_ID_VALUE 3
557#define MC_SEQ_MISC0_REV_ID_SHIFT 12
558#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
559#define MC_SEQ_MISC0_REV_ID_VALUE 1
560#define MC_SEQ_MISC0_GDDR5_SHIFT 28
561#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
562#define MC_SEQ_MISC0_GDDR5_VALUE 5
563#define MC_SEQ_MISC1 0xA81
564#define MC_SEQ_RESERVE_M 0xA82
565#define MC_PMG_CMD_EMRS 0xA83
566
567#define MC_SEQ_IO_DEBUG_INDEX 0xA91
568#define MC_SEQ_IO_DEBUG_DATA 0xA92
569
570#define MC_SEQ_MISC5 0xA95
571#define MC_SEQ_MISC6 0xA96
572
573#define MC_SEQ_MISC7 0xA99
574
575#define MC_SEQ_RAS_TIMING_LP 0xA9B
576#define MC_SEQ_CAS_TIMING_LP 0xA9C
577#define MC_SEQ_MISC_TIMING_LP 0xA9D
578#define MC_SEQ_MISC_TIMING2_LP 0xA9E
579#define MC_SEQ_WR_CTL_D0_LP 0xA9F
580#define MC_SEQ_WR_CTL_D1_LP 0xAA0
581#define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1
582#define MC_SEQ_PMG_CMD_MRS_LP 0xAA2
583
584#define MC_PMG_CMD_MRS 0xAAB
585
586#define MC_SEQ_RD_CTL_D0_LP 0xAC7
587#define MC_SEQ_RD_CTL_D1_LP 0xAC8
588
589#define MC_PMG_CMD_MRS1 0xAD1
590#define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2
591#define MC_SEQ_PMG_TIMING_LP 0xAD3
592
593#define MC_SEQ_WR_CTL_2 0xAD5
594#define MC_SEQ_WR_CTL_2_LP 0xAD6
595#define MC_PMG_CMD_MRS2 0xAD7
596#define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8
597
598#define MCLK_PWRMGT_CNTL 0xAE8
599# define DLL_SPEED(x) ((x) << 0)
600# define DLL_SPEED_MASK (0x1f << 0)
601# define DLL_READY (1 << 6)
602# define MC_INT_CNTL (1 << 7)
603# define MRDCK0_PDNB (1 << 8)
604# define MRDCK1_PDNB (1 << 9)
605# define MRDCK0_RESET (1 << 16)
606# define MRDCK1_RESET (1 << 17)
607# define DLL_READY_READ (1 << 24)
608#define DLL_CNTL 0xAE9
609# define MRDCK0_BYPASS (1 << 24)
610# define MRDCK1_BYPASS (1 << 25)
611
612#define MPLL_CNTL_MODE 0xAEC
613# define MPLL_MCLK_SEL (1 << 11)
614#define MPLL_FUNC_CNTL 0xAED
615#define BWCTRL(x) ((x) << 20)
616#define BWCTRL_MASK (0xff << 20)
617#define MPLL_FUNC_CNTL_1 0xAEE
618#define VCO_MODE(x) ((x) << 0)
619#define VCO_MODE_MASK (3 << 0)
620#define CLKFRAC(x) ((x) << 4)
621#define CLKFRAC_MASK (0xfff << 4)
622#define CLKF(x) ((x) << 16)
623#define CLKF_MASK (0xfff << 16)
624#define MPLL_FUNC_CNTL_2 0xAEF
625#define MPLL_AD_FUNC_CNTL 0xAF0
626#define YCLK_POST_DIV(x) ((x) << 0)
627#define YCLK_POST_DIV_MASK (7 << 0)
628#define MPLL_DQ_FUNC_CNTL 0xAF1
629#define YCLK_SEL(x) ((x) << 4)
630#define YCLK_SEL_MASK (1 << 4)
631
632#define MPLL_SS1 0xAF3
633#define CLKV(x) ((x) << 0)
634#define CLKV_MASK (0x3ffffff << 0)
635#define MPLL_SS2 0xAF4
636#define CLKS(x) ((x) << 0)
637#define CLKS_MASK (0xfff << 0)
638
639#define HDP_HOST_PATH_CNTL 0xB00
640#define CLOCK_GATING_DIS (1 << 23)
641#define HDP_NONSURFACE_BASE 0xB01
642#define HDP_NONSURFACE_INFO 0xB02
643#define HDP_NONSURFACE_SIZE 0xB03
644
645#define HDP_ADDR_CONFIG 0xBD2
646#define HDP_MISC_CNTL 0xBD3
647#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
648#define HDP_MEM_POWER_LS 0xBD4
649#define HDP_LS_ENABLE (1 << 0)
650
651#define ATC_MISC_CG 0xCD4
652
653#define IH_RB_CNTL 0xF80
654# define IH_RB_ENABLE (1 << 0)
655# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
656# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
657# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
658# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
659# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
660# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
661#define IH_RB_BASE 0xF81
662#define IH_RB_RPTR 0xF82
663#define IH_RB_WPTR 0xF83
664# define RB_OVERFLOW (1 << 0)
665# define WPTR_OFFSET_MASK 0x3fffc
666#define IH_RB_WPTR_ADDR_HI 0xF84
667#define IH_RB_WPTR_ADDR_LO 0xF85
668#define IH_CNTL 0xF86
669# define ENABLE_INTR (1 << 0)
670# define IH_MC_SWAP(x) ((x) << 1)
671# define IH_MC_SWAP_NONE 0
672# define IH_MC_SWAP_16BIT 1
673# define IH_MC_SWAP_32BIT 2
674# define IH_MC_SWAP_64BIT 3
675# define RPTR_REARM (1 << 4)
676# define MC_WRREQ_CREDIT(x) ((x) << 15)
677# define MC_WR_CLEAN_CNT(x) ((x) << 20)
678# define MC_VMID(x) ((x) << 25)
679
680#define CONFIG_MEMSIZE 0x150A
681
682#define INTERRUPT_CNTL 0x151A
683# define IH_DUMMY_RD_OVERRIDE (1 << 0)
684# define IH_DUMMY_RD_EN (1 << 1)
685# define IH_REQ_NONSNOOP_EN (1 << 3)
686# define GEN_IH_INT_EN (1 << 8)
687#define INTERRUPT_CNTL2 0x151B
688
689#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
690
691#define BIF_FB_EN 0x1524
692#define FB_READ_EN (1 << 0)
693#define FB_WRITE_EN (1 << 1)
694
695#define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528
696
697/* DCE6 ELD audio interface */
698#define AZ_F0_CODEC_ENDPOINT_INDEX 0x1780
699# define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
700# define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
701#define AZ_F0_CODEC_ENDPOINT_DATA 0x1781
702
703#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
704#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
705#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
706#define SPEAKER_ALLOCATION_SHIFT 0
707#define HDMI_CONNECTION (1 << 16)
708#define DP_CONNECTION (1 << 17)
709
710#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
711#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
712#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
713#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
714#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
715#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
716#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
717#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
718#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */
719#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
720#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
721#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
722#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
723#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
724# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
725/* max channels minus one. 7 = 8 channels */
726# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
727# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
728# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
729/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
730 * bit0 = 32 kHz
731 * bit1 = 44.1 kHz
732 * bit2 = 48 kHz
733 * bit3 = 88.2 kHz
734 * bit4 = 96 kHz
735 * bit5 = 176.4 kHz
736 * bit6 = 192 kHz
737 */
738
739#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
740# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
741# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
742/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
743 * 0 = invalid
744 * x = legal delay value
745 * 255 = sync not supported
746 */
747#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
748# define HBR_CAPABLE (1 << 0) /* enabled by default */
749
750#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
751# define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
752# define PRODUCT_ID(x) (((x) & 0xffff) << 16)
753#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
754# define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
755#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
756# define PORT_ID0(x) (((x) & 0xffffffff) << 0)
757#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
758# define PORT_ID1(x) (((x) & 0xffffffff) << 0)
759#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
760# define DESCRIPTION0(x) (((x) & 0xff) << 0)
761# define DESCRIPTION1(x) (((x) & 0xff) << 8)
762# define DESCRIPTION2(x) (((x) & 0xff) << 16)
763# define DESCRIPTION3(x) (((x) & 0xff) << 24)
764#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
765# define DESCRIPTION4(x) (((x) & 0xff) << 0)
766# define DESCRIPTION5(x) (((x) & 0xff) << 8)
767# define DESCRIPTION6(x) (((x) & 0xff) << 16)
768# define DESCRIPTION7(x) (((x) & 0xff) << 24)
769#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
770# define DESCRIPTION8(x) (((x) & 0xff) << 0)
771# define DESCRIPTION9(x) (((x) & 0xff) << 8)
772# define DESCRIPTION10(x) (((x) & 0xff) << 16)
773# define DESCRIPTION11(x) (((x) & 0xff) << 24)
774#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
775# define DESCRIPTION12(x) (((x) & 0xff) << 0)
776# define DESCRIPTION13(x) (((x) & 0xff) << 8)
777# define DESCRIPTION14(x) (((x) & 0xff) << 16)
778# define DESCRIPTION15(x) (((x) & 0xff) << 24)
779#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
780# define DESCRIPTION16(x) (((x) & 0xff) << 0)
781# define DESCRIPTION17(x) (((x) & 0xff) << 8)
782
783#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
784# define AUDIO_ENABLED (1 << 31)
785
786#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
787#define PORT_CONNECTIVITY_MASK (3 << 30)
788#define PORT_CONNECTIVITY_SHIFT 30
789
790#define DC_LB_MEMORY_SPLIT 0x1AC3
791#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
792
793#define PRIORITY_A_CNT 0x1AC6
794#define PRIORITY_MARK_MASK 0x7fff
795#define PRIORITY_OFF (1 << 16)
796#define PRIORITY_ALWAYS_ON (1 << 20)
797#define PRIORITY_B_CNT 0x1AC7
798
799#define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32
800# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
801#define DPG_PIPE_LATENCY_CONTROL 0x1B33
802# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
803# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
804
805/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
806#define VLINE_STATUS 0x1AEE
807# define VLINE_OCCURRED (1 << 0)
808# define VLINE_ACK (1 << 4)
809# define VLINE_STAT (1 << 12)
810# define VLINE_INTERRUPT (1 << 16)
811# define VLINE_INTERRUPT_TYPE (1 << 17)
812/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
813#define VBLANK_STATUS 0x1AEF
814# define VBLANK_OCCURRED (1 << 0)
815# define VBLANK_ACK (1 << 4)
816# define VBLANK_STAT (1 << 12)
817# define VBLANK_INTERRUPT (1 << 16)
818# define VBLANK_INTERRUPT_TYPE (1 << 17)
819
820/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
821#define INT_MASK 0x1AD0
822# define VBLANK_INT_MASK (1 << 0)
823# define VLINE_INT_MASK (1 << 4)
824
825#define DISP_INTERRUPT_STATUS 0x183D
826# define LB_D1_VLINE_INTERRUPT (1 << 2)
827# define LB_D1_VBLANK_INTERRUPT (1 << 3)
828# define DC_HPD1_INTERRUPT (1 << 17)
829# define DC_HPD1_RX_INTERRUPT (1 << 18)
830# define DACA_AUTODETECT_INTERRUPT (1 << 22)
831# define DACB_AUTODETECT_INTERRUPT (1 << 23)
832# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
833# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
834#define DISP_INTERRUPT_STATUS_CONTINUE 0x183E
835# define LB_D2_VLINE_INTERRUPT (1 << 2)
836# define LB_D2_VBLANK_INTERRUPT (1 << 3)
837# define DC_HPD2_INTERRUPT (1 << 17)
838# define DC_HPD2_RX_INTERRUPT (1 << 18)
839# define DISP_TIMER_INTERRUPT (1 << 24)
840#define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F
841# define LB_D3_VLINE_INTERRUPT (1 << 2)
842# define LB_D3_VBLANK_INTERRUPT (1 << 3)
843# define DC_HPD3_INTERRUPT (1 << 17)
844# define DC_HPD3_RX_INTERRUPT (1 << 18)
845#define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840
846# define LB_D4_VLINE_INTERRUPT (1 << 2)
847# define LB_D4_VBLANK_INTERRUPT (1 << 3)
848# define DC_HPD4_INTERRUPT (1 << 17)
849# define DC_HPD4_RX_INTERRUPT (1 << 18)
850#define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853
851# define LB_D5_VLINE_INTERRUPT (1 << 2)
852# define LB_D5_VBLANK_INTERRUPT (1 << 3)
853# define DC_HPD5_INTERRUPT (1 << 17)
854# define DC_HPD5_RX_INTERRUPT (1 << 18)
855#define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854
856# define LB_D6_VLINE_INTERRUPT (1 << 2)
857# define LB_D6_VBLANK_INTERRUPT (1 << 3)
858# define DC_HPD6_INTERRUPT (1 << 17)
859# define DC_HPD6_RX_INTERRUPT (1 << 18)
860
861/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
862#define GRPH_INT_STATUS 0x1A16
863# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
864# define GRPH_PFLIP_INT_CLEAR (1 << 8)
865/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
866#define GRPH_INT_CONTROL 0x1A17
867# define GRPH_PFLIP_INT_MASK (1 << 0)
868# define GRPH_PFLIP_INT_TYPE (1 << 8)
869
870#define DAC_AUTODETECT_INT_CONTROL 0x19F2
871
872#define DC_HPD1_INT_STATUS 0x1807
873#define DC_HPD2_INT_STATUS 0x180A
874#define DC_HPD3_INT_STATUS 0x180D
875#define DC_HPD4_INT_STATUS 0x1810
876#define DC_HPD5_INT_STATUS 0x1813
877#define DC_HPD6_INT_STATUS 0x1816
878# define DC_HPDx_INT_STATUS (1 << 0)
879# define DC_HPDx_SENSE (1 << 1)
880# define DC_HPDx_RX_INT_STATUS (1 << 8)
881
882#define DC_HPD1_INT_CONTROL 0x1808
883#define DC_HPD2_INT_CONTROL 0x180B
884#define DC_HPD3_INT_CONTROL 0x180E
885#define DC_HPD4_INT_CONTROL 0x1811
886#define DC_HPD5_INT_CONTROL 0x1814
887#define DC_HPD6_INT_CONTROL 0x1817
888# define DC_HPDx_INT_ACK (1 << 0)
889# define DC_HPDx_INT_POLARITY (1 << 8)
890# define DC_HPDx_INT_EN (1 << 16)
891# define DC_HPDx_RX_INT_ACK (1 << 20)
892# define DC_HPDx_RX_INT_EN (1 << 24)
893
894#define DC_HPD1_CONTROL 0x1809
895#define DC_HPD2_CONTROL 0x180C
896#define DC_HPD3_CONTROL 0x180F
897#define DC_HPD4_CONTROL 0x1812
898#define DC_HPD5_CONTROL 0x1815
899#define DC_HPD6_CONTROL 0x1818
900# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
901# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
902# define DC_HPDx_EN (1 << 28)
903
904#define DPG_PIPE_STUTTER_CONTROL 0x1B35
905# define STUTTER_ENABLE (1 << 0)
906
907/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
908#define CRTC_STATUS_FRAME_COUNT 0x1BA6
909
910/* Audio clocks */
911#define DCCG_AUDIO_DTO_SOURCE 0x05ac
912# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
913# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
914
915#define DCCG_AUDIO_DTO0_PHASE 0x05b0
916#define DCCG_AUDIO_DTO0_MODULE 0x05b4
917#define DCCG_AUDIO_DTO1_PHASE 0x05c0
918#define DCCG_AUDIO_DTO1_MODULE 0x05c4
919
920#define AFMT_AUDIO_SRC_CONTROL 0x1c4f
921#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
922/* AFMT_AUDIO_SRC_SELECT
923 * 0 = stream0
924 * 1 = stream1
925 * 2 = stream2
926 * 3 = stream3
927 * 4 = stream4
928 * 5 = stream5
929 */
930
931#define GRBM_CNTL 0x2000
932#define GRBM_READ_TIMEOUT(x) ((x) << 0)
933
934#define GRBM_STATUS2 0x2002
935#define RLC_RQ_PENDING (1 << 0)
936#define RLC_BUSY (1 << 8)
937#define TC_BUSY (1 << 9)
938
939#define GRBM_STATUS 0x2004
940#define CMDFIFO_AVAIL_MASK 0x0000000F
941#define RING2_RQ_PENDING (1 << 4)
942#define SRBM_RQ_PENDING (1 << 5)
943#define RING1_RQ_PENDING (1 << 6)
944#define CF_RQ_PENDING (1 << 7)
945#define PF_RQ_PENDING (1 << 8)
946#define GDS_DMA_RQ_PENDING (1 << 9)
947#define GRBM_EE_BUSY (1 << 10)
948#define DB_CLEAN (1 << 12)
949#define CB_CLEAN (1 << 13)
950#define TA_BUSY (1 << 14)
951#define GDS_BUSY (1 << 15)
952#define VGT_BUSY (1 << 17)
953#define IA_BUSY_NO_DMA (1 << 18)
954#define IA_BUSY (1 << 19)
955#define SX_BUSY (1 << 20)
956#define SPI_BUSY (1 << 22)
957#define BCI_BUSY (1 << 23)
958#define SC_BUSY (1 << 24)
959#define PA_BUSY (1 << 25)
960#define DB_BUSY (1 << 26)
961#define CP_COHERENCY_BUSY (1 << 28)
962#define CP_BUSY (1 << 29)
963#define CB_BUSY (1 << 30)
964#define GUI_ACTIVE (1 << 31)
965#define GRBM_STATUS_SE0 0x2005
966#define GRBM_STATUS_SE1 0x2006
967#define SE_DB_CLEAN (1 << 1)
968#define SE_CB_CLEAN (1 << 2)
969#define SE_BCI_BUSY (1 << 22)
970#define SE_VGT_BUSY (1 << 23)
971#define SE_PA_BUSY (1 << 24)
972#define SE_TA_BUSY (1 << 25)
973#define SE_SX_BUSY (1 << 26)
974#define SE_SPI_BUSY (1 << 27)
975#define SE_SC_BUSY (1 << 29)
976#define SE_DB_BUSY (1 << 30)
977#define SE_CB_BUSY (1 << 31)
978
979#define GRBM_SOFT_RESET 0x2008
980#define SOFT_RESET_CP (1 << 0)
981#define SOFT_RESET_CB (1 << 1)
982#define SOFT_RESET_RLC (1 << 2)
983#define SOFT_RESET_DB (1 << 3)
984#define SOFT_RESET_GDS (1 << 4)
985#define SOFT_RESET_PA (1 << 5)
986#define SOFT_RESET_SC (1 << 6)
987#define SOFT_RESET_BCI (1 << 7)
988#define SOFT_RESET_SPI (1 << 8)
989#define SOFT_RESET_SX (1 << 10)
990#define SOFT_RESET_TC (1 << 11)
991#define SOFT_RESET_TA (1 << 12)
992#define SOFT_RESET_VGT (1 << 14)
993#define SOFT_RESET_IA (1 << 15)
994
995#define GRBM_GFX_INDEX 0x200B
996#define INSTANCE_INDEX(x) ((x) << 0)
997#define SH_INDEX(x) ((x) << 8)
998#define SE_INDEX(x) ((x) << 16)
999#define SH_BROADCAST_WRITES (1 << 29)
1000#define INSTANCE_BROADCAST_WRITES (1 << 30)
1001#define SE_BROADCAST_WRITES (1 << 31)
1002
1003#define GRBM_INT_CNTL 0x2018
1004# define RDERR_INT_ENABLE (1 << 0)
1005# define GUI_IDLE_INT_ENABLE (1 << 19)
1006
1007#define CP_STRMOUT_CNTL 0x213F
1008#define SCRATCH_REG0 0x2140
1009#define SCRATCH_REG1 0x2141
1010#define SCRATCH_REG2 0x2142
1011#define SCRATCH_REG3 0x2143
1012#define SCRATCH_REG4 0x2144
1013#define SCRATCH_REG5 0x2145
1014#define SCRATCH_REG6 0x2146
1015#define SCRATCH_REG7 0x2147
1016
1017#define SCRATCH_UMSK 0x2150
1018#define SCRATCH_ADDR 0x2151
1019
1020#define CP_SEM_WAIT_TIMER 0x216F
1021
1022#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x2172
1023
1024#define CP_ME_CNTL 0x21B6
1025#define CP_CE_HALT (1 << 24)
1026#define CP_PFP_HALT (1 << 26)
1027#define CP_ME_HALT (1 << 28)
1028
1029#define CP_COHER_CNTL2 0x217A
1030
1031#define CP_RB2_RPTR 0x21BE
1032#define CP_RB1_RPTR 0x21BF
1033#define CP_RB0_RPTR 0x21C0
1034#define CP_RB_WPTR_DELAY 0x21C1
1035
1036#define CP_QUEUE_THRESHOLDS 0x21D8
1037#define ROQ_IB1_START(x) ((x) << 0)
1038#define ROQ_IB2_START(x) ((x) << 8)
1039#define CP_MEQ_THRESHOLDS 0x21D9
1040#define MEQ1_START(x) ((x) << 0)
1041#define MEQ2_START(x) ((x) << 8)
1042
1043#define CP_PERFMON_CNTL 0x21FF
1044
1045#define VGT_VTX_VECT_EJECT_REG 0x222C
1046
1047#define VGT_CACHE_INVALIDATION 0x2231
1048#define CACHE_INVALIDATION(x) ((x) << 0)
1049#define VC_ONLY 0
1050#define TC_ONLY 1
1051#define VC_AND_TC 2
1052#define AUTO_INVLD_EN(x) ((x) << 6)
1053#define NO_AUTO 0
1054#define ES_AUTO 1
1055#define GS_AUTO 2
1056#define ES_AND_GS_AUTO 3
1057#define VGT_ESGS_RING_SIZE 0x2232
1058#define VGT_GSVS_RING_SIZE 0x2233
1059
1060#define VGT_GS_VERTEX_REUSE 0x2235
1061
1062#define VGT_PRIMITIVE_TYPE 0x2256
1063#define VGT_INDEX_TYPE 0x2257
1064
1065#define VGT_NUM_INDICES 0x225C
1066#define VGT_NUM_INSTANCES 0x225D
1067
1068#define VGT_TF_RING_SIZE 0x2262
1069
1070#define VGT_HS_OFFCHIP_PARAM 0x226C
1071
1072#define VGT_TF_MEMORY_BASE 0x226E
1073
1074#define CC_GC_SHADER_ARRAY_CONFIG 0x226F
1075#define INACTIVE_CUS_MASK 0xFFFF0000
1076#define INACTIVE_CUS_SHIFT 16
1077#define GC_USER_SHADER_ARRAY_CONFIG 0x2270
1078
1079#define PA_CL_ENHANCE 0x2285
1080#define CLIP_VTX_REORDER_ENA (1 << 0)
1081#define NUM_CLIP_SEQ(x) ((x) << 1)
1082
1083#define PA_SU_LINE_STIPPLE_VALUE 0x2298
1084
1085#define PA_SC_LINE_STIPPLE_STATE 0x22C4
1086
1087#define PA_SC_FORCE_EOV_MAX_CNTS 0x22C9
1088#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1089#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1090
1091#define PA_SC_FIFO_SIZE 0x22F3
1092#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1093#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1094#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1095#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1096
1097#define PA_SC_ENHANCE 0x22FC
1098
1099#define SQ_CONFIG 0x2300
1100
1101#define SQC_CACHES 0x2302
1102
1103#define SQ_POWER_THROTTLE 0x2396
1104#define MIN_POWER(x) ((x) << 0)
1105#define MIN_POWER_MASK (0x3fff << 0)
1106#define MIN_POWER_SHIFT 0
1107#define MAX_POWER(x) ((x) << 16)
1108#define MAX_POWER_MASK (0x3fff << 16)
1109#define MAX_POWER_SHIFT 0
1110#define SQ_POWER_THROTTLE2 0x2397
1111#define MAX_POWER_DELTA(x) ((x) << 0)
1112#define MAX_POWER_DELTA_MASK (0x3fff << 0)
1113#define MAX_POWER_DELTA_SHIFT 0
1114#define STI_SIZE(x) ((x) << 16)
1115#define STI_SIZE_MASK (0x3ff << 16)
1116#define STI_SIZE_SHIFT 16
1117#define LTI_RATIO(x) ((x) << 27)
1118#define LTI_RATIO_MASK (0xf << 27)
1119#define LTI_RATIO_SHIFT 27
1120
1121#define SX_DEBUG_1 0x2418
1122
1123#define SPI_STATIC_THREAD_MGMT_1 0x2438
1124#define SPI_STATIC_THREAD_MGMT_2 0x2439
1125#define SPI_STATIC_THREAD_MGMT_3 0x243A
1126#define SPI_PS_MAX_WAVE_ID 0x243B
1127
1128#define SPI_CONFIG_CNTL 0x2440
1129
1130#define SPI_CONFIG_CNTL_1 0x244F
1131#define VTX_DONE_DELAY(x) ((x) << 0)
1132#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1133
1134#define CGTS_TCC_DISABLE 0x2452
1135#define CGTS_USER_TCC_DISABLE 0x2453
1136#define TCC_DISABLE_MASK 0xFFFF0000
1137#define TCC_DISABLE_SHIFT 16
1138#define CGTS_SM_CTRL_REG 0x2454
1139#define OVERRIDE (1 << 21)
1140#define LS_OVERRIDE (1 << 22)
1141
1142#define SPI_LB_CU_MASK 0x24D5
1143
1144#define TA_CNTL_AUX 0x2542
1145
1146#define CC_RB_BACKEND_DISABLE 0x263D
1147#define BACKEND_DISABLE(x) ((x) << 16)
1148#define GB_ADDR_CONFIG 0x263E
1149#define NUM_PIPES(x) ((x) << 0)
1150#define NUM_PIPES_MASK 0x00000007
1151#define NUM_PIPES_SHIFT 0
1152#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1153#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1154#define PIPE_INTERLEAVE_SIZE_SHIFT 4
1155#define NUM_SHADER_ENGINES(x) ((x) << 12)
1156#define NUM_SHADER_ENGINES_MASK 0x00003000
1157#define NUM_SHADER_ENGINES_SHIFT 12
1158#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1159#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1160#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1161#define NUM_GPUS(x) ((x) << 20)
1162#define NUM_GPUS_MASK 0x00700000
1163#define NUM_GPUS_SHIFT 20
1164#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
1165#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
1166#define MULTI_GPU_TILE_SIZE_SHIFT 24
1167#define ROW_SIZE(x) ((x) << 28)
1168#define ROW_SIZE_MASK 0x30000000
1169#define ROW_SIZE_SHIFT 28
1170
1171#define GB_TILE_MODE0 0x2644
1172# define MICRO_TILE_MODE(x) ((x) << 0)
1173# define ADDR_SURF_DISPLAY_MICRO_TILING 0
1174# define ADDR_SURF_THIN_MICRO_TILING 1
1175# define ADDR_SURF_DEPTH_MICRO_TILING 2
1176# define ARRAY_MODE(x) ((x) << 2)
1177# define ARRAY_LINEAR_GENERAL 0
1178# define ARRAY_LINEAR_ALIGNED 1
1179# define ARRAY_1D_TILED_THIN1 2
1180# define ARRAY_2D_TILED_THIN1 4
1181# define PIPE_CONFIG(x) ((x) << 6)
1182# define ADDR_SURF_P2 0
1183# define ADDR_SURF_P4_8x16 4
1184# define ADDR_SURF_P4_16x16 5
1185# define ADDR_SURF_P4_16x32 6
1186# define ADDR_SURF_P4_32x32 7
1187# define ADDR_SURF_P8_16x16_8x16 8
1188# define ADDR_SURF_P8_16x32_8x16 9
1189# define ADDR_SURF_P8_32x32_8x16 10
1190# define ADDR_SURF_P8_16x32_16x16 11
1191# define ADDR_SURF_P8_32x32_16x16 12
1192# define ADDR_SURF_P8_32x32_16x32 13
1193# define ADDR_SURF_P8_32x64_32x32 14
1194# define TILE_SPLIT(x) ((x) << 11)
1195# define ADDR_SURF_TILE_SPLIT_64B 0
1196# define ADDR_SURF_TILE_SPLIT_128B 1
1197# define ADDR_SURF_TILE_SPLIT_256B 2
1198# define ADDR_SURF_TILE_SPLIT_512B 3
1199# define ADDR_SURF_TILE_SPLIT_1KB 4
1200# define ADDR_SURF_TILE_SPLIT_2KB 5
1201# define ADDR_SURF_TILE_SPLIT_4KB 6
1202# define BANK_WIDTH(x) ((x) << 14)
1203# define ADDR_SURF_BANK_WIDTH_1 0
1204# define ADDR_SURF_BANK_WIDTH_2 1
1205# define ADDR_SURF_BANK_WIDTH_4 2
1206# define ADDR_SURF_BANK_WIDTH_8 3
1207# define BANK_HEIGHT(x) ((x) << 16)
1208# define ADDR_SURF_BANK_HEIGHT_1 0
1209# define ADDR_SURF_BANK_HEIGHT_2 1
1210# define ADDR_SURF_BANK_HEIGHT_4 2
1211# define ADDR_SURF_BANK_HEIGHT_8 3
1212# define MACRO_TILE_ASPECT(x) ((x) << 18)
1213# define ADDR_SURF_MACRO_ASPECT_1 0
1214# define ADDR_SURF_MACRO_ASPECT_2 1
1215# define ADDR_SURF_MACRO_ASPECT_4 2
1216# define ADDR_SURF_MACRO_ASPECT_8 3
1217# define NUM_BANKS(x) ((x) << 20)
1218# define ADDR_SURF_2_BANK 0
1219# define ADDR_SURF_4_BANK 1
1220# define ADDR_SURF_8_BANK 2
1221# define ADDR_SURF_16_BANK 3
1222
1223#define CB_PERFCOUNTER0_SELECT0 0x2688
1224#define CB_PERFCOUNTER0_SELECT1 0x2689
1225#define CB_PERFCOUNTER1_SELECT0 0x268A
1226#define CB_PERFCOUNTER1_SELECT1 0x268B
1227#define CB_PERFCOUNTER2_SELECT0 0x268C
1228#define CB_PERFCOUNTER2_SELECT1 0x268D
1229#define CB_PERFCOUNTER3_SELECT0 0x268E
1230#define CB_PERFCOUNTER3_SELECT1 0x268F
1231
1232#define CB_CGTT_SCLK_CTRL 0x2698
1233
1234#define GC_USER_RB_BACKEND_DISABLE 0x26DF
1235#define BACKEND_DISABLE_MASK 0x00FF0000
1236#define BACKEND_DISABLE_SHIFT 16
1237
1238#define TCP_CHAN_STEER_LO 0x2B03
1239#define TCP_CHAN_STEER_HI 0x2B94
1240
1241#define CP_RB0_BASE 0x3040
1242#define CP_RB0_CNTL 0x3041
1243#define RB_BUFSZ(x) ((x) << 0)
1244#define RB_BLKSZ(x) ((x) << 8)
1245#define BUF_SWAP_32BIT (2 << 16)
1246#define RB_NO_UPDATE (1 << 27)
1247#define RB_RPTR_WR_ENA (1 << 31)
1248
1249#define CP_RB0_RPTR_ADDR 0x3043
1250#define CP_RB0_RPTR_ADDR_HI 0x3044
1251#define CP_RB0_WPTR 0x3045
1252
1253#define CP_PFP_UCODE_ADDR 0x3054
1254#define CP_PFP_UCODE_DATA 0x3055
1255#define CP_ME_RAM_RADDR 0x3056
1256#define CP_ME_RAM_WADDR 0x3057
1257#define CP_ME_RAM_DATA 0x3058
1258
1259#define CP_CE_UCODE_ADDR 0x305A
1260#define CP_CE_UCODE_DATA 0x305B
1261
1262#define CP_RB1_BASE 0x3060
1263#define CP_RB1_CNTL 0x3061
1264#define CP_RB1_RPTR_ADDR 0x3062
1265#define CP_RB1_RPTR_ADDR_HI 0x3063
1266#define CP_RB1_WPTR 0x3064
1267#define CP_RB2_BASE 0x3065
1268#define CP_RB2_CNTL 0x3066
1269#define CP_RB2_RPTR_ADDR 0x3067
1270#define CP_RB2_RPTR_ADDR_HI 0x3068
1271#define CP_RB2_WPTR 0x3069
1272#define CP_INT_CNTL_RING0 0x306A
1273#define CP_INT_CNTL_RING1 0x306B
1274#define CP_INT_CNTL_RING2 0x306C
1275# define CNTX_BUSY_INT_ENABLE (1 << 19)
1276# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1277# define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1278# define TIME_STAMP_INT_ENABLE (1 << 26)
1279# define CP_RINGID2_INT_ENABLE (1 << 29)
1280# define CP_RINGID1_INT_ENABLE (1 << 30)
1281# define CP_RINGID0_INT_ENABLE (1 << 31)
1282#define CP_INT_STATUS_RING0 0x306D
1283#define CP_INT_STATUS_RING1 0x306E
1284#define CP_INT_STATUS_RING2 0x306F
1285# define WAIT_MEM_SEM_INT_STAT (1 << 21)
1286# define TIME_STAMP_INT_STAT (1 << 26)
1287# define CP_RINGID2_INT_STAT (1 << 29)
1288# define CP_RINGID1_INT_STAT (1 << 30)
1289# define CP_RINGID0_INT_STAT (1 << 31)
1290
1291#define CP_MEM_SLP_CNTL 0x3079
1292# define CP_MEM_LS_EN (1 << 0)
1293
1294#define CP_DEBUG 0x307F
1295
1296#define RLC_CNTL 0x30C0
1297# define RLC_ENABLE (1 << 0)
1298#define RLC_RL_BASE 0x30C1
1299#define RLC_RL_SIZE 0x30C2
1300#define RLC_LB_CNTL 0x30C3
1301# define LOAD_BALANCE_ENABLE (1 << 0)
1302#define RLC_SAVE_AND_RESTORE_BASE 0x30C4
1303#define RLC_LB_CNTR_MAX 0x30C5
1304#define RLC_LB_CNTR_INIT 0x30C6
1305
1306#define RLC_CLEAR_STATE_RESTORE_BASE 0x30C8
1307
1308#define RLC_UCODE_ADDR 0x30CB
1309#define RLC_UCODE_DATA 0x30CC
1310
1311#define RLC_GPU_CLOCK_COUNT_LSB 0x30CE
1312#define RLC_GPU_CLOCK_COUNT_MSB 0x30CF
1313#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0
1314#define RLC_MC_CNTL 0x30D1
1315#define RLC_UCODE_CNTL 0x30D2
1316#define RLC_STAT 0x30D3
1317# define RLC_BUSY_STATUS (1 << 0)
1318# define GFX_POWER_STATUS (1 << 1)
1319# define GFX_CLOCK_STATUS (1 << 2)
1320# define GFX_LS_STATUS (1 << 3)
1321
1322#define RLC_PG_CNTL 0x30D7
1323# define GFX_PG_ENABLE (1 << 0)
1324# define GFX_PG_SRC (1 << 1)
1325
1326#define RLC_CGTT_MGCG_OVERRIDE 0x3100
1327#define RLC_CGCG_CGLS_CTRL 0x3101
1328# define CGCG_EN (1 << 0)
1329# define CGLS_EN (1 << 1)
1330
1331#define RLC_TTOP_D 0x3105
1332# define RLC_PUD(x) ((x) << 0)
1333# define RLC_PUD_MASK (0xff << 0)
1334# define RLC_PDD(x) ((x) << 8)
1335# define RLC_PDD_MASK (0xff << 8)
1336# define RLC_TTPD(x) ((x) << 16)
1337# define RLC_TTPD_MASK (0xff << 16)
1338# define RLC_MSD(x) ((x) << 24)
1339# define RLC_MSD_MASK (0xff << 24)
1340
1341#define RLC_LB_INIT_CU_MASK 0x3107
1342
1343#define RLC_PG_AO_CU_MASK 0x310B
1344#define RLC_MAX_PG_CU 0x310C
1345# define MAX_PU_CU(x) ((x) << 0)
1346# define MAX_PU_CU_MASK (0xff << 0)
1347#define RLC_AUTO_PG_CTRL 0x310C
1348# define AUTO_PG_EN (1 << 0)
1349# define GRBM_REG_SGIT(x) ((x) << 3)
1350# define GRBM_REG_SGIT_MASK (0xffff << 3)
1351# define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
1352# define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
1353
1354#define RLC_SERDES_WR_MASTER_MASK_0 0x3115
1355#define RLC_SERDES_WR_MASTER_MASK_1 0x3116
1356#define RLC_SERDES_WR_CTRL 0x3117
1357
1358#define RLC_SERDES_MASTER_BUSY_0 0x3119
1359#define RLC_SERDES_MASTER_BUSY_1 0x311A
1360
1361#define RLC_GCPM_GENERAL_3 0x311E
1362
1363#define DB_RENDER_CONTROL 0xA000
1364
1365#define DB_DEPTH_INFO 0xA00F
1366
1367#define PA_SC_RASTER_CONFIG 0xA0D4
1368# define RASTER_CONFIG_RB_MAP_0 0
1369# define RASTER_CONFIG_RB_MAP_1 1
1370# define RASTER_CONFIG_RB_MAP_2 2
1371# define RASTER_CONFIG_RB_MAP_3 3
1372
1373#define VGT_EVENT_INITIATOR 0xA2A4
1374# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1375# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1376# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1377# define CACHE_FLUSH_TS (4 << 0)
1378# define CACHE_FLUSH (6 << 0)
1379# define CS_PARTIAL_FLUSH (7 << 0)
1380# define VGT_STREAMOUT_RESET (10 << 0)
1381# define END_OF_PIPE_INCR_DE (11 << 0)
1382# define END_OF_PIPE_IB_END (12 << 0)
1383# define RST_PIX_CNT (13 << 0)
1384# define VS_PARTIAL_FLUSH (15 << 0)
1385# define PS_PARTIAL_FLUSH (16 << 0)
1386# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1387# define ZPASS_DONE (21 << 0)
1388# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1389# define PERFCOUNTER_START (23 << 0)
1390# define PERFCOUNTER_STOP (24 << 0)
1391# define PIPELINESTAT_START (25 << 0)
1392# define PIPELINESTAT_STOP (26 << 0)
1393# define PERFCOUNTER_SAMPLE (27 << 0)
1394# define SAMPLE_PIPELINESTAT (30 << 0)
1395# define SAMPLE_STREAMOUTSTATS (32 << 0)
1396# define RESET_VTX_CNT (33 << 0)
1397# define VGT_FLUSH (36 << 0)
1398# define BOTTOM_OF_PIPE_TS (40 << 0)
1399# define DB_CACHE_FLUSH_AND_INV (42 << 0)
1400# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1401# define FLUSH_AND_INV_DB_META (44 << 0)
1402# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1403# define FLUSH_AND_INV_CB_META (46 << 0)
1404# define CS_DONE (47 << 0)
1405# define PS_DONE (48 << 0)
1406# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1407# define THREAD_TRACE_START (51 << 0)
1408# define THREAD_TRACE_STOP (52 << 0)
1409# define THREAD_TRACE_FLUSH (54 << 0)
1410# define THREAD_TRACE_FINISH (55 << 0)
1411
1412/* PIF PHY0 registers idx/data 0x8/0xc */
1413#define PB0_PIF_CNTL 0x10
1414# define LS2_EXIT_TIME(x) ((x) << 17)
1415# define LS2_EXIT_TIME_MASK (0x7 << 17)
1416# define LS2_EXIT_TIME_SHIFT 17
1417#define PB0_PIF_PAIRING 0x11
1418# define MULTI_PIF (1 << 25)
1419#define PB0_PIF_PWRDOWN_0 0x12
1420# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1421# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1422# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1423# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1424# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1425# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1426# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1427# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1428# define PLL_RAMP_UP_TIME_0_SHIFT 24
1429#define PB0_PIF_PWRDOWN_1 0x13
1430# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1431# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1432# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1433# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1434# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1435# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1436# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1437# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1438# define PLL_RAMP_UP_TIME_1_SHIFT 24
1439
1440#define PB0_PIF_PWRDOWN_2 0x17
1441# define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
1442# define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1443# define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
1444# define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
1445# define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1446# define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
1447# define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
1448# define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1449# define PLL_RAMP_UP_TIME_2_SHIFT 24
1450#define PB0_PIF_PWRDOWN_3 0x18
1451# define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
1452# define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1453# define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
1454# define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
1455# define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1456# define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
1457# define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
1458# define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1459# define PLL_RAMP_UP_TIME_3_SHIFT 24
1460/* PIF PHY1 registers idx/data 0x10/0x14 */
1461#define PB1_PIF_CNTL 0x10
1462#define PB1_PIF_PAIRING 0x11
1463#define PB1_PIF_PWRDOWN_0 0x12
1464#define PB1_PIF_PWRDOWN_1 0x13
1465
1466#define PB1_PIF_PWRDOWN_2 0x17
1467#define PB1_PIF_PWRDOWN_3 0x18
1468/* PCIE registers idx/data 0x30/0x34 */
1469#define PCIE_CNTL2 0x1c /* PCIE */
1470# define SLV_MEM_LS_EN (1 << 16)
1471# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1472# define MST_MEM_LS_EN (1 << 18)
1473# define REPLAY_MEM_LS_EN (1 << 19)
1474#define PCIE_LC_STATUS1 0x28 /* PCIE */
1475# define LC_REVERSE_RCVR (1 << 0)
1476# define LC_REVERSE_XMIT (1 << 1)
1477# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1478# define LC_OPERATING_LINK_WIDTH_SHIFT 2
1479# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1480# define LC_DETECTED_LINK_WIDTH_SHIFT 5
1481
1482#define PCIE_P_CNTL 0x40 /* PCIE */
1483# define P_IGNORE_EDB_ERR (1 << 6)
1484
1485/* PCIE PORT registers idx/data 0x38/0x3c */
1486#define PCIE_LC_CNTL 0xa0
1487# define LC_L0S_INACTIVITY(x) ((x) << 8)
1488# define LC_L0S_INACTIVITY_MASK (0xf << 8)
1489# define LC_L0S_INACTIVITY_SHIFT 8
1490# define LC_L1_INACTIVITY(x) ((x) << 12)
1491# define LC_L1_INACTIVITY_MASK (0xf << 12)
1492# define LC_L1_INACTIVITY_SHIFT 12
1493# define LC_PMI_TO_L1_DIS (1 << 16)
1494# define LC_ASPM_TO_L1_DIS (1 << 24)
1495#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1496# define LC_LINK_WIDTH_SHIFT 0
1497# define LC_LINK_WIDTH_MASK 0x7
1498# define LC_LINK_WIDTH_X0 0
1499# define LC_LINK_WIDTH_X1 1
1500# define LC_LINK_WIDTH_X2 2
1501# define LC_LINK_WIDTH_X4 3
1502# define LC_LINK_WIDTH_X8 4
1503# define LC_LINK_WIDTH_X16 6
1504# define LC_LINK_WIDTH_RD_SHIFT 4
1505# define LC_LINK_WIDTH_RD_MASK 0x70
1506# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1507# define LC_RECONFIG_NOW (1 << 8)
1508# define LC_RENEGOTIATION_SUPPORT (1 << 9)
1509# define LC_RENEGOTIATE_EN (1 << 10)
1510# define LC_SHORT_RECONFIG_EN (1 << 11)
1511# define LC_UPCONFIGURE_SUPPORT (1 << 12)
1512# define LC_UPCONFIGURE_DIS (1 << 13)
1513# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1514# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1515# define LC_DYN_LANES_PWR_STATE_SHIFT 21
1516#define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1517# define LC_XMIT_N_FTS(x) ((x) << 0)
1518# define LC_XMIT_N_FTS_MASK (0xff << 0)
1519# define LC_XMIT_N_FTS_SHIFT 0
1520# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1521# define LC_N_FTS_MASK (0xff << 24)
1522#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1523# define LC_GEN2_EN_STRAP (1 << 0)
1524# define LC_GEN3_EN_STRAP (1 << 1)
1525# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1526# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1527# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
1528# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1529# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1530# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1531# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1532# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1533# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1534# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
1535# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1536# define LC_CURRENT_DATA_RATE_SHIFT 13
1537# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1538# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1539# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1540# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1541# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1542
1543#define PCIE_LC_CNTL2 0xb1
1544# define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1545# define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1546
1547#define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1548# define LC_GO_TO_RECOVERY (1 << 30)
1549#define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1550# define LC_REDO_EQ (1 << 5)
1551# define LC_SET_QUIESCE (1 << 13)
1552
1553/*
1554 * UVD
1555 */
1556#define UVD_UDEC_ADDR_CONFIG 0x3bd3
1557#define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4
1558#define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
1559#define UVD_RBC_RB_RPTR 0x3da4
1560#define UVD_RBC_RB_WPTR 0x3da5
1561#define UVD_STATUS 0x3daf
1562
1563#define UVD_CGC_CTRL 0x3dc2
1564# define DCM (1 << 0)
1565# define CG_DT(x) ((x) << 2)
1566# define CG_DT_MASK (0xf << 2)
1567# define CLK_OD(x) ((x) << 6)
1568# define CLK_OD_MASK (0x1f << 6)
1569
1570 /* UVD CTX indirect */
1571#define UVD_CGC_MEM_CTRL 0xC0
1572#define UVD_CGC_CTRL2 0xC1
1573# define DYN_OR_EN (1 << 0)
1574# define DYN_RR_EN (1 << 1)
1575# define G_DIV_ID(x) ((x) << 2)
1576# define G_DIV_ID_MASK (0x7 << 2)
1577
1578/*
1579 * PM4
1580 */
1581#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1582 (((reg) >> 2) & 0xFFFF) | \
1583 ((n) & 0x3FFF) << 16)
1584#define CP_PACKET2 0x80000000
1585#define PACKET2_PAD_SHIFT 0
1586#define PACKET2_PAD_MASK (0x3fffffff << 0)
1587
1588#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1589#define RADEON_PACKET_TYPE3 3
1590#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1591 (((op) & 0xFF) << 8) | \
1592 ((n) & 0x3FFF) << 16)
1593
1594#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1595
1596/* Packet 3 types */
1597#define PACKET3_NOP 0x10
1598#define PACKET3_SET_BASE 0x11
1599#define PACKET3_BASE_INDEX(x) ((x) << 0)
1600#define GDS_PARTITION_BASE 2
1601#define CE_PARTITION_BASE 3
1602#define PACKET3_CLEAR_STATE 0x12
1603#define PACKET3_INDEX_BUFFER_SIZE 0x13
1604#define PACKET3_DISPATCH_DIRECT 0x15
1605#define PACKET3_DISPATCH_INDIRECT 0x16
1606#define PACKET3_ALLOC_GDS 0x1B
1607#define PACKET3_WRITE_GDS_RAM 0x1C
1608#define PACKET3_ATOMIC_GDS 0x1D
1609#define PACKET3_ATOMIC 0x1E
1610#define PACKET3_OCCLUSION_QUERY 0x1F
1611#define PACKET3_SET_PREDICATION 0x20
1612#define PACKET3_REG_RMW 0x21
1613#define PACKET3_COND_EXEC 0x22
1614#define PACKET3_PRED_EXEC 0x23
1615#define PACKET3_DRAW_INDIRECT 0x24
1616#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1617#define PACKET3_INDEX_BASE 0x26
1618#define PACKET3_DRAW_INDEX_2 0x27
1619#define PACKET3_CONTEXT_CONTROL 0x28
1620#define PACKET3_INDEX_TYPE 0x2A
1621#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1622#define PACKET3_DRAW_INDEX_AUTO 0x2D
1623#define PACKET3_DRAW_INDEX_IMMD 0x2E
1624#define PACKET3_NUM_INSTANCES 0x2F
1625#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1626#define PACKET3_INDIRECT_BUFFER_CONST 0x31
1627#define PACKET3_INDIRECT_BUFFER 0x3F
1628#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1629#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1630#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1631#define PACKET3_WRITE_DATA 0x37
1632#define WRITE_DATA_DST_SEL(x) ((x) << 8)
1633 /* 0 - register
1634 * 1 - memory (sync - via GRBM)
1635 * 2 - tc/l2
1636 * 3 - gds
1637 * 4 - reserved
1638 * 5 - memory (async - direct)
1639 */
1640#define WR_ONE_ADDR (1 << 16)
1641#define WR_CONFIRM (1 << 20)
1642#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1643 /* 0 - me
1644 * 1 - pfp
1645 * 2 - ce
1646 */
1647#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1648#define PACKET3_MEM_SEMAPHORE 0x39
1649#define PACKET3_MPEG_INDEX 0x3A
1650#define PACKET3_COPY_DW 0x3B
1651#define PACKET3_WAIT_REG_MEM 0x3C
1652#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1653 /* 0 - always
1654 * 1 - <
1655 * 2 - <=
1656 * 3 - ==
1657 * 4 - !=
1658 * 5 - >=
1659 * 6 - >
1660 */
1661#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1662 /* 0 - reg
1663 * 1 - mem
1664 */
1665#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1666 /* 0 - me
1667 * 1 - pfp
1668 */
1669#define PACKET3_MEM_WRITE 0x3D
1670#define PACKET3_COPY_DATA 0x40
1671#define PACKET3_CP_DMA 0x41
1672/* 1. header
1673 * 2. SRC_ADDR_LO or DATA [31:0]
1674 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1675 * SRC_ADDR_HI [7:0]
1676 * 4. DST_ADDR_LO [31:0]
1677 * 5. DST_ADDR_HI [7:0]
1678 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1679 */
1680# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1681 /* 0 - DST_ADDR
1682 * 1 - GDS
1683 */
1684# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1685 /* 0 - ME
1686 * 1 - PFP
1687 */
1688# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1689 /* 0 - SRC_ADDR
1690 * 1 - GDS
1691 * 2 - DATA
1692 */
1693# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1694/* COMMAND */
1695# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1696# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1697 /* 0 - none
1698 * 1 - 8 in 16
1699 * 2 - 8 in 32
1700 * 3 - 8 in 64
1701 */
1702# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1703 /* 0 - none
1704 * 1 - 8 in 16
1705 * 2 - 8 in 32
1706 * 3 - 8 in 64
1707 */
1708# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1709 /* 0 - memory
1710 * 1 - register
1711 */
1712# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1713 /* 0 - memory
1714 * 1 - register
1715 */
1716# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1717# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1718# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1719#define PACKET3_PFP_SYNC_ME 0x42
1720#define PACKET3_SURFACE_SYNC 0x43
1721# define PACKET3_DEST_BASE_0_ENA (1 << 0)
1722# define PACKET3_DEST_BASE_1_ENA (1 << 1)
1723# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1724# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1725# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1726# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1727# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1728# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1729# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1730# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1731# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1732# define PACKET3_DEST_BASE_2_ENA (1 << 19)
1733# define PACKET3_DEST_BASE_3_ENA (1 << 21)
1734# define PACKET3_TCL1_ACTION_ENA (1 << 22)
1735# define PACKET3_TC_ACTION_ENA (1 << 23)
1736# define PACKET3_CB_ACTION_ENA (1 << 25)
1737# define PACKET3_DB_ACTION_ENA (1 << 26)
1738# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1739# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1740#define PACKET3_ME_INITIALIZE 0x44
1741#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1742#define PACKET3_COND_WRITE 0x45
1743#define PACKET3_EVENT_WRITE 0x46
1744#define EVENT_TYPE(x) ((x) << 0)
1745#define EVENT_INDEX(x) ((x) << 8)
1746 /* 0 - any non-TS event
1747 * 1 - ZPASS_DONE
1748 * 2 - SAMPLE_PIPELINESTAT
1749 * 3 - SAMPLE_STREAMOUTSTAT*
1750 * 4 - *S_PARTIAL_FLUSH
1751 * 5 - EOP events
1752 * 6 - EOS events
1753 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1754 */
1755#define INV_L2 (1 << 20)
1756 /* INV TC L2 cache when EVENT_INDEX = 7 */
1757#define PACKET3_EVENT_WRITE_EOP 0x47
1758#define DATA_SEL(x) ((x) << 29)
1759 /* 0 - discard
1760 * 1 - send low 32bit data
1761 * 2 - send 64bit data
1762 * 3 - send 64bit counter value
1763 */
1764#define INT_SEL(x) ((x) << 24)
1765 /* 0 - none
1766 * 1 - interrupt only (DATA_SEL = 0)
1767 * 2 - interrupt when data write is confirmed
1768 */
1769#define PACKET3_EVENT_WRITE_EOS 0x48
1770#define PACKET3_PREAMBLE_CNTL 0x4A
1771# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1772# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1773#define PACKET3_ONE_REG_WRITE 0x57
1774#define PACKET3_LOAD_CONFIG_REG 0x5F
1775#define PACKET3_LOAD_CONTEXT_REG 0x60
1776#define PACKET3_LOAD_SH_REG 0x61
1777#define PACKET3_SET_CONFIG_REG 0x68
1778#define PACKET3_SET_CONFIG_REG_START 0x00002000
1779#define PACKET3_SET_CONFIG_REG_END 0x00002c00
1780#define PACKET3_SET_CONTEXT_REG 0x69
1781#define PACKET3_SET_CONTEXT_REG_START 0x000a000
1782#define PACKET3_SET_CONTEXT_REG_END 0x000a400
1783#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1784#define PACKET3_SET_RESOURCE_INDIRECT 0x74
1785#define PACKET3_SET_SH_REG 0x76
1786#define PACKET3_SET_SH_REG_START 0x00002c00
1787#define PACKET3_SET_SH_REG_END 0x00003000
1788#define PACKET3_SET_SH_REG_OFFSET 0x77
1789#define PACKET3_ME_WRITE 0x7A
1790#define PACKET3_SCRATCH_RAM_WRITE 0x7D
1791#define PACKET3_SCRATCH_RAM_READ 0x7E
1792#define PACKET3_CE_WRITE 0x7F
1793#define PACKET3_LOAD_CONST_RAM 0x80
1794#define PACKET3_WRITE_CONST_RAM 0x81
1795#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1796#define PACKET3_DUMP_CONST_RAM 0x83
1797#define PACKET3_INCREMENT_CE_COUNTER 0x84
1798#define PACKET3_INCREMENT_DE_COUNTER 0x85
1799#define PACKET3_WAIT_ON_CE_COUNTER 0x86
1800#define PACKET3_WAIT_ON_DE_COUNTER 0x87
1801#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1802#define PACKET3_SET_CE_DE_COUNTERS 0x89
1803#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1804#define PACKET3_SWITCH_BUFFER 0x8B
1805
1806/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1807#define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1808#define DMA1_REGISTER_OFFSET 0x200 /* not a register */
1809
1810#define DMA_RB_CNTL 0x3400
1811# define DMA_RB_ENABLE (1 << 0)
1812# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1813# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1814# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1815# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1816# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1817#define DMA_RB_BASE 0x3401
1818#define DMA_RB_RPTR 0x3402
1819#define DMA_RB_WPTR 0x3403
1820
1821#define DMA_RB_RPTR_ADDR_HI 0x3407
1822#define DMA_RB_RPTR_ADDR_LO 0x3408
1823
1824#define DMA_IB_CNTL 0x3409
1825# define DMA_IB_ENABLE (1 << 0)
1826# define DMA_IB_SWAP_ENABLE (1 << 4)
1827# define CMD_VMID_FORCE (1 << 31)
1828#define DMA_IB_RPTR 0x340a
1829#define DMA_CNTL 0x340b
1830# define TRAP_ENABLE (1 << 0)
1831# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1832# define SEM_WAIT_INT_ENABLE (1 << 2)
1833# define DATA_SWAP_ENABLE (1 << 3)
1834# define FENCE_SWAP_ENABLE (1 << 4)
1835# define CTXEMPTY_INT_ENABLE (1 << 28)
1836#define DMA_STATUS_REG 0x340d
1837# define DMA_IDLE (1 << 0)
1838#define DMA_TILING_CONFIG 0x342e
1839
1840#define DMA_POWER_CNTL 0x342f
1841# define MEM_POWER_OVERRIDE (1 << 8)
1842#define DMA_CLK_CTRL 0x3430
1843
1844#define DMA_PG 0x3435
1845# define PG_CNTL_ENABLE (1 << 0)
1846#define DMA_PGFSM_CONFIG 0x3436
1847#define DMA_PGFSM_WRITE 0x3437
1848
1849#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1850 (((b) & 0x1) << 26) | \
1851 (((t) & 0x1) << 23) | \
1852 (((s) & 0x1) << 22) | \
1853 (((n) & 0xFFFFF) << 0))
1854
1855#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1856 (((vmid) & 0xF) << 20) | \
1857 (((n) & 0xFFFFF) << 0))
1858
1859#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1860 (1 << 26) | \
1861 (1 << 21) | \
1862 (((n) & 0xFFFFF) << 0))
1863
1864/* async DMA Packet types */
1865#define DMA_PACKET_WRITE 0x2
1866#define DMA_PACKET_COPY 0x3
1867#define DMA_PACKET_INDIRECT_BUFFER 0x4
1868#define DMA_PACKET_SEMAPHORE 0x5
1869#define DMA_PACKET_FENCE 0x6
1870#define DMA_PACKET_TRAP 0x7
1871#define DMA_PACKET_SRBM_WRITE 0x9
1872#define DMA_PACKET_CONSTANT_FILL 0xd
1873#define DMA_PACKET_POLL_REG_MEM 0xe
1874#define DMA_PACKET_NOP 0xf
1875
1876#define VCE_STATUS 0x20004
1877#define VCE_VCPU_CNTL 0x20014
1878#define VCE_CLK_EN (1 << 0)
1879#define VCE_VCPU_CACHE_OFFSET0 0x20024
1880#define VCE_VCPU_CACHE_SIZE0 0x20028
1881#define VCE_VCPU_CACHE_OFFSET1 0x2002c
1882#define VCE_VCPU_CACHE_SIZE1 0x20030
1883#define VCE_VCPU_CACHE_OFFSET2 0x20034
1884#define VCE_VCPU_CACHE_SIZE2 0x20038
1885#define VCE_SOFT_RESET 0x20120
1886#define VCE_ECPU_SOFT_RESET (1 << 0)
1887#define VCE_FME_SOFT_RESET (1 << 2)
1888#define VCE_RB_BASE_LO2 0x2016c
1889#define VCE_RB_BASE_HI2 0x20170
1890#define VCE_RB_SIZE2 0x20174
1891#define VCE_RB_RPTR2 0x20178
1892#define VCE_RB_WPTR2 0x2017c
1893#define VCE_RB_BASE_LO 0x20180
1894#define VCE_RB_BASE_HI 0x20184
1895#define VCE_RB_SIZE 0x20188
1896#define VCE_RB_RPTR 0x2018c
1897#define VCE_RB_WPTR 0x20190
1898#define VCE_CLOCK_GATING_A 0x202f8
1899#define VCE_CLOCK_GATING_B 0x202fc
1900#define VCE_UENC_CLOCK_GATING 0x205bc
1901#define VCE_UENC_REG_CLOCK_GATING 0x205c0
1902#define VCE_FW_REG_STATUS 0x20e10
1903# define VCE_FW_REG_STATUS_BUSY (1 << 0)
1904# define VCE_FW_REG_STATUS_PASS (1 << 3)
1905# define VCE_FW_REG_STATUS_DONE (1 << 11)
1906#define VCE_LMI_FW_START_KEYSEL 0x20e18
1907#define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
1908#define VCE_LMI_CTRL2 0x20e74
1909#define VCE_LMI_CTRL 0x20e98
1910#define VCE_LMI_VM_CTRL 0x20ea0
1911#define VCE_LMI_SWAP_CNTL 0x20eb4
1912#define VCE_LMI_SWAP_CNTL1 0x20eb8
1913#define VCE_LMI_CACHE_CTRL 0x20ef4
1914
1915#define VCE_CMD_NO_OP 0x00000000
1916#define VCE_CMD_END 0x00000001
1917#define VCE_CMD_IB 0x00000002
1918#define VCE_CMD_FENCE 0x00000003
1919#define VCE_CMD_TRAP 0x00000004
1920#define VCE_CMD_IB_AUTO 0x00000005
1921#define VCE_CMD_SEMAPHORE 0x00000006
1922
1923
1924//#dce stupp
1925/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
1926#define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4
1927#define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/4
1928#define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/4
1929#define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/4
1930#define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/4
1931#define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/4
1932
1933#define CURSOR_WIDTH 64
1934#define CURSOR_HEIGHT 64
1935#define AMDGPU_MM_INDEX 0x0000
1936#define AMDGPU_MM_DATA 0x0001
1937
1938#define VERDE_NUM_CRTC 6
1939#define BLACKOUT_MODE_MASK 0x00000007
1940#define VGA_RENDER_CONTROL 0xC0
1941#define R_000300_VGA_RENDER_CONTROL 0xC0
1942#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
1943#define EVERGREEN_CRTC_STATUS 0x1BA3
1944#define EVERGREEN_CRTC_V_BLANK (1 << 0)
1945#define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4
1946/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
1947#define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d
1948#define EVERGREEN_CRTC_CONTROL 0x1b9c
1949#define EVERGREEN_CRTC_MASTER_EN (1 << 0)
1950#define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
1951#define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d
1952#define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
1953#define EVERGREEN_CRTC_V_BLANK (1 << 0)
1954#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8
1955#define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5
1956#define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd
1957#define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe
1958#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
1959#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
1960#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
1961#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
1962#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
1963#define EVERGREEN_GRPH_UPDATE 0x1a11
1964#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4
1965#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
1966#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
1967
1968#define EVERGREEN_DATA_FORMAT 0x1ac0
1969# define EVERGREEN_INTERLEAVE_EN (1 << 0)
1970
1971#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
1972#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
1973
1974#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
1975#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
1976#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
1977#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
1978
1979#define AMDGPU_TILING_MACRO 0x1
1980#define AMDGPU_TILING_MICRO 0x2
1981
1982#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a45
1983#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1845
1984
1985#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847
1986#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47
1987
1988#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
1989#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
1990#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
1991#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
1992#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
1993#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
1994
1995#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
1996#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
1997#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
1998#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
1999#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
2000#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
2001
2002#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
2003#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
2004#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
2005#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
2006#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
2007#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
2008
2009#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
2010#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
2011
2012#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1
2013
2014#define R600_D1GRPH_SWAP_CONTROL 0x1843
2015#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
2016#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
2017#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
2018#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
2019
2020#define AVIVO_D1VGA_CONTROL 0x00cc
2021#define AVIVO_D2VGA_CONTROL 0x00ce
2022
2023#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
2024
2025#define FMT_BIT_DEPTH_CONTROL 0x1bf2
2026#define FMT_TRUNCATE_EN (1 << 0)
2027#define FMT_TRUNCATE_DEPTH (1 << 4)
2028#define FMT_SPATIAL_DITHER_EN (1 << 8)
2029#define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
2030#define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
2031#define FMT_FRAME_RANDOM_ENABLE (1 << 13)
2032#define FMT_RGB_RANDOM_ENABLE (1 << 14)
2033#define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
2034#define FMT_TEMPORAL_DITHER_EN (1 << 16)
2035#define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
2036#define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
2037#define FMT_TEMPORAL_LEVEL (1 << 24)
2038#define FMT_TEMPORAL_DITHER_RESET (1 << 25)
2039#define FMT_25FRC_SEL(x) ((x) << 26)
2040#define FMT_50FRC_SEL(x) ((x) << 28)
2041#define FMT_75FRC_SEL(x) ((x) << 30)
2042
2043#define EVERGREEN_DC_LUT_CONTROL 0x1a80
2044#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
2045#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
2046#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x1a83
2047#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
2048#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
2049#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x1a86
2050#define EVERGREEN_DC_LUT_30_COLOR 0x1a7c
2051#define EVERGREEN_DC_LUT_RW_INDEX 0x1a79
2052#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x1a7e
2053#define EVERGREEN_DC_LUT_RW_MODE 0x1a78
2054
2055#define EVERGREEN_GRPH_ENABLE 0x1a00
2056#define EVERGREEN_GRPH_CONTROL 0x1a01
2057#define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
2058#define EVERGREEN_GRPH_DEPTH_8BPP 0
2059#define EVERGREEN_GRPH_DEPTH_16BPP 1
2060#define EVERGREEN_GRPH_DEPTH_32BPP 2
2061#define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
2062#define EVERGREEN_ADDR_SURF_2_BANK 0
2063#define EVERGREEN_ADDR_SURF_4_BANK 1
2064#define EVERGREEN_ADDR_SURF_8_BANK 2
2065#define EVERGREEN_ADDR_SURF_16_BANK 3
2066#define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4)
2067#define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
2068#define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0
2069#define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1
2070#define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2
2071#define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3
2072#define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
2073
2074#define EVERGREEN_GRPH_FORMAT_INDEXED 0
2075#define EVERGREEN_GRPH_FORMAT_ARGB1555 0
2076#define EVERGREEN_GRPH_FORMAT_ARGB565 1
2077#define EVERGREEN_GRPH_FORMAT_ARGB4444 2
2078#define EVERGREEN_GRPH_FORMAT_AI88 3
2079#define EVERGREEN_GRPH_FORMAT_MONO16 4
2080#define EVERGREEN_GRPH_FORMAT_BGRA5551 5
2081
2082/* 32 BPP */
2083#define EVERGREEN_GRPH_FORMAT_ARGB8888 0
2084#define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
2085#define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
2086#define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3
2087#define EVERGREEN_GRPH_FORMAT_BGRA1010102 4
2088#define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
2089#define EVERGREEN_GRPH_FORMAT_RGB111110 6
2090#define EVERGREEN_GRPH_FORMAT_BGR101111 7
2091#define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
2092#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0
2093#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1
2094#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2
2095#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3
2096#define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
2097#define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0
2098#define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1
2099#define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2
2100#define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3
2101#define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4
2102#define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5
2103#define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6
2104#define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
2105#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
2106#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
2107#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
2108#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3
2109#define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
2110#define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0
2111#define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
2112#define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2
2113#define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4
2114#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
2115#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
2116#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
2117#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3
2118
2119#define EVERGREEN_GRPH_SWAP_CONTROL 0x1a03
2120#define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
2121#define EVERGREEN_GRPH_ENDIAN_NONE 0
2122
2123/* this object requires a surface when mapped - i.e. front buffer */
2124#define RADEON_TILING_SURFACE 0x10
2125#define RADEON_TILING_MICRO_SQUARE 0x20
2126#define RADEON_TILING_EG_BANKW_SHIFT 8
2127#define RADEON_TILING_EG_BANKW_MASK 0xf
2128#define RADEON_TILING_EG_BANKH_SHIFT 12
2129#define RADEON_TILING_EG_BANKH_MASK 0xf
2130#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
2131#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
2132#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
2133#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
2134#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
2135#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
2136
2137#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
2138#define SI_TILE_MODE_COLOR_1D 13
2139#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
2140#define SI_TILE_MODE_COLOR_2D_8BPP 14
2141#define SI_TILE_MODE_COLOR_2D_16BPP 15
2142#define SI_TILE_MODE_COLOR_2D_32BPP 16
2143#define SI_TILE_MODE_COLOR_2D_64BPP 17
2144#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
2145#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
2146#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
2147#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
2148#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
2149#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
2150#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
2151
2152#define EVERGREEN_D3VGA_CONTROL 0xf8
2153#define EVERGREEN_D4VGA_CONTROL 0xf9
2154#define EVERGREEN_D5VGA_CONTROL 0xfa
2155#define EVERGREEN_D6VGA_CONTROL 0xfb
2156
2157#define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00
2158
2159#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02
2160#define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)
2161
2162#define EVERGREEN_GRPH_PITCH 0x1a06
2163#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
2164#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
2165#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a09
2166#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a
2167#define EVERGREEN_GRPH_X_START 0x1a0b
2168#define EVERGREEN_GRPH_Y_START 0x1a0c
2169#define EVERGREEN_GRPH_X_END 0x1a0d
2170#define EVERGREEN_GRPH_Y_END 0x1a0e
2171#define EVERGREEN_GRPH_UPDATE 0x1a11
2172#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2173#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2174#define EVERGREEN_GRPH_FLIP_CONTROL 0x1a12
2175#define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
2176
2177#define EVERGREEN_VIEWPORT_START 0x1b5c
2178#define EVERGREEN_VIEWPORT_SIZE 0x1b5d
2179#define EVERGREEN_DESKTOP_HEIGHT 0x1ac1
2180
2181/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
2182#define EVERGREEN_CUR_CONTROL 0x1a66
2183# define EVERGREEN_CURSOR_EN (1 << 0)
2184# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
2185# define EVERGREEN_CURSOR_MONO 0
2186# define EVERGREEN_CURSOR_24_1 1
2187# define EVERGREEN_CURSOR_24_8_PRE_MULT 2
2188# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3
2189# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
2190# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
2191# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
2192# define EVERGREEN_CURSOR_URGENT_ALWAYS 0
2193# define EVERGREEN_CURSOR_URGENT_1_8 1
2194# define EVERGREEN_CURSOR_URGENT_1_4 2
2195# define EVERGREEN_CURSOR_URGENT_3_8 3
2196# define EVERGREEN_CURSOR_URGENT_1_2 4
2197#define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a67
2198# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000
2199#define EVERGREEN_CUR_SIZE 0x1a68
2200#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a69
2201#define EVERGREEN_CUR_POSITION 0x1a6a
2202#define EVERGREEN_CUR_HOT_SPOT 0x1a6b
2203#define EVERGREEN_CUR_COLOR1 0x1a6c
2204#define EVERGREEN_CUR_COLOR2 0x1a6d
2205#define EVERGREEN_CUR_UPDATE 0x1a6e
2206# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
2207# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
2208# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
2209# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
2210
2211
2212#define NI_INPUT_CSC_CONTROL 0x1a35
2213# define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
2214# define NI_INPUT_CSC_BYPASS 0
2215# define NI_INPUT_CSC_PROG_COEFF 1
2216# define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2
2217# define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
2218
2219#define NI_OUTPUT_CSC_CONTROL 0x1a3c
2220# define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0)
2221# define NI_OUTPUT_CSC_BYPASS 0
2222# define NI_OUTPUT_CSC_TV_RGB 1
2223# define NI_OUTPUT_CSC_YCBCR_601 2
2224# define NI_OUTPUT_CSC_YCBCR_709 3
2225# define NI_OUTPUT_CSC_PROG_COEFF 4
2226# define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5
2227# define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)
2228
2229#define NI_DEGAMMA_CONTROL 0x1a58
2230# define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
2231# define NI_DEGAMMA_BYPASS 0
2232# define NI_DEGAMMA_SRGB_24 1
2233# define NI_DEGAMMA_XVYCC_222 2
2234# define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
2235# define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
2236# define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)
2237
2238#define NI_GAMUT_REMAP_CONTROL 0x1a59
2239# define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)
2240# define NI_GAMUT_REMAP_BYPASS 0
2241# define NI_GAMUT_REMAP_PROG_COEFF 1
2242# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2
2243# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3
2244# define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4)
2245
2246#define NI_REGAMMA_CONTROL 0x1aa0
2247# define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0)
2248# define NI_REGAMMA_BYPASS 0
2249# define NI_REGAMMA_SRGB_24 1
2250# define NI_REGAMMA_XVYCC_222 2
2251# define NI_REGAMMA_PROG_A 3
2252# define NI_REGAMMA_PROG_B 4
2253# define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)
2254
2255
2256#define NI_PRESCALE_GRPH_CONTROL 0x1a2d
2257# define NI_GRPH_PRESCALE_BYPASS (1 << 4)
2258
2259#define NI_PRESCALE_OVL_CONTROL 0x1a31
2260# define NI_OVL_PRESCALE_BYPASS (1 << 4)
2261
2262#define NI_INPUT_GAMMA_CONTROL 0x1a10
2263# define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
2264# define NI_INPUT_GAMMA_USE_LUT 0
2265# define NI_INPUT_GAMMA_BYPASS 1
2266# define NI_INPUT_GAMMA_SRGB_24 2
2267# define NI_INPUT_GAMMA_XVYCC_222 3
2268# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
2269
2270#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
2271#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
2272#define SRBM_STATUS__IH_BUSY_MASK 0x20000
2273#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
2274
2275#define BLACKOUT_MODE_MASK 0x00000007
2276#define VGA_RENDER_CONTROL 0xC0
2277#define R_000300_VGA_RENDER_CONTROL 0xC0
2278#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
2279#define EVERGREEN_CRTC_STATUS 0x1BA3
2280#define EVERGREEN_CRTC_V_BLANK (1 << 0)
2281#define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4
2282/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
2283#define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d
2284#define EVERGREEN_CRTC_CONTROL 0x1b9c
2285# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
2286# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2287#define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d
2288# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
2289# define EVERGREEN_CRTC_V_BLANK (1 << 0)
2290#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8
2291#define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5
2292#define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd
2293#define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe
2294#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2295#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
2296#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
2297#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
2298#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
2299#define EVERGREEN_GRPH_UPDATE 0x1a11
2300#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4
2301#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
2302#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2303
2304#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
2305#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
2306#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
2307#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
2308#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
2309#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
2310#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
2311#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
2312#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
2313#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
2314#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
2315#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
2316
2317#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000
2318#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19
2319#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff
2320#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0
2321#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000
2322#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc
2323#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000
2324#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18
2325
2326#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7
2327#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0
2328
2329#define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1
2330#define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0
2331#define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2
2332#define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1
2333
2334#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000
2335#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11
2336#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800
2337#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb
2338
2339#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
2340#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
2341#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
2342#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
2343#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
2344#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
2345#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
2346#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
2347#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
2348#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
2349#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
2350#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
2351
2352#define MC_SEQ_MISC0__MT__MASK 0xf0000000
2353#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
2354#define MC_SEQ_MISC0__MT__DDR2 0x20000000
2355#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
2356#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
2357#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
2358#define MC_SEQ_MISC0__MT__HBM 0x60000000
2359#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
2360
2361#define SRBM_STATUS__MCB_BUSY_MASK 0x200
2362#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
2363#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
2364#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
2365#define SRBM_STATUS__MCC_BUSY_MASK 0x800
2366#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
2367#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
2368#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
2369#define SRBM_STATUS__VMC_BUSY_MASK 0x100
2370#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
2371
2372
2373#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
2374#define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2375#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
2376#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2377#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
2378#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
2379#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
2380
2381#define CONFIG_CNTL 0x1509
2382#define CC_DRM_ID_STRAPS 0X1559
2383#define AMDGPU_PCIE_INDEX 0xc
2384#define AMDGPU_PCIE_DATA 0xd
2385
2386#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0x3411
2387#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0x3412
2388#define DMA_MODE 0x342f
2389#define DMA_RB_RPTR_ADDR_HI 0x3407
2390#define DMA_RB_RPTR_ADDR_LO 0x3408
2391#define DMA_BUSY_MASK 0x20
2392#define DMA1_BUSY_MASK 0X40
2393#define SDMA_MAX_INSTANCE 2
2394
2395#define PCIE_BUS_CLK 10000
2396#define TCLK (PCIE_BUS_CLK / 10)
2397#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
2398#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
2399#define PCIE_PORT_INDEX 0xe
2400#define PCIE_PORT_DATA 0xf
2401#define EVERGREEN_PIF_PHY0_INDEX 0x8
2402#define EVERGREEN_PIF_PHY0_DATA 0xc
2403#define EVERGREEN_PIF_PHY1_INDEX 0x10
2404#define EVERGREEN_PIF_PHY1_DATA 0x14
2405
2406#define MC_VM_FB_OFFSET 0x81a
2407
2408#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-05 04:50:10 -0500