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authorDave Airlie <airlied@redhat.com>2015-10-29 19:48:28 -0400
committerDave Airlie <airlied@redhat.com>2015-10-29 19:48:28 -0400
commitf1a04d82585032d906e6a7d5b16d38a369033bd0 (patch)
tree9dfc40edfe73d33f380a78c785a71a49ff77bfa1 /drivers/gpu/drm/amd/amdgpu
parent974e59ba0bc3bcc94d11fce9b34c10af32b5930f (diff)
parented885b210752563b5e90dc0933e262f768ea9fa4 (diff)
Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-next
More amdgpu and radeon stuff for drm-next. Stoney support is the big change. The rest is just bug fixes and code cleanups. The Stoney stuff is pretty low impact with respect to existing chips. * 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: change VM size default to 64GB drm/amdgpu: add Stoney pci ids drm/amdgpu: update the core VI support for Stoney drm/amdgpu: add VCE support for Stoney (v2) drm/amdgpu: add UVD support for Stoney drm/amdgpu: add GFX support for Stoney (v2) drm/amdgpu: add SDMA support for Stoney (v2) drm/amdgpu: add DCE support for Stoney drm/amdgpu: Update SMC/DPM for Stoney drm/amdgpu: add GMC support for Stoney drm/amdgpu: add Stoney chip family drm/amdgpu: fix the broken vm->mutex V2 drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any() drm/amdgpu: remove the exclusive lock drm/amdgpu: remove old lockup detection infrastructure drm: fix trivial typos drm/amdgpu/dce: simplify suspend/resume drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet drm/radeon: Use rdev->gem.mutex to protect hyperz/cmask owners
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c50
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c35
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_smc.c60
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c36
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c412
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c47
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c36
30 files changed, 603 insertions, 345 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3fa1397fd7ae..5c400f4b87fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -345,7 +345,6 @@ struct amdgpu_ring_funcs {
345 /* testing functions */ 345 /* testing functions */
346 int (*test_ring)(struct amdgpu_ring *ring); 346 int (*test_ring)(struct amdgpu_ring *ring);
347 int (*test_ib)(struct amdgpu_ring *ring); 347 int (*test_ib)(struct amdgpu_ring *ring);
348 bool (*is_lockup)(struct amdgpu_ring *ring);
349 /* insert NOP packets */ 348 /* insert NOP packets */
350 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
351}; 350};
@@ -448,8 +447,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
448int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 447int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
449unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 448unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
450 449
451signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, 450signed long amdgpu_fence_wait_any(struct fence **array,
452 struct fence **array,
453 uint32_t count, 451 uint32_t count,
454 bool intr, 452 bool intr,
455 signed long t); 453 signed long t);
@@ -907,8 +905,6 @@ struct amdgpu_ring {
907 unsigned ring_size; 905 unsigned ring_size;
908 unsigned ring_free_dw; 906 unsigned ring_free_dw;
909 int count_dw; 907 int count_dw;
910 atomic_t last_rptr;
911 atomic64_t last_activity;
912 uint64_t gpu_addr; 908 uint64_t gpu_addr;
913 uint32_t align_mask; 909 uint32_t align_mask;
914 uint32_t ptr_mask; 910 uint32_t ptr_mask;
@@ -1230,8 +1226,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring);
1230void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1226void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1231void amdgpu_ring_undo(struct amdgpu_ring *ring); 1227void amdgpu_ring_undo(struct amdgpu_ring *ring);
1232void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1228void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1233void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1234bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1235unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1229unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1236 uint32_t **data); 1230 uint32_t **data);
1237int amdgpu_ring_restore(struct amdgpu_ring *ring, 1231int amdgpu_ring_restore(struct amdgpu_ring *ring,
@@ -1960,7 +1954,6 @@ struct amdgpu_device {
1960 struct device *dev; 1954 struct device *dev;
1961 struct drm_device *ddev; 1955 struct drm_device *ddev;
1962 struct pci_dev *pdev; 1956 struct pci_dev *pdev;
1963 struct rw_semaphore exclusive_lock;
1964 1957
1965 /* ASIC */ 1958 /* ASIC */
1966 enum amd_asic_type asic_type; 1959 enum amd_asic_type asic_type;
@@ -1974,7 +1967,6 @@ struct amdgpu_device {
1974 bool suspend; 1967 bool suspend;
1975 bool need_dma32; 1968 bool need_dma32;
1976 bool accel_working; 1969 bool accel_working;
1977 bool needs_reset;
1978 struct work_struct reset_work; 1970 struct work_struct reset_work;
1979 struct notifier_block acpi_nb; 1971 struct notifier_block acpi_nb;
1980 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1972 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
@@ -2253,7 +2245,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2253#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2245#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2254#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2246#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2255#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2247#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2256#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2257#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2248#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2258#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2249#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2259#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2250#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index baf00617fe90..27ef52847e6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -609,7 +609,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
609 } 609 }
610 } 610 }
611 611
612 mutex_lock(&vm->mutex);
613 r = amdgpu_bo_vm_update_pte(parser, vm); 612 r = amdgpu_bo_vm_update_pte(parser, vm);
614 if (r) { 613 if (r) {
615 goto out; 614 goto out;
@@ -620,7 +619,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
620 parser->filp); 619 parser->filp);
621 620
622out: 621out:
623 mutex_unlock(&vm->mutex);
624 return r; 622 return r;
625} 623}
626 624
@@ -828,15 +826,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
828{ 826{
829 struct amdgpu_device *adev = dev->dev_private; 827 struct amdgpu_device *adev = dev->dev_private;
830 union drm_amdgpu_cs *cs = data; 828 union drm_amdgpu_cs *cs = data;
829 struct amdgpu_fpriv *fpriv = filp->driver_priv;
830 struct amdgpu_vm *vm = &fpriv->vm;
831 struct amdgpu_cs_parser *parser; 831 struct amdgpu_cs_parser *parser;
832 bool reserved_buffers = false; 832 bool reserved_buffers = false;
833 int i, r; 833 int i, r;
834 834
835 down_read(&adev->exclusive_lock); 835 if (!adev->accel_working)
836 if (!adev->accel_working) {
837 up_read(&adev->exclusive_lock);
838 return -EBUSY; 836 return -EBUSY;
839 }
840 837
841 parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); 838 parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
842 if (!parser) 839 if (!parser)
@@ -844,12 +841,11 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
844 r = amdgpu_cs_parser_init(parser, data); 841 r = amdgpu_cs_parser_init(parser, data);
845 if (r) { 842 if (r) {
846 DRM_ERROR("Failed to initialize parser !\n"); 843 DRM_ERROR("Failed to initialize parser !\n");
847 kfree(parser); 844 amdgpu_cs_parser_fini(parser, r, false);
848 up_read(&adev->exclusive_lock);
849 r = amdgpu_cs_handle_lockup(adev, r); 845 r = amdgpu_cs_handle_lockup(adev, r);
850 return r; 846 return r;
851 } 847 }
852 848 mutex_lock(&vm->mutex);
853 r = amdgpu_cs_parser_relocs(parser); 849 r = amdgpu_cs_parser_relocs(parser);
854 if (r == -ENOMEM) 850 if (r == -ENOMEM)
855 DRM_ERROR("Not enough memory for command submission!\n"); 851 DRM_ERROR("Not enough memory for command submission!\n");
@@ -916,14 +912,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
916 912
917 mutex_unlock(&job->job_lock); 913 mutex_unlock(&job->job_lock);
918 amdgpu_cs_parser_fini_late(parser); 914 amdgpu_cs_parser_fini_late(parser);
919 up_read(&adev->exclusive_lock); 915 mutex_unlock(&vm->mutex);
920 return 0; 916 return 0;
921 } 917 }
922 918
923 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; 919 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
924out: 920out:
925 amdgpu_cs_parser_fini(parser, r, reserved_buffers); 921 amdgpu_cs_parser_fini(parser, r, reserved_buffers);
926 up_read(&adev->exclusive_lock); 922 mutex_unlock(&vm->mutex);
927 r = amdgpu_cs_handle_lockup(adev, r); 923 r = amdgpu_cs_handle_lockup(adev, r);
928 return r; 924 return r;
929} 925}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 901a460b2c55..d5b421330145 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -57,6 +57,7 @@ static const char *amdgpu_asic_name[] = {
57 "TONGA", 57 "TONGA",
58 "FIJI", 58 "FIJI",
59 "CARRIZO", 59 "CARRIZO",
60 "STONEY",
60 "LAST", 61 "LAST",
61}; 62};
62 63
@@ -1165,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
1165 case CHIP_TONGA: 1166 case CHIP_TONGA:
1166 case CHIP_FIJI: 1167 case CHIP_FIJI:
1167 case CHIP_CARRIZO: 1168 case CHIP_CARRIZO:
1168 if (adev->asic_type == CHIP_CARRIZO) 1169 case CHIP_STONEY:
1170 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1169 adev->family = AMDGPU_FAMILY_CZ; 1171 adev->family = AMDGPU_FAMILY_CZ;
1170 else 1172 else
1171 adev->family = AMDGPU_FAMILY_VI; 1173 adev->family = AMDGPU_FAMILY_VI;
@@ -1418,7 +1420,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
1418 mutex_init(&adev->gfx.gpu_clock_mutex); 1420 mutex_init(&adev->gfx.gpu_clock_mutex);
1419 mutex_init(&adev->srbm_mutex); 1421 mutex_init(&adev->srbm_mutex);
1420 mutex_init(&adev->grbm_idx_mutex); 1422 mutex_init(&adev->grbm_idx_mutex);
1421 init_rwsem(&adev->exclusive_lock);
1422 mutex_init(&adev->mn_lock); 1423 mutex_init(&adev->mn_lock);
1423 hash_init(adev->mn_hash); 1424 hash_init(adev->mn_hash);
1424 1425
@@ -1814,14 +1815,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
1814 int i, r; 1815 int i, r;
1815 int resched; 1816 int resched;
1816 1817
1817 down_write(&adev->exclusive_lock);
1818
1819 if (!adev->needs_reset) {
1820 up_write(&adev->exclusive_lock);
1821 return 0;
1822 }
1823
1824 adev->needs_reset = false;
1825 atomic_inc(&adev->gpu_reset_counter); 1818 atomic_inc(&adev->gpu_reset_counter);
1826 1819
1827 /* block TTM */ 1820 /* block TTM */
@@ -1885,7 +1878,6 @@ retry:
1885 dev_info(adev->dev, "GPU reset failed\n"); 1878 dev_info(adev->dev, "GPU reset failed\n");
1886 } 1879 }
1887 1880
1888 up_write(&adev->exclusive_lock);
1889 return r; 1881 return r;
1890} 1882}
1891 1883
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index de116398fa49..d747fca59669 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
47 fence = to_amdgpu_fence(*f); 47 fence = to_amdgpu_fence(*f);
48 if (fence) { 48 if (fence) {
49 r = fence_wait(&fence->base, false); 49 r = fence_wait(&fence->base, false);
50 if (r == -EDEADLK) { 50 if (r == -EDEADLK)
51 up_read(&adev->exclusive_lock);
52 r = amdgpu_gpu_reset(adev); 51 r = amdgpu_gpu_reset(adev);
53 down_read(&adev->exclusive_lock);
54 }
55 } else 52 } else
56 r = fence_wait(*f, false); 53 r = fence_wait(*f, false);
57 54
@@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
77 unsigned long flags; 74 unsigned long flags;
78 unsigned i; 75 unsigned i;
79 76
80 down_read(&adev->exclusive_lock);
81 amdgpu_flip_wait_fence(adev, &work->excl); 77 amdgpu_flip_wait_fence(adev, &work->excl);
82 for (i = 0; i < work->shared_count; ++i) 78 for (i = 0; i < work->shared_count; ++i)
83 amdgpu_flip_wait_fence(adev, &work->shared[i]); 79 amdgpu_flip_wait_fence(adev, &work->shared[i]);
@@ -93,7 +89,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
93 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 89 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
94 90
95 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
96 up_read(&adev->exclusive_lock);
97} 92}
98 93
99/* 94/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ef58774b242c..0508c5cd103a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -73,7 +73,7 @@ int amdgpu_hard_reset = 0;
73unsigned amdgpu_ip_block_mask = 0xffffffff; 73unsigned amdgpu_ip_block_mask = 0xffffffff;
74int amdgpu_bapm = -1; 74int amdgpu_bapm = -1;
75int amdgpu_deep_color = 0; 75int amdgpu_deep_color = 0;
76int amdgpu_vm_size = 8; 76int amdgpu_vm_size = 64;
77int amdgpu_vm_block_size = -1; 77int amdgpu_vm_block_size = -1;
78int amdgpu_vm_fault_stop = 0; 78int amdgpu_vm_fault_stop = 0;
79int amdgpu_vm_debug = 0; 79int amdgpu_vm_debug = 0;
@@ -137,7 +137,7 @@ module_param_named(bapm, amdgpu_bapm, int, 0444);
137MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 137MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
138module_param_named(deep_color, amdgpu_deep_color, int, 0444); 138module_param_named(deep_color, amdgpu_deep_color, int, 0444);
139 139
140MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); 140MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
141module_param_named(vm_size, amdgpu_vm_size, int, 0444); 141module_param_named(vm_size, amdgpu_vm_size, int, 0444);
142 142
143MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 143MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
@@ -273,6 +273,8 @@ static struct pci_device_id pciidlist[] = {
273 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 273 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
274 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 274 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
275 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 275 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
276 /* stoney */
277 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
276 278
277 {0, 0, 0} 279 {0, 0, 0}
278}; 280};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index fcad7e060938..003a219943f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -260,27 +260,8 @@ static void amdgpu_fence_check_lockup(struct work_struct *work)
260 lockup_work.work); 260 lockup_work.work);
261 ring = fence_drv->ring; 261 ring = fence_drv->ring;
262 262
263 if (!down_read_trylock(&ring->adev->exclusive_lock)) { 263 if (amdgpu_fence_activity(ring))
264 /* just reschedule the check if a reset is going on */
265 amdgpu_fence_schedule_check(ring);
266 return;
267 }
268
269 if (amdgpu_fence_activity(ring)) {
270 wake_up_all(&ring->fence_drv.fence_queue);
271 }
272 else if (amdgpu_ring_is_lockup(ring)) {
273 /* good news we believe it's a lockup */
274 dev_warn(ring->adev->dev, "GPU lockup (current fence id "
275 "0x%016llx last fence id 0x%016llx on ring %d)\n",
276 (uint64_t)atomic64_read(&fence_drv->last_seq),
277 fence_drv->sync_seq[ring->idx], ring->idx);
278
279 /* remember that we need an reset */
280 ring->adev->needs_reset = true;
281 wake_up_all(&ring->fence_drv.fence_queue); 264 wake_up_all(&ring->fence_drv.fence_queue);
282 }
283 up_read(&ring->adev->exclusive_lock);
284} 265}
285 266
286/** 267/**
@@ -328,18 +309,15 @@ static bool amdgpu_fence_is_signaled(struct fence *f)
328{ 309{
329 struct amdgpu_fence *fence = to_amdgpu_fence(f); 310 struct amdgpu_fence *fence = to_amdgpu_fence(f);
330 struct amdgpu_ring *ring = fence->ring; 311 struct amdgpu_ring *ring = fence->ring;
331 struct amdgpu_device *adev = ring->adev;
332 312
333 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 313 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
334 return true; 314 return true;
335 315
336 if (down_read_trylock(&adev->exclusive_lock)) { 316 amdgpu_fence_process(ring);
337 amdgpu_fence_process(ring); 317
338 up_read(&adev->exclusive_lock); 318 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
319 return true;
339 320
340 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
341 return true;
342 }
343 return false; 321 return false;
344} 322}
345 323
@@ -380,7 +358,6 @@ static bool amdgpu_fence_enable_signaling(struct fence *f)
380 */ 358 */
381static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) 359static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
382{ 360{
383 struct amdgpu_device *adev = ring->adev;
384 bool signaled = false; 361 bool signaled = false;
385 362
386 BUG_ON(!ring); 363 BUG_ON(!ring);
@@ -391,8 +368,7 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
391 return 0; 368 return 0;
392 369
393 wait_event(ring->fence_drv.fence_queue, ( 370 wait_event(ring->fence_drv.fence_queue, (
394 (signaled = amdgpu_fence_seq_signaled(ring, seq)) 371 (signaled = amdgpu_fence_seq_signaled(ring, seq))));
395 || adev->needs_reset));
396 372
397 if (signaled) 373 if (signaled)
398 return 0; 374 return 0;
@@ -881,16 +857,12 @@ static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
881static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, 857static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
882 signed long t) 858 signed long t)
883{ 859{
884 struct amdgpu_fence *fence = to_amdgpu_fence(f); 860 return amdgpu_fence_wait_any(&f, 1, intr, t);
885 struct amdgpu_device *adev = fence->ring->adev;
886
887 return amdgpu_fence_wait_any(adev, &f, 1, intr, t);
888} 861}
889 862
890/** 863/**
891 * Wait the fence array with timeout 864 * Wait the fence array with timeout
892 * 865 *
893 * @adev: amdgpu device
894 * @array: the fence array with amdgpu fence pointer 866 * @array: the fence array with amdgpu fence pointer
895 * @count: the number of the fence array 867 * @count: the number of the fence array
896 * @intr: when sleep, set the current task interruptable or not 868 * @intr: when sleep, set the current task interruptable or not
@@ -898,8 +870,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
898 * 870 *
899 * It will return when any fence is signaled or timeout. 871 * It will return when any fence is signaled or timeout.
900 */ 872 */
901signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, 873signed long amdgpu_fence_wait_any(struct fence **array, uint32_t count,
902 struct fence **array, uint32_t count,
903 bool intr, signed long t) 874 bool intr, signed long t)
904{ 875{
905 struct amdgpu_wait_cb *cb; 876 struct amdgpu_wait_cb *cb;
@@ -939,11 +910,6 @@ signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
939 if (amdgpu_test_signaled_any(array, count)) 910 if (amdgpu_test_signaled_any(array, count))
940 break; 911 break;
941 912
942 if (adev->needs_reset) {
943 t = -EDEADLK;
944 break;
945 }
946
947 t = schedule_timeout(t); 913 t = schedule_timeout(t);
948 914
949 if (t > 0 && intr && signal_pending(current)) 915 if (t > 0 && intr && signal_pending(current))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7297ca3a0ba7..087332858853 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -115,9 +115,10 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
115 struct amdgpu_vm *vm = &fpriv->vm; 115 struct amdgpu_vm *vm = &fpriv->vm;
116 struct amdgpu_bo_va *bo_va; 116 struct amdgpu_bo_va *bo_va;
117 int r; 117 int r;
118 118 mutex_lock(&vm->mutex);
119 r = amdgpu_bo_reserve(rbo, false); 119 r = amdgpu_bo_reserve(rbo, false);
120 if (r) { 120 if (r) {
121 mutex_unlock(&vm->mutex);
121 return r; 122 return r;
122 } 123 }
123 124
@@ -128,7 +129,7 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
128 ++bo_va->ref_count; 129 ++bo_va->ref_count;
129 } 130 }
130 amdgpu_bo_unreserve(rbo); 131 amdgpu_bo_unreserve(rbo);
131 132 mutex_unlock(&vm->mutex);
132 return 0; 133 return 0;
133} 134}
134 135
@@ -141,9 +142,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
141 struct amdgpu_vm *vm = &fpriv->vm; 142 struct amdgpu_vm *vm = &fpriv->vm;
142 struct amdgpu_bo_va *bo_va; 143 struct amdgpu_bo_va *bo_va;
143 int r; 144 int r;
144 145 mutex_lock(&vm->mutex);
145 r = amdgpu_bo_reserve(rbo, true); 146 r = amdgpu_bo_reserve(rbo, true);
146 if (r) { 147 if (r) {
148 mutex_unlock(&vm->mutex);
147 dev_err(adev->dev, "leaking bo va because " 149 dev_err(adev->dev, "leaking bo va because "
148 "we fail to reserve bo (%d)\n", r); 150 "we fail to reserve bo (%d)\n", r);
149 return; 151 return;
@@ -155,6 +157,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
155 } 157 }
156 } 158 }
157 amdgpu_bo_unreserve(rbo); 159 amdgpu_bo_unreserve(rbo);
160 mutex_unlock(&vm->mutex);
158} 161}
159 162
160static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 163static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
@@ -181,7 +184,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
181 bool kernel = false; 184 bool kernel = false;
182 int r; 185 int r;
183 186
184 down_read(&adev->exclusive_lock);
185 /* create a gem object to contain this object in */ 187 /* create a gem object to contain this object in */
186 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 188 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
187 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 189 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -214,11 +216,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
214 216
215 memset(args, 0, sizeof(*args)); 217 memset(args, 0, sizeof(*args));
216 args->out.handle = handle; 218 args->out.handle = handle;
217 up_read(&adev->exclusive_lock);
218 return 0; 219 return 0;
219 220
220error_unlock: 221error_unlock:
221 up_read(&adev->exclusive_lock);
222 r = amdgpu_gem_handle_lockup(adev, r); 222 r = amdgpu_gem_handle_lockup(adev, r);
223 return r; 223 return r;
224} 224}
@@ -250,8 +250,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
250 return -EACCES; 250 return -EACCES;
251 } 251 }
252 252
253 down_read(&adev->exclusive_lock);
254
255 /* create a gem object to contain this object in */ 253 /* create a gem object to contain this object in */
256 r = amdgpu_gem_object_create(adev, args->size, 0, 254 r = amdgpu_gem_object_create(adev, args->size, 0,
257 AMDGPU_GEM_DOMAIN_CPU, 0, 255 AMDGPU_GEM_DOMAIN_CPU, 0,
@@ -293,14 +291,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
293 goto handle_lockup; 291 goto handle_lockup;
294 292
295 args->handle = handle; 293 args->handle = handle;
296 up_read(&adev->exclusive_lock);
297 return 0; 294 return 0;
298 295
299release_object: 296release_object:
300 drm_gem_object_unreference_unlocked(gobj); 297 drm_gem_object_unreference_unlocked(gobj);
301 298
302handle_lockup: 299handle_lockup:
303 up_read(&adev->exclusive_lock);
304 r = amdgpu_gem_handle_lockup(adev, r); 300 r = amdgpu_gem_handle_lockup(adev, r);
305 301
306 return r; 302 return r;
@@ -488,18 +484,13 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
488 goto error_unreserve; 484 goto error_unreserve;
489 } 485 }
490 486
491 mutex_lock(&bo_va->vm->mutex);
492 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 487 r = amdgpu_vm_clear_freed(adev, bo_va->vm);
493 if (r) 488 if (r)
494 goto error_unlock; 489 goto error_unreserve;
495
496 490
497 if (operation == AMDGPU_VA_OP_MAP) 491 if (operation == AMDGPU_VA_OP_MAP)
498 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 492 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
499 493
500error_unlock:
501 mutex_unlock(&bo_va->vm->mutex);
502
503error_unreserve: 494error_unreserve:
504 ttm_eu_backoff_reservation(&ticket, &list); 495 ttm_eu_backoff_reservation(&ticket, &list);
505 496
@@ -556,10 +547,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
556 gobj = drm_gem_object_lookup(dev, filp, args->handle); 547 gobj = drm_gem_object_lookup(dev, filp, args->handle);
557 if (gobj == NULL) 548 if (gobj == NULL)
558 return -ENOENT; 549 return -ENOENT;
559 550 mutex_lock(&fpriv->vm.mutex);
560 rbo = gem_to_amdgpu_bo(gobj); 551 rbo = gem_to_amdgpu_bo(gobj);
561 r = amdgpu_bo_reserve(rbo, false); 552 r = amdgpu_bo_reserve(rbo, false);
562 if (r) { 553 if (r) {
554 mutex_unlock(&fpriv->vm.mutex);
563 drm_gem_object_unreference_unlocked(gobj); 555 drm_gem_object_unreference_unlocked(gobj);
564 return r; 556 return r;
565 } 557 }
@@ -567,6 +559,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
567 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 559 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
568 if (!bo_va) { 560 if (!bo_va) {
569 amdgpu_bo_unreserve(rbo); 561 amdgpu_bo_unreserve(rbo);
562 mutex_unlock(&fpriv->vm.mutex);
570 return -ENOENT; 563 return -ENOENT;
571 } 564 }
572 565
@@ -591,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
591 584
592 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 585 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
593 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 586 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
594 587 mutex_unlock(&fpriv->vm.mutex);
595 drm_gem_object_unreference_unlocked(gobj); 588 drm_gem_object_unreference_unlocked(gobj);
596 return r; 589 return r;
597} 590}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index c439735ee670..aad4c1c69448 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -298,7 +298,6 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
298 r = amdgpu_ring_test_ib(ring); 298 r = amdgpu_ring_test_ib(ring);
299 if (r) { 299 if (r) {
300 ring->ready = false; 300 ring->ready = false;
301 adev->needs_reset = false;
302 301
303 if (ring == &adev->gfx.gfx_ring[0]) { 302 if (ring == &adev->gfx.gfx_ring[0]) {
304 /* oh, oh, that's really bad */ 303 /* oh, oh, that's really bad */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index b13a74b273a6..b2df348aa223 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -67,8 +67,6 @@ void amdgpu_ring_free_size(struct amdgpu_ring *ring)
67 if (!ring->ring_free_dw) { 67 if (!ring->ring_free_dw) {
68 /* this is an empty ring */ 68 /* this is an empty ring */
69 ring->ring_free_dw = ring->ring_size / 4; 69 ring->ring_free_dw = ring->ring_size / 4;
70 /* update lockup info to avoid false positive */
71 amdgpu_ring_lockup_update(ring);
72 } 70 }
73} 71}
74 72
@@ -209,46 +207,6 @@ void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring)
209} 207}
210 208
211/** 209/**
212 * amdgpu_ring_lockup_update - update lockup variables
213 *
214 * @ring: amdgpu_ring structure holding ring information
215 *
216 * Update the last rptr value and timestamp (all asics).
217 */
218void amdgpu_ring_lockup_update(struct amdgpu_ring *ring)
219{
220 atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring));
221 atomic64_set(&ring->last_activity, jiffies_64);
222}
223
224/**
225 * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information
226 * @ring: amdgpu_ring structure holding ring information
227 *
228 */
229bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring)
230{
231 uint32_t rptr = amdgpu_ring_get_rptr(ring);
232 uint64_t last = atomic64_read(&ring->last_activity);
233 uint64_t elapsed;
234
235 if (rptr != atomic_read(&ring->last_rptr)) {
236 /* ring is still working, no lockup */
237 amdgpu_ring_lockup_update(ring);
238 return false;
239 }
240
241 elapsed = jiffies_to_msecs(jiffies_64 - last);
242 if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) {
243 dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n",
244 ring->idx, elapsed);
245 return true;
246 }
247 /* give a chance to the GPU ... */
248 return false;
249}
250
251/**
252 * amdgpu_ring_backup - Back up the content of a ring 210 * amdgpu_ring_backup - Back up the content of a ring
253 * 211 *
254 * @ring: the ring we want to back up 212 * @ring: the ring we want to back up
@@ -436,7 +394,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
436 if (amdgpu_debugfs_ring_init(adev, ring)) { 394 if (amdgpu_debugfs_ring_init(adev, ring)) {
437 DRM_ERROR("Failed to register debugfs file for rings !\n"); 395 DRM_ERROR("Failed to register debugfs file for rings !\n");
438 } 396 }
439 amdgpu_ring_lockup_update(ring);
440 return 0; 397 return 0;
441} 398}
442 399
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index e90712443fe9..5cb27d525e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -372,7 +372,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev,
372 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries)); 372 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
373 373
374 spin_unlock(&sa_manager->wq.lock); 374 spin_unlock(&sa_manager->wq.lock);
375 t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS, 375 t = amdgpu_fence_wait_any(fences, AMDGPU_MAX_RINGS,
376 false, MAX_SCHEDULE_TIMEOUT); 376 false, MAX_SCHEDULE_TIMEOUT);
377 r = (t > 0) ? 0 : t; 377 r = (t > 0) ? 0 : t;
378 spin_lock(&sa_manager->wq.lock); 378 spin_lock(&sa_manager->wq.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d0312364d950..53f987aeeacf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -53,6 +53,7 @@
53#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 53#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 54#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 55#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
56#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
56 57
57/** 58/**
58 * amdgpu_uvd_cs_ctx - Command submission parser context 59 * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -83,6 +84,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS);
83MODULE_FIRMWARE(FIRMWARE_TONGA); 84MODULE_FIRMWARE(FIRMWARE_TONGA);
84MODULE_FIRMWARE(FIRMWARE_CARRIZO); 85MODULE_FIRMWARE(FIRMWARE_CARRIZO);
85MODULE_FIRMWARE(FIRMWARE_FIJI); 86MODULE_FIRMWARE(FIRMWARE_FIJI);
87MODULE_FIRMWARE(FIRMWARE_STONEY);
86 88
87static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); 89static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
88static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 90static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
@@ -124,6 +126,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
124 case CHIP_CARRIZO: 126 case CHIP_CARRIZO:
125 fw_name = FIRMWARE_CARRIZO; 127 fw_name = FIRMWARE_CARRIZO;
126 break; 128 break;
129 case CHIP_STONEY:
130 fw_name = FIRMWARE_STONEY;
131 break;
127 default: 132 default:
128 return -EINVAL; 133 return -EINVAL;
129 } 134 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 74f2038ac747..03f0c3bae516 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -49,6 +49,7 @@
49#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" 49#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" 50#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51#define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" 51#define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
52 53
53#ifdef CONFIG_DRM_AMDGPU_CIK 54#ifdef CONFIG_DRM_AMDGPU_CIK
54MODULE_FIRMWARE(FIRMWARE_BONAIRE); 55MODULE_FIRMWARE(FIRMWARE_BONAIRE);
@@ -60,6 +61,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS);
60MODULE_FIRMWARE(FIRMWARE_TONGA); 61MODULE_FIRMWARE(FIRMWARE_TONGA);
61MODULE_FIRMWARE(FIRMWARE_CARRIZO); 62MODULE_FIRMWARE(FIRMWARE_CARRIZO);
62MODULE_FIRMWARE(FIRMWARE_FIJI); 63MODULE_FIRMWARE(FIRMWARE_FIJI);
64MODULE_FIRMWARE(FIRMWARE_STONEY);
63 65
64static void amdgpu_vce_idle_work_handler(struct work_struct *work); 66static void amdgpu_vce_idle_work_handler(struct work_struct *work);
65 67
@@ -106,6 +108,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
106 case CHIP_FIJI: 108 case CHIP_FIJI:
107 fw_name = FIRMWARE_FIJI; 109 fw_name = FIRMWARE_FIJI;
108 break; 110 break;
111 case CHIP_STONEY:
112 fw_name = FIRMWARE_STONEY;
113 break;
109 114
110 default: 115 default:
111 return -EINVAL; 116 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 644fd9b8591f..ff26e330ccd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -90,11 +90,9 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
90 struct amdgpu_bo_list_entry *list; 90 struct amdgpu_bo_list_entry *list;
91 unsigned i, idx; 91 unsigned i, idx;
92 92
93 mutex_lock(&vm->mutex);
94 list = drm_malloc_ab(vm->max_pde_used + 2, 93 list = drm_malloc_ab(vm->max_pde_used + 2,
95 sizeof(struct amdgpu_bo_list_entry)); 94 sizeof(struct amdgpu_bo_list_entry));
96 if (!list) { 95 if (!list) {
97 mutex_unlock(&vm->mutex);
98 return NULL; 96 return NULL;
99 } 97 }
100 98
@@ -119,7 +117,6 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
119 list[idx].tv.shared = true; 117 list[idx].tv.shared = true;
120 list_add(&list[idx++].tv.head, head); 118 list_add(&list[idx++].tv.head, head);
121 } 119 }
122 mutex_unlock(&vm->mutex);
123 120
124 return list; 121 return list;
125} 122}
@@ -972,9 +969,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
972 INIT_LIST_HEAD(&bo_va->invalids); 969 INIT_LIST_HEAD(&bo_va->invalids);
973 INIT_LIST_HEAD(&bo_va->vm_status); 970 INIT_LIST_HEAD(&bo_va->vm_status);
974 971
975 mutex_lock(&vm->mutex);
976 list_add_tail(&bo_va->bo_list, &bo->va); 972 list_add_tail(&bo_va->bo_list, &bo->va);
977 mutex_unlock(&vm->mutex);
978 973
979 return bo_va; 974 return bo_va;
980} 975}
@@ -1027,8 +1022,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1027 return -EINVAL; 1022 return -EINVAL;
1028 } 1023 }
1029 1024
1030 mutex_lock(&vm->mutex);
1031
1032 saddr /= AMDGPU_GPU_PAGE_SIZE; 1025 saddr /= AMDGPU_GPU_PAGE_SIZE;
1033 eaddr /= AMDGPU_GPU_PAGE_SIZE; 1026 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1034 1027
@@ -1042,14 +1035,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1042 tmp->it.start, tmp->it.last + 1); 1035 tmp->it.start, tmp->it.last + 1);
1043 amdgpu_bo_unreserve(bo_va->bo); 1036 amdgpu_bo_unreserve(bo_va->bo);
1044 r = -EINVAL; 1037 r = -EINVAL;
1045 goto error_unlock; 1038 goto error;
1046 } 1039 }
1047 1040
1048 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); 1041 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1049 if (!mapping) { 1042 if (!mapping) {
1050 amdgpu_bo_unreserve(bo_va->bo); 1043 amdgpu_bo_unreserve(bo_va->bo);
1051 r = -ENOMEM; 1044 r = -ENOMEM;
1052 goto error_unlock; 1045 goto error;
1053 } 1046 }
1054 1047
1055 INIT_LIST_HEAD(&mapping->list); 1048 INIT_LIST_HEAD(&mapping->list);
@@ -1081,9 +1074,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1081 if (vm->page_tables[pt_idx].bo) 1074 if (vm->page_tables[pt_idx].bo)
1082 continue; 1075 continue;
1083 1076
1084 /* drop mutex to allocate and clear page table */
1085 mutex_unlock(&vm->mutex);
1086
1087 ww_mutex_lock(&resv->lock, NULL); 1077 ww_mutex_lock(&resv->lock, NULL);
1088 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, 1078 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1089 AMDGPU_GPU_PAGE_SIZE, true, 1079 AMDGPU_GPU_PAGE_SIZE, true,
@@ -1100,32 +1090,19 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1100 goto error_free; 1090 goto error_free;
1101 } 1091 }
1102 1092
1103 /* aquire mutex again */
1104 mutex_lock(&vm->mutex);
1105 if (vm->page_tables[pt_idx].bo) {
1106 /* someone else allocated the pt in the meantime */
1107 mutex_unlock(&vm->mutex);
1108 amdgpu_bo_unref(&pt);
1109 mutex_lock(&vm->mutex);
1110 continue;
1111 }
1112
1113 vm->page_tables[pt_idx].addr = 0; 1093 vm->page_tables[pt_idx].addr = 0;
1114 vm->page_tables[pt_idx].bo = pt; 1094 vm->page_tables[pt_idx].bo = pt;
1115 } 1095 }
1116 1096
1117 mutex_unlock(&vm->mutex);
1118 return 0; 1097 return 0;
1119 1098
1120error_free: 1099error_free:
1121 mutex_lock(&vm->mutex);
1122 list_del(&mapping->list); 1100 list_del(&mapping->list);
1123 interval_tree_remove(&mapping->it, &vm->va); 1101 interval_tree_remove(&mapping->it, &vm->va);
1124 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1102 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1125 kfree(mapping); 1103 kfree(mapping);
1126 1104
1127error_unlock: 1105error:
1128 mutex_unlock(&vm->mutex);
1129 return r; 1106 return r;
1130} 1107}
1131 1108
@@ -1170,7 +1147,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1170 } 1147 }
1171 } 1148 }
1172 1149
1173 mutex_lock(&vm->mutex);
1174 list_del(&mapping->list); 1150 list_del(&mapping->list);
1175 interval_tree_remove(&mapping->it, &vm->va); 1151 interval_tree_remove(&mapping->it, &vm->va);
1176 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1152 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
@@ -1179,7 +1155,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1179 list_add(&mapping->list, &vm->freed); 1155 list_add(&mapping->list, &vm->freed);
1180 else 1156 else
1181 kfree(mapping); 1157 kfree(mapping);
1182 mutex_unlock(&vm->mutex);
1183 amdgpu_bo_unreserve(bo_va->bo); 1158 amdgpu_bo_unreserve(bo_va->bo);
1184 1159
1185 return 0; 1160 return 0;
@@ -1203,8 +1178,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1203 1178
1204 list_del(&bo_va->bo_list); 1179 list_del(&bo_va->bo_list);
1205 1180
1206 mutex_lock(&vm->mutex);
1207
1208 spin_lock(&vm->status_lock); 1181 spin_lock(&vm->status_lock);
1209 list_del(&bo_va->vm_status); 1182 list_del(&bo_va->vm_status);
1210 spin_unlock(&vm->status_lock); 1183 spin_unlock(&vm->status_lock);
@@ -1223,8 +1196,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1223 1196
1224 fence_put(bo_va->last_pt_update); 1197 fence_put(bo_va->last_pt_update);
1225 kfree(bo_va); 1198 kfree(bo_va);
1226
1227 mutex_unlock(&vm->mutex);
1228} 1199}
1229 1200
1230/** 1201/**
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 814598e76c98..5f712ceddf08 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1290,24 +1290,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = {
1290 .set_powergating_state = cik_sdma_set_powergating_state, 1290 .set_powergating_state = cik_sdma_set_powergating_state,
1291}; 1291};
1292 1292
1293/**
1294 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1295 *
1296 * @ring: amdgpu_ring structure holding ring information
1297 *
1298 * Check if the async DMA engine is locked up (CIK).
1299 * Returns true if the engine appears to be locked up, false if not.
1300 */
1301static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
1302{
1303
1304 if (cik_sdma_is_idle(ring->adev)) {
1305 amdgpu_ring_lockup_update(ring);
1306 return false;
1307 }
1308 return amdgpu_ring_test_lockup(ring);
1309}
1310
1311static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1293static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1312 .get_rptr = cik_sdma_ring_get_rptr, 1294 .get_rptr = cik_sdma_ring_get_rptr,
1313 .get_wptr = cik_sdma_ring_get_wptr, 1295 .get_wptr = cik_sdma_ring_get_wptr,
@@ -1320,7 +1302,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1320 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1302 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1321 .test_ring = cik_sdma_ring_test_ring, 1303 .test_ring = cik_sdma_ring_test_ring,
1322 .test_ib = cik_sdma_ring_test_ib, 1304 .test_ib = cik_sdma_ring_test_ib,
1323 .is_lockup = cik_sdma_ring_is_lockup,
1324 .insert_nop = cik_sdma_ring_insert_nop, 1305 .insert_nop = cik_sdma_ring_insert_nop,
1325}; 1306};
1326 1307
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 2e3373ed4c94..8035d4d6a4f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -1264,6 +1264,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1264 1264
1265static int cz_dpm_enable(struct amdgpu_device *adev) 1265static int cz_dpm_enable(struct amdgpu_device *adev)
1266{ 1266{
1267 const char *chip_name;
1267 int ret = 0; 1268 int ret = 0;
1268 1269
1269 /* renable will hang up SMU, so check first */ 1270 /* renable will hang up SMU, so check first */
@@ -1272,21 +1273,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev)
1272 1273
1273 cz_program_voting_clients(adev); 1274 cz_program_voting_clients(adev);
1274 1275
1276 switch (adev->asic_type) {
1277 case CHIP_CARRIZO:
1278 chip_name = "carrizo";
1279 break;
1280 case CHIP_STONEY:
1281 chip_name = "stoney";
1282 break;
1283 default:
1284 BUG();
1285 }
1286
1287
1275 ret = cz_start_dpm(adev); 1288 ret = cz_start_dpm(adev);
1276 if (ret) { 1289 if (ret) {
1277 DRM_ERROR("Carrizo DPM enable failed\n"); 1290 DRM_ERROR("%s DPM enable failed\n", chip_name);
1278 return -EINVAL; 1291 return -EINVAL;
1279 } 1292 }
1280 1293
1281 ret = cz_program_bootup_state(adev); 1294 ret = cz_program_bootup_state(adev);
1282 if (ret) { 1295 if (ret) {
1283 DRM_ERROR("Carrizo bootup state program failed\n"); 1296 DRM_ERROR("%s bootup state program failed\n", chip_name);
1284 return -EINVAL; 1297 return -EINVAL;
1285 } 1298 }
1286 1299
1287 ret = cz_enable_didt(adev, true); 1300 ret = cz_enable_didt(adev, true);
1288 if (ret) { 1301 if (ret) {
1289 DRM_ERROR("Carrizo enable di/dt failed\n"); 1302 DRM_ERROR("%s enable di/dt failed\n", chip_name);
1290 return -EINVAL; 1303 return -EINVAL;
1291 } 1304 }
1292 1305
@@ -1353,7 +1366,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
1353 1366
1354 ret = cz_enable_didt(adev, false); 1367 ret = cz_enable_didt(adev, false);
1355 if (ret) { 1368 if (ret) {
1356 DRM_ERROR("Carrizo disable di/dt failed\n"); 1369 DRM_ERROR("disable di/dt failed\n");
1357 return -EINVAL; 1370 return -EINVAL;
1358 } 1371 }
1359 1372
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
index e33180d3314a..ac7fee7b7eca 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
@@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev)
312 UCODE_ID_CP_MEC_JT1_MASK | 312 UCODE_ID_CP_MEC_JT1_MASK |
313 UCODE_ID_CP_MEC_JT2_MASK; 313 UCODE_ID_CP_MEC_JT2_MASK;
314 314
315 if (adev->asic_type == CHIP_STONEY)
316 fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
317
315 cz_smu_request_load_fw(adev); 318 cz_smu_request_load_fw(adev);
316 ret = cz_smu_check_fw_load_finish(adev, fw_to_check); 319 ret = cz_smu_check_fw_load_finish(adev, fw_to_check);
317 if (ret) 320 if (ret)
318 return ret; 321 return ret;
319 322
320 /* manually load MEC firmware for CZ */ 323 /* manually load MEC firmware for CZ */
321 if (adev->asic_type == CHIP_CARRIZO) { 324 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
322 ret = cz_load_mec_firmware(adev); 325 ret = cz_load_mec_firmware(adev);
323 if (ret) { 326 if (ret) {
324 dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret); 327 dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
@@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev)
336 AMDGPU_CPMEC2_UCODE_LOADED | 339 AMDGPU_CPMEC2_UCODE_LOADED |
337 AMDGPU_CPRLC_UCODE_LOADED; 340 AMDGPU_CPRLC_UCODE_LOADED;
338 341
342 if (adev->asic_type == CHIP_STONEY)
343 adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED);
344
339 return ret; 345 return ret;
340} 346}
341 347
@@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev)
601 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); 607 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
602 cz_smu_populate_single_ucode_load_task(adev, 608 cz_smu_populate_single_ucode_load_task(adev,
603 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); 609 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
604 cz_smu_populate_single_ucode_load_task(adev, 610 if (adev->asic_type == CHIP_STONEY) {
611 cz_smu_populate_single_ucode_load_task(adev,
612 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
613 } else {
614 cz_smu_populate_single_ucode_load_task(adev,
605 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); 615 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
616 }
606 cz_smu_populate_single_ucode_load_task(adev, 617 cz_smu_populate_single_ucode_load_task(adev,
607 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); 618 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
608 } 619 }
@@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
642 if (adev->firmware.smu_load) { 653 if (adev->firmware.smu_load) {
643 cz_smu_populate_single_ucode_load_task(adev, 654 cz_smu_populate_single_ucode_load_task(adev,
644 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); 655 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
645 cz_smu_populate_single_ucode_load_task(adev, 656 if (adev->asic_type == CHIP_STONEY) {
657 cz_smu_populate_single_ucode_load_task(adev,
658 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
659 } else {
660 cz_smu_populate_single_ucode_load_task(adev,
646 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); 661 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
662 }
647 cz_smu_populate_single_ucode_load_task(adev, 663 cz_smu_populate_single_ucode_load_task(adev,
648 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); 664 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
649 cz_smu_populate_single_ucode_load_task(adev, 665 cz_smu_populate_single_ucode_load_task(adev,
@@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
652 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); 668 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
653 cz_smu_populate_single_ucode_load_task(adev, 669 cz_smu_populate_single_ucode_load_task(adev,
654 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); 670 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
655 cz_smu_populate_single_ucode_load_task(adev, 671 if (adev->asic_type == CHIP_STONEY) {
672 cz_smu_populate_single_ucode_load_task(adev,
673 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
674 } else {
675 cz_smu_populate_single_ucode_load_task(adev,
656 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); 676 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
677 }
657 cz_smu_populate_single_ucode_load_task(adev, 678 cz_smu_populate_single_ucode_load_task(adev,
658 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); 679 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
659 } 680 }
@@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev)
888 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, 909 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
889 &priv->driver_buffer[priv->driver_buffer_length++])) 910 &priv->driver_buffer[priv->driver_buffer_length++]))
890 goto smu_init_failed; 911 goto smu_init_failed;
891 if (cz_smu_populate_single_firmware_entry(adev, 912
892 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, 913 if (adev->asic_type == CHIP_STONEY) {
893 &priv->driver_buffer[priv->driver_buffer_length++])) 914 if (cz_smu_populate_single_firmware_entry(adev,
894 goto smu_init_failed; 915 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
916 &priv->driver_buffer[priv->driver_buffer_length++]))
917 goto smu_init_failed;
918 } else {
919 if (cz_smu_populate_single_firmware_entry(adev,
920 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
921 &priv->driver_buffer[priv->driver_buffer_length++]))
922 goto smu_init_failed;
923 }
895 if (cz_smu_populate_single_firmware_entry(adev, 924 if (cz_smu_populate_single_firmware_entry(adev,
896 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, 925 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
897 &priv->driver_buffer[priv->driver_buffer_length++])) 926 &priv->driver_buffer[priv->driver_buffer_length++]))
@@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev)
908 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, 937 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
909 &priv->driver_buffer[priv->driver_buffer_length++])) 938 &priv->driver_buffer[priv->driver_buffer_length++]))
910 goto smu_init_failed; 939 goto smu_init_failed;
911 if (cz_smu_populate_single_firmware_entry(adev, 940 if (adev->asic_type == CHIP_STONEY) {
912 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, 941 if (cz_smu_populate_single_firmware_entry(adev,
913 &priv->driver_buffer[priv->driver_buffer_length++])) 942 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
914 goto smu_init_failed; 943 &priv->driver_buffer[priv->driver_buffer_length++]))
944 goto smu_init_failed;
945 } else {
946 if (cz_smu_populate_single_firmware_entry(adev,
947 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
948 &priv->driver_buffer[priv->driver_buffer_length++]))
949 goto smu_init_failed;
950 }
915 if (cz_smu_populate_single_firmware_entry(adev, 951 if (cz_smu_populate_single_firmware_entry(adev,
916 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, 952 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
917 &priv->driver_buffer[priv->driver_buffer_length++])) 953 &priv->driver_buffer[priv->driver_buffer_length++]))
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 37073930e2c9..a6ea2d8e85df 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3086,22 +3086,18 @@ static int dce_v10_0_suspend(void *handle)
3086 3086
3087 amdgpu_atombios_scratch_regs_save(adev); 3087 amdgpu_atombios_scratch_regs_save(adev);
3088 3088
3089 dce_v10_0_hpd_fini(adev); 3089 return dce_v10_0_hw_fini(handle);
3090
3091 return 0;
3092} 3090}
3093 3091
3094static int dce_v10_0_resume(void *handle) 3092static int dce_v10_0_resume(void *handle)
3095{ 3093{
3096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3095 int ret;
3097 3096
3098 dce_v10_0_init_golden_registers(adev); 3097 ret = dce_v10_0_hw_init(handle);
3099 3098
3100 amdgpu_atombios_scratch_regs_restore(adev); 3099 amdgpu_atombios_scratch_regs_restore(adev);
3101 3100
3102 /* init dig PHYs, disp eng pll */
3103 amdgpu_atombios_encoder_init_dig(adev);
3104 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3105 /* turn on the BL */ 3101 /* turn on the BL */
3106 if (adev->mode_info.bl_encoder) { 3102 if (adev->mode_info.bl_encoder) {
3107 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3103 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3110,10 +3106,7 @@ static int dce_v10_0_resume(void *handle)
3110 bl_level); 3106 bl_level);
3111 } 3107 }
3112 3108
3113 /* initialize hpd */ 3109 return ret;
3114 dce_v10_0_hpd_init(adev);
3115
3116 return 0;
3117} 3110}
3118 3111
3119static bool dce_v10_0_is_idle(void *handle) 3112static bool dce_v10_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 5be83a3f0192..784afb5978ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] =
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127}; 127};
128 128
129static const u32 stoney_golden_settings_a11[] =
130{
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
133};
134
135
129static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 136static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
130{ 137{
131 switch (adev->asic_type) { 138 switch (adev->asic_type) {
@@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
137 cz_golden_settings_a11, 144 cz_golden_settings_a11,
138 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 145 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
139 break; 146 break;
147 case CHIP_STONEY:
148 amdgpu_program_register_sequence(adev,
149 stoney_golden_settings_a11,
150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
151 break;
140 default: 152 default:
141 break; 153 break;
142 } 154 }
@@ -2425,7 +2437,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2425 2437
2426 /* XXX need to determine what plls are available on each DCE11 part */ 2438 /* XXX need to determine what plls are available on each DCE11 part */
2427 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2439 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2428 if (adev->asic_type == CHIP_CARRIZO) { 2440 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2429 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2441 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2430 return ATOM_PPLL1; 2442 return ATOM_PPLL1;
2431 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2443 if (!(pll_in_use & (1 << ATOM_PPLL0)))
@@ -2930,6 +2942,11 @@ static int dce_v11_0_early_init(void *handle)
2930 adev->mode_info.num_hpd = 6; 2942 adev->mode_info.num_hpd = 6;
2931 adev->mode_info.num_dig = 9; 2943 adev->mode_info.num_dig = 9;
2932 break; 2944 break;
2945 case CHIP_STONEY:
2946 adev->mode_info.num_crtc = 2;
2947 adev->mode_info.num_hpd = 6;
2948 adev->mode_info.num_dig = 9;
2949 break;
2933 default: 2950 default:
2934 /* FIXME: not supported yet */ 2951 /* FIXME: not supported yet */
2935 return -EINVAL; 2952 return -EINVAL;
@@ -3028,6 +3045,7 @@ static int dce_v11_0_hw_init(void *handle)
3028 dce_v11_0_init_golden_registers(adev); 3045 dce_v11_0_init_golden_registers(adev);
3029 3046
3030 /* init dig PHYs, disp eng pll */ 3047 /* init dig PHYs, disp eng pll */
3048 amdgpu_atombios_crtc_powergate_init(adev);
3031 amdgpu_atombios_encoder_init_dig(adev); 3049 amdgpu_atombios_encoder_init_dig(adev);
3032 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3050 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3033 3051
@@ -3061,23 +3079,18 @@ static int dce_v11_0_suspend(void *handle)
3061 3079
3062 amdgpu_atombios_scratch_regs_save(adev); 3080 amdgpu_atombios_scratch_regs_save(adev);
3063 3081
3064 dce_v11_0_hpd_fini(adev); 3082 return dce_v11_0_hw_fini(handle);
3065
3066 return 0;
3067} 3083}
3068 3084
3069static int dce_v11_0_resume(void *handle) 3085static int dce_v11_0_resume(void *handle)
3070{ 3086{
3071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3088 int ret;
3072 3089
3073 dce_v11_0_init_golden_registers(adev); 3090 ret = dce_v11_0_hw_init(handle);
3074 3091
3075 amdgpu_atombios_scratch_regs_restore(adev); 3092 amdgpu_atombios_scratch_regs_restore(adev);
3076 3093
3077 /* init dig PHYs, disp eng pll */
3078 amdgpu_atombios_crtc_powergate_init(adev);
3079 amdgpu_atombios_encoder_init_dig(adev);
3080 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3081 /* turn on the BL */ 3094 /* turn on the BL */
3082 if (adev->mode_info.bl_encoder) { 3095 if (adev->mode_info.bl_encoder) {
3083 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3096 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3086,10 +3099,7 @@ static int dce_v11_0_resume(void *handle)
3086 bl_level); 3099 bl_level);
3087 } 3100 }
3088 3101
3089 /* initialize hpd */ 3102 return ret;
3090 dce_v11_0_hpd_init(adev);
3091
3092 return 0;
3093} 3103}
3094 3104
3095static bool dce_v11_0_is_idle(void *handle) 3105static bool dce_v11_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index d784fb43efc2..00c34f87ac20 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2994,20 +2994,18 @@ static int dce_v8_0_suspend(void *handle)
2994 2994
2995 amdgpu_atombios_scratch_regs_save(adev); 2995 amdgpu_atombios_scratch_regs_save(adev);
2996 2996
2997 dce_v8_0_hpd_fini(adev); 2997 return dce_v8_0_hw_fini(handle);
2998
2999 return 0;
3000} 2998}
3001 2999
3002static int dce_v8_0_resume(void *handle) 3000static int dce_v8_0_resume(void *handle)
3003{ 3001{
3004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3003 int ret;
3004
3005 ret = dce_v8_0_hw_init(handle);
3005 3006
3006 amdgpu_atombios_scratch_regs_restore(adev); 3007 amdgpu_atombios_scratch_regs_restore(adev);
3007 3008
3008 /* init dig PHYs, disp eng pll */
3009 amdgpu_atombios_encoder_init_dig(adev);
3010 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3011 /* turn on the BL */ 3009 /* turn on the BL */
3012 if (adev->mode_info.bl_encoder) { 3010 if (adev->mode_info.bl_encoder) {
3013 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3011 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3016,10 +3014,7 @@ static int dce_v8_0_resume(void *handle)
3016 bl_level); 3014 bl_level);
3017 } 3015 }
3018 3016
3019 /* initialize hpd */ 3017 return ret;
3020 dce_v8_0_hpd_init(adev);
3021
3022 return 0;
3023} 3018}
3024 3019
3025static bool dce_v8_0_is_idle(void *handle) 3020static bool dce_v8_0_is_idle(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e992bf2ff66c..72793f93e2fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5542,24 +5542,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5542 .set_powergating_state = gfx_v7_0_set_powergating_state, 5542 .set_powergating_state = gfx_v7_0_set_powergating_state,
5543}; 5543};
5544 5544
5545/**
5546 * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up
5547 *
5548 * @adev: amdgpu_device pointer
5549 * @ring: amdgpu_ring structure holding ring information
5550 *
5551 * Check if the 3D engine is locked up (CIK).
5552 * Returns true if the engine is locked, false if not.
5553 */
5554static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring)
5555{
5556 if (gfx_v7_0_is_idle(ring->adev)) {
5557 amdgpu_ring_lockup_update(ring);
5558 return false;
5559 }
5560 return amdgpu_ring_test_lockup(ring);
5561}
5562
5563static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5545static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5564 .get_rptr = gfx_v7_0_ring_get_rptr_gfx, 5546 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5565 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5547 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
@@ -5573,7 +5555,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5573 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5555 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5574 .test_ring = gfx_v7_0_ring_test_ring, 5556 .test_ring = gfx_v7_0_ring_test_ring,
5575 .test_ib = gfx_v7_0_ring_test_ib, 5557 .test_ib = gfx_v7_0_ring_test_ib,
5576 .is_lockup = gfx_v7_0_ring_is_lockup,
5577 .insert_nop = amdgpu_ring_insert_nop, 5558 .insert_nop = amdgpu_ring_insert_nop,
5578}; 5559};
5579 5560
@@ -5590,7 +5571,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5590 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5571 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5591 .test_ring = gfx_v7_0_ring_test_ring, 5572 .test_ring = gfx_v7_0_ring_test_ring,
5592 .test_ib = gfx_v7_0_ring_test_ib, 5573 .test_ib = gfx_v7_0_ring_test_ib,
5593 .is_lockup = gfx_v7_0_ring_is_lockup,
5594 .insert_nop = amdgpu_ring_insert_nop, 5574 .insert_nop = amdgpu_ring_insert_nop,
5595}; 5575};
5596 5576
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 718250ae9856..cbc46a34987c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -73,6 +73,12 @@ MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); 73MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); 74MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75 75
76MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
77MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
78MODULE_FIRMWARE("amdgpu/stoney_me.bin");
79MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
80MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
81
76MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); 82MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); 83MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78MODULE_FIRMWARE("amdgpu/tonga_me.bin"); 84MODULE_FIRMWARE("amdgpu/tonga_me.bin");
@@ -493,6 +499,42 @@ static const u32 cz_mgcg_cgcg_init[] =
493 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 499 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
494}; 500};
495 501
502static const u32 stoney_golden_settings_a11[] =
503{
504 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
505 mmGB_GPU_ID, 0x0000000f, 0x00000000,
506 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
507 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
508 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
509 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
510 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
511 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
512 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
513 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
514};
515
516static const u32 stoney_golden_common_all[] =
517{
518 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
519 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
520 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
521 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
522 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
523 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
524 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
525 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
526};
527
528static const u32 stoney_mgcg_cgcg_init[] =
529{
530 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
531 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
532 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
533 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
534 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
535 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
536};
537
496static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); 538static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
497static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); 539static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
498static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); 540static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -545,6 +587,17 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
545 cz_golden_common_all, 587 cz_golden_common_all,
546 (const u32)ARRAY_SIZE(cz_golden_common_all)); 588 (const u32)ARRAY_SIZE(cz_golden_common_all));
547 break; 589 break;
590 case CHIP_STONEY:
591 amdgpu_program_register_sequence(adev,
592 stoney_mgcg_cgcg_init,
593 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
594 amdgpu_program_register_sequence(adev,
595 stoney_golden_settings_a11,
596 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
597 amdgpu_program_register_sequence(adev,
598 stoney_golden_common_all,
599 (const u32)ARRAY_SIZE(stoney_golden_common_all));
600 break;
548 default: 601 default:
549 break; 602 break;
550 } 603 }
@@ -691,6 +744,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
691 case CHIP_FIJI: 744 case CHIP_FIJI:
692 chip_name = "fiji"; 745 chip_name = "fiji";
693 break; 746 break;
747 case CHIP_STONEY:
748 chip_name = "stoney";
749 break;
694 default: 750 default:
695 BUG(); 751 BUG();
696 } 752 }
@@ -748,21 +804,23 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
748 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 804 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
749 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 805 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
750 806
751 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 807 if (adev->asic_type != CHIP_STONEY) {
752 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 808 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
753 if (!err) { 809 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
754 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 810 if (!err) {
755 if (err) 811 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
756 goto out; 812 if (err)
757 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 813 goto out;
758 adev->gfx.mec2_fw->data; 814 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
759 adev->gfx.mec2_fw_version = le32_to_cpu( 815 adev->gfx.mec2_fw->data;
760 cp_hdr->header.ucode_version); 816 adev->gfx.mec2_fw_version =
761 adev->gfx.mec2_feature_version = le32_to_cpu( 817 le32_to_cpu(cp_hdr->header.ucode_version);
762 cp_hdr->ucode_feature_version); 818 adev->gfx.mec2_feature_version =
763 } else { 819 le32_to_cpu(cp_hdr->ucode_feature_version);
764 err = 0; 820 } else {
765 adev->gfx.mec2_fw = NULL; 821 err = 0;
822 adev->gfx.mec2_fw = NULL;
823 }
766 } 824 }
767 825
768 if (adev->firmware.smu_load) { 826 if (adev->firmware.smu_load) {
@@ -1010,6 +1068,40 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1010 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1068 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1011 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1069 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1012 break; 1070 break;
1071 case CHIP_STONEY:
1072 adev->gfx.config.max_shader_engines = 1;
1073 adev->gfx.config.max_tile_pipes = 2;
1074 adev->gfx.config.max_sh_per_se = 1;
1075 adev->gfx.config.max_backends_per_se = 1;
1076
1077 switch (adev->pdev->revision) {
1078 case 0xc0:
1079 case 0xc1:
1080 case 0xc2:
1081 case 0xc4:
1082 case 0xc8:
1083 case 0xc9:
1084 adev->gfx.config.max_cu_per_sh = 3;
1085 break;
1086 case 0xd0:
1087 case 0xd1:
1088 case 0xd2:
1089 default:
1090 adev->gfx.config.max_cu_per_sh = 2;
1091 break;
1092 }
1093
1094 adev->gfx.config.max_texture_channel_caches = 2;
1095 adev->gfx.config.max_gprs = 256;
1096 adev->gfx.config.max_gs_threads = 16;
1097 adev->gfx.config.max_hw_contexts = 8;
1098
1099 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1100 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1101 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1102 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1103 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1104 break;
1013 default: 1105 default:
1014 adev->gfx.config.max_shader_engines = 2; 1106 adev->gfx.config.max_shader_engines = 2;
1015 adev->gfx.config.max_tile_pipes = 4; 1107 adev->gfx.config.max_tile_pipes = 4;
@@ -1797,6 +1889,273 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1797 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1889 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1798 } 1890 }
1799 break; 1891 break;
1892 case CHIP_STONEY:
1893 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1894 switch (reg_offset) {
1895 case 0:
1896 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1897 PIPE_CONFIG(ADDR_SURF_P2) |
1898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1899 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1900 break;
1901 case 1:
1902 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1903 PIPE_CONFIG(ADDR_SURF_P2) |
1904 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1905 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1906 break;
1907 case 2:
1908 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1909 PIPE_CONFIG(ADDR_SURF_P2) |
1910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1911 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1912 break;
1913 case 3:
1914 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1915 PIPE_CONFIG(ADDR_SURF_P2) |
1916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1917 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1918 break;
1919 case 4:
1920 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1921 PIPE_CONFIG(ADDR_SURF_P2) |
1922 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1923 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1924 break;
1925 case 5:
1926 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1927 PIPE_CONFIG(ADDR_SURF_P2) |
1928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1929 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1930 break;
1931 case 6:
1932 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1933 PIPE_CONFIG(ADDR_SURF_P2) |
1934 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1935 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1936 break;
1937 case 8:
1938 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1939 PIPE_CONFIG(ADDR_SURF_P2));
1940 break;
1941 case 9:
1942 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1943 PIPE_CONFIG(ADDR_SURF_P2) |
1944 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1945 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1946 break;
1947 case 10:
1948 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1949 PIPE_CONFIG(ADDR_SURF_P2) |
1950 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1951 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1952 break;
1953 case 11:
1954 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1955 PIPE_CONFIG(ADDR_SURF_P2) |
1956 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1957 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1958 break;
1959 case 13:
1960 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1961 PIPE_CONFIG(ADDR_SURF_P2) |
1962 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1963 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1964 break;
1965 case 14:
1966 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1967 PIPE_CONFIG(ADDR_SURF_P2) |
1968 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1969 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1970 break;
1971 case 15:
1972 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1973 PIPE_CONFIG(ADDR_SURF_P2) |
1974 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1975 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1976 break;
1977 case 16:
1978 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1979 PIPE_CONFIG(ADDR_SURF_P2) |
1980 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1981 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1982 break;
1983 case 18:
1984 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1985 PIPE_CONFIG(ADDR_SURF_P2) |
1986 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1987 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1988 break;
1989 case 19:
1990 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1991 PIPE_CONFIG(ADDR_SURF_P2) |
1992 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1993 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1994 break;
1995 case 20:
1996 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1997 PIPE_CONFIG(ADDR_SURF_P2) |
1998 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1999 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2000 break;
2001 case 21:
2002 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2003 PIPE_CONFIG(ADDR_SURF_P2) |
2004 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2005 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2006 break;
2007 case 22:
2008 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2009 PIPE_CONFIG(ADDR_SURF_P2) |
2010 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2011 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2012 break;
2013 case 24:
2014 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2015 PIPE_CONFIG(ADDR_SURF_P2) |
2016 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2017 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2018 break;
2019 case 25:
2020 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2021 PIPE_CONFIG(ADDR_SURF_P2) |
2022 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2023 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2024 break;
2025 case 26:
2026 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2027 PIPE_CONFIG(ADDR_SURF_P2) |
2028 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2029 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2030 break;
2031 case 27:
2032 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2033 PIPE_CONFIG(ADDR_SURF_P2) |
2034 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2035 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2036 break;
2037 case 28:
2038 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2039 PIPE_CONFIG(ADDR_SURF_P2) |
2040 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2041 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2042 break;
2043 case 29:
2044 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2045 PIPE_CONFIG(ADDR_SURF_P2) |
2046 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2047 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2048 break;
2049 case 7:
2050 case 12:
2051 case 17:
2052 case 23:
2053 /* unused idx */
2054 continue;
2055 default:
2056 gb_tile_moden = 0;
2057 break;
2058 };
2059 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2060 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2061 }
2062 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2063 switch (reg_offset) {
2064 case 0:
2065 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2068 NUM_BANKS(ADDR_SURF_8_BANK));
2069 break;
2070 case 1:
2071 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2074 NUM_BANKS(ADDR_SURF_8_BANK));
2075 break;
2076 case 2:
2077 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2078 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2079 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2080 NUM_BANKS(ADDR_SURF_8_BANK));
2081 break;
2082 case 3:
2083 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2084 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2085 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2086 NUM_BANKS(ADDR_SURF_8_BANK));
2087 break;
2088 case 4:
2089 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2092 NUM_BANKS(ADDR_SURF_8_BANK));
2093 break;
2094 case 5:
2095 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2096 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2097 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2098 NUM_BANKS(ADDR_SURF_8_BANK));
2099 break;
2100 case 6:
2101 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2102 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2103 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2104 NUM_BANKS(ADDR_SURF_8_BANK));
2105 break;
2106 case 8:
2107 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2110 NUM_BANKS(ADDR_SURF_16_BANK));
2111 break;
2112 case 9:
2113 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2114 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2115 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2116 NUM_BANKS(ADDR_SURF_16_BANK));
2117 break;
2118 case 10:
2119 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2122 NUM_BANKS(ADDR_SURF_16_BANK));
2123 break;
2124 case 11:
2125 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2128 NUM_BANKS(ADDR_SURF_16_BANK));
2129 break;
2130 case 12:
2131 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2133 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2134 NUM_BANKS(ADDR_SURF_16_BANK));
2135 break;
2136 case 13:
2137 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2140 NUM_BANKS(ADDR_SURF_16_BANK));
2141 break;
2142 case 14:
2143 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2145 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2146 NUM_BANKS(ADDR_SURF_8_BANK));
2147 break;
2148 case 7:
2149 /* unused idx */
2150 continue;
2151 default:
2152 gb_tile_moden = 0;
2153 break;
2154 };
2155 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2156 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2157 }
2158 break;
1800 case CHIP_CARRIZO: 2159 case CHIP_CARRIZO:
1801 default: 2160 default:
1802 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 2161 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
@@ -2384,7 +2743,7 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2384 WREG32(mmRLC_CNTL, tmp); 2743 WREG32(mmRLC_CNTL, tmp);
2385 2744
2386 /* carrizo do enable cp interrupt after cp inited */ 2745 /* carrizo do enable cp interrupt after cp inited */
2387 if (adev->asic_type != CHIP_CARRIZO) 2746 if (!(adev->flags & AMD_IS_APU))
2388 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 2747 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2389 2748
2390 udelay(50); 2749 udelay(50);
@@ -2606,6 +2965,10 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2606 amdgpu_ring_write(ring, 0x00000002); 2965 amdgpu_ring_write(ring, 0x00000002);
2607 amdgpu_ring_write(ring, 0x00000000); 2966 amdgpu_ring_write(ring, 0x00000000);
2608 break; 2967 break;
2968 case CHIP_STONEY:
2969 amdgpu_ring_write(ring, 0x00000000);
2970 amdgpu_ring_write(ring, 0x00000000);
2971 break;
2609 default: 2972 default:
2610 BUG(); 2973 BUG();
2611 } 2974 }
@@ -3240,7 +3603,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3240 /* enable the doorbell if requested */ 3603 /* enable the doorbell if requested */
3241 if (use_doorbell) { 3604 if (use_doorbell) {
3242 if ((adev->asic_type == CHIP_CARRIZO) || 3605 if ((adev->asic_type == CHIP_CARRIZO) ||
3243 (adev->asic_type == CHIP_FIJI)) { 3606 (adev->asic_type == CHIP_FIJI) ||
3607 (adev->asic_type == CHIP_STONEY)) {
3244 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, 3608 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3245 AMDGPU_DOORBELL_KIQ << 2); 3609 AMDGPU_DOORBELL_KIQ << 2);
3246 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, 3610 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
@@ -3312,7 +3676,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3312{ 3676{
3313 int r; 3677 int r;
3314 3678
3315 if (adev->asic_type != CHIP_CARRIZO) 3679 if (!(adev->flags & AMD_IS_APU))
3316 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 3680 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3317 3681
3318 if (!adev->firmware.smu_load) { 3682 if (!adev->firmware.smu_load) {
@@ -4075,15 +4439,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4075 } 4439 }
4076} 4440}
4077 4441
4078static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4079{
4080 if (gfx_v8_0_is_idle(ring->adev)) {
4081 amdgpu_ring_lockup_update(ring);
4082 return false;
4083 }
4084 return amdgpu_ring_test_lockup(ring);
4085}
4086
4087static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4442static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4088{ 4443{
4089 return ring->adev->wb.wb[ring->rptr_offs]; 4444 return ring->adev->wb.wb[ring->rptr_offs];
@@ -4114,6 +4469,7 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4114 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 4469 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4115 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 4470 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4116 EOP_TC_ACTION_EN | 4471 EOP_TC_ACTION_EN |
4472 EOP_TC_WB_ACTION_EN |
4117 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4473 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4118 EVENT_INDEX(5))); 4474 EVENT_INDEX(5)));
4119 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 4475 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
@@ -4364,7 +4720,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4364 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 4720 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4365 .test_ring = gfx_v8_0_ring_test_ring, 4721 .test_ring = gfx_v8_0_ring_test_ring,
4366 .test_ib = gfx_v8_0_ring_test_ib, 4722 .test_ib = gfx_v8_0_ring_test_ib,
4367 .is_lockup = gfx_v8_0_ring_is_lockup,
4368 .insert_nop = amdgpu_ring_insert_nop, 4723 .insert_nop = amdgpu_ring_insert_nop,
4369}; 4724};
4370 4725
@@ -4381,7 +4736,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4381 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 4736 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4382 .test_ring = gfx_v8_0_ring_test_ring, 4737 .test_ring = gfx_v8_0_ring_test_ring,
4383 .test_ib = gfx_v8_0_ring_test_ib, 4738 .test_ib = gfx_v8_0_ring_test_ib,
4384 .is_lockup = gfx_v8_0_ring_is_lockup,
4385 .insert_nop = amdgpu_ring_insert_nop, 4739 .insert_nop = amdgpu_ring_insert_nop,
4386}; 4740};
4387 4741
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 42b5ff827055..72e977b1685d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -93,6 +93,12 @@ static const u32 cz_mgcg_cgcg_init[] =
93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
94}; 94};
95 95
96static const u32 stoney_mgcg_cgcg_init[] =
97{
98 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
99};
100
101
96static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 102static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
97{ 103{
98 switch (adev->asic_type) { 104 switch (adev->asic_type) {
@@ -125,6 +131,11 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
125 cz_mgcg_cgcg_init, 131 cz_mgcg_cgcg_init,
126 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 132 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
127 break; 133 break;
134 case CHIP_STONEY:
135 amdgpu_program_register_sequence(adev,
136 stoney_mgcg_cgcg_init,
137 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
138 break;
128 default: 139 default:
129 break; 140 break;
130 } 141 }
@@ -228,6 +239,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
228 chip_name = "fiji"; 239 chip_name = "fiji";
229 break; 240 break;
230 case CHIP_CARRIZO: 241 case CHIP_CARRIZO:
242 case CHIP_STONEY:
231 return 0; 243 return 0;
232 default: BUG(); 244 default: BUG();
233 } 245 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f8b868c7c496..2cf50180cc51 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1295,24 +1295,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1295 .set_powergating_state = sdma_v2_4_set_powergating_state, 1295 .set_powergating_state = sdma_v2_4_set_powergating_state,
1296}; 1296};
1297 1297
1298/**
1299 * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1300 *
1301 * @ring: amdgpu_ring structure holding ring information
1302 *
1303 * Check if the async DMA engine is locked up (VI).
1304 * Returns true if the engine appears to be locked up, false if not.
1305 */
1306static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
1307{
1308
1309 if (sdma_v2_4_is_idle(ring->adev)) {
1310 amdgpu_ring_lockup_update(ring);
1311 return false;
1312 }
1313 return amdgpu_ring_test_lockup(ring);
1314}
1315
1316static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1298static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1317 .get_rptr = sdma_v2_4_ring_get_rptr, 1299 .get_rptr = sdma_v2_4_ring_get_rptr,
1318 .get_wptr = sdma_v2_4_ring_get_wptr, 1300 .get_wptr = sdma_v2_4_ring_get_wptr,
@@ -1325,7 +1307,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1325 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1307 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1326 .test_ring = sdma_v2_4_ring_test_ring, 1308 .test_ring = sdma_v2_4_ring_test_ring,
1327 .test_ib = sdma_v2_4_ring_test_ib, 1309 .test_ib = sdma_v2_4_ring_test_ib,
1328 .is_lockup = sdma_v2_4_ring_is_lockup,
1329 .insert_nop = sdma_v2_4_ring_insert_nop, 1310 .insert_nop = sdma_v2_4_ring_insert_nop,
1330}; 1311};
1331 1312
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 670555a45da9..7253132f04b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -55,6 +55,7 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
58 59
59static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 60static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
60{ 61{
@@ -122,6 +123,19 @@ static const u32 cz_mgcg_cgcg_init[] =
122 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 123 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
123}; 124};
124 125
126static const u32 stoney_golden_settings_a11[] =
127{
128 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
129 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
130 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
131 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
132};
133
134static const u32 stoney_mgcg_cgcg_init[] =
135{
136 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
137};
138
125/* 139/*
126 * sDMA - System DMA 140 * sDMA - System DMA
127 * Starting with CIK, the GPU has new asynchronous 141 * Starting with CIK, the GPU has new asynchronous
@@ -166,6 +180,14 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
166 cz_golden_settings_a11, 180 cz_golden_settings_a11,
167 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 181 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
168 break; 182 break;
183 case CHIP_STONEY:
184 amdgpu_program_register_sequence(adev,
185 stoney_mgcg_cgcg_init,
186 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
187 amdgpu_program_register_sequence(adev,
188 stoney_golden_settings_a11,
189 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
190 break;
169 default: 191 default:
170 break; 192 break;
171 } 193 }
@@ -201,6 +223,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
201 case CHIP_CARRIZO: 223 case CHIP_CARRIZO:
202 chip_name = "carrizo"; 224 chip_name = "carrizo";
203 break; 225 break;
226 case CHIP_STONEY:
227 chip_name = "stoney";
228 break;
204 default: BUG(); 229 default: BUG();
205 } 230 }
206 231
@@ -1071,6 +1096,9 @@ static int sdma_v3_0_early_init(void *handle)
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072 1097
1073 switch (adev->asic_type) { 1098 switch (adev->asic_type) {
1099 case CHIP_STONEY:
1100 adev->sdma.num_instances = 1;
1101 break;
1074 default: 1102 default:
1075 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1103 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1076 break; 1104 break;
@@ -1428,24 +1456,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1428 .set_powergating_state = sdma_v3_0_set_powergating_state, 1456 .set_powergating_state = sdma_v3_0_set_powergating_state,
1429}; 1457};
1430 1458
1431/**
1432 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1433 *
1434 * @ring: amdgpu_ring structure holding ring information
1435 *
1436 * Check if the async DMA engine is locked up (VI).
1437 * Returns true if the engine appears to be locked up, false if not.
1438 */
1439static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1440{
1441
1442 if (sdma_v3_0_is_idle(ring->adev)) {
1443 amdgpu_ring_lockup_update(ring);
1444 return false;
1445 }
1446 return amdgpu_ring_test_lockup(ring);
1447}
1448
1449static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1459static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1450 .get_rptr = sdma_v3_0_ring_get_rptr, 1460 .get_rptr = sdma_v3_0_ring_get_rptr,
1451 .get_wptr = sdma_v3_0_ring_get_wptr, 1461 .get_wptr = sdma_v3_0_ring_get_wptr,
@@ -1458,7 +1468,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1458 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1468 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1459 .test_ring = sdma_v3_0_ring_test_ring, 1469 .test_ring = sdma_v3_0_ring_test_ring,
1460 .test_ib = sdma_v3_0_ring_test_ib, 1470 .test_ib = sdma_v3_0_ring_test_ib,
1461 .is_lockup = sdma_v3_0_ring_is_lockup,
1462 .insert_nop = sdma_v3_0_ring_insert_nop, 1471 .insert_nop = sdma_v3_0_ring_insert_nop,
1463}; 1472};
1464 1473
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index ed50dd725788..5e9f73af83a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -885,7 +885,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
885 .emit_semaphore = uvd_v4_2_ring_emit_semaphore, 885 .emit_semaphore = uvd_v4_2_ring_emit_semaphore,
886 .test_ring = uvd_v4_2_ring_test_ring, 886 .test_ring = uvd_v4_2_ring_test_ring,
887 .test_ib = uvd_v4_2_ring_test_ib, 887 .test_ib = uvd_v4_2_ring_test_ib,
888 .is_lockup = amdgpu_ring_test_lockup,
889 .insert_nop = amdgpu_ring_insert_nop, 888 .insert_nop = amdgpu_ring_insert_nop,
890}; 889};
891 890
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 9ad8b9906c0b..38864f562981 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -824,7 +824,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
824 .emit_semaphore = uvd_v5_0_ring_emit_semaphore, 824 .emit_semaphore = uvd_v5_0_ring_emit_semaphore,
825 .test_ring = uvd_v5_0_ring_test_ring, 825 .test_ring = uvd_v5_0_ring_test_ring,
826 .test_ib = uvd_v5_0_ring_test_ib, 826 .test_ib = uvd_v5_0_ring_test_ib,
827 .is_lockup = amdgpu_ring_test_lockup,
828 .insert_nop = amdgpu_ring_insert_nop, 827 .insert_nop = amdgpu_ring_insert_nop,
829}; 828};
830 829
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7e9934fa4193..121915bbc3b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -808,7 +808,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
808 .emit_semaphore = uvd_v6_0_ring_emit_semaphore, 808 .emit_semaphore = uvd_v6_0_ring_emit_semaphore,
809 .test_ring = uvd_v6_0_ring_test_ring, 809 .test_ring = uvd_v6_0_ring_test_ring,
810 .test_ib = uvd_v6_0_ring_test_ib, 810 .test_ib = uvd_v6_0_ring_test_ib,
811 .is_lockup = amdgpu_ring_test_lockup,
812 .insert_nop = amdgpu_ring_insert_nop, 811 .insert_nop = amdgpu_ring_insert_nop,
813}; 812};
814 813
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index cd16df543f64..52ac7a8f1e58 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -642,7 +642,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
642 .emit_semaphore = amdgpu_vce_ring_emit_semaphore, 642 .emit_semaphore = amdgpu_vce_ring_emit_semaphore,
643 .test_ring = amdgpu_vce_ring_test_ring, 643 .test_ring = amdgpu_vce_ring_test_ring,
644 .test_ib = amdgpu_vce_ring_test_ib, 644 .test_ib = amdgpu_vce_ring_test_ib,
645 .is_lockup = amdgpu_ring_test_lockup,
646 .insert_nop = amdgpu_ring_insert_nop, 645 .insert_nop = amdgpu_ring_insert_nop,
647}; 646};
648 647
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index f0656dfb53f3..6a52db6ad8d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -205,8 +205,9 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
205 u32 tmp; 205 u32 tmp;
206 unsigned ret; 206 unsigned ret;
207 207
208 /* Fiji is single pipe */ 208 /* Fiji, Stoney are single pipe */
209 if (adev->asic_type == CHIP_FIJI) { 209 if ((adev->asic_type == CHIP_FIJI) ||
210 (adev->asic_type == CHIP_STONEY)){
210 ret = AMDGPU_VCE_HARVEST_VCE1; 211 ret = AMDGPU_VCE_HARVEST_VCE1;
211 return ret; 212 return ret;
212 } 213 }
@@ -643,7 +644,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
643 .emit_semaphore = amdgpu_vce_ring_emit_semaphore, 644 .emit_semaphore = amdgpu_vce_ring_emit_semaphore,
644 .test_ring = amdgpu_vce_ring_test_ring, 645 .test_ring = amdgpu_vce_ring_test_ring,
645 .test_ib = amdgpu_vce_ring_test_ib, 646 .test_ib = amdgpu_vce_ring_test_ib,
646 .is_lockup = amdgpu_ring_test_lockup,
647 .insert_nop = amdgpu_ring_insert_nop, 647 .insert_nop = amdgpu_ring_insert_nop,
648}; 648};
649 649
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0bac8702e934..d8c93f14c3b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -232,6 +232,13 @@ static const u32 cz_mgcg_cgcg_init[] =
232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
233}; 233};
234 234
235static const u32 stoney_mgcg_cgcg_init[] =
236{
237 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
238 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
239 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
240};
241
235static void vi_init_golden_registers(struct amdgpu_device *adev) 242static void vi_init_golden_registers(struct amdgpu_device *adev)
236{ 243{
237 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 244 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
@@ -258,6 +265,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
258 cz_mgcg_cgcg_init, 265 cz_mgcg_cgcg_init,
259 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 266 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
260 break; 267 break;
268 case CHIP_STONEY:
269 amdgpu_program_register_sequence(adev,
270 stoney_mgcg_cgcg_init,
271 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
272 break;
261 default: 273 default:
262 break; 274 break;
263 } 275 }
@@ -488,6 +500,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
488 case CHIP_FIJI: 500 case CHIP_FIJI:
489 case CHIP_TONGA: 501 case CHIP_TONGA:
490 case CHIP_CARRIZO: 502 case CHIP_CARRIZO:
503 case CHIP_STONEY:
491 asic_register_table = cz_allowed_read_registers; 504 asic_register_table = cz_allowed_read_registers;
492 size = ARRAY_SIZE(cz_allowed_read_registers); 505 size = ARRAY_SIZE(cz_allowed_read_registers);
493 break; 506 break;
@@ -543,8 +556,10 @@ static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
543 RREG32(mmSRBM_STATUS2)); 556 RREG32(mmSRBM_STATUS2));
544 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", 557 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
545 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); 558 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
546 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", 559 if (adev->sdma.num_instances > 1) {
547 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); 560 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
561 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
562 }
548 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 563 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
549 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 564 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
550 RREG32(mmCP_STALLED_STAT1)); 565 RREG32(mmCP_STALLED_STAT1));
@@ -639,9 +654,11 @@ u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
639 reset_mask |= AMDGPU_RESET_DMA; 654 reset_mask |= AMDGPU_RESET_DMA;
640 655
641 /* SDMA1_STATUS_REG */ 656 /* SDMA1_STATUS_REG */
642 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); 657 if (adev->sdma.num_instances > 1) {
643 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 658 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
644 reset_mask |= AMDGPU_RESET_DMA1; 659 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
660 reset_mask |= AMDGPU_RESET_DMA1;
661 }
645#if 0 662#if 0
646 /* VCE_STATUS */ 663 /* VCE_STATUS */
647 if (adev->asic_type != CHIP_TOPAZ) { 664 if (adev->asic_type != CHIP_TOPAZ) {
@@ -1319,6 +1336,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
1319 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); 1336 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1320 break; 1337 break;
1321 case CHIP_CARRIZO: 1338 case CHIP_CARRIZO:
1339 case CHIP_STONEY:
1322 adev->ip_blocks = cz_ip_blocks; 1340 adev->ip_blocks = cz_ip_blocks;
1323 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); 1341 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1324 break; 1342 break;
@@ -1330,11 +1348,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
1330 return 0; 1348 return 0;
1331} 1349}
1332 1350
1351#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1352#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1353#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1354
1333static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 1355static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1334{ 1356{
1335 if (adev->asic_type == CHIP_TOPAZ) 1357 if (adev->asic_type == CHIP_TOPAZ)
1336 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 1358 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1337 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 1359 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1360 else if (adev->flags & AMD_IS_APU)
1361 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1362 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1338 else 1363 else
1339 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1364 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1340 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1365 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
@@ -1401,6 +1426,7 @@ static int vi_common_early_init(void *handle)
1401 adev->firmware.smu_load = true; 1426 adev->firmware.smu_load = true;
1402 break; 1427 break;
1403 case CHIP_CARRIZO: 1428 case CHIP_CARRIZO:
1429 case CHIP_STONEY:
1404 adev->has_uvd = true; 1430 adev->has_uvd = true;
1405 adev->cg_flags = 0; 1431 adev->cg_flags = 0;
1406 /* Disable UVD pg */ 1432 /* Disable UVD pg */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 23:10:26 -0400