drm/amdgpu: remove 128 NOP hack from vm_flush v2

With the padding raised to 256 DW that shouldn't be needed any more.

v2: reduce estimation as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 5 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8efcc8d2ad60..bb17538ff109 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6249,10 +6249,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
 
-        /* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE finish CEIB */
-        if (usepfp)
-                amdgpu_ring_insert_nop(ring, 128);
-
         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
                                  WRITE_DATA_DST_SEL(0)) |
@@ -6381,7 +6377,7 @@ static unsigned gfx_v8_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
                 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
                 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */
                 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
-                256 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
+                128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
                 2 + /* gfx_v8_ring_emit_sb */
                 3; /* gfx_v8_ring_emit_cntxcntl */
 }