drm/amdgpu: add new rlc firmware header format v2.1

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 51 insertions, 2 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index dd6f98921918..84d652599d5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -161,8 +161,38 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
                           le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
                 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
                           le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
-                DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
-                          le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
+                DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
+                          le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
+                if (version_minor == 1) {
+                        const struct rlc_firmware_header_v2_1 *v2_1 =
+                                container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
+                        DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
+                                  le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
+                        DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
+                        DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
+                        DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
+                        DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
+                        DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
+                        DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
+                        DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
+                        DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
+                        DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
+                        DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
+                        DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
+                        DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
+                                  le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
+                }
         } else {
                 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 30b5500dc152..0b262f4bb4fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -98,6 +98,24 @@ struct rlc_firmware_header_v2_0 {
         uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 };
 
+/* version_major=2, version_minor=1 */
+struct rlc_firmware_header_v2_1 {
+        struct rlc_firmware_header_v2_0 v2_0;
+        uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
+        uint32_t save_restore_list_cntl_ucode_ver;
+        uint32_t save_restore_list_cntl_feature_ver;
+        uint32_t save_restore_list_cntl_size_bytes;
+        uint32_t save_restore_list_cntl_offset_bytes;
+        uint32_t save_restore_list_gpm_ucode_ver;
+        uint32_t save_restore_list_gpm_feature_ver;
+        uint32_t save_restore_list_gpm_size_bytes;
+        uint32_t save_restore_list_gpm_offset_bytes;
+        uint32_t save_restore_list_srm_ucode_ver;
+        uint32_t save_restore_list_srm_feature_ver;
+        uint32_t save_restore_list_srm_size_bytes;
+        uint32_t save_restore_list_srm_offset_bytes;
+};
+
 /* version_major=1, version_minor=0 */
 struct sdma_firmware_header_v1_0 {
         struct common_firmware_header header;
@@ -148,6 +166,7 @@ union amdgpu_firmware_header {
         struct gfx_firmware_header_v1_0 gfx;
         struct rlc_firmware_header_v1_0 rlc;
         struct rlc_firmware_header_v2_0 rlc_v2_0;
+        struct rlc_firmware_header_v2_1 rlc_v2_1;
         struct sdma_firmware_header_v1_0 sdma;
         struct sdma_firmware_header_v1_1 sdma_v1_1;
         struct gpu_info_firmware_header_v1_0 gpu_info;