drm/amdgpu: initialize vcn jpeg ring

Add implementations for vcn jpeg ring initialization

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 076c49c91c2a..ea1d677d02c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -115,6 +115,12 @@ static int vcn_v1_0_sw_init(void *handle)
                         return r;
         }
 
+        ring = &adev->vcn.ring_jpeg;
+        sprintf(ring->name, "vcn_jpeg");
+        r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+        if (r)
+                return r;
+
         return r;
 }
 
@@ -169,6 +175,14 @@ static int vcn_v1_0_hw_init(void *handle)
                 }
         }
 
+        ring = &adev->vcn.ring_jpeg;
+        ring->ready = true;
+        r = amdgpu_ring_test_ring(ring);
+        if (r) {
+                ring->ready = false;
+                goto done;
+        }
+
 done:
         if (!r)
                 DRM_INFO("VCN decode and encode initialized successfully.\n");
@@ -736,6 +750,15 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 
+        ring = &adev->vcn.ring_jpeg;
+        WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+        WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+        WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
+        WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
+        WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+        WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+        WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+
         return 0;
 }