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authorAlex Deucher <alexander.deucher@amd.com>2016-02-04 10:21:23 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-08 10:37:41 -0500
commitcd474ba0d6048aeefe6f1066a6bfb5eac36a2a81 (patch)
tree4854307a6b0b4be42ee7885f27597ca652b51048 /drivers/gpu/drm/amd/amdgpu
parent6739b3d7bc18a5373efd863b11831e8f515fffe1 (diff)
drm/amdgpu: add pcie cap module parameters (v2)
Allows the user to force the supported pcie gen and lane config on both the asic and the chipset. Useful for debugging pcie problems and for virtualization where we may not be able to query the pcie bridge caps. Default to: gen: chipset 1/2, asic 1/2/3 lanes: 1/2/4/8/16 v2: fix bare metal case Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c147
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c8
3 files changed, 92 insertions, 65 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 82edf95b7740..4021c8a97fc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
87extern int amdgpu_sched_hw_submission; 87extern int amdgpu_sched_hw_submission;
88extern int amdgpu_enable_semaphores; 88extern int amdgpu_enable_semaphores;
89extern int amdgpu_powerplay; 89extern int amdgpu_powerplay;
90extern unsigned amdgpu_pcie_gen_cap;
91extern unsigned amdgpu_pcie_lane_cap;
90 92
91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 93#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 94#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65531463f88e..85991cee62e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1933,80 +1933,97 @@ retry:
1933 return r; 1933 return r;
1934} 1934}
1935 1935
1936#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1937#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1938
1936void amdgpu_get_pcie_info(struct amdgpu_device *adev) 1939void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1937{ 1940{
1938 u32 mask; 1941 u32 mask;
1939 int ret; 1942 int ret;
1940 1943
1941 if (pci_is_root_bus(adev->pdev->bus)) 1944 if (amdgpu_pcie_gen_cap)
1942 return; 1945 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1943 1946
1944 if (amdgpu_pcie_gen2 == 0) 1947 if (amdgpu_pcie_lane_cap)
1945 return; 1948 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1946 1949
1947 if (adev->flags & AMD_IS_APU) 1950 /* covers APUs as well */
1951 if (pci_is_root_bus(adev->pdev->bus)) {
1952 if (adev->pm.pcie_gen_mask == 0)
1953 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1954 if (adev->pm.pcie_mlw_mask == 0)
1955 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1948 return; 1956 return;
1957 }
1949 1958
1950 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1959 if (adev->pm.pcie_gen_mask == 0) {
1951 if (!ret) { 1960 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1952 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | 1961 if (!ret) {
1953 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1962 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1954 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); 1963 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1955 1964 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1956 if (mask & DRM_PCIE_SPEED_25) 1965
1957 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; 1966 if (mask & DRM_PCIE_SPEED_25)
1958 if (mask & DRM_PCIE_SPEED_50) 1967 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1959 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; 1968 if (mask & DRM_PCIE_SPEED_50)
1960 if (mask & DRM_PCIE_SPEED_80) 1969 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1961 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; 1970 if (mask & DRM_PCIE_SPEED_80)
1962 } 1971 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1963 ret = drm_pcie_get_max_link_width(adev->ddev, &mask); 1972 } else {
1964 if (!ret) { 1973 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1965 switch (mask) { 1974 }
1966 case 32: 1975 }
1967 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | 1976 if (adev->pm.pcie_mlw_mask == 0) {
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1977 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1978 if (!ret) {
1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1979 switch (mask) {
1971 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1980 case 32:
1972 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1981 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1974 break; 1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1975 case 16: 1984 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1976 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1985 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1978 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1979 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1988 break;
1980 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1989 case 16:
1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1990 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1982 break; 1991 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1983 case 12: 1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1984 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1985 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1986 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1995 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1996 break;
1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1997 case 12:
1989 break; 1998 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1990 case 8: 1999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1991 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 2000 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 2001 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1993 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2002 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1994 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2003 break;
1995 break; 2004 case 8:
1996 case 4: 2005 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1997 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 2006 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1998 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2007 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1999 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2008 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2000 break; 2009 break;
2001 case 2: 2010 case 4:
2002 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 2011 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2003 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 2012 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2004 break; 2013 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2005 case 1: 2014 break;
2006 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; 2015 case 2:
2007 break; 2016 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2008 default: 2017 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2009 break; 2018 break;
2019 case 1:
2020 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2021 break;
2022 default:
2023 break;
2024 }
2025 } else {
2026 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2010 } 2027 }
2011 } 2028 }
2012} 2029}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 9c1af8976bef..9ef1db87cf26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32;
83int amdgpu_sched_hw_submission = 2; 83int amdgpu_sched_hw_submission = 2;
84int amdgpu_enable_semaphores = 0; 84int amdgpu_enable_semaphores = 0;
85int amdgpu_powerplay = -1; 85int amdgpu_powerplay = -1;
86unsigned amdgpu_pcie_gen_cap = 0;
87unsigned amdgpu_pcie_lane_cap = 0;
86 88
87MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 89MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
88module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 90module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
170module_param_named(powerplay, amdgpu_powerplay, int, 0444); 172module_param_named(powerplay, amdgpu_powerplay, int, 0444);
171#endif 173#endif
172 174
175MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
176module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
177
178MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
179module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
180
173static struct pci_device_id pciidlist[] = { 181static struct pci_device_id pciidlist[] = {
174#ifdef CONFIG_DRM_AMDGPU_CIK 182#ifdef CONFIG_DRM_AMDGPU_CIK
175 /* Kaveri */ 183 /* Kaveri */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 13:20:45 -0400