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authorDave Airlie <airlied@redhat.com>2016-03-13 19:42:34 -0400
committerDave Airlie <airlied@redhat.com>2016-03-13 19:46:02 -0400
commit9b61c0fcdf0cfd20a85d9856d46142e7f297de0a (patch)
treed4abe6aa3f4e1e088f9da1d0597e078b1fe58912 /drivers/gpu/drm/amd/amdgpu
parent550e3b23a53c88adfa46e64f9d442743e65d47da (diff)
parent125234dc8b1cc862f52d8bd5b37c36cc59b2cb86 (diff)
Merge drm-fixes into drm-next.
Nouveau wanted this to avoid some worse conflicts when I merge that.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h46
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c160
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c35
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_dp.c20
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c157
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c83
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c3
26 files changed, 361 insertions, 281 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0c42a85ca5a5..d0489722fc7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -85,6 +85,8 @@ extern int amdgpu_vm_debug;
85extern int amdgpu_sched_jobs; 85extern int amdgpu_sched_jobs;
86extern int amdgpu_sched_hw_submission; 86extern int amdgpu_sched_hw_submission;
87extern int amdgpu_powerplay; 87extern int amdgpu_powerplay;
88extern unsigned amdgpu_pcie_gen_cap;
89extern unsigned amdgpu_pcie_lane_cap;
88 90
89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -127,47 +129,6 @@ extern int amdgpu_powerplay;
127#define AMDGPU_RESET_VCE (1 << 13) 129#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14) 130#define AMDGPU_RESET_VCE1 (1 << 14)
129 131
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */ 132/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L 133#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L 134#define AMDGPU_GFX_SAFE_MODE 0x00000001L
@@ -592,8 +553,6 @@ struct amdgpu_sa_manager {
592 uint32_t align; 553 uint32_t align;
593}; 554};
594 555
595struct amdgpu_sa_bo;
596
597/* sub-allocation buffer */ 556/* sub-allocation buffer */
598struct amdgpu_sa_bo { 557struct amdgpu_sa_bo {
599 struct list_head olist; 558 struct list_head olist;
@@ -2357,6 +2316,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2357bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2316bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2358int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2317int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2359 uint32_t flags); 2318 uint32_t flags);
2319bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2360struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2320struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2361bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2321bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2362 unsigned long end); 2322 unsigned long end);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a081dda9fa2f..7a4b101e10c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -795,6 +795,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
795 case CGS_SYSTEM_INFO_PCIE_MLW: 795 case CGS_SYSTEM_INFO_PCIE_MLW:
796 sys_info->value = adev->pm.pcie_mlw_mask; 796 sys_info->value = adev->pm.pcie_mlw_mask;
797 break; 797 break;
798 case CGS_SYSTEM_INFO_CG_FLAGS:
799 sys_info->value = adev->cg_flags;
800 break;
801 case CGS_SYSTEM_INFO_PG_FLAGS:
802 sys_info->value = adev->pg_flags;
803 break;
798 default: 804 default:
799 return -ENODEV; 805 return -ENODEV;
800 } 806 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 89c3dd62ba21..119cdc2c43e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -77,7 +77,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78 /* Don't try to start link training before we 78 /* Don't try to start link training before we
79 * have the dpcd */ 79 * have the dpcd */
80 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
81 return; 81 return;
82 82
83 /* set it to OFF so that drm_helper_connector_dpms() 83 /* set it to OFF so that drm_helper_connector_dpms()
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index db20d2783def..2139da773da6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1762,15 +1762,20 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1762 } 1762 }
1763 1763
1764 /* post card */ 1764 /* post card */
1765 amdgpu_atom_asic_init(adev->mode_info.atom_context); 1765 if (!amdgpu_card_posted(adev))
1766 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1766 1767
1767 r = amdgpu_resume(adev); 1768 r = amdgpu_resume(adev);
1769 if (r)
1770 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1768 1771
1769 amdgpu_fence_driver_resume(adev); 1772 amdgpu_fence_driver_resume(adev);
1770 1773
1771 r = amdgpu_ib_ring_tests(adev); 1774 if (resume) {
1772 if (r) 1775 r = amdgpu_ib_ring_tests(adev);
1773 DRM_ERROR("ib ring test failed (%d).\n", r); 1776 if (r)
1777 DRM_ERROR("ib ring test failed (%d).\n", r);
1778 }
1774 1779
1775 r = amdgpu_late_init(adev); 1780 r = amdgpu_late_init(adev);
1776 if (r) 1781 if (r)
@@ -1903,80 +1908,97 @@ retry:
1903 return r; 1908 return r;
1904} 1909}
1905 1910
1911#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1912#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1913
1906void amdgpu_get_pcie_info(struct amdgpu_device *adev) 1914void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1907{ 1915{
1908 u32 mask; 1916 u32 mask;
1909 int ret; 1917 int ret;
1910 1918
1911 if (pci_is_root_bus(adev->pdev->bus)) 1919 if (amdgpu_pcie_gen_cap)
1912 return; 1920 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1913 1921
1914 if (amdgpu_pcie_gen2 == 0) 1922 if (amdgpu_pcie_lane_cap)
1915 return; 1923 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1916 1924
1917 if (adev->flags & AMD_IS_APU) 1925 /* covers APUs as well */
1926 if (pci_is_root_bus(adev->pdev->bus)) {
1927 if (adev->pm.pcie_gen_mask == 0)
1928 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1929 if (adev->pm.pcie_mlw_mask == 0)
1930 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1918 return; 1931 return;
1932 }
1919 1933
1920 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1934 if (adev->pm.pcie_gen_mask == 0) {
1921 if (!ret) { 1935 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1922 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | 1936 if (!ret) {
1923 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1937 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1924 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); 1938 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1925 1939 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1926 if (mask & DRM_PCIE_SPEED_25) 1940
1927 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; 1941 if (mask & DRM_PCIE_SPEED_25)
1928 if (mask & DRM_PCIE_SPEED_50) 1942 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1929 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; 1943 if (mask & DRM_PCIE_SPEED_50)
1930 if (mask & DRM_PCIE_SPEED_80) 1944 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1931 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; 1945 if (mask & DRM_PCIE_SPEED_80)
1932 } 1946 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1933 ret = drm_pcie_get_max_link_width(adev->ddev, &mask); 1947 } else {
1934 if (!ret) { 1948 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1935 switch (mask) { 1949 }
1936 case 32: 1950 }
1937 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | 1951 if (adev->pm.pcie_mlw_mask == 0) {
1938 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1952 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1939 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1953 if (!ret) {
1940 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1954 switch (mask) {
1941 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1955 case 32:
1942 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1956 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1943 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1957 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1944 break; 1958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1945 case 16: 1959 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1946 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | 1960 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1947 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1961 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1948 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1962 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1949 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1963 break;
1950 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1964 case 16:
1951 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1965 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1952 break; 1966 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1953 case 12: 1967 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1954 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | 1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1955 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1956 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1957 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1971 break;
1958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1972 case 12:
1959 break; 1973 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1960 case 8: 1974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1961 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | 1975 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1962 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1976 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1963 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1964 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1978 break;
1965 break; 1979 case 8:
1966 case 4: 1980 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1967 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | 1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1970 break; 1984 break;
1971 case 2: 1985 case 4:
1972 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | 1986 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1973 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); 1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1974 break; 1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1975 case 1: 1989 break;
1976 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; 1990 case 2:
1977 break; 1991 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1978 default: 1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1979 break; 1993 break;
1994 case 1:
1995 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
1996 break;
1997 default:
1998 break;
1999 }
2000 } else {
2001 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1980 } 2002 }
1981 } 2003 }
1982} 2004}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 2cb53c24dec0..f0ed974bd4e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -70,8 +70,8 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
70 70
71 struct drm_crtc *crtc = &amdgpuCrtc->base; 71 struct drm_crtc *crtc = &amdgpuCrtc->base;
72 unsigned long flags; 72 unsigned long flags;
73 unsigned i; 73 unsigned i, repcnt = 4;
74 int vpos, hpos, stat, min_udelay; 74 int vpos, hpos, stat, min_udelay = 0;
75 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 75 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
76 76
77 if (amdgpu_flip_handle_fence(work, &work->excl)) 77 if (amdgpu_flip_handle_fence(work, &work->excl))
@@ -97,7 +97,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
97 * In practice this won't execute very often unless on very fast 97 * In practice this won't execute very often unless on very fast
98 * machines because the time window for this to happen is very small. 98 * machines because the time window for this to happen is very small.
99 */ 99 */
100 for (;;) { 100 while (amdgpuCrtc->enabled && --repcnt) {
101 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 101 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
102 * start in hpos, and to the "fudged earlier" vblank start in 102 * start in hpos, and to the "fudged earlier" vblank start in
103 * vpos. 103 * vpos.
@@ -113,12 +113,24 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
113 break; 113 break;
114 114
115 /* Sleep at least until estimated real start of hw vblank */ 115 /* Sleep at least until estimated real start of hw vblank */
116 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
117 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 116 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
117 if (min_udelay > vblank->framedur_ns / 2000) {
118 /* Don't wait ridiculously long - something is wrong */
119 repcnt = 0;
120 break;
121 }
122 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
118 usleep_range(min_udelay, 2 * min_udelay); 123 usleep_range(min_udelay, 2 * min_udelay);
119 spin_lock_irqsave(&crtc->dev->event_lock, flags); 124 spin_lock_irqsave(&crtc->dev->event_lock, flags);
120 }; 125 };
121 126
127 if (!repcnt)
128 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
129 "framedur %d, linedur %d, stat %d, vpos %d, "
130 "hpos %d\n", work->crtc_id, min_udelay,
131 vblank->framedur_ns / 1000,
132 vblank->linedur_ns / 1000, stat, vpos, hpos);
133
122 /* set the flip status */ 134 /* set the flip status */
123 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 135 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
124 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 136 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 01b4fd6115c2..74a2f8a6be1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -80,6 +80,8 @@ int amdgpu_exp_hw_support = 0;
80int amdgpu_sched_jobs = 32; 80int amdgpu_sched_jobs = 32;
81int amdgpu_sched_hw_submission = 2; 81int amdgpu_sched_hw_submission = 2;
82int amdgpu_powerplay = -1; 82int amdgpu_powerplay = -1;
83unsigned amdgpu_pcie_gen_cap = 0;
84unsigned amdgpu_pcie_lane_cap = 0;
83 85
84MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 86MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
85module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 87module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -158,6 +160,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
158module_param_named(powerplay, amdgpu_powerplay, int, 0444); 160module_param_named(powerplay, amdgpu_powerplay, int, 0444);
159#endif 161#endif
160 162
163MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
164module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
165
166MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
167module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
168
161static struct pci_device_id pciidlist[] = { 169static struct pci_device_id pciidlist[] = {
162#ifdef CONFIG_DRM_AMDGPU_CIK 170#ifdef CONFIG_DRM_AMDGPU_CIK
163 /* Kaveri */ 171 /* Kaveri */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 2e26a517f2d6..7a47c45b2131 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -606,7 +606,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
606 break; 606 break;
607 } 607 }
608 ttm_eu_backoff_reservation(&ticket, &list); 608 ttm_eu_backoff_reservation(&ticket, &list);
609 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 609 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
610 !amdgpu_vm_debug)
610 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 611 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
611 612
612 drm_gem_object_unreference_unlocked(gobj); 613 drm_gem_object_unreference_unlocked(gobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d77b2bdbe800..ff9597ce268c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -113,6 +113,10 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
113 struct drm_device *ddev = dev_get_drvdata(dev); 113 struct drm_device *ddev = dev_get_drvdata(dev);
114 struct amdgpu_device *adev = ddev->dev_private; 114 struct amdgpu_device *adev = ddev->dev_private;
115 115
116 if ((adev->flags & AMD_IS_PX) &&
117 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
118 return snprintf(buf, PAGE_SIZE, "off\n");
119
116 if (adev->pp_enabled) { 120 if (adev->pp_enabled) {
117 enum amd_dpm_forced_level level; 121 enum amd_dpm_forced_level level;
118 122
@@ -142,6 +146,11 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
142 enum amdgpu_dpm_forced_level level; 146 enum amdgpu_dpm_forced_level level;
143 int ret = 0; 147 int ret = 0;
144 148
149 /* Can't force performance level when the card is off */
150 if ((adev->flags & AMD_IS_PX) &&
151 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
152 return -EINVAL;
153
145 if (strncmp("low", buf, strlen("low")) == 0) { 154 if (strncmp("low", buf, strlen("low")) == 0) {
146 level = AMDGPU_DPM_FORCED_LEVEL_LOW; 155 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
147 } else if (strncmp("high", buf, strlen("high")) == 0) { 156 } else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -161,6 +170,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
161 mutex_lock(&adev->pm.mutex); 170 mutex_lock(&adev->pm.mutex);
162 if (adev->pm.dpm.thermal_active) { 171 if (adev->pm.dpm.thermal_active) {
163 count = -EINVAL; 172 count = -EINVAL;
173 mutex_unlock(&adev->pm.mutex);
164 goto fail; 174 goto fail;
165 } 175 }
166 ret = amdgpu_dpm_force_performance_level(adev, level); 176 ret = amdgpu_dpm_force_performance_level(adev, level);
@@ -171,8 +181,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
171 mutex_unlock(&adev->pm.mutex); 181 mutex_unlock(&adev->pm.mutex);
172 } 182 }
173fail: 183fail:
174 mutex_unlock(&adev->pm.mutex);
175
176 return count; 184 return count;
177} 185}
178 186
@@ -469,8 +477,14 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
469 char *buf) 477 char *buf)
470{ 478{
471 struct amdgpu_device *adev = dev_get_drvdata(dev); 479 struct amdgpu_device *adev = dev_get_drvdata(dev);
480 struct drm_device *ddev = adev->ddev;
472 int temp; 481 int temp;
473 482
483 /* Can't get temperature when the card is off */
484 if ((adev->flags & AMD_IS_PX) &&
485 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
486 return -EINVAL;
487
474 if (!adev->pp_enabled && !adev->pm.funcs->get_temperature) 488 if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
475 temp = 0; 489 temp = 0;
476 else 490 else
@@ -919,11 +933,6 @@ force:
919 933
920 /* update display watermarks based on new power state */ 934 /* update display watermarks based on new power state */
921 amdgpu_display_bandwidth_update(adev); 935 amdgpu_display_bandwidth_update(adev);
922 /* update displays */
923 amdgpu_dpm_display_configuration_changed(adev);
924
925 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
926 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
927 936
928 /* wait for the rings to drain */ 937 /* wait for the rings to drain */
929 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 938 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
@@ -940,6 +949,12 @@ force:
940 949
941 amdgpu_dpm_post_set_power_state(adev); 950 amdgpu_dpm_post_set_power_state(adev);
942 951
952 /* update displays */
953 amdgpu_dpm_display_configuration_changed(adev);
954
955 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
956 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
957
943 if (adev->pm.funcs->force_performance_level) { 958 if (adev->pm.funcs->force_performance_level) {
944 if (adev->pm.dpm.thermal_active) { 959 if (adev->pm.dpm.thermal_active) {
945 enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; 960 enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
@@ -1174,12 +1189,16 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1174 struct drm_info_node *node = (struct drm_info_node *) m->private; 1189 struct drm_info_node *node = (struct drm_info_node *) m->private;
1175 struct drm_device *dev = node->minor->dev; 1190 struct drm_device *dev = node->minor->dev;
1176 struct amdgpu_device *adev = dev->dev_private; 1191 struct amdgpu_device *adev = dev->dev_private;
1192 struct drm_device *ddev = adev->ddev;
1177 1193
1178 if (!adev->pm.dpm_enabled) { 1194 if (!adev->pm.dpm_enabled) {
1179 seq_printf(m, "dpm not enabled\n"); 1195 seq_printf(m, "dpm not enabled\n");
1180 return 0; 1196 return 0;
1181 } 1197 }
1182 if (adev->pp_enabled) { 1198 if ((adev->flags & AMD_IS_PX) &&
1199 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1200 seq_printf(m, "PX asic powered off\n");
1201 } else if (adev->pp_enabled) {
1183 amdgpu_dpm_debugfs_print_current_performance_level(adev, m); 1202 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1184 } else { 1203 } else {
1185 mutex_lock(&adev->pm.mutex); 1204 mutex_lock(&adev->pm.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index b9d0d55f6b47..3cb6d6c413c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -143,8 +143,10 @@ static int amdgpu_pp_late_init(void *handle)
143 adev->powerplay.pp_handle); 143 adev->powerplay.pp_handle);
144 144
145#ifdef CONFIG_DRM_AMD_POWERPLAY 145#ifdef CONFIG_DRM_AMD_POWERPLAY
146 if (adev->pp_enabled) 146 if (adev->pp_enabled) {
147 amdgpu_pm_sysfs_init(adev); 147 amdgpu_pm_sysfs_init(adev);
148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
149 }
148#endif 150#endif
149 return ret; 151 return ret;
150} 152}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 7d8f8f1e3f7f..2faf03bcda21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -357,12 +357,15 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
357 357
358 for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i) 358 for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
359 if (fences[i]) 359 if (fences[i])
360 fences[count++] = fences[i]; 360 fences[count++] = fence_get(fences[i]);
361 361
362 if (count) { 362 if (count) {
363 spin_unlock(&sa_manager->wq.lock); 363 spin_unlock(&sa_manager->wq.lock);
364 t = fence_wait_any_timeout(fences, count, false, 364 t = fence_wait_any_timeout(fences, count, false,
365 MAX_SCHEDULE_TIMEOUT); 365 MAX_SCHEDULE_TIMEOUT);
366 for (i = 0; i < count; ++i)
367 fence_put(fences[i]);
368
366 r = (t > 0) ? 0 : t; 369 r = (t > 0) ? 0 : t;
367 spin_lock(&sa_manager->wq.lock); 370 spin_lock(&sa_manager->wq.lock);
368 } else { 371 } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e52fc641edfb..9ccdd189d717 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -725,7 +725,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
725 0, PAGE_SIZE, 725 0, PAGE_SIZE,
726 PCI_DMA_BIDIRECTIONAL); 726 PCI_DMA_BIDIRECTIONAL);
727 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 727 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
728 while (--i) { 728 while (i--) {
729 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 729 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
730 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 730 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
731 gtt->ttm.dma_address[i] = 0; 731 gtt->ttm.dma_address[i] = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index 21aacc1f45c1..bf731e9f643e 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -265,15 +265,27 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
265 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 265 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
266 unsigned lane_num, i, max_pix_clock; 266 unsigned lane_num, i, max_pix_clock;
267 267
268 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 268 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
269 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { 269 ENCODER_OBJECT_ID_NUTMEG) {
270 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; 270 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
271 max_pix_clock = (lane_num * 270000 * 8) / bpp;
271 if (max_pix_clock >= pix_clock) { 272 if (max_pix_clock >= pix_clock) {
272 *dp_lanes = lane_num; 273 *dp_lanes = lane_num;
273 *dp_rate = link_rates[i]; 274 *dp_rate = 270000;
274 return 0; 275 return 0;
275 } 276 }
276 } 277 }
278 } else {
279 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
280 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
281 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
282 if (max_pix_clock >= pix_clock) {
283 *dp_lanes = lane_num;
284 *dp_rate = link_rates[i];
285 return 0;
286 }
287 }
288 }
277 } 289 }
278 290
279 return -EINVAL; 291 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 8b4731d4e10e..474ca02b0949 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -31,6 +31,7 @@
31#include "ci_dpm.h" 31#include "ci_dpm.h"
32#include "gfx_v7_0.h" 32#include "gfx_v7_0.h"
33#include "atom.h" 33#include "atom.h"
34#include "amd_pcie.h"
34#include <linux/seq_file.h> 35#include <linux/seq_file.h>
35 36
36#include "smu/smu_7_0_1_d.h" 37#include "smu/smu_7_0_1_d.h"
@@ -5835,18 +5836,16 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5835 u8 frev, crev; 5836 u8 frev, crev;
5836 struct ci_power_info *pi; 5837 struct ci_power_info *pi;
5837 int ret; 5838 int ret;
5838 u32 mask;
5839 5839
5840 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); 5840 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5841 if (pi == NULL) 5841 if (pi == NULL)
5842 return -ENOMEM; 5842 return -ENOMEM;
5843 adev->pm.dpm.priv = pi; 5843 adev->pm.dpm.priv = pi;
5844 5844
5845 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 5845 pi->sys_pcie_mask =
5846 if (ret) 5846 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5847 pi->sys_pcie_mask = 0; 5847 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5848 else 5848
5849 pi->sys_pcie_mask = mask;
5850 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; 5849 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5851 5850
5852 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1; 5851 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6b1f0539ce9d..192ab13e9f05 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1462,6 +1462,9 @@ static void cik_program_aspm(struct amdgpu_device *adev)
1462 if (amdgpu_aspm == 0) 1462 if (amdgpu_aspm == 0)
1463 return; 1463 return;
1464 1464
1465 if (pci_is_root_bus(adev->pdev->bus))
1466 return;
1467
1465 /* XXX double check APUs */ 1468 /* XXX double check APUs */
1466 if (adev->flags & AMD_IS_APU) 1469 if (adev->flags & AMD_IS_APU)
1467 return; 1470 return;
@@ -2032,72 +2035,72 @@ static int cik_common_early_init(void *handle)
2032 switch (adev->asic_type) { 2035 switch (adev->asic_type) {
2033 case CHIP_BONAIRE: 2036 case CHIP_BONAIRE:
2034 adev->cg_flags = 2037 adev->cg_flags =
2035 AMDGPU_CG_SUPPORT_GFX_MGCG | 2038 AMD_CG_SUPPORT_GFX_MGCG |
2036 AMDGPU_CG_SUPPORT_GFX_MGLS | 2039 AMD_CG_SUPPORT_GFX_MGLS |
2037 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2040 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2038 AMDGPU_CG_SUPPORT_GFX_CGLS | 2041 AMD_CG_SUPPORT_GFX_CGLS |
2039 AMDGPU_CG_SUPPORT_GFX_CGTS | 2042 AMD_CG_SUPPORT_GFX_CGTS |
2040 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2043 AMD_CG_SUPPORT_GFX_CGTS_LS |
2041 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2044 AMD_CG_SUPPORT_GFX_CP_LS |
2042 AMDGPU_CG_SUPPORT_MC_LS | 2045 AMD_CG_SUPPORT_MC_LS |
2043 AMDGPU_CG_SUPPORT_MC_MGCG | 2046 AMD_CG_SUPPORT_MC_MGCG |
2044 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2047 AMD_CG_SUPPORT_SDMA_MGCG |
2045 AMDGPU_CG_SUPPORT_SDMA_LS | 2048 AMD_CG_SUPPORT_SDMA_LS |
2046 AMDGPU_CG_SUPPORT_BIF_LS | 2049 AMD_CG_SUPPORT_BIF_LS |
2047 AMDGPU_CG_SUPPORT_VCE_MGCG | 2050 AMD_CG_SUPPORT_VCE_MGCG |
2048 AMDGPU_CG_SUPPORT_UVD_MGCG | 2051 AMD_CG_SUPPORT_UVD_MGCG |
2049 AMDGPU_CG_SUPPORT_HDP_LS | 2052 AMD_CG_SUPPORT_HDP_LS |
2050 AMDGPU_CG_SUPPORT_HDP_MGCG; 2053 AMD_CG_SUPPORT_HDP_MGCG;
2051 adev->pg_flags = 0; 2054 adev->pg_flags = 0;
2052 adev->external_rev_id = adev->rev_id + 0x14; 2055 adev->external_rev_id = adev->rev_id + 0x14;
2053 break; 2056 break;
2054 case CHIP_HAWAII: 2057 case CHIP_HAWAII:
2055 adev->cg_flags = 2058 adev->cg_flags =
2056 AMDGPU_CG_SUPPORT_GFX_MGCG | 2059 AMD_CG_SUPPORT_GFX_MGCG |
2057 AMDGPU_CG_SUPPORT_GFX_MGLS | 2060 AMD_CG_SUPPORT_GFX_MGLS |
2058 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2061 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2059 AMDGPU_CG_SUPPORT_GFX_CGLS | 2062 AMD_CG_SUPPORT_GFX_CGLS |
2060 AMDGPU_CG_SUPPORT_GFX_CGTS | 2063 AMD_CG_SUPPORT_GFX_CGTS |
2061 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2064 AMD_CG_SUPPORT_GFX_CP_LS |
2062 AMDGPU_CG_SUPPORT_MC_LS | 2065 AMD_CG_SUPPORT_MC_LS |
2063 AMDGPU_CG_SUPPORT_MC_MGCG | 2066 AMD_CG_SUPPORT_MC_MGCG |
2064 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2067 AMD_CG_SUPPORT_SDMA_MGCG |
2065 AMDGPU_CG_SUPPORT_SDMA_LS | 2068 AMD_CG_SUPPORT_SDMA_LS |
2066 AMDGPU_CG_SUPPORT_BIF_LS | 2069 AMD_CG_SUPPORT_BIF_LS |
2067 AMDGPU_CG_SUPPORT_VCE_MGCG | 2070 AMD_CG_SUPPORT_VCE_MGCG |
2068 AMDGPU_CG_SUPPORT_UVD_MGCG | 2071 AMD_CG_SUPPORT_UVD_MGCG |
2069 AMDGPU_CG_SUPPORT_HDP_LS | 2072 AMD_CG_SUPPORT_HDP_LS |
2070 AMDGPU_CG_SUPPORT_HDP_MGCG; 2073 AMD_CG_SUPPORT_HDP_MGCG;
2071 adev->pg_flags = 0; 2074 adev->pg_flags = 0;
2072 adev->external_rev_id = 0x28; 2075 adev->external_rev_id = 0x28;
2073 break; 2076 break;
2074 case CHIP_KAVERI: 2077 case CHIP_KAVERI:
2075 adev->cg_flags = 2078 adev->cg_flags =
2076 AMDGPU_CG_SUPPORT_GFX_MGCG | 2079 AMD_CG_SUPPORT_GFX_MGCG |
2077 AMDGPU_CG_SUPPORT_GFX_MGLS | 2080 AMD_CG_SUPPORT_GFX_MGLS |
2078 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2081 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2079 AMDGPU_CG_SUPPORT_GFX_CGLS | 2082 AMD_CG_SUPPORT_GFX_CGLS |
2080 AMDGPU_CG_SUPPORT_GFX_CGTS | 2083 AMD_CG_SUPPORT_GFX_CGTS |
2081 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2084 AMD_CG_SUPPORT_GFX_CGTS_LS |
2082 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2085 AMD_CG_SUPPORT_GFX_CP_LS |
2083 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2086 AMD_CG_SUPPORT_SDMA_MGCG |
2084 AMDGPU_CG_SUPPORT_SDMA_LS | 2087 AMD_CG_SUPPORT_SDMA_LS |
2085 AMDGPU_CG_SUPPORT_BIF_LS | 2088 AMD_CG_SUPPORT_BIF_LS |
2086 AMDGPU_CG_SUPPORT_VCE_MGCG | 2089 AMD_CG_SUPPORT_VCE_MGCG |
2087 AMDGPU_CG_SUPPORT_UVD_MGCG | 2090 AMD_CG_SUPPORT_UVD_MGCG |
2088 AMDGPU_CG_SUPPORT_HDP_LS | 2091 AMD_CG_SUPPORT_HDP_LS |
2089 AMDGPU_CG_SUPPORT_HDP_MGCG; 2092 AMD_CG_SUPPORT_HDP_MGCG;
2090 adev->pg_flags = 2093 adev->pg_flags =
2091 /*AMDGPU_PG_SUPPORT_GFX_PG | 2094 /*AMD_PG_SUPPORT_GFX_PG |
2092 AMDGPU_PG_SUPPORT_GFX_SMG | 2095 AMD_PG_SUPPORT_GFX_SMG |
2093 AMDGPU_PG_SUPPORT_GFX_DMG |*/ 2096 AMD_PG_SUPPORT_GFX_DMG |*/
2094 AMDGPU_PG_SUPPORT_UVD | 2097 AMD_PG_SUPPORT_UVD |
2095 /*AMDGPU_PG_SUPPORT_VCE | 2098 /*AMD_PG_SUPPORT_VCE |
2096 AMDGPU_PG_SUPPORT_CP | 2099 AMD_PG_SUPPORT_CP |
2097 AMDGPU_PG_SUPPORT_GDS | 2100 AMD_PG_SUPPORT_GDS |
2098 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2101 AMD_PG_SUPPORT_RLC_SMU_HS |
2099 AMDGPU_PG_SUPPORT_ACP | 2102 AMD_PG_SUPPORT_ACP |
2100 AMDGPU_PG_SUPPORT_SAMU |*/ 2103 AMD_PG_SUPPORT_SAMU |*/
2101 0; 2104 0;
2102 if (adev->pdev->device == 0x1312 || 2105 if (adev->pdev->device == 0x1312 ||
2103 adev->pdev->device == 0x1316 || 2106 adev->pdev->device == 0x1316 ||
@@ -2109,29 +2112,29 @@ static int cik_common_early_init(void *handle)
2109 case CHIP_KABINI: 2112 case CHIP_KABINI:
2110 case CHIP_MULLINS: 2113 case CHIP_MULLINS:
2111 adev->cg_flags = 2114 adev->cg_flags =
2112 AMDGPU_CG_SUPPORT_GFX_MGCG | 2115 AMD_CG_SUPPORT_GFX_MGCG |
2113 AMDGPU_CG_SUPPORT_GFX_MGLS | 2116 AMD_CG_SUPPORT_GFX_MGLS |
2114 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2117 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2115 AMDGPU_CG_SUPPORT_GFX_CGLS | 2118 AMD_CG_SUPPORT_GFX_CGLS |
2116 AMDGPU_CG_SUPPORT_GFX_CGTS | 2119 AMD_CG_SUPPORT_GFX_CGTS |
2117 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2120 AMD_CG_SUPPORT_GFX_CGTS_LS |
2118 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2121 AMD_CG_SUPPORT_GFX_CP_LS |
2119 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2122 AMD_CG_SUPPORT_SDMA_MGCG |
2120 AMDGPU_CG_SUPPORT_SDMA_LS | 2123 AMD_CG_SUPPORT_SDMA_LS |
2121 AMDGPU_CG_SUPPORT_BIF_LS | 2124 AMD_CG_SUPPORT_BIF_LS |
2122 AMDGPU_CG_SUPPORT_VCE_MGCG | 2125 AMD_CG_SUPPORT_VCE_MGCG |
2123 AMDGPU_CG_SUPPORT_UVD_MGCG | 2126 AMD_CG_SUPPORT_UVD_MGCG |
2124 AMDGPU_CG_SUPPORT_HDP_LS | 2127 AMD_CG_SUPPORT_HDP_LS |
2125 AMDGPU_CG_SUPPORT_HDP_MGCG; 2128 AMD_CG_SUPPORT_HDP_MGCG;
2126 adev->pg_flags = 2129 adev->pg_flags =
2127 /*AMDGPU_PG_SUPPORT_GFX_PG | 2130 /*AMD_PG_SUPPORT_GFX_PG |
2128 AMDGPU_PG_SUPPORT_GFX_SMG | */ 2131 AMD_PG_SUPPORT_GFX_SMG | */
2129 AMDGPU_PG_SUPPORT_UVD | 2132 AMD_PG_SUPPORT_UVD |
2130 /*AMDGPU_PG_SUPPORT_VCE | 2133 /*AMD_PG_SUPPORT_VCE |
2131 AMDGPU_PG_SUPPORT_CP | 2134 AMD_PG_SUPPORT_CP |
2132 AMDGPU_PG_SUPPORT_GDS | 2135 AMD_PG_SUPPORT_GDS |
2133 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2136 AMD_PG_SUPPORT_RLC_SMU_HS |
2134 AMDGPU_PG_SUPPORT_SAMU |*/ 2137 AMD_PG_SUPPORT_SAMU |*/
2135 0; 2138 0;
2136 if (adev->asic_type == CHIP_KABINI) { 2139 if (adev->asic_type == CHIP_KABINI) {
2137 if (adev->rev_id == 0) 2140 if (adev->rev_id == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index e4e4b2ac77b7..266db15daf2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -856,7 +856,7 @@ static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
856{ 856{
857 u32 orig, data; 857 u32 orig, data;
858 858
859 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) { 859 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
860 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 860 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
861 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 861 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
862 } else { 862 } else {
@@ -877,7 +877,7 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
877{ 877{
878 u32 orig, data; 878 u32 orig, data;
879 879
880 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) { 880 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
881 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 881 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
882 data |= 0x100; 882 data |= 0x100;
883 if (orig != data) 883 if (orig != data)
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 4dd17f2dd905..e7ef2261ff4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -445,13 +445,13 @@ static int cz_dpm_init(struct amdgpu_device *adev)
445 pi->gfx_pg_threshold = 500; 445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true; 446 pi->caps_fps = true;
447 /* uvd */ 447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; 448 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true; 449 pi->caps_uvd_dpm = true;
450 /* vce */ 450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; 451 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true; 452 pi->caps_vce_dpm = true;
453 /* acp */ 453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; 454 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true; 455 pi->caps_acp_dpm = true;
456 456
457 pi->caps_stable_power_state = false; 457 pi->caps_stable_power_state = false;
@@ -2202,8 +2202,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
2202 AMD_PG_STATE_GATE); 2202 AMD_PG_STATE_GATE);
2203 2203
2204 cz_enable_vce_dpm(adev, false); 2204 cz_enable_vce_dpm(adev, false);
2205 /* TODO: to figure out why vce can't be poweroff. */ 2205 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
2206 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
2207 pi->vce_power_gated = true; 2206 pi->vce_power_gated = true;
2208 } else { 2207 } else {
2209 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON); 2208 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
@@ -2226,10 +2225,8 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
2226 } 2225 }
2227 } else { /*pi->caps_vce_pg*/ 2226 } else { /*pi->caps_vce_pg*/
2228 cz_update_vce_dpm(adev); 2227 cz_update_vce_dpm(adev);
2229 cz_enable_vce_dpm(adev, true); 2228 cz_enable_vce_dpm(adev, !gate);
2230 } 2229 }
2231
2232 return;
2233} 2230}
2234 2231
2235const struct amd_ip_funcs cz_dpm_ip_funcs = { 2232const struct amd_ip_funcs cz_dpm_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 8fb7ebf3be3e..4411b94775db 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3041,6 +3041,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3041 unsigned vm_id, uint64_t pd_addr) 3041 unsigned vm_id, uint64_t pd_addr)
3042{ 3042{
3043 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 3043 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3044 uint32_t seq = ring->fence_drv.sync_seq;
3045 uint64_t addr = ring->fence_drv.gpu_addr;
3046
3047 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3048 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3049 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3050 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3051 amdgpu_ring_write(ring, addr & 0xfffffffc);
3052 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3053 amdgpu_ring_write(ring, seq);
3054 amdgpu_ring_write(ring, 0xffffffff);
3055 amdgpu_ring_write(ring, 4); /* poll interval */
3056
3044 if (usepfp) { 3057 if (usepfp) {
3045 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3058 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3046 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3059 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
@@ -3522,7 +3535,7 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3522 3535
3523 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3536 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3524 3537
3525 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) { 3538 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3526 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3539 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3527 3540
3528 tmp = gfx_v7_0_halt_rlc(adev); 3541 tmp = gfx_v7_0_halt_rlc(adev);
@@ -3560,9 +3573,9 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3560{ 3573{
3561 u32 data, orig, tmp = 0; 3574 u32 data, orig, tmp = 0;
3562 3575
3563 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) { 3576 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3564 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) { 3577 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3565 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) { 3578 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3566 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3579 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3567 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3580 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3568 if (orig != data) 3581 if (orig != data)
@@ -3589,14 +3602,14 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3589 3602
3590 gfx_v7_0_update_rlc(adev, tmp); 3603 gfx_v7_0_update_rlc(adev, tmp);
3591 3604
3592 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) { 3605 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3593 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3606 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3594 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3607 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3595 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3608 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3596 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3609 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3597 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3610 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3598 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) && 3611 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3599 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS)) 3612 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3600 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3613 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3601 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3614 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3602 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3615 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
@@ -3662,7 +3675,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3662 u32 data, orig; 3675 u32 data, orig;
3663 3676
3664 orig = data = RREG32(mmRLC_PG_CNTL); 3677 orig = data = RREG32(mmRLC_PG_CNTL);
3665 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) 3678 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3666 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3679 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3667 else 3680 else
3668 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3681 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
@@ -3676,7 +3689,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3676 u32 data, orig; 3689 u32 data, orig;
3677 3690
3678 orig = data = RREG32(mmRLC_PG_CNTL); 3691 orig = data = RREG32(mmRLC_PG_CNTL);
3679 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) 3692 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3680 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3693 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3681 else 3694 else
3682 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3695 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
@@ -3689,7 +3702,7 @@ static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3689 u32 data, orig; 3702 u32 data, orig;
3690 3703
3691 orig = data = RREG32(mmRLC_PG_CNTL); 3704 orig = data = RREG32(mmRLC_PG_CNTL);
3692 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)) 3705 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3693 data &= ~0x8000; 3706 data &= ~0x8000;
3694 else 3707 else
3695 data |= 0x8000; 3708 data |= 0x8000;
@@ -3702,7 +3715,7 @@ static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3702 u32 data, orig; 3715 u32 data, orig;
3703 3716
3704 orig = data = RREG32(mmRLC_PG_CNTL); 3717 orig = data = RREG32(mmRLC_PG_CNTL);
3705 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS)) 3718 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3706 data &= ~0x2000; 3719 data &= ~0x2000;
3707 else 3720 else
3708 data |= 0x2000; 3721 data |= 0x2000;
@@ -3783,7 +3796,7 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3783{ 3796{
3784 u32 data, orig; 3797 u32 data, orig;
3785 3798
3786 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) { 3799 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3787 orig = data = RREG32(mmRLC_PG_CNTL); 3800 orig = data = RREG32(mmRLC_PG_CNTL);
3788 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3801 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3789 if (orig != data) 3802 if (orig != data)
@@ -3846,7 +3859,7 @@ static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3846 u32 data, orig; 3859 u32 data, orig;
3847 3860
3848 orig = data = RREG32(mmRLC_PG_CNTL); 3861 orig = data = RREG32(mmRLC_PG_CNTL);
3849 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)) 3862 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3850 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3863 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3851 else 3864 else
3852 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3865 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
@@ -3860,7 +3873,7 @@ static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3860 u32 data, orig; 3873 u32 data, orig;
3861 3874
3862 orig = data = RREG32(mmRLC_PG_CNTL); 3875 orig = data = RREG32(mmRLC_PG_CNTL);
3863 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)) 3876 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3864 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3877 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3865 else 3878 else
3866 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3879 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
@@ -4027,15 +4040,15 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4027 4040
4028static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4041static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4029{ 4042{
4030 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 4043 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4031 AMDGPU_PG_SUPPORT_GFX_SMG | 4044 AMD_PG_SUPPORT_GFX_SMG |
4032 AMDGPU_PG_SUPPORT_GFX_DMG | 4045 AMD_PG_SUPPORT_GFX_DMG |
4033 AMDGPU_PG_SUPPORT_CP | 4046 AMD_PG_SUPPORT_CP |
4034 AMDGPU_PG_SUPPORT_GDS | 4047 AMD_PG_SUPPORT_GDS |
4035 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 4048 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4036 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4049 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4037 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4050 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4038 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 4051 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4039 gfx_v7_0_init_gfx_cgpg(adev); 4052 gfx_v7_0_init_gfx_cgpg(adev);
4040 gfx_v7_0_enable_cp_pg(adev, true); 4053 gfx_v7_0_enable_cp_pg(adev, true);
4041 gfx_v7_0_enable_gds_pg(adev, true); 4054 gfx_v7_0_enable_gds_pg(adev, true);
@@ -4047,14 +4060,14 @@ static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4047 4060
4048static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4061static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4049{ 4062{
4050 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 4063 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4051 AMDGPU_PG_SUPPORT_GFX_SMG | 4064 AMD_PG_SUPPORT_GFX_SMG |
4052 AMDGPU_PG_SUPPORT_GFX_DMG | 4065 AMD_PG_SUPPORT_GFX_DMG |
4053 AMDGPU_PG_SUPPORT_CP | 4066 AMD_PG_SUPPORT_CP |
4054 AMDGPU_PG_SUPPORT_GDS | 4067 AMD_PG_SUPPORT_GDS |
4055 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 4068 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4056 gfx_v7_0_update_gfx_pg(adev, false); 4069 gfx_v7_0_update_gfx_pg(adev, false);
4057 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 4070 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4058 gfx_v7_0_enable_cp_pg(adev, false); 4071 gfx_v7_0_enable_cp_pg(adev, false);
4059 gfx_v7_0_enable_gds_pg(adev, false); 4072 gfx_v7_0_enable_gds_pg(adev, false);
4060 } 4073 }
@@ -5089,14 +5102,14 @@ static int gfx_v7_0_set_powergating_state(void *handle,
5089 if (state == AMD_PG_STATE_GATE) 5102 if (state == AMD_PG_STATE_GATE)
5090 gate = true; 5103 gate = true;
5091 5104
5092 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | 5105 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5093 AMDGPU_PG_SUPPORT_GFX_SMG | 5106 AMD_PG_SUPPORT_GFX_SMG |
5094 AMDGPU_PG_SUPPORT_GFX_DMG | 5107 AMD_PG_SUPPORT_GFX_DMG |
5095 AMDGPU_PG_SUPPORT_CP | 5108 AMD_PG_SUPPORT_CP |
5096 AMDGPU_PG_SUPPORT_GDS | 5109 AMD_PG_SUPPORT_GDS |
5097 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { 5110 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5098 gfx_v7_0_update_gfx_pg(adev, gate); 5111 gfx_v7_0_update_gfx_pg(adev, gate);
5099 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { 5112 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5100 gfx_v7_0_enable_cp_pg(adev, gate); 5113 gfx_v7_0_enable_cp_pg(adev, gate);
5101 gfx_v7_0_enable_gds_pg(adev, gate); 5114 gfx_v7_0_enable_gds_pg(adev, gate);
5102 } 5115 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e37378fe1edc..1b85c001f860 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4691,7 +4691,8 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4691 4691
4692 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4692 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4693 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 4693 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4694 WAIT_REG_MEM_FUNCTION(3))); /* equal */ 4694 WAIT_REG_MEM_FUNCTION(3) | /* equal */
4695 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
4695 amdgpu_ring_write(ring, addr & 0xfffffffc); 4696 amdgpu_ring_write(ring, addr & 0xfffffffc);
4696 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 4697 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4697 amdgpu_ring_write(ring, seq); 4698 amdgpu_ring_write(ring, seq);
@@ -4877,7 +4878,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4877 case AMDGPU_IRQ_STATE_ENABLE: 4878 case AMDGPU_IRQ_STATE_ENABLE:
4878 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4879 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4879 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4880 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4880 PRIV_REG_INT_ENABLE, 0); 4881 PRIV_REG_INT_ENABLE, 1);
4881 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4882 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4882 break; 4883 break;
4883 default: 4884 default:
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 68ee66b38e5c..711840a23bd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -793,7 +793,7 @@ static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
793 793
794 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 794 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
795 orig = data = RREG32(mc_cg_registers[i]); 795 orig = data = RREG32(mc_cg_registers[i]);
796 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 796 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
797 data |= mc_cg_ls_en[i]; 797 data |= mc_cg_ls_en[i];
798 else 798 else
799 data &= ~mc_cg_ls_en[i]; 799 data &= ~mc_cg_ls_en[i];
@@ -810,7 +810,7 @@ static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
810 810
811 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 811 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
812 orig = data = RREG32(mc_cg_registers[i]); 812 orig = data = RREG32(mc_cg_registers[i]);
813 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 813 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
814 data |= mc_cg_en[i]; 814 data |= mc_cg_en[i];
815 else 815 else
816 data &= ~mc_cg_en[i]; 816 data &= ~mc_cg_en[i];
@@ -826,7 +826,7 @@ static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
826 826
827 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 827 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
828 828
829 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 829 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
830 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 830 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
831 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 831 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
832 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 832 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
@@ -849,7 +849,7 @@ static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
849 849
850 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 850 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
851 851
852 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 852 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
853 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 853 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
854 else 854 else
855 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 855 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
@@ -865,7 +865,7 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
865 865
866 orig = data = RREG32(mmHDP_MEM_POWER_LS); 866 orig = data = RREG32(mmHDP_MEM_POWER_LS);
867 867
868 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 868 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
869 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 869 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
870 else 870 else
871 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 871 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 7e9154c7f1db..654d76723bc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2859,11 +2859,11 @@ static int kv_dpm_init(struct amdgpu_device *adev)
2859 pi->voltage_drop_t = 0; 2859 pi->voltage_drop_t = 0;
2860 pi->caps_sclk_throttle_low_notification = false; 2860 pi->caps_sclk_throttle_low_notification = false;
2861 pi->caps_fps = false; /* true? */ 2861 pi->caps_fps = false; /* true? */
2862 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; 2862 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2863 pi->caps_uvd_dpm = true; 2863 pi->caps_uvd_dpm = true;
2864 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; 2864 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2865 pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false; 2865 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2866 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; 2866 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2867 pi->caps_stable_p_state = false; 2867 pi->caps_stable_p_state = false;
2868 2868
2869 ret = kv_parse_sys_info_table(adev); 2869 ret = kv_parse_sys_info_table(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 70ed73fa5156..c606ccb38d8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -588,7 +588,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
588{ 588{
589 u32 orig, data; 589 u32 orig, data;
590 590
591 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) { 591 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
592 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 592 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
593 data = 0xfff; 593 data = 0xfff;
594 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 594 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
@@ -814,6 +814,9 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
814 bool gate = false; 814 bool gate = false;
815 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 815 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
816 816
817 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
818 return 0;
819
817 if (state == AMD_CG_STATE_GATE) 820 if (state == AMD_CG_STATE_GATE)
818 gate = true; 821 gate = true;
819 822
@@ -832,7 +835,10 @@ static int uvd_v4_2_set_powergating_state(void *handle,
832 * revisit this when there is a cleaner line between 835 * revisit this when there is a cleaner line between
833 * the smc and the hw blocks 836 * the smc and the hw blocks
834 */ 837 */
835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 838 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
839
840 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
841 return 0;
836 842
837 if (state == AMD_PG_STATE_GATE) { 843 if (state == AMD_PG_STATE_GATE) {
838 uvd_v4_2_stop(adev); 844 uvd_v4_2_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 578ffb62fdb2..e3c852d9d79a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -757,6 +757,11 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
757static int uvd_v5_0_set_clockgating_state(void *handle, 757static int uvd_v5_0_set_clockgating_state(void *handle,
758 enum amd_clockgating_state state) 758 enum amd_clockgating_state state)
759{ 759{
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
761
762 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
763 return 0;
764
760 return 0; 765 return 0;
761} 766}
762 767
@@ -772,6 +777,9 @@ static int uvd_v5_0_set_powergating_state(void *handle,
772 */ 777 */
773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
774 779
780 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
781 return 0;
782
775 if (state == AMD_PG_STATE_GATE) { 783 if (state == AMD_PG_STATE_GATE) {
776 uvd_v5_0_stop(adev); 784 uvd_v5_0_stop(adev);
777 return 0; 785 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index d4da1f04378c..3375e614ac67 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -536,7 +536,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
536 uvd_v6_0_mc_resume(adev); 536 uvd_v6_0_mc_resume(adev);
537 537
538 /* Set dynamic clock gating in S/W control mode */ 538 /* Set dynamic clock gating in S/W control mode */
539 if (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG) { 539 if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
540 if (adev->flags & AMD_IS_APU) 540 if (adev->flags & AMD_IS_APU)
541 cz_set_uvd_clock_gating_branches(adev, false); 541 cz_set_uvd_clock_gating_branches(adev, false);
542 else 542 else
@@ -983,7 +983,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
984 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 984 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
985 985
986 if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) 986 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
987 return 0; 987 return 0;
988 988
989 if (enable) { 989 if (enable) {
@@ -1013,6 +1013,9 @@ static int uvd_v6_0_set_powergating_state(void *handle,
1013 */ 1013 */
1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1015 1015
1016 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1017 return 0;
1018
1016 if (state == AMD_PG_STATE_GATE) { 1019 if (state == AMD_PG_STATE_GATE) {
1017 uvd_v6_0_stop(adev); 1020 uvd_v6_0_stop(adev);
1018 return 0; 1021 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 9c804f436974..c7e885bcfd41 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -373,7 +373,7 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
373{ 373{
374 bool sw_cg = false; 374 bool sw_cg = false;
375 375
376 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) { 376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
377 if (sw_cg) 377 if (sw_cg)
378 vce_v2_0_set_sw_cg(adev, true); 378 vce_v2_0_set_sw_cg(adev, true);
379 else 379 else
@@ -608,6 +608,9 @@ static int vce_v2_0_set_powergating_state(void *handle,
608 */ 608 */
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610 610
611 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
612 return 0;
613
611 if (state == AMD_PG_STATE_GATE) 614 if (state == AMD_PG_STATE_GATE)
612 /* XXX do we need a vce_v2_0_stop()? */ 615 /* XXX do we need a vce_v2_0_stop()? */
613 return 0; 616 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 8f8d479061f8..ce468ee5da2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -277,7 +277,7 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
277 WREG32_P(mmVCE_STATUS, 0, ~1); 277 WREG32_P(mmVCE_STATUS, 0, ~1);
278 278
279 /* Set Clock-Gating off */ 279 /* Set Clock-Gating off */
280 if (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG) 280 if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
281 vce_v3_0_set_vce_sw_clock_gating(adev, false); 281 vce_v3_0_set_vce_sw_clock_gating(adev, false);
282 282
283 if (r) { 283 if (r) {
@@ -676,7 +676,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
676 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 676 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
677 int i; 677 int i;
678 678
679 if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) 679 if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
680 return 0; 680 return 0;
681 681
682 mutex_lock(&adev->grbm_idx_mutex); 682 mutex_lock(&adev->grbm_idx_mutex);
@@ -728,6 +728,9 @@ static int vce_v3_0_set_powergating_state(void *handle,
728 */ 728 */
729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 729 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
730 730
731 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
732 return 0;
733
731 if (state == AMD_PG_STATE_GATE) 734 if (state == AMD_PG_STATE_GATE)
732 /* XXX do we need a vce_v3_0_stop()? */ 735 /* XXX do we need a vce_v3_0_stop()? */
733 return 0; 736 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 125003517544..b72cf063df1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1092,8 +1092,7 @@ static int vi_common_early_init(void *handle)
1092 case CHIP_STONEY: 1092 case CHIP_STONEY:
1093 adev->has_uvd = true; 1093 adev->has_uvd = true;
1094 adev->cg_flags = 0; 1094 adev->cg_flags = 0;
1095 /* Disable UVD pg */ 1095 adev->pg_flags = 0;
1096 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
1097 adev->external_rev_id = adev->rev_id + 0x1; 1096 adev->external_rev_id = adev->rev_id + 0x1;
1098 break; 1097 break;
1099 default: 1098 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 00:31:45 -0400