Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-next

A few other misc cleanups and bug fixes for 4.6.  Highlights:
- unify endian handling in powerplay
- powerplay fixes
- fix a regression in 4.5 on boards with no display connectors
- fence cleanups and locking fixes
- whitespace cleanups and code refactoring in radeon

* 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (35 commits)
  drm/amdgpu/gfx7: add MTYPE definition
  drm/amdgpu: removing BO_VAs shouldn't be interruptible
  drm/amd/powerplay: show uvd/vce power gate enablement for tonga.
  drm/amd/powerplay: show uvd/vce power gate info for fiji
  drm/amdgpu: use sched fence if possible
  drm/amdgpu: move ib.fence to job.fence
  drm/amdgpu: give a fence param to ib_free
  drm/amdgpu: include the right version of gmc header files for iceland
  drm/radeon: fix indentation.
  drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ
  drm/amdgpu: switch back to 32bit hw fences v2
  drm/amdgpu: remove amdgpu_fence_is_signaled
  drm/amdgpu: drop the extra fence range check v2
  drm/amdgpu: signal fences directly in amdgpu_fence_process
  drm/amdgpu: cleanup amdgpu_fence_wait_empty v2
  drm/amdgpu: keep all fences in an RCU protected array v2
  drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring
  drm/amdgpu: RCU protected amd_sched_fence_release
  drm/amdgpu: RCU protected amdgpu_fence_release
  drm/amdgpu: merge amdgpu_fence_process and _activity
  ...

15 files changed, 214 insertions, 364 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a80c8cea7609..c4a21c6428f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -141,7 +141,6 @@ extern unsigned amdgpu_pcie_lane_cap;
 #define CIK_CURSOR_HEIGHT 128
 
 struct amdgpu_device;
-struct amdgpu_fence;
 struct amdgpu_ib;
 struct amdgpu_vm;
 struct amdgpu_ring;
@@ -348,13 +347,15 @@ struct amdgpu_fence_driver {
         uint64_t                        gpu_addr;
         volatile uint32_t               *cpu_addr;
         /* sync_seq is protected by ring emission lock */
-        uint64_t                        sync_seq;
-        atomic64_t                      last_seq;
+        uint32_t                        sync_seq;
+        atomic_t                        last_seq;
         bool                            initialized;
         struct amdgpu_irq_src           *irq_src;
         unsigned                        irq_type;
         struct timer_list               fallback_timer;
-        wait_queue_head_t               fence_queue;
+        unsigned                        num_fences_mask;
+        spinlock_t                      lock;
+        struct fence                    **fences;
 };
 
 /* some special values for the owner field */
@@ -364,16 +365,6 @@ struct amdgpu_fence_driver {
 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
 
-struct amdgpu_fence {
-        struct fence base;
-
-        /* RB, DMA, etc. */
-        struct amdgpu_ring              *ring;
-        uint64_t                        seq;
-
-        wait_queue_t                    fence_wake;
-};
-
 struct amdgpu_user_fence {
         /* write-back bo */
         struct amdgpu_bo        *bo;
@@ -385,7 +376,8 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev);
 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
 
-int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
+                                  unsigned num_hw_submission);
 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
                                    struct amdgpu_irq_src *irq_src,
                                    unsigned irq_type);
@@ -393,7 +385,6 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
 void amdgpu_fence_process(struct amdgpu_ring *ring);
-int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 
@@ -539,11 +530,14 @@ int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
  * Assumption is that there won't be hole (all object on same
  * alignment).
  */
+
+#define AMDGPU_SA_NUM_FENCE_LISTS       32
+
 struct amdgpu_sa_manager {
         wait_queue_head_t       wq;
         struct amdgpu_bo        *bo;
         struct list_head        *hole;
-        struct list_head        flist[AMDGPU_MAX_RINGS];
+        struct list_head        flist[AMDGPU_SA_NUM_FENCE_LISTS];
         struct list_head        olist;
         unsigned                size;
         uint64_t                gpu_addr;
@@ -727,7 +721,6 @@ struct amdgpu_ib {
         uint32_t                        length_dw;
         uint64_t                        gpu_addr;
         uint32_t                        *ptr;
-        struct fence                    *fence;
         struct amdgpu_user_fence        *user;
         struct amdgpu_vm                *vm;
         unsigned                        vm_id;
@@ -1143,7 +1136,7 @@ struct amdgpu_gfx {
 
 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                   unsigned size, struct amdgpu_ib *ib);
-void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                        struct amdgpu_ib *ib, struct fence *last_vm_update,
                        struct fence **f);
@@ -1164,7 +1157,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                      struct amdgpu_irq_src *irq_src, unsigned irq_type,
                      enum amdgpu_ring_type ring_type);
 void amdgpu_ring_fini(struct amdgpu_ring *ring);
-struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
 
 /*
  * CS.
@@ -1206,6 +1198,7 @@ struct amdgpu_job {
         struct amdgpu_ring      *ring;
         struct amdgpu_sync      sync;
         struct amdgpu_ib        *ibs;
+        struct fence            *fence; /* the hw fence */
         uint32_t                num_ibs;
         void                    *owner;
         struct amdgpu_user_fence uf;
@@ -2067,20 +2060,6 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 
 /*
- * Cast helper
- */
-extern const struct fence_ops amdgpu_fence_ops;
-static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
-{
-        struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
-
-        if (__f->base.ops == &amdgpu_fence_ops)
-                return __f;
-
-        return NULL;
-}
-
-/*
  * Registers read & write functions.
  */
 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 83599f2a0387..4303b447efe8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -47,9 +47,30 @@
  * that the the relevant GPU caches have been flushed.
  */
 
+struct amdgpu_fence {
+        struct fence base;
+
+        /* RB, DMA, etc. */
+        struct amdgpu_ring              *ring;
+};
+
 static struct kmem_cache *amdgpu_fence_slab;
 static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
 
+/*
+ * Cast helper
+ */
+static const struct fence_ops amdgpu_fence_ops;
+static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
+{
+        struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
+
+        if (__f->base.ops == &amdgpu_fence_ops)
+                return __f;
+
+        return NULL;
+}
+
 /**
  * amdgpu_fence_write - write a fence value
  *
@@ -82,7 +103,7 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
         if (drv->cpu_addr)
                 seq = le32_to_cpu(*drv->cpu_addr);
         else
-                seq = lower_32_bits(atomic64_read(&drv->last_seq));
+                seq = atomic_read(&drv->last_seq);
 
         return seq;
 }
@@ -100,20 +121,32 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
 {
         struct amdgpu_device *adev = ring->adev;
         struct amdgpu_fence *fence;
+        struct fence **ptr;
+        uint32_t seq;
 
         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
         if (fence == NULL)
                 return -ENOMEM;
 
-        fence->seq = ++ring->fence_drv.sync_seq;
+        seq = ++ring->fence_drv.sync_seq;
         fence->ring = ring;
         fence_init(&fence->base, &amdgpu_fence_ops,
-                   &ring->fence_drv.fence_queue.lock,
+                   &ring->fence_drv.lock,
                    adev->fence_context + ring->idx,
-                   fence->seq);
+                   seq);
         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
-                               fence->seq, AMDGPU_FENCE_FLAG_INT);
+                               seq, AMDGPU_FENCE_FLAG_INT);
+
+        ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
+        /* This function can't be called concurrently anyway, otherwise
+         * emitting the fence would mess up the hardware ring buffer.
+         */
+        BUG_ON(rcu_dereference_protected(*ptr, 1));
+
+        rcu_assign_pointer(*ptr, fence_get(&fence->base));
+
         *f = &fence->base;
+
         return 0;
 }
 
@@ -131,89 +164,48 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 }
 
 /**
- * amdgpu_fence_activity - check for fence activity
+ * amdgpu_fence_process - check for fence activity
  *
  * @ring: pointer to struct amdgpu_ring
  *
  * Checks the current fence value and calculates the last
- * signalled fence value. Returns true if activity occured
- * on the ring, and the fence_queue should be waken up.
+ * signalled fence value. Wakes the fence queue if the
+ * sequence number has increased.
  */
-static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
+void amdgpu_fence_process(struct amdgpu_ring *ring)
 {
-        uint64_t seq, last_seq, last_emitted;
-        unsigned count_loop = 0;
-        bool wake = false;
-
-        /* Note there is a scenario here for an infinite loop but it's
-         * very unlikely to happen. For it to happen, the current polling
-         * process need to be interrupted by another process and another
-         * process needs to update the last_seq btw the atomic read and
-         * xchg of the current process.
-         *
-         * More over for this to go in infinite loop there need to be
-         * continuously new fence signaled ie amdgpu_fence_read needs
-         * to return a different value each time for both the currently
-         * polling process and the other process that xchg the last_seq
-         * btw atomic read and xchg of the current process. And the
-         * value the other process set as last seq must be higher than
-         * the seq value we just read. Which means that current process
-         * need to be interrupted after amdgpu_fence_read and before
-         * atomic xchg.
-         *
-         * To be even more safe we count the number of time we loop and
-         * we bail after 10 loop just accepting the fact that we might
-         * have temporarly set the last_seq not to the true real last
-         * seq but to an older one.
-         */
-        last_seq = atomic64_read(&ring->fence_drv.last_seq);
+        struct amdgpu_fence_driver *drv = &ring->fence_drv;
+        uint32_t seq, last_seq;
+        int r;
+
         do {
-                last_emitted = ring->fence_drv.sync_seq;
+                last_seq = atomic_read(&ring->fence_drv.last_seq);
                 seq = amdgpu_fence_read(ring);
-                seq |= last_seq & 0xffffffff00000000LL;
-                if (seq < last_seq) {
-                        seq &= 0xffffffff;
-                        seq |= last_emitted & 0xffffffff00000000LL;
-                }
 
-                if (seq <= last_seq || seq > last_emitted) {
-                        break;
-                }
-                /* If we loop over we don't want to return without
-                 * checking if a fence is signaled as it means that the
-                 * seq we just read is different from the previous on.
-                 */
-                wake = true;
-                last_seq = seq;
-                if ((count_loop++) > 10) {
-                        /* We looped over too many time leave with the
-                         * fact that we might have set an older fence
-                         * seq then the current real last seq as signaled
-                         * by the hw.
-                         */
-                        break;
-                }
-        } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
+        } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 
-        if (seq < last_emitted)
+        if (seq != ring->fence_drv.sync_seq)
                 amdgpu_fence_schedule_fallback(ring);
 
-        return wake;
-}
+        while (last_seq != seq) {
+                struct fence *fence, **ptr;
 
-/**
- * amdgpu_fence_process - process a fence
- *
- * @adev: amdgpu_device pointer
- * @ring: ring index the fence is associated with
- *
- * Checks the current fence value and wakes the fence queue
- * if the sequence number has increased (all asics).
- */
-void amdgpu_fence_process(struct amdgpu_ring *ring)
-{
-        if (amdgpu_fence_activity(ring))
-                wake_up_all(&ring->fence_drv.fence_queue);
+                ptr = &drv->fences[++last_seq & drv->num_fences_mask];
+
+                /* There is always exactly one thread signaling this fence slot */
+                fence = rcu_dereference_protected(*ptr, 1);
+                rcu_assign_pointer(*ptr, NULL);
+
+                BUG_ON(!fence);
+
+                r = fence_signal(fence);
+                if (!r)
+                        FENCE_TRACE(fence, "signaled from irq context\n");
+                else
+                        BUG();
+
+                fence_put(fence);
+        }
 }
 
 /**
@@ -231,77 +223,6 @@ static void amdgpu_fence_fallback(unsigned long arg)
 }
 
 /**
- * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
- *
- * @ring: ring the fence is associated with
- * @seq: sequence number
- *
- * Check if the last signaled fence sequnce number is >= the requested
- * sequence number (all asics).
- * Returns true if the fence has signaled (current fence value
- * is >= requested value) or false if it has not (current fence
- * value is < the requested value.  Helper function for
- * amdgpu_fence_signaled().
- */
-static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
-{
-        if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
-                return true;
-
-        /* poll new last sequence at least once */
-        amdgpu_fence_process(ring);
-        if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
-                return true;
-
-        return false;
-}
-
-/*
- * amdgpu_ring_wait_seq - wait for seq of the specific ring to signal
- * @ring: ring to wait on for the seq number
- * @seq: seq number wait for
- *
- * return value:
- * 0: seq signaled, and gpu not hang
- * -EINVAL: some paramter is not valid
- */
-static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
-{
-        BUG_ON(!ring);
-        if (seq > ring->fence_drv.sync_seq)
-                return -EINVAL;
-
-        if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
-                return 0;
-
-        amdgpu_fence_schedule_fallback(ring);
-        wait_event(ring->fence_drv.fence_queue,
-                   amdgpu_fence_seq_signaled(ring, seq));
-
-        return 0;
-}
-
-/**
- * amdgpu_fence_wait_next - wait for the next fence to signal
- *
- * @adev: amdgpu device pointer
- * @ring: ring index the fence is associated with
- *
- * Wait for the next fence on the requested ring to signal (all asics).
- * Returns 0 if the next fence has passed, error for all other cases.
- * Caller must hold ring lock.
- */
-int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
-{
-        uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
-
-        if (seq >= ring->fence_drv.sync_seq)
-                return -ENOENT;
-
-        return amdgpu_fence_ring_wait_seq(ring, seq);
-}
-
-/**
  * amdgpu_fence_wait_empty - wait for all fences to signal
  *
  * @adev: amdgpu device pointer
@@ -309,16 +230,28 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
  *
  * Wait for all fences on the requested ring to signal (all asics).
  * Returns 0 if the fences have passed, error for all other cases.
- * Caller must hold ring lock.
  */
 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 {
-        uint64_t seq = ring->fence_drv.sync_seq;
+        uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
+        struct fence *fence, **ptr;
+        int r;
 
         if (!seq)
                 return 0;
 
-        return amdgpu_fence_ring_wait_seq(ring, seq);
+        ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
+        rcu_read_lock();
+        fence = rcu_dereference(*ptr);
+        if (!fence || !fence_get_rcu(fence)) {
+                rcu_read_unlock();
+                return 0;
+        }
+        rcu_read_unlock();
+
+        r = fence_wait(fence, false);
+        fence_put(fence);
+        return r;
 }
 
 /**
@@ -338,13 +271,10 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
          * but it's ok to report slightly wrong fence count here.
          */
         amdgpu_fence_process(ring);
-        emitted = ring->fence_drv.sync_seq
-                - atomic64_read(&ring->fence_drv.last_seq);
-        /* to avoid 32bits warp around */
-        if (emitted > 0x10000000)
-                emitted = 0x10000000;
-
-        return (unsigned)emitted;
+        emitted = 0x100000000ull;
+        emitted -= atomic_read(&ring->fence_drv.last_seq);
+        emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
+        return lower_32_bits(emitted);
 }
 
 /**
@@ -376,7 +306,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
                 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
                 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
         }
-        amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
+        amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
         amdgpu_irq_get(adev, irq_src, irq_type);
 
         ring->fence_drv.irq_src = irq_src;
@@ -394,25 +324,36 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
  * for the requested ring.
  *
  * @ring: ring to init the fence driver on
+ * @num_hw_submission: number of entries on the hardware queue
  *
  * Init the fence driver for the requested ring (all asics).
  * Helper function for amdgpu_fence_driver_init().
  */
-int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
+                                  unsigned num_hw_submission)
 {
         long timeout;
         int r;
 
+        /* Check that num_hw_submission is a power of two */
+        if ((num_hw_submission & (num_hw_submission - 1)) != 0)
+                return -EINVAL;
+
         ring->fence_drv.cpu_addr = NULL;
         ring->fence_drv.gpu_addr = 0;
         ring->fence_drv.sync_seq = 0;
-        atomic64_set(&ring->fence_drv.last_seq, 0);
+        atomic_set(&ring->fence_drv.last_seq, 0);
         ring->fence_drv.initialized = false;
 
         setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
                     (unsigned long)ring);
 
-        init_waitqueue_head(&ring->fence_drv.fence_queue);
+        ring->fence_drv.num_fences_mask = num_hw_submission - 1;
+        spin_lock_init(&ring->fence_drv.lock);
+        ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
+                                         GFP_KERNEL);
+        if (!ring->fence_drv.fences)
+                return -ENOMEM;
 
         timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
         if (timeout == 0) {
@@ -426,7 +367,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
                 timeout = MAX_SCHEDULE_TIMEOUT;
         }
         r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
-                           amdgpu_sched_hw_submission,
+                           num_hw_submission,
                            timeout, ring->name);
         if (r) {
                 DRM_ERROR("Failed to create scheduler on ring %s.\n",
@@ -474,10 +415,9 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev)
  */
 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 {
-        int i, r;
+        unsigned i, j;
+        int r;
 
-        if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
-                kmem_cache_destroy(amdgpu_fence_slab);
         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
                 struct amdgpu_ring *ring = adev->rings[i];
 
@@ -488,13 +428,18 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
                         /* no need to trigger GPU reset as we are unloading */
                         amdgpu_fence_driver_force_completion(adev);
                 }
-                wake_up_all(&ring->fence_drv.fence_queue);
                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
                                ring->fence_drv.irq_type);
                 amd_sched_fini(&ring->sched);
                 del_timer_sync(&ring->fence_drv.fallback_timer);
+                for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
+                        fence_put(ring->fence_drv.fences[i]);
+                kfree(ring->fence_drv.fences);
                 ring->fence_drv.initialized = false;
         }
+
+        if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
+                kmem_cache_destroy(amdgpu_fence_slab);
 }
 
 /**
@@ -591,103 +536,57 @@ static const char *amdgpu_fence_get_timeline_name(struct fence *f)
 }
 
 /**
- * amdgpu_fence_is_signaled - test if fence is signaled
- *
- * @f: fence to test
+ * amdgpu_fence_enable_signaling - enable signalling on fence
+ * @fence: fence
  *
- * Test the fence sequence number if it is already signaled. If it isn't
- * signaled start fence processing. Returns True if the fence is signaled.
+ * This function is called with fence_queue lock held, and adds a callback
+ * to fence_queue that checks if this fence is signaled, and if so it
+ * signals the fence and removes itself.
  */
-static bool amdgpu_fence_is_signaled(struct fence *f)
+static bool amdgpu_fence_enable_signaling(struct fence *f)
 {
         struct amdgpu_fence *fence = to_amdgpu_fence(f);
         struct amdgpu_ring *ring = fence->ring;
 
-        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                return true;
-
-        amdgpu_fence_process(ring);
+        if (!timer_pending(&ring->fence_drv.fallback_timer))
+                amdgpu_fence_schedule_fallback(ring);
 
-        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                return true;
+        FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 
-        return false;
+        return true;
 }
 
 /**
- * amdgpu_fence_check_signaled - callback from fence_queue
+ * amdgpu_fence_free - free up the fence memory
+ *
+ * @rcu: RCU callback head
  *
- * this function is called with fence_queue lock held, which is also used
- * for the fence locking itself, so unlocked variants are used for
- * fence_signal, and remove_wait_queue.
+ * Free up the fence memory after the RCU grace period.
  */
-static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
+static void amdgpu_fence_free(struct rcu_head *rcu)
 {
-        struct amdgpu_fence *fence;
-        struct amdgpu_device *adev;
-        u64 seq;
-        int ret;
-
-        fence = container_of(wait, struct amdgpu_fence, fence_wake);
-        adev = fence->ring->adev;
-
-        /*
-         * We cannot use amdgpu_fence_process here because we're already
-         * in the waitqueue, in a call from wake_up_all.
-         */
-        seq = atomic64_read(&fence->ring->fence_drv.last_seq);
-        if (seq >= fence->seq) {
-                ret = fence_signal_locked(&fence->base);
-                if (!ret)
-                        FENCE_TRACE(&fence->base, "signaled from irq context\n");
-                else
-                        FENCE_TRACE(&fence->base, "was already signaled\n");
-
-                __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
-                fence_put(&fence->base);
-        } else
-                FENCE_TRACE(&fence->base, "pending\n");
-        return 0;
+        struct fence *f = container_of(rcu, struct fence, rcu);
+        struct amdgpu_fence *fence = to_amdgpu_fence(f);
+        kmem_cache_free(amdgpu_fence_slab, fence);
 }
 
 /**
- * amdgpu_fence_enable_signaling - enable signalling on fence
+ * amdgpu_fence_release - callback that fence can be freed
+ *
  * @fence: fence
  *
- * This function is called with fence_queue lock held, and adds a callback
- * to fence_queue that checks if this fence is signaled, and if so it
- * signals the fence and removes itself.
+ * This function is called when the reference count becomes zero.
+ * It just RCU schedules freeing up the fence.
  */
-static bool amdgpu_fence_enable_signaling(struct fence *f)
-{
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        struct amdgpu_ring *ring = fence->ring;
-
-        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                return false;
-
-        fence->fence_wake.flags = 0;
-        fence->fence_wake.private = NULL;
-        fence->fence_wake.func = amdgpu_fence_check_signaled;
-        __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
-        fence_get(f);
-        if (!timer_pending(&ring->fence_drv.fallback_timer))
-                amdgpu_fence_schedule_fallback(ring);
-        FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
-        return true;
-}
-
 static void amdgpu_fence_release(struct fence *f)
 {
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        kmem_cache_free(amdgpu_fence_slab, fence);
+        call_rcu(&f->rcu, amdgpu_fence_free);
 }
 
-const struct fence_ops amdgpu_fence_ops = {
+static const struct fence_ops amdgpu_fence_ops = {
         .get_driver_name = amdgpu_fence_get_driver_name,
         .get_timeline_name = amdgpu_fence_get_timeline_name,
         .enable_signaling = amdgpu_fence_enable_signaling,
-        .signaled = amdgpu_fence_is_signaled,
         .wait = fence_default_wait,
         .release = amdgpu_fence_release,
 };
@@ -711,9 +610,9 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
                 amdgpu_fence_process(ring);
 
                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
-                seq_printf(m, "Last signaled fence 0x%016llx\n",
-                           (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
-                seq_printf(m, "Last emitted        0x%016llx\n",
+                seq_printf(m, "Last signaled fence 0x%08x\n",
+                           atomic_read(&ring->fence_drv.last_seq));
+                seq_printf(m, "Last emitted        0x%08x\n",
                            ring->fence_drv.sync_seq);
         }
         return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 1ecdf6c01368..3e128c52bb87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -161,7 +161,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 
         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
 
-        r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
+        r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
         if (r) {
                 dev_err(adev->dev, "leaking bo va because "
                         "we fail to reserve bo (%d)\n", r);
@@ -258,12 +258,10 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
             AMDGPU_GEM_USERPTR_REGISTER))
                 return -EINVAL;
 
-        if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && (
-             !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
-             !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) {
+        if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
+             !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 
-                /* if we want to write to it we must require anonymous
-                   memory and install a MMU notifier */
+                /* if we want to write to it we must install a MMU notifier */
                 return -EACCES;
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 798d46626820..8443cea6821a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -85,13 +85,13 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  *
  * @adev: amdgpu_device pointer
  * @ib: IB object to free
+ * @f: the fence SA bo need wait on for the ib alloation
  *
  * Free an IB (all asics).
  */
-void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f)
 {
-        amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
-        fence_put(ib->fence);
+        amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
 }
 
 /**
@@ -123,6 +123,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
         struct amdgpu_ib *ib = &ibs[0];
         struct amdgpu_ctx *ctx, *old_ctx;
         struct amdgpu_vm *vm;
+        struct fence *hwf;
         unsigned i;
         int r = 0;
 
@@ -179,7 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                         amdgpu_ring_emit_hdp_invalidate(ring);
         }
 
-        r = amdgpu_fence_emit(ring, &ib->fence);
+        r = amdgpu_fence_emit(ring, &hwf);
         if (r) {
                 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
                 ring->current_ctx = old_ctx;
@@ -198,7 +199,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
         }
 
         if (f)
-                *f = fence_get(ib->fence);
+                *f = fence_get(hwf);
 
         amdgpu_ring_commit(ring);
         return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 692b45560d0a..9c9b19e2f353 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -70,9 +70,13 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 void amdgpu_job_free(struct amdgpu_job *job)
 {
         unsigned i;
+        struct fence *f;
+        /* use sched fence if available */
+        f = (job->base.s_fence)? &job->base.s_fence->base : job->fence;
 
         for (i = 0; i < job->num_ibs; ++i)
-                amdgpu_ib_free(job->adev, &job->ibs[i]);
+                amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, f);
+        fence_put(job->fence);
 
         amdgpu_bo_unref(&job->uf.bo);
         amdgpu_sync_free(&job->sync);
@@ -156,6 +160,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
         }
 
 err:
+        job->fence = fence;
         amdgpu_job_free(job);
         return fence;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9a025a77958d..151a2d42c639 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -308,7 +308,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 {
         bool is_iomem;
-        int r;
+        long r;
 
         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
                 return -EPERM;
@@ -319,14 +319,20 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
                 }
                 return 0;
         }
+
+        r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
+                                                MAX_SCHEDULE_TIMEOUT);
+        if (r < 0)
+                return r;
+
         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
-        if (r) {
+        if (r)
                 return r;
-        }
+
         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
-        if (ptr) {
+        if (ptr)
                 *ptr = bo->kptr;
-        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 56c07e3fdb33..972eed2ef787 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -236,7 +236,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                 ring->adev = adev;
                 ring->idx = adev->num_rings++;
                 adev->rings[ring->idx] = ring;
-                r = amdgpu_fence_driver_init_ring(ring);
+                r = amdgpu_fence_driver_init_ring(ring,
+                        amdgpu_sched_hw_submission);
                 if (r)
                         return r;
         }
@@ -352,30 +353,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
         }
 }
 
-/**
- * amdgpu_ring_from_fence - get ring from fence
- *
- * @f: fence structure
- *
- * Extract the ring a fence belongs to. Handles both scheduler as
- * well as hardware fences.
- */
-struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f)
-{
-        struct amdgpu_fence *a_fence;
-        struct amd_sched_fence *s_fence;
-
-        s_fence = to_amd_sched_fence(f);
-        if (s_fence)
-                return container_of(s_fence->sched, struct amdgpu_ring, sched);
-
-        a_fence = to_amdgpu_fence(f);
-        if (a_fence)
-                return a_fence->ring;
-
-        return NULL;
-}
-
 /*
  * Debugfs info
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 2faf03bcda21..8bf84efafb04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -60,9 +60,8 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
         sa_manager->align = align;
         sa_manager->hole = &sa_manager->olist;
         INIT_LIST_HEAD(&sa_manager->olist);
-        for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+        for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
                 INIT_LIST_HEAD(&sa_manager->flist[i]);
-        }
 
         r = amdgpu_bo_create(adev, size, align, true, domain,
                              0, NULL, NULL, &sa_manager->bo);
@@ -228,11 +227,9 @@ static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
         unsigned soffset, eoffset, wasted;
         int i;
 
-        for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-                if (!list_empty(&sa_manager->flist[i])) {
+        for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
+                if (!list_empty(&sa_manager->flist[i]))
                         return true;
-                }
-        }
 
         soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
         eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
@@ -265,12 +262,11 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
         /* go over all fence list and try to find the closest sa_bo
          * of the current last
          */
-        for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+        for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
                 struct amdgpu_sa_bo *sa_bo;
 
-                if (list_empty(&sa_manager->flist[i])) {
+                if (list_empty(&sa_manager->flist[i]))
                         continue;
-                }
 
                 sa_bo = list_first_entry(&sa_manager->flist[i],
                                          struct amdgpu_sa_bo, flist);
@@ -299,7 +295,9 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
         }
 
         if (best_bo) {
-                uint32_t idx = amdgpu_ring_from_fence(best_bo->fence)->idx;
+                uint32_t idx = best_bo->fence->context;
+
+                idx %= AMDGPU_SA_NUM_FENCE_LISTS;
                 ++tries[idx];
                 sa_manager->hole = best_bo->olist.prev;
 
@@ -315,8 +313,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
                      struct amdgpu_sa_bo **sa_bo,
                      unsigned size, unsigned align)
 {
-        struct fence *fences[AMDGPU_MAX_RINGS];
-        unsigned tries[AMDGPU_MAX_RINGS];
+        struct fence *fences[AMDGPU_SA_NUM_FENCE_LISTS];
+        unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS];
         unsigned count;
         int i, r;
         signed long t;
@@ -338,7 +336,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
 
         spin_lock(&sa_manager->wq.lock);
         do {
-                for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+                for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
                         fences[i] = NULL;
                         tries[i] = 0;
                 }
@@ -355,7 +353,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
                         /* see if we can skip over some allocations */
                 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
 
-                for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
+                for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
                         if (fences[i])
                                 fences[count++] = fence_get(fences[i]);
 
@@ -397,8 +395,9 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
         spin_lock(&sa_manager->wq.lock);
         if (fence && !fence_is_signaled(fence)) {
                 uint32_t idx;
+
                 (*sa_bo)->fence = fence_get(fence);
-                idx = amdgpu_ring_from_fence(fence)->idx;
+                idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS;
                 list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
         } else {
                 amdgpu_sa_bo_remove_locked(*sa_bo);
@@ -410,25 +409,6 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
 
 #if defined(CONFIG_DEBUG_FS)
 
-static void amdgpu_sa_bo_dump_fence(struct fence *fence, struct seq_file *m)
-{
-        struct amdgpu_fence *a_fence = to_amdgpu_fence(fence);
-        struct amd_sched_fence *s_fence = to_amd_sched_fence(fence);
-
-        if (a_fence)
-                seq_printf(m, " protected by 0x%016llx on ring %d",
-                           a_fence->seq, a_fence->ring->idx);
-
-        if (s_fence) {
-                struct amdgpu_ring *ring;
-
-
-                ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
-                seq_printf(m, " protected by 0x%016x on ring %d",
-                           s_fence->base.seqno, ring->idx);
-        }
-}
-
 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
                                   struct seq_file *m)
 {
@@ -445,8 +425,11 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
                 }
                 seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
                            soffset, eoffset, eoffset - soffset);
+
                 if (i->fence)
-                        amdgpu_sa_bo_dump_fence(i->fence, m);
+                        seq_printf(m, " protected by 0x%08x on context %d",
+                                   i->fence->seqno, i->fence->context);
+
                 seq_printf(m, "\n");
         }
         spin_unlock(&sa_manager->wq.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e5f0a5e29551..c1a581044417 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -539,13 +539,6 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
                 return -EINVAL;
         }
 
-        r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
-                                                MAX_SCHEDULE_TIMEOUT);
-        if (r < 0) {
-                DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
-                return r;
-        }
-
         r = amdgpu_bo_kmap(bo, &ptr);
         if (r) {
                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
@@ -887,6 +880,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 
         if (direct) {
                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+                job->fence = f;
                 if (r)
                         goto err_free;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 6d191fb40b38..4bec0c108cea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -426,6 +426,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
                 ib->ptr[i] = 0x0;
 
         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+        job->fence = f;
         if (r)
                 goto err;
 
@@ -487,6 +488,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 
         if (direct) {
                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+                job->fence = f;
                 if (r)
                         goto err;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 02122197d2b6..d3ac3298fba8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -669,7 +669,8 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 
 err1:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 err0:
         amdgpu_wb_free(adev, index);
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a06045f040f1..bb8709066fd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2163,7 +2163,8 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
 
 err2:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 err1:
         amdgpu_gfx_scratch_free(adev, scratch);
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 509d0baaeaae..f0c7b3596480 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -732,7 +732,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
         }
 err2:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 err1:
         amdgpu_gfx_scratch_free(adev, scratch);
         return r;
@@ -1289,7 +1290,8 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
 
 fail:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 
         return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index ab9ff89a3096..6e0a86a563f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -32,8 +32,8 @@
 #include "oss/oss_2_4_d.h"
 #include "oss/oss_2_4_sh_mask.h"
 
-#include "gmc/gmc_8_1_d.h"
-#include "gmc/gmc_8_1_sh_mask.h"
+#include "gmc/gmc_7_1_d.h"
+#include "gmc/gmc_7_1_sh_mask.h"
 
 #include "gca/gfx_8_0_d.h"
 #include "gca/gfx_8_0_enum.h"
@@ -727,7 +727,8 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 
 err1:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 err0:
         amdgpu_wb_free(adev, index);
         return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 4c24c371fec7..8c8ca98dd129 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -878,7 +878,8 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
         }
 err1:
         fence_put(f);
-        amdgpu_ib_free(adev, &ib);
+        amdgpu_ib_free(adev, &ib, NULL);
+        fence_put(f);
 err0:
         amdgpu_wb_free(adev, index);
         return r;